TW350124B - Manufacturing method of semiconductor devices - Google Patents
Manufacturing method of semiconductor devicesInfo
- Publication number
- TW350124B TW350124B TW086116380A TW86116380A TW350124B TW 350124 B TW350124 B TW 350124B TW 086116380 A TW086116380 A TW 086116380A TW 86116380 A TW86116380 A TW 86116380A TW 350124 B TW350124 B TW 350124B
- Authority
- TW
- Taiwan
- Prior art keywords
- manufacturing process
- groove
- manufacturing
- semiconductor substrate
- semiconductor devices
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9188286A JPH1131742A (ja) | 1997-07-14 | 1997-07-14 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW350124B true TW350124B (en) | 1999-01-11 |
Family
ID=16220983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086116380A TW350124B (en) | 1997-07-14 | 1997-11-04 | Manufacturing method of semiconductor devices |
Country Status (5)
Country | Link |
---|---|
US (1) | US6017800A (zh) |
JP (1) | JPH1131742A (zh) |
KR (1) | KR100272986B1 (zh) |
DE (1) | DE19806300C2 (zh) |
TW (1) | TW350124B (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10303291A (ja) * | 1997-04-25 | 1998-11-13 | Nippon Steel Corp | 半導体装置及びその製造方法 |
US6080628A (en) * | 1998-05-15 | 2000-06-27 | Vanguard International Semiconductor Corporation | Method of forming shallow trench isolation for integrated circuit applications |
US6251749B1 (en) * | 1998-09-15 | 2001-06-26 | Texas Instruments Incorporated | Shallow trench isolation formation with sidewall spacer |
US6268264B1 (en) * | 1998-12-04 | 2001-07-31 | Vanguard International Semiconductor Corp. | Method of forming shallow trench isolation |
US6825544B1 (en) * | 1998-12-09 | 2004-11-30 | Cypress Semiconductor Corporation | Method for shallow trench isolation and shallow trench isolation structure |
KR100351891B1 (ko) * | 1999-06-01 | 2002-09-12 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
JP4832629B2 (ja) * | 2000-10-04 | 2011-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100387531B1 (ko) * | 2001-07-30 | 2003-06-18 | 삼성전자주식회사 | 반도체소자 제조방법 |
JP2003163262A (ja) * | 2001-11-28 | 2003-06-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6913978B1 (en) * | 2004-02-25 | 2005-07-05 | United Microelectronics Corp. | Method for forming shallow trench isolation structure |
TWI253686B (en) * | 2004-08-03 | 2006-04-21 | Powerchip Semiconductor Corp | Method of fabricating a gate oxide layer |
US7981800B1 (en) | 2006-08-25 | 2011-07-19 | Cypress Semiconductor Corporation | Shallow trench isolation structures and methods for forming the same |
US9666668B2 (en) * | 2015-10-27 | 2017-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
CN113054004B (zh) * | 2021-03-11 | 2022-08-23 | 电子科技大学 | 一种应用于集成电路高低压隔离的反向电场耦合隔离结构 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
JPH05343516A (ja) * | 1992-06-05 | 1993-12-24 | Sony Corp | 素子分離構造とその製造方法 |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
JP2955459B2 (ja) * | 1993-12-20 | 1999-10-04 | 株式会社東芝 | 半導体装置の製造方法 |
WO1996002070A2 (en) * | 1994-07-12 | 1996-01-25 | National Semiconductor Corporation | Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit |
JP2762976B2 (ja) * | 1995-12-25 | 1998-06-11 | 日本電気株式会社 | 半導体装置の製造方法 |
TW434802B (en) * | 1997-10-09 | 2001-05-16 | United Microelectronics Corp | Method of manufacturing shallow trench isolation |
-
1997
- 1997-07-14 JP JP9188286A patent/JPH1131742A/ja active Pending
- 1997-11-04 TW TW086116380A patent/TW350124B/zh active
- 1997-12-12 US US08/989,941 patent/US6017800A/en not_active Expired - Fee Related
-
1998
- 1998-02-05 KR KR1019980003268A patent/KR100272986B1/ko not_active IP Right Cessation
- 1998-02-16 DE DE19806300A patent/DE19806300C2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE19806300A1 (de) | 1999-01-28 |
KR19990013309A (ko) | 1999-02-25 |
DE19806300C2 (de) | 2001-01-25 |
US6017800A (en) | 2000-01-25 |
JPH1131742A (ja) | 1999-02-02 |
KR100272986B1 (ko) | 2000-12-01 |
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