TW340243B - Manufacturing method of semiconductor elements - Google Patents
Manufacturing method of semiconductor elementsInfo
- Publication number
- TW340243B TW340243B TW086113672A TW86113672A TW340243B TW 340243 B TW340243 B TW 340243B TW 086113672 A TW086113672 A TW 086113672A TW 86113672 A TW86113672 A TW 86113672A TW 340243 B TW340243 B TW 340243B
- Authority
- TW
- Taiwan
- Prior art keywords
- manufacturing
- substrate
- semiconductor elements
- semiconductor chip
- hardened resin
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 4
- 239000011347 resin Substances 0.000 abstract 3
- 229920005989 resin Polymers 0.000 abstract 3
- 238000010348 incorporation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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- H01L2924/151—Die mounting substrate
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04025297A JP3604248B2 (ja) | 1997-02-25 | 1997-02-25 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW340243B true TW340243B (en) | 1998-09-11 |
Family
ID=12575506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086113672A TW340243B (en) | 1997-02-25 | 1997-09-20 | Manufacturing method of semiconductor elements |
Country Status (6)
Country | Link |
---|---|
US (2) | US5863815A (zh) |
EP (1) | EP0860871B1 (zh) |
JP (1) | JP3604248B2 (zh) |
KR (1) | KR100336329B1 (zh) |
CN (1) | CN1192041A (zh) |
TW (1) | TW340243B (zh) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09260533A (ja) | 1996-03-19 | 1997-10-03 | Hitachi Ltd | 半導体装置及びその実装構造 |
JP3604248B2 (ja) * | 1997-02-25 | 2004-12-22 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US6096578A (en) * | 1997-11-05 | 2000-08-01 | Texas Instruments Incorporated | Stress relief matrix for integrated circuit packaging |
JP3509507B2 (ja) * | 1997-11-10 | 2004-03-22 | 松下電器産業株式会社 | バンプ付電子部品の実装構造および実装方法 |
US6326241B1 (en) * | 1997-12-29 | 2001-12-04 | Visteon Global Technologies, Inc. | Solderless flip-chip assembly and method and material for same |
KR100247463B1 (ko) * | 1998-01-08 | 2000-03-15 | 윤종용 | 탄성중합체를 포함하는 반도체 집적회로 소자의 제조 방법 |
US6288905B1 (en) * | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
US6361146B1 (en) | 1999-06-15 | 2002-03-26 | Lexmark International, Inc. | Adhesive bonding laminates |
US6210522B1 (en) | 1999-06-15 | 2001-04-03 | Lexmark International, Inc. | Adhesive bonding laminates |
US6365977B1 (en) * | 1999-08-31 | 2002-04-02 | International Business Machines Corporation | Insulating interposer between two electronic components and process thereof |
US6090633A (en) * | 1999-09-22 | 2000-07-18 | International Business Machines Corporation | Multiple-plane pair thin-film structure and process of manufacture |
JP4405024B2 (ja) * | 2000-01-18 | 2010-01-27 | 株式会社ルネサステクノロジ | 半導体装置 |
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-
1997
- 1997-02-25 JP JP04025297A patent/JP3604248B2/ja not_active Expired - Lifetime
- 1997-09-20 TW TW086113672A patent/TW340243B/zh not_active IP Right Cessation
- 1997-10-08 US US08/940,954 patent/US5863815A/en not_active Expired - Lifetime
- 1997-10-17 EP EP97118056A patent/EP0860871B1/en not_active Expired - Lifetime
- 1997-11-03 KR KR1019970057730A patent/KR100336329B1/ko not_active IP Right Cessation
- 1997-12-31 CN CN97126243A patent/CN1192041A/zh active Pending
-
1998
- 1998-11-18 US US09/195,203 patent/US5994168A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100336329B1 (ko) | 2002-07-31 |
CN1192041A (zh) | 1998-09-02 |
US5863815A (en) | 1999-01-26 |
EP0860871A2 (en) | 1998-08-26 |
EP0860871A3 (en) | 1999-12-01 |
JP3604248B2 (ja) | 2004-12-22 |
EP0860871B1 (en) | 2011-05-25 |
US5994168A (en) | 1999-11-30 |
KR19980070074A (ko) | 1998-10-26 |
JPH10242208A (ja) | 1998-09-11 |
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