TW333626B - The data processing apparatus with hiding DRAM - Google Patents

The data processing apparatus with hiding DRAM

Info

Publication number
TW333626B
TW333626B TW086102268A TW86102268A TW333626B TW 333626 B TW333626 B TW 333626B TW 086102268 A TW086102268 A TW 086102268A TW 86102268 A TW86102268 A TW 86102268A TW 333626 B TW333626 B TW 333626B
Authority
TW
Taiwan
Prior art keywords
processing apparatus
data processing
picture memory
writing
hiding
Prior art date
Application number
TW086102268A
Other languages
English (en)
Inventor
Kazushige Yamagishi
Jun Satou
Takashi Miyamoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW333626B publication Critical patent/TW333626B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Dram (AREA)
  • Storage Device Security (AREA)
TW086102268A 1996-03-21 1997-02-25 The data processing apparatus with hiding DRAM TW333626B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/000730 WO1997035316A1 (fr) 1996-03-21 1996-03-21 Processeur a memoire dram integree

Publications (1)

Publication Number Publication Date
TW333626B true TW333626B (en) 1998-06-11

Family

ID=14153093

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086102268A TW333626B (en) 1996-03-21 1997-02-25 The data processing apparatus with hiding DRAM

Country Status (5)

Country Link
US (1) US6295074B1 (zh)
EP (1) EP0889478A4 (zh)
KR (1) KR20000064680A (zh)
TW (1) TW333626B (zh)
WO (1) WO1997035316A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118462A (en) 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
JP4314655B2 (ja) 1998-03-04 2009-08-19 ソニー株式会社 画像処理装置
JP2000011190A (ja) * 1998-06-25 2000-01-14 Sony Corp 画像処理装置
US7583270B2 (en) 1999-03-02 2009-09-01 Sony Corporation Image processing apparatus
US6864896B2 (en) * 2001-05-15 2005-03-08 Rambus Inc. Scalable unified memory architecture
JP2002366944A (ja) * 2001-06-06 2002-12-20 Sony Corp 画像処理装置
KR100494980B1 (ko) * 2002-12-02 2005-06-13 주식회사 넥서스칩스 범위선택 가능한 어드레스 디코더와 이를 이용한 고속그래픽 처리용 프레임 메모리 장치
US7668040B2 (en) * 2006-12-22 2010-02-23 Fujitsu Microelectronics Limited Memory device, memory controller and memory system

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891590A (ja) 1981-11-27 1983-05-31 Fujitsu Ltd メモリシステム
US4683555A (en) 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4725987A (en) 1985-10-23 1988-02-16 Eastman Kodak Company Architecture for a fast frame store using dynamic RAMS
US5038297A (en) * 1988-09-13 1991-08-06 Silicon Graphics, Inc. Method and apparatus for clearing a region of Z-buffer
US5148524A (en) 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporating on chip vector/image mode line modification
CA2028085A1 (en) 1989-11-03 1991-05-04 Dale J. Mayer Paged memory controller
DE68928980T2 (de) 1989-11-17 1999-08-19 Texas Instruments Inc Multiprozessor mit Koordinatenschalter zwischen Prozessoren und Speichern
JP3179788B2 (ja) 1991-01-17 2001-06-25 三菱電機株式会社 半導体記憶装置
JP3316851B2 (ja) 1991-07-08 2002-08-19 セイコーエプソン株式会社 シングル・チップ・ページ・プリンタ・コントローラ
KR950000504B1 (ko) 1992-01-31 1995-01-24 삼성전자 주식회사 복수개의 로우 어드레스 스트로브 신호를 가지는 반도체 메모리 장치
JPH05242257A (ja) 1992-02-28 1993-09-21 Hitachi Ltd 高速曲線描画用ビットマップ・メモリ
US6000027A (en) 1992-08-25 1999-12-07 Texas Instruments Incorporated Method and apparatus for improved graphics/image processing using a processor and a memory
US5572655A (en) * 1993-01-12 1996-11-05 Lsi Logic Corporation High-performance integrated bit-mapped graphics controller
JP3579461B2 (ja) 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
KR0122099B1 (ko) 1994-03-03 1997-11-26 김광호 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치
JPH07319436A (ja) * 1994-03-31 1995-12-08 Mitsubishi Electric Corp 半導体集積回路装置およびそれを用いた画像データ処理システム
US5544306A (en) * 1994-05-03 1996-08-06 Sun Microsystems, Inc. Flexible dram access in a frame buffer memory and system
JPH10502181A (ja) 1994-06-20 1998-02-24 ネオマジック・コーポレイション メモリインタフェースのないグラフィックスコントローラ集積回路
JPH08212185A (ja) 1995-01-31 1996-08-20 Mitsubishi Electric Corp マイクロコンピュータ
US6108015A (en) * 1995-11-02 2000-08-22 Cirrus Logic, Inc. Circuits, systems and methods for interfacing processing circuitry with a memory

Also Published As

Publication number Publication date
KR20000064680A (ko) 2000-11-06
EP0889478A4 (en) 2000-07-19
US6295074B1 (en) 2001-09-25
WO1997035316A1 (fr) 1997-09-25
EP0889478A1 (en) 1999-01-07

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