TW313699B - - Google Patents

Download PDF

Info

Publication number
TW313699B
TW313699B TW085113940A TW85113940A TW313699B TW 313699 B TW313699 B TW 313699B TW 085113940 A TW085113940 A TW 085113940A TW 85113940 A TW85113940 A TW 85113940A TW 313699 B TW313699 B TW 313699B
Authority
TW
Taiwan
Prior art keywords
layer
electrode layer
electrode
manufacturing
gate
Prior art date
Application number
TW085113940A
Other languages
English (en)
Chinese (zh)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW313699B publication Critical patent/TW313699B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10P10/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions

Landscapes

  • Thin Film Transistor (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
TW085113940A 1995-11-30 1996-11-14 TW313699B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19544721A DE19544721C1 (de) 1995-11-30 1995-11-30 Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor

Publications (1)

Publication Number Publication Date
TW313699B true TW313699B (enExample) 1997-08-21

Family

ID=7778860

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085113940A TW313699B (enExample) 1995-11-30 1996-11-14

Country Status (8)

Country Link
US (1) US6037196A (enExample)
EP (1) EP0864172B1 (enExample)
JP (1) JP2000501237A (enExample)
KR (1) KR100395973B1 (enExample)
AT (1) ATE206558T1 (enExample)
DE (2) DE19544721C1 (enExample)
TW (1) TW313699B (enExample)
WO (1) WO1997020336A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476904B (zh) * 2007-01-26 2015-03-11 半導體能源研究所股份有限公司 半導體裝置和其製造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333205B1 (en) * 1999-08-16 2001-12-25 Micron Technology, Inc. CMOS imager with selectively silicided gates
KR100328710B1 (ko) * 1999-08-23 2002-03-20 박종섭 인덕터 및 그의 제조방법
JP4794782B2 (ja) * 2001-09-18 2011-10-19 セイコーインスツル株式会社 電圧検出回路、及び電子機器
US6649457B2 (en) * 2001-09-24 2003-11-18 Sharp Laboratories Of America, Inc. Method for SOI device isolation
JP4193097B2 (ja) * 2002-02-18 2008-12-10 日本電気株式会社 半導体装置およびその製造方法
US6855988B2 (en) * 2002-07-08 2005-02-15 Viciciv Technology Semiconductor switching devices
DE10248723A1 (de) * 2002-10-18 2004-05-06 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Kondensatoren und mit vorzugsweise planaren Transistoren und Herstellungsverfahren
US6913959B2 (en) * 2003-06-23 2005-07-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having a MESA structure
US7202123B1 (en) 2004-07-02 2007-04-10 Advanced Micro Devices, Inc. Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123266A (ja) * 1982-12-28 1984-07-17 Toshiba Corp Ｍｉｓトランジスタ及びその製造方法
US5144390A (en) * 1988-09-02 1992-09-01 Texas Instruments Incorporated Silicon-on insulator transistor with internal body node to source node connection
JP2510710B2 (ja) * 1988-12-13 1996-06-26 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ
US5047356A (en) * 1990-02-16 1991-09-10 Hughes Aircraft Company High speed silicon-on-insulator device and process of fabricating same
US5102809A (en) * 1990-10-11 1992-04-07 Texas Instruments Incorporated SOI BICMOS process
US5177028A (en) * 1991-10-22 1993-01-05 Micron Technology, Inc. Trench isolation method having a double polysilicon gate formed on mesas

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476904B (zh) * 2007-01-26 2015-03-11 半導體能源研究所股份有限公司 半導體裝置和其製造方法

Also Published As

Publication number Publication date
WO1997020336A2 (de) 1997-06-05
EP0864172B1 (de) 2001-10-04
EP0864172A2 (de) 1998-09-16
DE19544721C1 (de) 1997-04-30
ATE206558T1 (de) 2001-10-15
JP2000501237A (ja) 2000-02-02
US6037196A (en) 2000-03-14
KR100395973B1 (ko) 2003-10-17
WO1997020336A3 (de) 1997-08-28
DE59607846D1 (de) 2001-11-08
KR19990071491A (ko) 1999-09-27

Similar Documents

Publication Publication Date Title
TW578201B (en) Semiconductor device having patterned silicon on insulator structure and method for manufacturing semiconductor device
KR101316959B1 (ko) 전기적 절연을 제공하는 방법 및 전기적 절연을 포함하는 반도체 구조물
TWI412086B (zh) 用於絕緣層上覆半導體溝渠裝置之自我對準體接點及其製造方法
TW405220B (en) Soi/bulk hybrid substrate and method of forming the same
US6225147B1 (en) Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS
US6429484B1 (en) Multiple active layer structure and a method of making such a structure
TW396498B (en) A DRAM cell and a method of fabricating an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell
JP3860672B2 (ja) トランジスタの製造方法およびその製造方法によって製造されたトランジスタ
CN101540326B (zh) 半导体元件
US10109637B1 (en) Cross couple structure for vertical transistors
TW404046B (en) Improved controllability of a buried device layer
US20060252228A1 (en) Shallow trench isolation structure having reduced dislocation density
TW441128B (en) Semiconductor device and method for producing the same
US20120187523A1 (en) Method and structure for shallow trench isolation to mitigate active shorts
TW201114036A (en) Integrated circuit structure and method for forming the same
KR20090008034A (ko) 반도체 집적 회로 장치 및 그 제조 방법
TW313699B (enExample)
JP3887267B2 (ja) Ｄｒａｍデバイス及びｄｒａｍデバイスのトランジスタ・ゲートとセル・キャパシタ・デバイスを同時に製造する方法
TW557538B (en) Method of forming side dielectrically isolated semiconductor devices and MOS semiconductor devices fabricated by this method
TWI286344B (en) Isolation spacer for thin SOI devices
TW304286B (enExample)
KR20240157043A (ko) 활성 영역을 통한 후면 전력 레일에 대한 비아
TW201005943A (en) Transistor with contact over gate active area
TW400649B (en) Semiconductor device and method for manufacturing the same
TW211081B (enExample)

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent