TW302513B - - Google Patents

Download PDF

Info

Publication number
TW302513B
TW302513B TW085108325A TW85108325A TW302513B TW 302513 B TW302513 B TW 302513B TW 085108325 A TW085108325 A TW 085108325A TW 85108325 A TW85108325 A TW 85108325A TW 302513 B TW302513 B TW 302513B
Authority
TW
Taiwan
Prior art keywords
cavity
aluminum
item
copper
patent application
Prior art date
Application number
TW085108325A
Other languages
English (en)
Chinese (zh)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW302513B publication Critical patent/TW302513B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/049—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by diffusing alloying elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
TW085108325A 1995-05-23 1996-07-10 TW302513B (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44749095A 1995-05-23 1995-05-23

Publications (1)

Publication Number Publication Date
TW302513B true TW302513B (https=) 1997-04-11

Family

ID=23776586

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085108325A TW302513B (https=) 1995-05-23 1996-07-10

Country Status (5)

Country Link
US (1) US6150252A (https=)
EP (1) EP0793268A3 (https=)
JP (1) JPH09223741A (https=)
KR (1) KR960042974A (https=)
TW (1) TW302513B (https=)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115866A (ja) * 1995-10-17 1997-05-02 Mitsubishi Electric Corp 半導体装置の製造方法
JPH09275142A (ja) * 1995-12-12 1997-10-21 Texas Instr Inc <Ti> 半導体の空隙を低温低圧で充填を行う処理方法
US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6143655A (en) 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US6121126A (en) * 1998-02-25 2000-09-19 Micron Technologies, Inc. Methods and structures for metal interconnections in integrated circuits
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
US6627539B1 (en) 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US5948467A (en) * 1998-07-24 1999-09-07 Sharp Laboratories Of America, Inc. Enhanced CVD copper adhesion by two-step deposition process
JP2000106397A (ja) * 1998-07-31 2000-04-11 Sony Corp 半導体装置における配線構造及びその形成方法
TW439204B (en) * 1998-09-18 2001-06-07 Ibm Improved-reliability damascene interconnects and process of manufacture
US6383915B1 (en) * 1999-02-03 2002-05-07 Applied Materials, Inc. Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect
US6486063B2 (en) * 2000-03-02 2002-11-26 Tokyo Electron Limited Semiconductor device manufacturing method for a copper connection
US6723634B1 (en) * 2002-03-14 2004-04-20 Advanced Micro Devices, Inc. Method of forming interconnects with improved barrier layer adhesion
US20050006770A1 (en) * 2003-07-08 2005-01-13 Valeriy Sukharev Copper-low-K dual damascene interconnect with improved reliability
US7118801B2 (en) * 2003-11-10 2006-10-10 Gore Enterprise Holdings, Inc. Aerogel/PTFE composite insulating material
US7101787B1 (en) 2004-04-09 2006-09-05 National Semiconductor Corporation System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition
US7482266B2 (en) * 2007-02-15 2009-01-27 United Microelectronics Corp. Method of forming composite opening and method of dual damascene process using the same
US7772123B2 (en) * 2008-06-06 2010-08-10 Infineon Technologies Ag Through substrate via semiconductor components
US8525343B2 (en) * 2010-09-28 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device with through-silicon via (TSV) and method of forming the same
US8901701B2 (en) * 2011-02-10 2014-12-02 Chia-Sheng Lin Chip package and fabrication method thereof
US9685366B1 (en) 2016-04-21 2017-06-20 International Business Machines Corporation Forming chamferless vias using thermally decomposable porefiller
US10998221B2 (en) * 2017-07-14 2021-05-04 Micron Technology, Inc. Semiconductor constructions having fluorocarbon material

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0199216A (ja) * 1987-10-13 1989-04-18 Fujitsu Ltd 半導体装置の製造方法
US5008216A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Process for improved contact stud structure for semiconductor devices
JP2697796B2 (ja) * 1988-11-14 1998-01-14 東京エレクトロン株式会社 半導体装置の製造方法
DE69023382T2 (de) * 1989-04-17 1996-06-20 Ibm Laminierungsverfahren zum Überdecken der Seitenwände einer Höhlung in einem Substrat sowie zur Füllung dieser Höhlung.
US5073518A (en) * 1989-11-27 1991-12-17 Micron Technology, Inc. Process to mechanically and plastically deform solid ductile metal to fill contacts of conductive channels with ductile metal and process for dry polishing excess metal from a semiconductor wafer
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
US5011793A (en) * 1990-06-19 1991-04-30 Nihon Shinku Gijutsu Kabushiki Kaisha Vacuum deposition using pressurized reflow process
CA2061119C (en) * 1991-04-19 1998-02-03 Pei-Ing P. Lee Method of depositing conductors in high aspect ratio apertures
GB9414145D0 (en) * 1994-07-13 1994-08-31 Electrotech Ltd Forming a layer
DE69233222T2 (de) * 1991-05-28 2004-08-26 Trikon Technologies Ltd., Thornbury Verfahren zum Füllen eines Hohlraumes in einem Substrat
TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
JP2718842B2 (ja) * 1991-07-17 1998-02-25 シャープ株式会社 半導体集積回路用配線金属膜の製造方法
EP0526889B1 (en) * 1991-08-06 1997-05-07 Nec Corporation Method of depositing a metal or passivation fabric with high adhesion on an insulated semiconductor substrate
US5371042A (en) * 1992-06-16 1994-12-06 Applied Materials, Inc. Method of filling contacts in semiconductor devices
US5288665A (en) * 1992-08-12 1994-02-22 Applied Materials, Inc. Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures
GB9224260D0 (en) * 1992-11-19 1993-01-06 Electrotech Ltd Forming a layer
US5356836A (en) * 1993-08-19 1994-10-18 Industrial Technology Research Institute Aluminum plug process
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer
KR960026249A (ko) * 1994-12-12 1996-07-22 윌리엄 이. 힐러 고압, 저온 반도체 갭 충진 프로세스

Also Published As

Publication number Publication date
EP0793268A2 (en) 1997-09-03
US6150252A (en) 2000-11-21
EP0793268A3 (en) 1999-03-03
JPH09223741A (ja) 1997-08-26
KR960042974A (https=) 1996-12-21

Similar Documents

Publication Publication Date Title
TW302513B (https=)
JP3330495B2 (ja) 電気的相互接続用薄膜金属バリア層
KR100386529B1 (ko) 알파 더블유 장벽층 형성 방법 및 그 구조물
US6218302B1 (en) Method for forming a semiconductor device
US4988423A (en) Method for fabricating interconnection structure
KR910007108B1 (ko) 알루미늄 또는 알루미늄 화합물로 구성된 적어도 2개의 도체층을 포함하는 반도체 집적회로 및 그 제조방법
US6790774B2 (en) Method of forming a wiring film by applying high temperature/high pressure
US5668055A (en) Method of filling of contact openings and vias by self-extrusion of overlying compressively stressed matal layer
US6607978B2 (en) Method of making a semiconductor device with alloy film between barrier metal and interconnect
US6828233B2 (en) Enhanced barrier liner formation for vias
TW201223358A (en) Method and structure to improve the conductivity of narrow copper filled vias
KR100331906B1 (ko) 반도체 장치의 제조 방법
US6093968A (en) Germanium alloy contact to a silicon substrate
EP0731503A2 (en) Semiconductor cavity filling process
JP4799715B2 (ja) 多層メタリゼーション用低温アルミニウムリフロー
US5977636A (en) Method of forming an electrically conductive contact plug, method of forming a reactive or diffusion barrier layer over a substrate, integrated circuitry, and method of forming a layer of titanium boride
US20050095828A1 (en) Process for sealing plasma-damaged, porous low-k materials
JP2000332106A (ja) 半導体装置およびその製造方法
Misawa et al. Planarized copper multilevel interconnections for ULSI applications
US20040087147A1 (en) Fast ramp anneal for hillock suppression in copper-containing structures
US20040183201A1 (en) Wiring structure for semiconductor device
US11610813B2 (en) Interconnection element and method of manufacturing the same
TW455954B (en) Manufacturing process using thermal annealing process to reduce the generation of hillock on the surface of Cu damascene structure
JP2795277B2 (ja) 半導体装置
JP2800818B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees
MM4A Annulment or lapse of patent due to non-payment of fees