TW282542B - - Google Patents

Info

Publication number
TW282542B
TW282542B TW084107138A TW84107138A TW282542B TW 282542 B TW282542 B TW 282542B TW 084107138 A TW084107138 A TW 084107138A TW 84107138 A TW84107138 A TW 84107138A TW 282542 B TW282542 B TW 282542B
Authority
TW
Taiwan
Application number
TW084107138A
Other languages
Chinese (zh)
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Application granted granted Critical
Publication of TW282542B publication Critical patent/TW282542B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
TW084107138A 1994-10-25 1995-07-10 TW282542B (en, 2012)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6260449A JPH08123717A (ja) 1994-10-25 1994-10-25 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW282542B true TW282542B (en, 2012) 1996-08-01

Family

ID=17348098

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084107138A TW282542B (en, 2012) 1994-10-25 1995-07-10

Country Status (6)

Country Link
US (1) US5646904A (en, 2012)
EP (2) EP1035478A3 (en, 2012)
JP (1) JPH08123717A (en, 2012)
KR (1) KR100356076B1 (en, 2012)
DE (1) DE69530041T2 (en, 2012)
TW (1) TW282542B (en, 2012)

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JP4146006B2 (ja) * 1998-09-28 2008-09-03 富士通株式会社 フラッシュメモリを有する電子機器
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KR20020016430A (ko) * 2000-08-25 2002-03-04 윤종용 멀티미디어 모듈러 카드와 모듈러 카드 운영장치 및통합형 멀티미디어 시스템
KR100389916B1 (ko) * 2000-08-28 2003-07-04 삼성전자주식회사 메모리 모듈 및 메모리 컨트롤러
US6928571B1 (en) 2000-09-15 2005-08-09 Intel Corporation Digital system of adjusting delays on circuit boards
JP4014801B2 (ja) * 2000-12-28 2007-11-28 株式会社ルネサステクノロジ 不揮発性メモリ装置
US6487141B2 (en) * 2001-03-15 2002-11-26 Micron Technology, Inc. Digital delay, digital phase shifter
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US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
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JP3808799B2 (ja) * 2002-05-15 2006-08-16 株式会社東芝 磁気ランダムアクセスメモリ
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US7389364B2 (en) * 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
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US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
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US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
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JP2006059046A (ja) * 2004-08-19 2006-03-02 Nec Computertechno Ltd メモリの制御方式およびメモリ制御回路
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KR100897298B1 (ko) * 2007-12-27 2009-05-14 (주)인디링스 읽기 신호 타이밍을 조정하는 플래시 메모리 장치 및플래시 메모리 장치의 읽기 제어 방법
JP2010257260A (ja) * 2009-04-24 2010-11-11 Kyocera Corp 電子機器
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
KR101217937B1 (ko) * 2010-12-30 2013-01-02 (주)인디링스 고속의 외부 메모리 인터페이스를 위한 적응적 디지털 ｐｈｙ
JP5810962B2 (ja) * 2011-03-30 2015-11-11 富士通株式会社 記憶制御装置、記憶制御方法及び記憶制御プログラム
TWI543597B (zh) * 2013-02-27 2016-07-21 晨星半導體股份有限公司 訊號取樣方法、資料加解密方法、以及使用這些方法的電子裝置
JP2015056105A (ja) 2013-09-13 2015-03-23 株式会社東芝 不揮発性半導体記憶装置
JP6500693B2 (ja) * 2015-08-19 2019-04-17 富士通株式会社 可変遅延制御回路の縮退故障診断方法および可変遅延制御回路を有するメモリコントローラ
JP6662735B2 (ja) * 2016-08-03 2020-03-11 ルネサスエレクトロニクス株式会社 半導体装置、割り当て方法及び表示システム
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US20250044827A1 (en) * 2023-08-02 2025-02-06 Xilinx, Inc. Measuring and compensating for clock tree variation
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Also Published As

Publication number Publication date
KR100356076B1 (ko) 2002-12-26
DE69530041D1 (de) 2003-04-30
EP1035478A2 (en) 2000-09-13
US5646904A (en) 1997-07-08
KR960015250A (ko) 1996-05-22
DE69530041T2 (de) 2004-01-08
EP0709786B1 (en) 2003-03-26
JPH08123717A (ja) 1996-05-17
EP0709786A1 (en) 1996-05-01
EP1035478A3 (en) 2007-04-18

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