TW282542B - - Google Patents

Info

Publication number
TW282542B
TW282542B TW84107138A TW84107138A TW282542B TW 282542 B TW282542 B TW 282542B TW 84107138 A TW84107138 A TW 84107138A TW 84107138 A TW84107138 A TW 84107138A TW 282542 B TW282542 B TW 282542B
Authority
TW
Taiwan
Application number
TW84107138A
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP6260449A priority Critical patent/JPH08123717A/ja
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Application granted granted Critical
Publication of TW282542B publication Critical patent/TW282542B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
TW84107138A 1994-10-25 1995-07-10 TW282542B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6260449A JPH08123717A (ja) 1994-10-25 1994-10-25 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW282542B true TW282542B (zh) 1996-08-01

Family

ID=17348098

Family Applications (1)

Application Number Title Priority Date Filing Date
TW84107138A TW282542B (zh) 1994-10-25 1995-07-10

Country Status (5)

Country Link
US (1) US5646904A (zh)
EP (2) EP1035478A3 (zh)
JP (1) JPH08123717A (zh)
DE (2) DE69530041T2 (zh)
TW (1) TW282542B (zh)

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JP4146006B2 (ja) * 1998-09-28 2008-09-03 富士通株式会社 フラッシュメモリを有する電子機器
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JP3542967B2 (ja) * 1998-12-15 2004-07-14 松下電器産業株式会社 クロック位相調整方法、及び集積回路とその設計方法
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US6578125B2 (en) * 2000-02-14 2003-06-10 Sanyo Electric Co., Ltd. Memory access circuit and memory access control circuit
JP2002082830A (ja) 2000-02-14 2002-03-22 Mitsubishi Electric Corp インターフェイス回路
JP3757757B2 (ja) * 2000-05-18 2006-03-22 株式会社日立製作所 リード優先メモリシステム
KR20020016430A (ko) * 2000-08-25 2002-03-04 윤종용 멀티미디어 모듈러 카드와 모듈러 카드 운영장치 및통합형 멀티미디어 시스템
KR100389916B1 (ko) * 2000-08-28 2003-07-04 삼성전자주식회사 메모리 모듈 및 메모리 컨트롤러
US6928571B1 (en) * 2000-09-15 2005-08-09 Intel Corporation Digital system of adjusting delays on circuit boards
JP4014801B2 (ja) * 2000-12-28 2007-11-28 株式会社ルネサステクノロジ 不揮発性メモリ装置
US6487141B2 (en) * 2001-03-15 2002-11-26 Micron Technology, Inc. Digital delay, digital phase shifter
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
JP3808799B2 (ja) * 2002-05-15 2006-08-16 株式会社東芝 磁気ランダムアクセスメモリ
JP2004192488A (ja) * 2002-12-13 2004-07-08 Renasas Northern Japan Semiconductor Inc データプロセッサ及びメモリカード
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7389364B2 (en) * 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
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DE102004046957B4 (de) * 2004-09-28 2016-02-04 Polaris Innovations Ltd. Verfahren und Schaltungsanordnungen zum Abgleichen von Signallaufzeiten in einem Speichersystem
DE102004047663B4 (de) * 2004-09-30 2007-07-19 Infineon Technologies Ag Speicherschaltung mit einer Initialisierungseinheit, sowie Verfahren zum Optimieren von Datenempfangsparametern in einem Speichercontroller
KR100567908B1 (ko) * 2004-12-30 2006-03-29 주식회사 하이닉스반도체 반도체 소자의 보정 회로 및 그 구동 방법
US20060184726A1 (en) * 2005-02-11 2006-08-17 Nokia Corporation Flexible access and control of Dynamic Random Access Memory
DE102005016684A1 (de) * 2005-04-11 2006-10-12 Deutsche Thomson-Brandt Gmbh Speicheranordnung, insbesondere zur nichtflüchtigen Speicherung von unkomprmierten Video-und/oder Audiodaten
US20070260778A1 (en) * 2006-04-04 2007-11-08 Ming-Shiang Lai Memory controller with bi-directional buffer for achieving high speed capability and related method thereof
TW200901042A (en) * 2007-06-23 2009-01-01 Jmicron Technology Corp Storage device and circuit element switching method thereof
KR100897298B1 (ko) * 2007-12-27 2009-05-14 (주)인디링스 읽기 신호 타이밍을 조정하는 플래시 메모리 장치 및플래시 메모리 장치의 읽기 제어 방법
JP2010257260A (ja) * 2009-04-24 2010-11-11 Kyocera Corp 電子機器
US8547736B2 (en) 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
JP5810962B2 (ja) * 2011-03-30 2015-11-11 富士通株式会社 記憶制御装置、記憶制御方法及び記憶制御プログラム
TWI543597B (zh) * 2013-02-27 2016-07-21 晨星半導體股份有限公司 訊號取樣方法、資料加解密方法、以及使用這些方法的電子裝置
JP2015056105A (ja) 2013-09-13 2015-03-23 株式会社東芝 不揮発性半導体記憶装置
JP6500693B2 (ja) * 2015-08-19 2019-04-17 富士通株式会社 可変遅延制御回路の縮退故障診断方法および可変遅延制御回路を有するメモリコントローラ
JP2018022319A (ja) * 2016-08-03 2018-02-08 ルネサスエレクトロニクス株式会社 半導体装置、割り当て方法及び表示システム

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JP2627475B2 (ja) * 1992-10-07 1997-07-09 三菱電機株式会社 半導体メモリ装置
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US5422781A (en) * 1993-12-30 1995-06-06 Intel Corporation Sense amplifier timing method and apparatus for peak power production

Also Published As

Publication number Publication date
EP1035478A3 (en) 2007-04-18
KR960015250A (ko) 1996-05-22
EP0709786B1 (en) 2003-03-26
JPH08123717A (ja) 1996-05-17
US5646904A (en) 1997-07-08
DE69530041D1 (de) 2003-04-30
DE69530041T2 (de) 2004-01-08
EP1035478A2 (en) 2000-09-13
EP0709786A1 (en) 1996-05-01

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