TW202420439A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202420439A
TW202420439A TW112143593A TW112143593A TW202420439A TW 202420439 A TW202420439 A TW 202420439A TW 112143593 A TW112143593 A TW 112143593A TW 112143593 A TW112143593 A TW 112143593A TW 202420439 A TW202420439 A TW 202420439A
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Taiwan
Prior art keywords
chip
capacitor
semiconductor
electrode pad
wire
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TW112143593A
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English (en)
Inventor
土山和晃
佃龍明
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日商瑞薩電子股份有限公司
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Publication of TW202420439A publication Critical patent/TW202420439A/zh

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Abstract

一種半導體裝置，包括：具有第一端子的基底材料；半導體晶片，具有與第一端子電連接的第一電極墊、待被提供電源電位的第二電極墊以及待被提供基準電位的第三電極墊，並且半導體晶片經由第一構件被安裝在基底材料上；晶片電容器，具有第一電極和第二電極，並且經由第二構件被安裝在半導體晶片上；第一導線，將第一電極墊與第一端子電連接；第二導線，在不穿過基底材料的情況下將第二電極墊與第一電極電連接；以及第三導線，在不穿過基底材料的情況下將第三電極墊與第二電極電連接。

Description

半導體裝置
[相關申請案的交叉引用] 於2022年11月14日提交的日本專利申請號2022-181925的公開內容（包括說明書、附圖和摘要）藉由引用以其整體併入本文。
本揭示內容涉及一種半導體裝置。
這裡，公開了下面列出的技術。
[專利文獻1]日本未審查專利申請公開號2002-184933
[專利文獻2]日本未審查專利申請公開號2011-124604
專利文獻1和專利文獻2公開了一種半導體裝置，該半導體裝置具有半導體晶片的主表面，即在其上安裝晶片電容器的電極墊形成表面。晶片電容器被提供在電源電位和基準電位之間，並且作為旁路電容器進行操作。
需要根據半導體裝置的速度的增加，來減小電源的目標阻抗（也被稱為電源阻抗）。例如，在DDR4 SDRAM（雙倍數據速率4同步動態隨機存取記憶體）中，資料傳輸速率可能高於或等於2000Mbps（百萬位元每秒），並且因此，減小電源阻抗的必要性很高。本申請案的發明人研究了一種藉由在半導體晶片上佈置旁路電容器來減小電源阻抗的方法，該旁路電容器將電源電位佈線和基準電位佈線彼此連接，如專利文獻1和專利文獻2中所示。
作為他們審閱的結果，如果將旁路電容器直接焊接到半導體晶片上（如專利文獻1的圖1中所示），覆蓋半導體晶片的主表面的保護膜（也被稱為鈍化膜）可能由於使焊接材料回流的步驟而破裂。此外，如果旁路電容器與基底材料（例如佈線襯底）連接（如專利文獻2的圖21B中所示），則電源端子與旁路電容器之間的距離變長，並且因此，可以減小電源阻抗的效果不充分。
其他目的和新穎特徵將從本說明書的描述和附圖變得明顯。
根據一個實施例的半導體裝置包括：具有第一端子的基底材料；半導體晶片，具有與第一端子電連接的第一電極墊、待被提供電源電位的第二電極墊以及待被提供基準電位的第三電極墊，並且半導體晶片經由第一構件被安裝在基底材料上；晶片電容器，具有第一電極和第二電極，並且經由第二構件被安裝在半導體晶片上；第一導線，將第一電極墊與第一端子電連接；第二導線，在不穿過基底材料的情況下將第二電極墊與第一電極電連接；第三導線，在不穿過基底材料的情況下將第三電極墊與第二電極電連接；以及樹脂密封體，將半導體晶片、晶片電容器、第一導線、第二導線和第三導線密封。此外，第二導線和第三導線中的每個導線的長度比第一導線的長度短。
根據上述實施例，可以減小電源阻抗，同時防止在半導體晶片的保護膜中出現裂紋。
為了說明清楚，以下描述和附圖被適當省略和簡化。此外，圖中被描述為用於執行各種過程的功能塊的元件，在硬體方面可以被配置為CPU（中央處理單元）、記憶體和其他電路，並且在軟體方面可以藉由載入到記憶體中的程式來進行實現。因此，本領域技術人員應當理解，這些功能塊可以藉由單獨的硬體、單獨的軟體或它們的組合以各種形式來進行實現，並且本發明不限於其中的任何一種。在圖中，相同的元件由相同的附圖標記表示，並且根據需要省略其重複描述。 [01] （第一實施例）
圖1是從上方觀察的根據第一實施例的半導體裝置1的上表面視圖。由於半導體裝置1被樹脂密封體17密封，所以半導體晶片12等實際上從上方不可見。圖2是示意性示出了沿圖1中的A-A’線的截面的概念圖。雖然它是截面圖，但為了清楚起見省略了影線。
如圖2中所示，半導體裝置1包括基底材料11、半導體晶片12、晶片電容器13、第一導線14、第二導線15、第三導線16和樹脂密封體17。
基底材料11是其上安裝半導體晶片12的半導體封裝襯底。雖然圖1和圖2示出了基底材料11是BGA（球柵陣列）襯底，但基底材料11可以是引線框架。
如圖2中所示，電連接到半導體晶片12的第一端子T1被佈置在基底材料11的上表面上。第一端子T1包括例如用於向半導體晶片12提供電源（例如，電源電位或基準電位）的端子、用於向半導體晶片12輸入電信號的端子、或者用於向半導體晶片12輸出電信號的端子。如圖2中所示，第二端子T2被佈置在基底材料11的下表面上，第二端子T2經由在上表面與下表面之間設置的導線電連接到第一端子T1。電連接到外部襯底的外部連接端子（例如，焊球）形成在第二端子T2上。
如圖2中所示，半導體晶片12經由第一構件21被安裝在基底材料11上。在本第一實施例中，第一構件21例如是晶粒附接膜（DAF）。半導體晶片12可以是處理高頻信號的半導體晶片。處理高頻信號的半導體晶片例如是具有高資料傳輸速率的DRAM晶片（例如，2000Mbps或更高），或者是與DRAM晶片通信的邏輯晶片。
半導體裝置1可以是包括多個半導體晶片的SiP（系統級封裝）。多個半導體晶片可以被並排佈置或者被垂直堆疊。注意，用作旁路電容器的晶片電容器13不需要被安裝在所有半導體晶片上。
半導體晶片12包括多個電極墊PD。在本第一實施例中，多個電極墊PD沿著半導體晶片12的相應邊進行佈置，如圖1中所示。多個電極墊PD可以沿著半導體晶片12的相應邊進行佈置，並且被佈置在多個列之上。參考圖2，除了佈置電極墊PD的區域之外的區域被保護膜121覆蓋。保護膜121（也被稱為鈍化膜）可以包括例如氧化矽膜和聚醯亞胺膜。
多個電極墊PD包括第一電極墊P1、第二電極墊P2和第三電極墊P3。
第一電極墊P1電連接到第一端子T1。可以經由第一電極墊P1從半導體晶片12輸入電信號，或者可以將電信號輸出到半導體晶片12，或者可以經由第一電極墊P1向半導體晶片12提供電源。
電源電位被提供給第二電極墊P2。第二電極墊P2可以電連接到在半導體晶片12中設置的電源電位線。
基準電位被提供給第三電極墊P3。第三電極墊P3可以電連接到在半導體晶片12中設置的基準電位線。
如上所述，多個電極墊PD可以沿著半導體晶片12的每一側而設置，並且以多個列進行設置。這裡，第二電極墊P2和第三電極墊P3可以被佈置在以下列中，該列是多個列之中的、位於半導體晶片最內側的列。因此，如圖1中所示，當晶片電容器13被佈置在由半導體晶片12的表面上的多個電極墊PD圍繞的區域中時，稍後描述的第二導線15和第三導線16中的每個導線的長度可以比稍後描述的第一導線14的長度減小得多。這裡，第一電極墊P1可以被佈置在外列中。第二電極墊P2和第三電極墊P3中的一個電極墊可以被佈置在內列中，並且另一個可以被佈置在外列中。
如圖2中所示，晶片電容器13經由第二構件22被安裝在半導體晶片12上。在本第一實施例中，第二構件22例如是晶粒附接膜（DAF）。晶片電容器13包括第一電極131和第二電極132。晶片電容器13用作所謂的旁路電容器。晶片電容器13的數目可以是多個（例如6個）。
注意，第一構件21和第二構件22不限於晶粒附接膜。第一構件21和第二構件22可以是黏合劑或絕緣膏。然而，在從施加膏劑到固化膏劑的時段期間，膏劑的形狀比晶粒附接膜更容易變形。因此，為了減少第二導線15和第三導線16中的每個導線的長度，在將晶片電容器13佈置在每個電極墊P2、P3附近時，優選使用晶粒附接膜而不是膏劑。
第一導線14將第一電極墊P1與第一端子T1電連接。因此，基底材料11和半導體晶片12彼此電連接。第一導線14的金屬材料沒有特別限制，但例如是金、銅、鋁等。
在不穿過基底材料11的情況下，第二導線15將第二電極墊P2與第一電極131電連接。第二導線15的金屬材料沒有特別限制，但例如是金、銅、鋁等。
在不穿過基底材料11的情況下，第三導線16將第三電極墊P3與第二電極132電連接。第二導線15和第三導線16的金屬材料沒有特別限制，但例如是金、銅、鋁等。
藉由第二導線15和第三導線16，晶片電容器13用作旁路電容器。晶片電容器13用於減少電源雜訊和穩定電源電位。
樹脂密封體17將半導體晶片12、晶片電容器13、第一導線14、第二導線15和第三導線16密封。
如圖1和圖2中所示，在不穿過基底材料11的情況下，第二導線15和第三導線16中的每個導線將晶片電容器13與半導體晶片12電連接。即，在本第一實施例中，在不穿過基底材料11的情況下，從晶片電容器13向半導體晶片12提供（傳輸）電源電位和基準電位中的每個電位。此外，藉由將晶片電容器13安裝在半導體晶片12上，可以使第二導線15和第三導線16中的每個導線的長度短於將基底材料11和半導體晶片12彼此電連接的第一導線14的長度。因此，可以減少第二導線15和第三導線16中的每個導線的長度，並且可以減小電源阻抗。即，可以減小從晶片電容器13到半導體晶片12的電源電位和基準電位的每個供給路徑（傳輸路徑）中的電源阻抗。此外，由於晶片電容器13未被直接焊接到半導體晶片12，因此可以防止保護膜121中出現裂紋。
現在參考圖3和圖4，將描述製造根據第一實施例的半導體裝置1的方法。圖3是說明了製造根據相關技術的半導體裝置的方法的視圖。圖4是說明了製造根據第一實施例的半導體裝置的方法的視圖。
參考圖3，在製造相關半導體裝置的方法中，將晶片電容器13焊接到基底材料11上，在基底材料11上，藉由回流在最高上表面（也被稱為頂表面）處形成電源電位佈線（也被稱為電源電位的佈線圖案）和基準電位佈線（也被稱為基準電位的佈線圖案）（步驟S101）。溫度條件被設置為例如200℃至250℃。附圖標記S表示焊料。
接下來，藉由晶粒接合，經由第一構件21將半導體晶片12安裝在基底材料11上（步驟S102）。溫度條件被設置為例如100℃至200℃。
接下來，藉由導線接合，將半導體晶片12和基底材料11彼此電連接（步驟S103）。
在相關技術中，由於半導體晶片12與晶片電容器13之間的距離較大，所以存在電源阻抗較大的問題。此外，當晶片電容器13被安裝在半導體晶片12外部時，減少了基底材料11的佈線資源。即，當多個晶片電容器13被安裝在基底材料11上時，基底材料11的最上面的上表面需要用於對電源電位佈線和基準電位佈線進行路由。在該情況下，需要增加基底材料11的佈線層的數目，例如需要將基底材料11的佈線層的數目從兩層增加到四層。
還可以想到將晶片電容器13回流焊接在半導體晶片12上的方法。然而，在該情況下，由於回流溫度，可能在半導體晶片12的保護膜121中產生應力，並且可能在保護膜121中產生裂紋。
參考圖4，在製造根據第一實施例的半導體裝置的方法中，首先，藉由晶粒接合，經由第一構件21將半導體晶片12安裝在基底材料11上（步驟S201）。溫度條件被設置為例如100℃至200℃。
接下來，藉由晶粒接合，經由第二構件22將晶片電容器13安裝在半導體晶片12上（步驟S202）。溫度條件被設置為例如100℃至200℃。
接下來，藉由導線接合，將半導體晶片12和基底材料11彼此電連接，並且將半導體晶片12和晶片電容器13彼此電連接（步驟S203）。然後，利用樹脂密封體來密封半導體晶片12等。
在第一實施例中，需要步驟S202，但是具有不需要增加基底材料11的互連層的數目的優點。與相關技術相比，第一實施例可以是成本高效的。
根據第一實施例，可以減小電源阻抗，同時防止半導體晶片12的保護膜中出現裂紋。此外，第一實施例可以防止基底材料11被損壞，並且可以減少製造成本。 [02] （第二實施例）
第二實施例是第一實施例的具體示例。根據第二實施例的半導體裝置是SiP（系統級封裝），在該SiP中，DRAM（動態隨機存取記憶體）晶片32和控制DRAM晶片32的邏輯晶片31被密封在一個封裝中。注意，晶片電容器13可以不被安裝在記憶體晶片和邏輯晶片兩者上。
邏輯晶片31包括與DRAM晶片32通信的記憶體控制器。邏輯晶片31可以是所謂的SoC（片上系統），其中多個功能被形成到一個晶片中。
圖5是說明了根據第二實施例的半導體裝置1a的電路配置的圖。如稍後將描述的，所有旁路電容器C1、C2、C3和C4不需要作為晶片電容器13被安裝在邏輯晶片31或DRAM晶片32上。
半導體裝置1a包括邏輯晶片31和DRAM晶片32。DRAM晶片32具有DDR_SDRAM。
邏輯晶片31包括CPU 311和信號驅動器D。CPU 311被設置在核心系統電源電位VDD和基準電位VSS之間。信號驅動器D被設置在DDR系統電源電位VDDQ（也被稱為DDR_VDDQ）和DDR系統基準電位VSSQ（也被稱為DDR_VSSQ）之間。核心系統電源電位VDD、基準電位VSS、DDR系統電源電位VDDQ和DDR系統基準電位VSSQ可以從上面描述的基底材料11的第一端子T1而提供。此外，如圖5中所示，在用於將邏輯晶片31和DRAM晶片32彼此電連接的路徑中，基準電位VSS和DDR系統基準電位VSSQ可以彼此共用。
DRAM晶片32包括記憶體單元（未示出）和輸入/輸出電路（未示出）。輸入/輸出電路被設置在DDR系統電源電位VDDQ和DDR系統基準電位VSSQ之間。輸入/輸出電路回應於從信號驅動器D接收到控制信號，而從記憶體單元讀取資料並且將資料寫入到記憶體單元。
附圖標記41表示DDR系統電源。旁路電容器C1和旁路電容器C2中的每個旁路電容器被耦合到用於將DDR系統電源41提供到邏輯晶片31的路徑。每個旁路電容器C1、C2被配置成減小從邏輯晶片31所見的電源阻抗。旁路電容器C1是減小高頻範圍內的電源阻抗的小電容電容器。旁路電容器C2是減小低頻範圍內的電源阻抗的大電容電容器。
藉由將旁路電容器C1和C2中的至少一個旁路電容器作為晶片電容器13安裝在邏輯晶片31上，可以減小從邏輯晶片31所見的DDR電源41的電源阻抗。
構成信號驅動器D的電晶體比構成CPU 311的電晶體消耗更大的驅動電流。此外，存在多個信號驅動器D經由平行匯流排介面同時操作的可能性。因此，減小高頻範圍內的電源阻抗的旁路電容器C1特別關鍵，因為瞬態電流會生成較大的電源雜訊。因此，旁路電容器C1和C2之中的旁路電容器C1優選作為晶片電容器13被安裝在邏輯晶片31上。應當注意，DRAM晶片32的資料傳輸速率越高，越需要降低電源阻抗。因此，當旁路電容器C1被安裝在邏輯晶片31上時，可以如相關技術中那樣將減小低頻範圍中的電源阻抗的旁路電容器C2安裝在基底材料11上。此外，如果第二導線15和第三導線16中的每個導線的長度與將邏輯晶片31和基底材料11電連接的第一導線14的長度相同，則旁路電容器C1、C2可以被安裝在基底材料11上。
旁路電容器C3連接到用於將DDR系統電源41提供到DRAM晶片32的路徑。旁路電容器C3減小從DRAM晶片32所見的電源阻抗。旁路電容器C3更可以包括用於去除高頻範圍內的雜訊的小電容電容器、以及用於去除低頻範圍內的雜訊的大電容電容器。
藉由將旁路電容器C3作為晶片電容器13安裝在DRAM晶片32上，可以減小從DRAM晶片32所見的DDR電源41的電源阻抗。
附圖標記42表示核心電源。核心電源42的負極側上的符號未被示出。旁路電容器C4連接到用於將核心系統電源42提供到邏輯晶片31的路徑。旁路電容器C4降低從邏輯晶片31所見的核心系統電源42的電源阻抗。
藉由將旁路電容器C4作為晶片電容器13安裝在邏輯晶片31上，可以減小核心系統電源42的電源阻抗。然而，如果CPU 311的消耗電流隨著核心系統電源42的電源阻抗變得更成問題而變大，則邏輯晶片31和基底材料11由於散熱或IR下降而未藉由導線連接的可能性更高。在該情況下，邏輯晶片31可以是安裝的倒裝晶片。
如上所述，旁路電容器C1優選作為晶片電容器13被安裝在邏輯晶片31上。旁路電容器C1的第一電極和第二電極分別電連接到邏輯晶片31的第二電極墊P2和第三電極墊P3。這裡，旁路電容器C2、C3和C4可以如相關技術中那樣被安裝在基底材料11上。當在邏輯晶片31的正面上存在可以安裝除了旁路電容器C1之外的旁路電容器的區域時，減小從邏輯晶片31所見的電源阻抗的旁路電容器C2也可以被安裝在邏輯晶片31上，與旁路電容器C1相同。
接下來，將描述根據第二實施例的半導體裝置1a的示例性配置。圖6是從上方觀察的半導體裝置1a的上表面視圖。圖7是沿圖6中的B-B’線的截面圖。在圖6和圖7中，省略了對第一構件和第二構件的圖示。
圖6和圖7示出了晶片電容器13被安裝在邏輯晶片31上的情況。邏輯晶片31對應於根據第一實施例的半導體晶片12。邏輯晶片31和DRAM晶片32被垂直堆疊。注意，邏輯晶片31可以被堆疊在DRAM晶片32上，並且DRAM晶片32可以被堆疊在邏輯晶片31上。
DRAM晶片32經由第一構件（未示出）被安裝在作為引線框架的基底材料11上。當基底材料11是引線框架時，存在電源阻抗比在基底材料11是BGA時更高的問題。邏輯晶片31經由第一構件（未示出）被安裝在DRAM晶片32上。
邏輯晶片31和DRAM晶片32具有上述第一電極墊P1。第一電極墊P1是經由第一導線14連接到第一端子T1的電極墊。第一電極墊P1可以是用於輸入和輸出信號的電極墊，或者可以是被提供電源（例如，DDR系統電源的電源電位）的電極墊。
邏輯晶片31包括上面描述的第二電極墊P2和第三電極墊P3。第二電極墊P2是經由第二導線15連接到晶片電容器13的第一電極P1的電極墊。第三電極墊P3是經由第三導線16連接到晶片電容器13的第二電極的電極墊。
再分佈層RDL（Redistribution layer）形成在DRAM晶片32上。可以經由第一導線14、再分佈層RDL和導線51，從基底材料11向邏輯晶片31提供DDR電源。第一導線14是將基底材料11和DRAM晶片32彼此電連接的導線。導線51是將邏輯晶片31和DRAM晶片32彼此電連接的導線。除了提供電源電位和基準電位的導線之外，第一導線14和導線51中的每個導線更可以包括傳送信號的導線。當邏輯晶片31和DRAM晶片32被垂直堆疊時，可以減小導線51的長度。
晶片電容器13可以是減小高頻範圍內的電源阻抗的旁路電容器C1。這裡，用於減小低頻範圍內的電源阻抗的旁路電容器C2可以如相關技術那樣被安裝在基底材料11上。此外，當邏輯晶片31的表面上存在可以安裝除旁路電容器C1以外的旁路電容器的區域時，也可以在邏輯晶片31上安裝減小低頻區域中的電源阻抗的旁路電容器C2。
DRAM晶片32更可以被設置有用作旁路電容器C3的晶片電容器13。在該情況下，可以減小從邏輯晶片31所見的電源阻抗和從DRAM晶片32所見的電源阻抗兩者。這裡，邏輯晶片31和DRAM晶片32中的每個晶片對應於根據第一實施例的半導體晶片12。
圖8是說明了參考圖6和圖7描述的配置的修改示例的視圖。參考圖8，晶片電容器18被安裝在作為引線框架的基底材料11上。安裝在半導體晶片12上的晶片電容器13也被稱為第一晶片電容器13，並且安裝在基底材料11上的晶片電容器18也被稱為第二晶片電容器18。
第二晶片電容器18被設置在向DRAM晶片32提供的DDR系統電源電位VDDQ與基準電位VSS之間。結果，第二晶片電容器18用作旁路電容器C3。
DRAM晶片32具有連接到DDR系統電源電位VDDQ的電極墊，並且具有連接到基準電位VSS的電極墊。第二晶片電容器18電連接到DRAM晶片32的兩個電極墊。導線52是將第二晶片電容器18和DRAM晶片32連接的導線。導線52可以比上面描述的第二導線15和第三導線16長，但與相關技術相比，具有減小電源阻抗的效果。
在其中安裝第一晶片電容器13的區域，可以不被固定在邏輯晶片31下方所設置的DRAM晶片32上。在該實施例中，第二晶片電容器18被設置在基底材料11上，使得可以減小從DRAM晶片32所見的電源阻抗。
此外，邏輯晶片31和DRAM晶片32可以被並排佈置。圖9示出了邏輯晶片31和DRAM晶片32被並排佈置的配置，並且晶片電容器13被安裝在邏輯晶片31上。晶片電容器13可以被安裝在DRAM晶片32上。第一導線14可以包括連接到晶粒墊的導線（例如，連接到基準電位的導線）。 [03] （第三實施例）
第三實施例是第二實施例的修改示例。根據第三實施例的半導體裝置1b包括多個DRAM晶片32。圖10是說明了根據第三實施例的半導體裝置1b的圖。在圖10中，省略了對基底材料11、第一構件、第二構件等中的每一者的圖示。
半導體裝置1b包括邏輯晶片31、間隔器構件33、DRAM晶片321和DRAM晶片322。DRAM晶片32的數目不限於兩個，並且可以是三個或更多個。注意，邏輯晶片31可以被設置在DRAM晶片321和322上，或者可以被設置在DRAM晶片321和322下方。
SoC 31被安裝在襯底（未示出）上。間隔器構件33被安裝在邏輯晶片31上。結果，在其中安裝晶片電容器13的區域可以被固定在邏輯晶片31上。間隔器構件33可以是例如虛設矽晶片。
DRAM晶片321被安裝在間隔器構件33上，並且DRAM晶片322被安裝在DRAM晶片321上。可以使用黏合膜（例如，晶粒附接膜）或黏合劑來堆疊DRAM晶片321和322。
晶片電容器13被安裝在邏輯晶片31、DRAM晶片321和DRAM晶片322中的每個晶片上。DRAM晶片321連接到安裝在DRAM晶片321上的晶片電容器13，並且DRAM晶片322連接到安裝在DRAM晶片322上的晶片電容器13。結果，可以減小從DRAM晶片321和DRAM晶片322中的每個DRAM晶片所見的電源阻抗。
邏輯晶片31、DRAM晶片321和DRAM晶片322中的每個晶片具有第二電極墊和第三電極墊（未示出）。第二導線15將晶片電容器13和第二電極墊電連接。第三導線（未示出）將晶片電容器13和第三電極墊電連接。
半導體裝置1b包括將邏輯晶片31和DRAM晶片321電連接的導線51，並且包括將邏輯晶片31和DRAM晶片322電連接的導線51。導線51可以包括提供電源電位和基準電位的導線，並且控制信號和資料可以經由導線51進行交換。
除了晶片電容器13，用於改善信號品質的終端電阻器可以被安裝在DRAM晶片322上。終端電阻器的一端可以電連接到導線51，並且終端電阻器的另一端可以連接到基準電位、電源電位或信號。
在第三實施例中，由於針對每個DRAM晶片設置了旁路電容器，所以可以減小每個DRAM晶片的電源阻抗。
儘管已經基於實施例具體描述了由本發明人做出的發明，但是本發明不限於上述實施例，並且不用說，在不偏離其要點的情況下可以進行各種修改。
例如，在根據上述實施例的分壓電路中，可以採用其中諸如半導體襯底、半導體層或擴散層（擴散區域）的導電類型（p型或n型）被反轉的配置。因此，在n型或p型的導電類型中的一種導電類型是第一導電類型並且另一種導電類型是第二導電類型的情況下，第一導電類型可以是p型，第二導電類型可以是n型，或者相反，第一導電類型可以是n型，第二導電類型可以是p型。
在上述實施例中，晶片電容器13經由晶粒附接膜22被安裝在半導體晶片12上。然而，如圖11中所示，另一個BGA襯底61可以被安裝在佈置在半導體晶片12上的晶粒附接膜22上，並且晶片電容器13可以經由焊接材料62被安裝在另一個BGA襯底61上。
在圖11中所示的配置中，晶片電容器13的相應電極131和132與BGA襯底61的相應導線（端子）611經由焊接材料62彼此電連接，但是由於不僅晶粒附接膜22而且另一個BGA襯底61被插置在晶片電容器13和半導體晶片12之間，因此可以抑制在半導體晶片12的表面（上表面）上形成的保護膜121中出現上述裂紋。
此外，為了可靠地抑制裂紋，優選的是，要使用的另一個BGA襯底61或晶粒附接膜22的厚度相對較大。然而，如果另一個BGA襯底61或晶粒附接膜22的厚度太大，則將另一個BGA襯底61的導線（端子）611和半導體晶片12的電極墊P2、P3彼此電連接的導線的長度變長。即，從晶片電容器13到半導體晶片12的電源電位和基準電位的供給路徑（傳輸路徑）的長度變得更長。此外，與例如上面描述的第一實施例相比，在使用另一個BGA襯底61或焊接材料62的情況下，半導體裝置的製造步驟的數目增加。因此，當在減少半導體裝置的製造成本時，從晶片電容器13到半導體晶片12的電源電位和基準電位中的每個電位的供給路徑（傳輸路徑）中的電源阻抗也減小時，優選不使用如上述實施例中的另一個BGA襯底61。
1, 1a, 1b:半導體裝置 11:基底材料 12:半導體晶片 121:保護膜 13:晶片電容器 131:第一電極 132:第二電極 14:第一導線 15:第二導線 16:第三導線 17:樹脂密封體 18:晶片電容器 21:第一構件 22:第二構件 31:邏輯晶片 311:CPU 32, 321, 322:DRAM晶片 41:DDR系統電源 42:核心系統電源 51, 52:導線 61:BGA襯底 611:導線 62:焊接材料 T1:第一端子 T2:第二端子 P1:第一電極墊 P2:第二電極墊 P3:第三電極墊 PD:電極墊 S:焊料 C1, C2, C3, C4:旁路電容器 VDD:核心系統電源電位 VDDQ:DDR系統電源電位 VSS:基準電位 D:信號驅動器
圖1是根據第一實施例的半導體裝置的上表面視圖。
圖2是示意性示出了沿圖1中的A-A’線的截面的概念圖。
圖3是說明了製造根據相關技術的半導體裝置的方法的圖。
圖4是說明了製造根據第一實施例的半導體裝置的方法的圖。
圖5是說明了根據第二實施例的半導體裝置的電路配置的圖。
圖6是根據第二實施例的半導體裝置的上表面視圖。
圖7是示意性示出了沿圖6中的B-B’線的截面的概念圖。
圖8是說明了根據第二實施例的半導體裝置的修改示例的圖。
圖9是說明了根據第二實施例的半導體裝置的修改示例的圖。
圖10是說明了根據第三實施例的半導體裝置的圖。
圖11是說明了根據每個實施例的半導體裝置的修改示例的圖。
1:半導體裝置
11:基底材料
12:半導體晶片
121:保護膜
13:晶片電容器
14:第一導線
15:第二導線
17:樹脂密封體
21:第一構件
22:第二構件
T1:第一端子
T2:第二端子
P1:第一電極墊
P2:第二電極墊
PD:電極墊

Claims (10)

  1. 一種半導體裝置，包括： 基底材料，具有第一端子； 半導體晶片，其具有與該第一端子電連接的第一電極墊、待被提供電源電位的第二電極墊、以及待被提供基準電位的第三電極墊，並且該半導體晶片經由第一構件被安裝在該基底材料上； 晶片電容器，具有第一電極和第二電極，並且經由第二構件被安裝在該半導體晶片上； 第一導線，將該第一電極墊與該第一端子電連接； 第二導線，在不穿過該基底材料的情況下，將該第二電極墊與該第一電極電連接； 第三導線，在不穿過該基底材料的情況下，將該第三電極墊與該第二電極電連接；以及 樹脂密封體，將該半導體晶片、該晶片電容器、該第一導線、該第二導線和該第三導線密封， 其中該第二導線和該第三導線中的每一者的長度比該第一導線的長度更短。
  2. 如請求項1的半導體裝置，更包括： DRAM晶片；以及 邏輯晶片，控制該DRAM晶片， 其中該DRAM晶片和該邏輯晶片中的至少一者被設置為該半導體晶片，該半導體晶片具有在其上安裝該晶片電容器的表面。
  3. 如請求項2的半導體裝置， 其中該DRAM晶片和該邏輯晶片其中一者被設置為具有在其上安裝該晶片電容器的該表面的該半導體晶片，並且 其中該DRAM晶片和該邏輯晶片其中另一者被設置為另一半導體晶片，該另一半導體晶片具有在其上安裝另一晶片電容器的表面。
  4. 如請求項2的半導體裝置， 其中該邏輯晶片被設置為具有在其上安裝該晶片電容器的該表面的該半導體晶片， 其中安裝在該邏輯晶片上的該晶片電容器被配置成：減小從該邏輯晶片所見在高頻範圍中的電源阻抗，並且 其中安裝在該基底材料上的另一晶片電容器被配置成：減小從該邏輯晶片所見在低頻範圍中的電源阻抗。
  5. 如請求項2的半導體裝置， 其中該DRAM晶片和該邏輯晶片中的一半導體晶片被堆疊在該DRAM晶片和該邏輯晶片中的另一半導體晶片上， 其中該一半導體晶片被設置為具有在其上安裝該晶片電容器的該表面的該半導體晶片，並且 其中該另一半導體晶片與安裝在該基底材料上的另一晶片電容器耦合。
  6. 如請求項2的半導體裝置，更包括： 堆疊的多個DRAM晶片， 其中該晶片電容器被安裝在每個DRAM晶片上。
  7. 如請求項1的半導體裝置， 其中，在平面圖中，包括該第一電極墊、該第二電極墊和該第三電極墊的多個電極墊，沿著該半導體晶片的每一側而佈置，並且被佈置成多個列，並且 其中該第二電極墊和該第三電極墊中每一者被佈置在第一列中，在平面圖中，該第一列是該多個列之中位於該半導體晶片最內側的列。
  8. 如請求項2的半導體裝置，其中該DRAM晶片的資料傳輸速率是2000Mbps或更大。
  9. 如請求項1的半導體裝置，其中該第二構件是晶粒附接膜。
  10. 如請求項1的半導體裝置， 其中該電源電位將從該晶片電容器被提供到該半導體晶片，而不穿過該基底材料，並且 其中該基準電位將從該晶片電容器被提供到該半導體晶片，而不穿過該基底材料。
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