CN118039613A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN118039613A
CN118039613A CN202311326519.4A CN202311326519A CN118039613A CN 118039613 A CN118039613 A CN 118039613A CN 202311326519 A CN202311326519 A CN 202311326519A CN 118039613 A CN118039613 A CN 118039613A
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China
Prior art keywords
chip
semiconductor
capacitor
electrode pad
base material
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Pending
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CN202311326519.4A
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English (en)
Inventor
土山和晃
佃龙明
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN118039613A publication Critical patent/CN118039613A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract

一种半导体器件，包括：具有第一端子的基底材料；半导体芯片，具有与第一端子电连接的第一电极垫、要被提供电源电位的第二电极垫以及要被提供基准电位的第三电极垫，并且半导体芯片经由第一构件被安装在基底材料上；芯片电容器，具有第一电极和第二电极，并且经由第二构件被安装在半导体芯片上；第一导线，将第一电极垫与第一端子电连接；第二导线，在不穿过基底材料的情况下将第二电极垫与第一电极电连接；以及第三导线，在不穿过基底材料的情况下将第三电极垫与第二电极电连接。

Description

半导体器件
相关申请的交叉引用
于2022年11月14日提交的日本专利申请号2022-181925的公开内容(包括说明书、附图和摘要)通过引用以其整体并入本文。
技术领域
本公开涉及一种半导体器件。
背景技术
这里，公开了下面列出的技术。
[专利文献1]日本未审查专利申请公开号2002-184933
[专利文献2]日本未审查专利申请公开号2011-124604
专利文献1和专利文献2公开了一种半导体器件，该半导体器件具有半导体芯片的主表面，即在其上安装芯片电容器的电极垫形成表面。芯片电容器被提供在电源电位和基准电位之间，并且作为旁路电容器进行操作。
发明内容
需要根据半导体器件的速度的增加，来减小电源的目标阻抗(也被称为电源阻抗)。例如，在DDR4 SDRAM(双倍数据速率4同步动态随机存取存储器)中，数据传输速率可能高于或等于2000Mbps(兆位每秒)，并且因此，减小电源阻抗的必要性很高。本申请的发明人研究了一种通过在半导体芯片上布置旁路电容器来减小电源阻抗的方法，该旁路电容器将电源电位布线和基准电位布线彼此连接，如专利文献1和专利文献2中所示。
作为他们审阅的结果，如果将旁路电容器直接焊接到半导体芯片上(如专利文献1的图1中所示)，覆盖半导体芯片的主表面的保护膜(也被称为钝化膜)可能由于使焊接材料回流的步骤而破裂。此外，如果旁路电容器与基底材料(例如布线衬底)连接(如专利文献2的图21B中所示)，则电源端子与旁路电容器之间的距离变长，并且因此，可以减小电源阻抗的效果不充分。
其他目的和新颖特征将从本说明书的描述和附图变得明显。
根据一个实施例的半导体器件包括：具有第一端子的基底材料；半导体芯片，具有与第一端子电连接的第一电极垫、要被提供电源电位的第二电极垫以及要被提供基准电位的第三电极垫，并且半导体芯片经由第一构件被安装在基底材料上；芯片电容器，具有第一电极和第二电极，并且经由第二构件被安装在半导体芯片上；第一导线，将第一电极垫与第一端子电连接；第二导线，在不穿过基底材料的情况下将第二电极垫与第一电极电连接；第三导线，在不穿过基底材料的情况下将第三电极垫与第二电极电连接；以及树脂密封体，将半导体芯片、芯片电容器、第一导线、第二导线和第三导线密封。此外，第二导线和第三导线中的每个导线的长度比第一导线的长度短。
根据上述实施例，可以减小电源阻抗，同时防止在半导体芯片的保护膜中出现裂纹。
附图说明
图1是根据第一实施例的半导体器件的上表面视图。
图2是示意性示出了沿图1中的A-A’线的截面的概念图。
图3是说明了制造根据相关技术的半导体器件的方法的图。
图4是说明了制造根据第一实施例的半导体器件的方法的图。
图5是说明了根据第二实施例的半导体器件的电路配置的图。
图6是根据第二实施例的半导体器件的上表面视图。
图7是示意性示出了沿图6中的B-B’线的截面的概念图。
图8是说明了根据第二实施例的半导体器件的修改示例的图。
图9是说明了根据第二实施例的半导体器件的修改示例的图。
图10是说明了根据第三实施例的半导体器件的图。
图11是说明了根据每个实施例的半导体器件的修改示例的图。
具体实施方式
为了说明清楚，以下描述和附图被适当省略和简化。此外，图中被描述为用于执行各种过程的功能块的元件，在硬件方面可以被配置为CPU(中央处理单元)、存储器和其他电路，并且在软件方面可以通过加载到存储器中的程序来进行实现。因此，本领域技术人员应当理解，这些功能块可以通过单独的硬件、单独的软件或它们的组合以各种形式来进行实现，并且本发明不限于其中的任何一种。在图中，相同的元件由相同的附图标记表示，并且根据需要省略其重复描述。
(第一实施例)
图1是从上方观察的根据第一实施例的半导体器件1的上表面视图。由于半导体器件1被树脂密封体17密封，所以半导体芯片12等实际上从上方不可见。图2是示意性示出了沿图1中的A-A’线的截面的概念图。虽然它是截面图，但为了清楚起见省略了影线。
如图2中所示，半导体器件1包括基底材料11、半导体芯片12、芯片电容器13、第一导线14、第二导线15、第三导线16和树脂密封体17。
基底材料11是其上安装半导体芯片12的半导体封装衬底。虽然图1和图2示出了基底材料11是BGA(球栅阵列)衬底，但基底材料11可以是引线框架。
如图2中所示，电连接到半导体芯片12的第一端子T1被布置在基底材料11的上表面上。第一端子T1包括例如用于向半导体芯片12提供电源(例如，电源电位或基准电位)的端子、用于向半导体芯片12输入电信号的端子、或者用于向半导体芯片12输出电信号的端子。如图2中所示，第二端子T2被布置在基底材料11的下表面上，第二端子T2经由在上表面与下表面之间设置的导线电连接到第一端子T1。电连接到外部衬底的外部连接端子(例如，焊球)形成在第二端子T2上。
如图2中所示，半导体芯片12经由第一构件21被安装在基底材料11上。在本第一实施例中，第一构件21例如是裸片附接膜(DAF)。半导体芯片12可以是处理高频信号的半导体芯片。处理高频信号的半导体芯片例如是具有高数据传输速率的DRAM芯片(例如，2000Mbps或更高)，或者是与DRAM芯片通信的逻辑芯片。
半导体器件1可以是包括多个半导体芯片的SiP(系统级封装)。多个半导体芯片可以被并排布置或者被垂直堆叠。注意，用作旁路电容器的芯片电容器13不需要被安装在所有半导体芯片上。
半导体芯片12包括多个电极垫PD。在本第一实施例中，多个电极垫PD沿着半导体芯片12的相应边进行布置，如图1中所示。多个电极垫PD可以沿着半导体芯片12的相应边进行布置，并且被布置在多个行之上。参考图2，除了布置电极垫PD的区域之外的区域被保护膜121覆盖。保护膜121(也被称为钝化膜)可以包括例如氧化硅膜和聚酰亚胺膜。
多个电极垫PD包括第一电极垫P1、第二电极垫P2和第三电极垫P3。
第一电极垫P1电连接到第一端子T1。可以经由第一电极垫P1从半导体芯片12输入电信号，或者可以将电信号输出到半导体芯片12，或者可以经由第一电极垫P1向半导体芯片12提供电源。
电源电位被提供给第二电极垫P2。第二电极垫P2可以电连接到在半导体芯片12中设置的电源电位线。
基准电位被提供给第三电极垫P3。第三电极垫P3可以电连接到在半导体芯片12中设置的基准电位线。
如上所述，多个电极垫PD可以沿着半导体芯片12的每一侧而设置，并且以多个行进行设置。这里，第二电极垫P2和第三电极垫P3可以被布置在以下行中，该行是多个行之中的、位于半导体芯片最内侧的行。因此，如图1中所示，当芯片电容器13被布置在由半导体芯片12的表面上的多个电极垫PD围绕的区域中时，稍后描述的第二导线15和第三导线16中的每个导线的长度可以比稍后描述的第一导线14的长度减小得多。这里，第一电极垫P1可以被布置在外行中。第二电极垫P2和第三电极垫P3中的一个电极垫可以被布置在内行中，并且另一个可以被布置在外行中。
如图2中所示，芯片电容器13经由第二构件22被安装在半导体芯片12上。在本第一实施例中，第二构件22例如是裸片附接膜(DAF)。芯片电容器13包括第一电极131和第二电极132。芯片电容器13用作所谓的旁路电容器。芯片电容器13的数目可以是多个(例如6个)。
注意，第一构件21和第二构件22不限于裸片附接膜。第一构件21和第二构件22可以是粘合剂或绝缘膏。然而，在从施加膏剂到固化膏剂的时段期间，膏剂的形状比裸片附接膜更容易变形。因此，为了减少第二导线15和第三导线16中的每个导线的长度，在将芯片电容器13布置在每个电极垫P2、P3附近时，优选使用裸片附接膜而不是膏剂。
第一导线14将第一电极垫P1与第一端子T1电连接。因此，基底材料11和半导体芯片12彼此电连接。第一导线14的金属材料没有特别限制，但例如是金、铜、铝等。
在不穿过基底材料11的情况下，第二导线15将第二电极垫P2与第一电极131电连接。第二导线15的金属材料没有特别限制，但例如是金、铜、铝等。
在不穿过基底材料11的情况下，第三导线16将第三电极垫P3与第二电极132电连接。第二导线15和第三导线16的金属材料没有特别限制，但例如是金、铜、铝等。
通过第二导线15和第三导线16，芯片电容器13用作旁路电容器。芯片电容器13用于减少电源噪声和稳定电源电位。
树脂密封体17将半导体芯片12、芯片电容器13、第一导线14、第二导线15和第三导线16密封。
如图1和图2中所示，在不穿过基底材料11的情况下，第二导线15和第三导线16中的每个导线将芯片电容器13与半导体芯片12电连接。即，在本第一实施例中，在不穿过基底材料11的情况下，从芯片电容器13向半导体芯片12提供(传输)电源电位和基准电位中的每个电位。此外，通过将芯片电容器13安装在半导体芯片12上，可以使第二导线15和第三导线16中的每个导线的长度短于将基底材料11和半导体芯片12彼此电连接的第一导线14的长度。因此，可以减少第二导线15和第三导线16中的每个导线的长度，并且可以减小电源阻抗。即，可以减小从芯片电容器13到半导体芯片12的电源电位和基准电位的每个供给路径(传输路径)中的电源阻抗。此外，由于芯片电容器13未被直接焊接到半导体芯片12，因此可以防止保护膜121中出现裂纹。
现在参考图3和图4，将描述制造根据第一实施例的半导体器件1的方法。图3是说明了制造根据相关技术的半导体器件的方法的视图。图4是说明了制造根据第一实施例的半导体器件的方法的视图。
参考图3，在制造相关半导体器件的方法中，将芯片电容器13焊接到基底材料11上，在基底材料11上，通过回流在最高上表面(也被称为顶表面)处形成电源电位布线(也被称为电源电位的布线图案)和基准电位布线(也被称为基准电位的布线图案)(步骤S101)。温度条件被设置为例如200℃至250℃。附图标记S表示焊料。
接下来，通过裸片键合，经由第一构件21将半导体芯片12安装在基底材料11上(步骤S102)。温度条件被设置为例如100℃至200℃。
接下来，通过导线键合，将半导体芯片12和基底材料11彼此电连接(步骤S103)。
在相关技术中，由于半导体芯片12与芯片电容器13之间的距离较大，所以存在电源阻抗较大的问题。此外，当芯片电容器13被安装在半导体芯片12外部时，减少了基底材料11的布线资源。即，当多个芯片电容器13被安装在基底材料11上时，基底材料11的最上面的上表面需要用于对电源电位布线和基准电位布线进行路由。在该情况下，需要增加基底材料11的布线层的数目，例如需要将基底材料11的布线层的数目从两层增加到四层。
还可以想到将芯片电容器13回流焊接在半导体芯片12上的方法。然而，在该情况下，由于回流温度，可能在半导体芯片12的保护膜121中产生应力，并且可能在保护膜121中产生裂纹。
参考图4，在制造根据第一实施例的半导体器件的方法中，首先，通过裸片键合，经由第一构件21将半导体芯片12安装在基底材料11上(步骤S201)。温度条件被设置为例如100℃至200℃。
接下来，通过裸片键合，经由第二构件22将芯片电容器13安装在半导体芯片12上(步骤S202)。温度条件被设置为例如100℃至200℃。
接下来，通过导线键合，将半导体芯片12和基底材料11彼此电连接，并且将半导体芯片12和芯片电容器13彼此电连接(步骤S203)。然后，利用树脂密封体来密封半导体芯片12等。
在第一实施例中，需要步骤S202，但是具有不需要增加基底材料11的互连层的数目的优点。与相关技术相比，第一实施例可以是成本高效的。
根据第一实施例，可以减小电源阻抗，同时防止半导体芯片12的保护膜中出现裂纹。此外，第一实施例可以防止基底材料11被损坏，并且可以减少制造成本。
(第二实施例)
第二实施例是第一实施例的具体示例。根据第二实施例的半导体器件是SiP(系统级封装)，在该SiP中，DRAM(动态随机存取存储器)芯片32和控制DRAM芯片32的逻辑芯片31被密封在一个封装中。注意，芯片电容器13可以不被安装在存储器芯片和逻辑芯片两者上。
逻辑芯片31包括与DRAM芯片32通信的存储器控制器。逻辑芯片31可以是所谓的SoC(片上系统)，其中多个功能被形成到一个芯片中。
图5是说明了根据第二实施例的半导体器件1a的电路配置的图。如稍后将描述的，所有旁路电容器C1、C2、C3和C4不需要作为芯片电容器13被安装在逻辑芯片31或DRAM芯片32上。
半导体器件1a包括逻辑芯片31和DRAM芯片32。DRAM芯片32具有DDR_SDRAM。
逻辑芯片31包括CPU 311和信号驱动器D。CPU 311被设置在核心系统电源电位VDD和基准电位VSS之间。信号驱动器D被设置在DDR系统电源电位VDDQ(也被称为DDR_VDDQ)和DDR系统基准电位VSSQ(也被称为DDR_VSSQ)之间。核心系统电源电位VDD、基准电位VSS、DDR系统电源电位VDDQ和DDR系统基准电位VSSQ可以从上面描述的基底材料11的第一端子T1而提供。此外，如图5中所示，在用于将逻辑芯片31和DRAM芯片32彼此电连接的路径中，基准电位VSS和DDR系统基准电位VSSQ可以彼此共享。
DRAM芯片32包括存储器单元(未示出)和输入/输出电路(未示出)。输入/输出电路被设置在DDR系统电源电位VDDQ和DDR系统基准电位VSSQ之间。输入/输出电路响应于从信号驱动器D接收到控制信号，而从存储器单元读取数据并且将数据写入到存储器单元。
附图标记41表示DDR系统电源。旁路电容器C1和旁路电容器C2中的每个旁路电容器被耦合到用于将DDR系统电源41提供到逻辑芯片31的路径。每个旁路电容器C1、C2被配置成减小从逻辑芯片31看到的电源阻抗。旁路电容器C1是减小高频范围内的电源阻抗的小电容电容器。旁路电容器C2是减小低频范围内的电源阻抗的大电容电容器。
通过将旁路电容器C1和C2中的至少一个旁路电容器作为芯片电容器13安装在逻辑芯片31上，可以减小从逻辑芯片31看到的DDR电源41的电源阻抗。
构成信号驱动器D的晶体管比构成CPU 311的晶体管消耗更大的驱动电流。此外，存在多个信号驱动器D经由并行总线接口同时操作的可能性。因此，减小高频范围内的电源阻抗的旁路电容器C1特别关键，因为瞬态电流会生成较大的电源噪声。因此，旁路电容器C1和C2之中的旁路电容器C1优选作为芯片电容器13被安装在逻辑芯片31上。应当注意，DRAM芯片32的数据传输速率越高，越需要降低电源阻抗。因此，当旁路电容器C1被安装在逻辑芯片31上时，可以如相关技术中那样将减小低频范围中的电源阻抗的旁路电容器C2安装在基底材料11上。此外，如果第二导线15和第三导线16中的每个导线的长度与将逻辑芯片31和基底材料11电连接的第一导线14的长度相同，则旁路电容器C1、C2可以被安装在基底材料11上。
旁路电容器C3连接到用于将DDR系统电源41提供到DRAM芯片32的路径。旁路电容器C3减小从DRAM芯片32看到的电源阻抗。旁路电容器C3还可以包括用于去除高频范围内的噪声的小电容电容器、以及用于去除低频范围内的噪声的大电容电容器。
通过将旁路电容器C3作为芯片电容器13安装在DRAM芯片32上，可以减小从DRAM芯片32看到的DDR电源41的电源阻抗。
附图标记42表示核心电源。核心电源42的负极侧上的符号未被示出。旁路电容器C4连接到用于将核心系统电源42提供到逻辑芯片31的路径。旁路电容器C4降低从逻辑芯片31看到的核心系统电源42的电源阻抗。
通过将旁路电容器C4作为芯片电容器13安装在逻辑芯片31上，可以减小核心系统电源42的电源阻抗。然而，如果CPU 311的消耗电流随着核心系统电源42的电源阻抗变得更成问题而变大，则逻辑芯片31和基底材料11由于散热或IR下降而未通过导线连接的可能性更高。在该情况下，逻辑芯片31可以是安装的倒装芯片。
如上所述，旁路电容器C1优选作为芯片电容器13被安装在逻辑芯片31上。旁路电容器C1的第一电极和第二电极分别电连接到逻辑芯片31的第二电极垫P2和第三电极垫P3。这里，旁路电容器C2、C3和C4可以如相关技术中那样被安装在基底材料11上。当在逻辑芯片31的正面上存在可以安装除了旁路电容器C1之外的旁路电容器的区域时，减小从逻辑芯片31看到的电源阻抗的旁路电容器C2也可以被安装在逻辑芯片31上，与旁路电容器C1相同。
接下来，将描述根据第二实施例的半导体器件1a的示例性配置。图6是从上方观察的半导体器件1a的上表面视图。图7是沿图6中的B-B’线的截面图。在图6和图7中，省略了对第一构件和第二构件的图示。
图6和图7示出了芯片电容器13被安装在逻辑芯片31上的情况。逻辑芯片31对应于根据第一实施例的半导体芯片12。逻辑芯片31和DRAM芯片32被垂直堆叠。注意，逻辑芯片31可以被堆叠在DRAM芯片32上，并且DRAM芯片32可以被堆叠在逻辑芯片31上。
DRAM芯片32经由第一构件(未示出)被安装在作为引线框架的基底材料11上。当基底材料11是引线框架时，存在电源阻抗比在基底材料11是BGA时更高的问题。逻辑芯片31经由第一构件(未示出)被安装在DRAM芯片32上。
逻辑芯片31和DRAM芯片32具有上述第一电极垫P1。第一电极垫P1是经由第一导线14连接到第一端子T1的电极垫。第一电极垫P1可以是用于输入和输出信号的电极垫，或者可以是被提供电源(例如，DDR系统电源的电源电位)的电极垫。
逻辑芯片31包括上面描述的第二电极垫P2和第三电极垫P3。第二电极垫P2是经由第二导线15连接到芯片电容器13的第一电极P1的电极垫。第三电极垫P3是经由第三导线16连接到芯片电容器13的第二电极的电极垫。
再分布层RDL(Redistribution layer)形成在DRAM芯片32上。可以经由第一导线14、再分布层RDL和导线51，从基底材料11向逻辑芯片31提供DDR电源。第一导线14是将基底材料11和DRAM芯片32彼此电连接的导线。导线51是将逻辑芯片31和DRAM芯片32彼此电连接的导线。除了提供电源电位和基准电位的导线之外，第一导线14和导线51中的每个导线还可以包括传送信号的导线。当逻辑芯片31和DRAM芯片32被垂直堆叠时，可以减小导线51的长度。
芯片电容器13可以是减小高频范围内的电源阻抗的旁路电容器C1。这里，用于减小低频范围内的电源阻抗的旁路电容器C2可以如相关技术那样被安装在基底材料11上。此外，当逻辑芯片31的表面上存在可以安装除旁路电容器C1以外的旁路电容器的区域时，也可以在逻辑芯片31上安装减小低频区域中的电源阻抗的旁路电容器C2。
DRAM芯片32还可以被设置有用作旁路电容器C3的芯片电容器13。在该情况下，可以减小从逻辑芯片31看到的电源阻抗和从DRAM芯片32看到的电源阻抗两者。这里，逻辑芯片31和DRAM芯片32中的每个芯片对应于根据第一实施例的半导体芯片12。
图8是说明了参考图6和图7描述的配置的修改示例的视图。参考图8，芯片电容器18被安装在作为引线框架的基底材料11上。安装在半导体芯片12上的芯片电容器13也被称为第一芯片电容器13，并且安装在基底材料11上的芯片电容器18也被称为第二芯片电容器18。
第二芯片电容器18被设置在向DRAM芯片32提供的DDR系统电源电位VDDQ与基准电位VSS之间。结果，第二芯片电容器18用作旁路电容器C3。
DRAM芯片32具有连接到DDR系统电源电位VDDQ的电极垫，并且具有连接到基准电位VSS的电极垫。第二芯片电容器18电连接到DRAM芯片32的两个电极垫。导线52是将第二芯片电容器18和DRAM芯片32连接的导线。导线52可以比上面描述的第二导线15和第三导线16长，但与相关技术相比，具有减小电源阻抗的效果。
在其中安装第一芯片电容器13的区域，可以不被固定在逻辑芯片31下方所设置的DRAM芯片32上。在该实施例中，第二芯片电容器18被设置在基底材料11上，使得可以减小从DRAM芯片32看到的电源阻抗。
此外，逻辑芯片31和DRAM芯片32可以被并排布置。图9示出了逻辑芯片31和DRAM芯片32被并排布置的配置，并且芯片电容器13被安装在逻辑芯片31上。芯片电容器13可以被安装在DRAM芯片32上。第一导线14可以包括连接到裸片垫的导线(例如，连接到基准电位的导线)。
(第三实施例)
第三实施例是第二实施例的修改示例。根据第三实施例的半导体器件1b包括多个DRAM芯片32。图10是说明了根据第三实施例的半导体器件1b的图。在图10中，省略了对基底材料11、第一构件、第二构件等中的每一者的图示。
半导体器件1b包括逻辑芯片31、间隔器构件33、DRAM芯片321和DRAM芯片322。DRAM芯片32的数目不限于两个，并且可以是三个或更多个。注意，逻辑芯片31可以被设置在DRAM芯片321和322上，或者可以被设置在DRAM芯片321和322下方。
SoC 31被安装在衬底(未示出)上。间隔器构件33被安装在逻辑芯片31上。结果，在其中安装芯片电容器13的区域可以被固定在逻辑芯片31上。间隔器构件33可以是例如虚设硅芯片。
DRAM芯片321被安装在间隔器构件33上，并且DRAM芯片322被安装在DRAM芯片321上。可以使用粘合膜(例如，裸片附接膜)或粘合剂来堆叠DRAM芯片321和322。
芯片电容器13被安装在逻辑芯片31、DRAM芯片321和DRAM芯片322中的每个芯片上。DRAM芯片321连接到安装在DRAM芯片321上的芯片电容器13，并且DRAM芯片322连接到安装在DRAM芯片322上的芯片电容器13。结果，可以减小从DRAM芯片321和DRAM芯片322中的每个DRAM芯片看到的电源阻抗。
逻辑芯片31、DRAM芯片321和DRAM芯片322中的每个芯片具有第二电极垫和第三电极垫(未示出)。第二导线15将芯片电容器13和第二电极垫电连接。第三导线(未示出)将芯片电容器13和第三电极垫电连接。
半导体器件1b包括将逻辑芯片31和DRAM芯片321电连接的导线51，并且包括将逻辑芯片31和DRAM芯片322电连接的导线51。导线51可以包括提供电源电位和基准电位的导线，并且控制信号和数据可以经由导线51进行交换。
除了芯片电容器13，用于改善信号质量的终端电阻器可以被安装在DRAM芯片322上。终端电阻器的一端可以电连接到导线51，并且终端电阻器的另一端可以连接到基准电位、电源电位或信号。
在第三实施例中，由于针对每个DRAM芯片设置了旁路电容器，所以可以减小每个DRAM芯片的电源阻抗。
尽管已经基于实施例具体描述了由本发明人做出的发明，但是本发明不限于上述实施例，并且不用说，在不偏离其要点的情况下可以进行各种修改。
例如，在根据上述实施例的分压电路中，可以采用其中诸如半导体衬底、半导体层或扩散层(扩散区域)的导电类型(p型或n型)被反转的配置。因此，在n型或p型的导电类型中的一种导电类型是第一导电类型并且另一种导电类型是第二导电类型的情况下，第一导电类型可以是p型，第二导电类型可以是n型，或者相反，第一导电类型可以是n型，第二导电类型可以是p型。
在上述实施例中，芯片电容器13经由裸片附接膜22被安装在半导体芯片12上。然而，如图11中所示，另一个BGA衬底61可以被安装在布置在半导体芯片12上的裸片附接膜22上，并且芯片电容器13可以经由焊接材料62被安装在另一个BGA衬底61上。
在图11中所示的配置中，芯片电容器13的相应电极131和132与BGA衬底61的相应导线(端子)611经由焊接材料62彼此电连接，但是由于不仅裸片附接膜22而且另一个BGA衬底61被插置在芯片电容器13和半导体芯片12之间，因此可以抑制在半导体芯片12的表面(上表面)上形成的保护膜121中出现上述裂纹。
此外，为了可靠地抑制裂纹，优选的是，要使用的另一个BGA衬底61或裸片附接膜22的厚度相对较大。然而，如果另一个BGA衬底61或裸片附接膜22的厚度太大，则将另一个BGA衬底61的导线(端子)611和半导体芯片12的电极垫P2、P3彼此电连接的导线的长度变长。即，从芯片电容器13到半导体芯片12的电源电位和基准电位的供给路径(传输路径)的长度变得更长。此外，与例如上面描述的第一实施例相比，在使用另一个BGA衬底61或焊接材料62的情况下，半导体器件的制造步骤的数目增加。因此，当在减少半导体器件的制造成本时，从芯片电容器13到半导体芯片12的电源电位和基准电位中的每个电位的供给路径(传输路径)中的电源阻抗也减小时，优选不使用如上述实施例中的另一个BGA衬底61。

Claims (10)

1.一种半导体器件，包括：
基底材料，具有第一端子；
半导体芯片，具有与所述第一端子电连接的第一电极垫、要被提供电源电位的第二电极垫以及要被提供基准电位的第三电极垫，并且所述半导体芯片经由第一构件被安装在所述基底材料上；
芯片电容器，具有第一电极和第二电极并且经由第二构件被安装在所述半导体芯片上；
第一导线，将所述第一电极垫与所述第一端子电连接；
第二导线，在不穿过所述基底材料的情况下将所述第二电极垫与所述第一电极电连接；
第三导线，在不穿过所述基底材料的情况下将所述第三电极垫与所述第二电极电连接；以及
树脂密封体，将所述半导体芯片、所述芯片电容器、所述第一导线、所述第二导线和所述第三导线密封，
其中所述第二导线和所述第三导线中的每个导线的长度比所述第一导线的长度短。
2.根据权利要求1所述的半导体器件，还包括：
DRAM芯片；以及
逻辑芯片，控制所述DRAM芯片，
其中所述DRAM芯片和所述逻辑芯片中的至少一个芯片被设置为所述半导体芯片，所述半导体芯片具有在其上安装所述芯片电容器的表面。
3.根据权利要求2所述的半导体器件，
其中所述DRAM芯片和所述逻辑芯片中的一个芯片被设置为具有在其上安装所述芯片电容器的所述表面的所述半导体芯片，并且
其中所述DRAM芯片和所述逻辑芯片中的另一个芯片被设置为另一个半导体芯片，所述另一个半导体芯片具有在其上安装另一个芯片电容器的表面。
4.根据权利要求2所述的半导体器件，
其中所述逻辑芯片被设置为具有在其上安装所述芯片电容器的所述表面的所述半导体芯片，
其中安装在所述逻辑芯片上的所述芯片电容器被配置成：减小从所述逻辑芯片看在高频范围中的电源阻抗，并且
其中安装在所述基底材料上的另一个芯片电容器被配置成：减小从所述逻辑芯片看在低频范围中的电源阻抗。
5.根据权利要求2所述的半导体器件，
其中所述DRAM芯片和所述逻辑芯片中的一个半导体芯片被堆叠在所述DRAM芯片和所述逻辑芯片中的另一个半导体芯片上，
其中所述一个半导体芯片被设置为具有在其上安装所述芯片电容器的所述表面的所述半导体芯片，并且
其中所述另一个半导体芯片与安装在所述基底材料上的另一个芯片电容器耦合。
6.根据权利要求2所述的半导体器件，还包括：
堆叠的多个DRAM芯片，
其中所述芯片电容器被安装在每个DRAM芯片上。
7.根据权利要求1所述的半导体器件，
其中，在平面图中，包括所述第一电极垫、所述第二电极垫和所述第三电极垫的多个电极垫，沿着所述半导体芯片的每一侧而布置，并且被布置成多个行，并且
其中所述第二电极垫和所述第三电极垫中的每个电极垫被布置在第一行中，在平面图中，所述第一行是所述多个行之中的、位于所述半导体芯片最内侧的行。
8.根据权利要求2所述的半导体器件，其中所述DRAM芯片的数据传输速率是2000Mbps或更大。
9.根据权利要求1所述的半导体器件，其中所述第二构件是裸片附接膜。
10.根据权利要求1所述的半导体器件，
其中所述电源电位要从所述芯片电容器被提供到所述半导体芯片，而不穿过所述基底材料，并且
其中所述基准电位要从所述芯片电容器被提供到所述半导体芯片，而不穿过所述基底材料。
CN202311326519.4A 2022-11-14 2023-10-13 半导体器件 Pending CN118039613A (zh)

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