TW202332066A - Sensing device - Google Patents
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- TW202332066A TW202332066A TW111120548A TW111120548A TW202332066A TW 202332066 A TW202332066 A TW 202332066A TW 111120548 A TW111120548 A TW 111120548A TW 111120548 A TW111120548 A TW 111120548A TW 202332066 A TW202332066 A TW 202332066A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
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- G01T1/16—Measuring radiation intensity
- G01T1/24—Measuring radiation intensity with semiconductor detectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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Abstract
Description
本發明是有關於一種光電裝置,且特別是有關於一種感測裝置。The present invention relates to an optoelectronic device, and more particularly to a sensing device.
光感測器因其出色的性能,已被廣泛應用於安檢、工業檢測及醫療診察等領域。舉例而言,在醫療診察方面,X射線感測器可用於人體胸腔、血管、牙齒等之影像擷取。一般而言,此類感測器主要包括薄膜電晶體(thin film transistor,TFT)以及PIN二極體(PIN diode),其中PIN二極體可將光能轉換成電訊號,而薄膜電晶體則用於讀取PIN二極體所測得的電訊號。Due to its excellent performance, light sensors have been widely used in fields such as security inspection, industrial inspection and medical diagnosis. For example, in medical diagnosis, X-ray sensors can be used to capture images of human chest, blood vessels, teeth, etc. Generally speaking, this type of sensor mainly includes thin film transistor (thin film transistor, TFT) and PIN diode (PIN diode), wherein PIN diode can convert light energy into electrical signal, and thin film transistor is Used to read the electrical signal measured by the PIN diode.
傳統上,此類感測器的製造流程是在製作完薄膜電晶體之後再製作PIN二極體。為了支援較高的影格速率(frame rate)及降低漏電流,目前技術傾向於採用金屬氧化物薄膜電晶體(Metal Oxide Transistor)。然而,在製作PIN二極體的過程中,由於需要使用SiH 2及H 2等含氫氣體的電漿來沉積薄膜,造成氫離子擴散進入金屬氧化物薄膜電晶體的金屬氧化物半導體層中,導致薄膜電晶體的表現異常,因而影響感測器的良率及可靠度。 Traditionally, the manufacturing process for this type of sensor is to fabricate the PIN diode after the thin film transistor. In order to support higher frame rate and reduce leakage current, the current technology tends to use Metal Oxide Transistor (Metal Oxide Transistor). However, in the process of making PIN diodes, due to the need to use hydrogen-containing gases such as SiH 2 and H 2 to deposit thin films, hydrogen ions diffuse into the metal oxide semiconductor layer of metal oxide thin film transistors, This results in abnormal performance of the thin film transistor, thereby affecting the yield and reliability of the sensor.
本發明提供一種感測裝置,具有提高的良率及改善的可靠度。The present invention provides a sensing device with improved yield and improved reliability.
本發明的一個實施例提出一種感測裝置,包括:基板;感測元件,位於基板上;開關元件,位於感測元件的一側;以及擋牆結構,電性連接感測元件與開關元件,其中擋牆結構的牆面平行於感測元件的鄰近開關元件的側面。An embodiment of the present invention proposes a sensing device, comprising: a substrate; a sensing element located on the substrate; a switching element located on one side of the sensing element; and a retaining wall structure electrically connecting the sensing element and the switching element, Wherein the wall surface of the retaining wall structure is parallel to the side of the sensing element adjacent to the switch element.
在本發明的一實施例中,上述的擋牆結構的牆面垂直於基板的上表面。In an embodiment of the present invention, the wall surface of the above-mentioned retaining wall structure is perpendicular to the upper surface of the substrate.
在本發明的一實施例中,上述的擋牆結構位於開關元件的半導體層與感測元件的光電轉換層之間。In an embodiment of the present invention, the above-mentioned retaining wall structure is located between the semiconductor layer of the switching element and the photoelectric conversion layer of the sensing element.
在本發明的一實施例中,上述的感測元件的鄰近開關元件的側面至少包括光電轉換層的側面,且光電轉換層的側面垂直於基板的上表面。In an embodiment of the present invention, the side of the sensing element adjacent to the switching element at least includes a side of the photoelectric conversion layer, and the side of the photoelectric conversion layer is perpendicular to the upper surface of the substrate.
在本發明的一實施例中,上述的開關元件的源極屬於擋牆結構的一部分。In an embodiment of the present invention, the source of the above-mentioned switching element is a part of the retaining wall structure.
在本發明的一實施例中,上述的擋牆結構電性連接感測元件的下電極。In an embodiment of the present invention, the above-mentioned retaining wall structure is electrically connected to the lower electrode of the sensing element.
在本發明的一實施例中,上述的感測裝置還包括輔助結構,電性連接源極與下電極,且輔助結構的延伸面與基板的上表面的夾角小於90度。In an embodiment of the present invention, the above-mentioned sensing device further includes an auxiliary structure electrically connected to the source electrode and the lower electrode, and the angle between the extension surface of the auxiliary structure and the upper surface of the substrate is less than 90 degrees.
在本發明的一實施例中,上述的輔助結構的電性連接源極的第一端與基板的間距大於輔助結構的電性連接下電極的第二端與基板的間距。In an embodiment of the present invention, the distance between the first end of the auxiliary structure electrically connected to the source and the substrate is greater than the distance between the second end of the auxiliary structure electrically connected to the lower electrode and the substrate.
在本發明的一實施例中,上述的擋牆結構在牆面的延伸方向上的長度大於開關元件的半導體層在平行於延伸方向上的寬度。In an embodiment of the present invention, the length of the retaining wall structure in the extending direction of the wall surface is greater than the width of the semiconductor layer of the switching element parallel to the extending direction.
在本發明的一實施例中,上述的擋牆結構在牆面的延伸方向上的長度不小於感測元件的側面在平行於延伸方向的方向上的長度。In an embodiment of the present invention, the length of the retaining wall structure in the extension direction of the wall surface is not less than the length of the side surface of the sensing element in a direction parallel to the extension direction.
在本發明的一實施例中,上述的開關元件的半導體層與基板的間距小於感測元件與基板的間距。In an embodiment of the present invention, the distance between the semiconductor layer of the switching element and the substrate is smaller than the distance between the sensing element and the substrate.
在本發明的一實施例中,上述的感測裝置還包括金屬氧化物層,且金屬氧化物層層疊於擋牆結構上。In an embodiment of the present invention, the above-mentioned sensing device further includes a metal oxide layer, and the metal oxide layer is stacked on the retaining wall structure.
在本發明的一實施例中,上述的擋牆結構的牆面為L形,且感測元件的鄰近開關元件的側面為L形。In an embodiment of the present invention, the wall surface of the above-mentioned retaining wall structure is L-shaped, and the side of the sensing element adjacent to the switch element is L-shaped.
在本發明的一實施例中,上述的開關元件的源極與開關元件的汲極屬於不同膜層。In an embodiment of the present invention, the source of the switch element and the drain of the switch element belong to different film layers.
本發明的另一個實施例提出一種感測裝置,包括:基板;感測元件層,位於基板上,且包括多個感測元件;波長轉換層,位於感測元件層的背離基板的一側;以及開關元件層,位於感測元件層與波長轉換層之間,且包括多個開關元件,其中多個開關元件分別電性連接多個感測元件的背離波長轉換層的一側。Another embodiment of the present invention proposes a sensing device, including: a substrate; a sensing element layer located on the substrate and including a plurality of sensing elements; a wavelength conversion layer located on a side of the sensing element layer away from the substrate; and the switch element layer, located between the sensing element layer and the wavelength conversion layer, and includes a plurality of switch elements, wherein the plurality of switch elements are respectively electrically connected to sides of the plurality of sensing elements away from the wavelength conversion layer.
在本發明的一實施例中,上述的多個感測元件彼此實體連接。In an embodiment of the present invention, the above-mentioned plurality of sensing elements are physically connected to each other.
在本發明的一實施例中,上述的感測元件層具有多個通孔,且感測元件位於多個通孔之間。In an embodiment of the present invention, the above sensing element layer has a plurality of through holes, and the sensing element is located between the plurality of through holes.
在本發明的一實施例中,上述的多個開關元件的源極分別通過多個通孔電性連接多個感測元件的下電極。In an embodiment of the present invention, the sources of the aforementioned plurality of switching elements are electrically connected to the lower electrodes of the plurality of sensing elements through a plurality of through holes, respectively.
在本發明的一實施例中,上述的感測裝置還包括遮光結構,位於波長轉換層與開關元件層之間,且具有多個開口,其中多個開口分別重疊多個感測元件。In an embodiment of the present invention, the above-mentioned sensing device further includes a light-shielding structure located between the wavelength conversion layer and the switch element layer, and having a plurality of openings, wherein the plurality of openings respectively overlap the plurality of sensing elements.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反地,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接。再者,「電性連接」或「耦接」可為二元件間存在其它元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.
應當理解,儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、層及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的第一「元件」、「部件」、「區域」、「層」或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
這裡使用的術語僅僅是為了描述特定實施例的目的,而不是限制性的。如本文所使用的,除非內容清楚地指示,否則單數形式「一」、「一個」和「該」旨在包括複數形式,包括「至少一個」或表示「及/或」。如本文所使用的,術語「及/或」包括一個或多個相關所列項目的任何和所有組合。還應當理解,當在本說明書中使用時,術語「包含」及/或「包括」指定所述特徵、區域、整體、步驟、操作、元件及/或部件的存在,但不排除一個或多個其它特徵、區域、整體、步驟、操作、元件、部件及/或其組合的存在或添加。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" or meaning "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the existence of said features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more Existence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.
此外,諸如「下」或「底部」和「上」或「頂部」的相對術語可在本文中用於描述一個元件與另一元件的關係,如圖所示。應當理解,相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如,如果一個附圖中的裝置翻轉,則被描述為在其他元件的「下」側的元件將被定向在其他元件的「上」側。因此,示例性術語「下」可以包括「下」和「上」的取向,取決於附圖的特定取向。類似地,如果一個附圖中的裝置翻轉,則被描述為在其它元件「下」或「下方」的元件將被定向為在其它元件「上方」。因此,示例性術語「下」或「下方」可以包括上方和下方的取向。Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制),本文使用的「約」、「近似」、或「實質上」包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值。例如,「約」可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的「約」、「近似」、或「實質上」可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。The terms "about," "approximately," or "substantially" as used herein include stated values and those within ordinary skill in the art, taking into account the measurements in question and the specific amount of error associated with the measurements (i.e., limitations of the measurement system). The average value within an acceptable range of deviation from a specified value as determined by a human being. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" used herein may select a more acceptable range of deviation or standard deviation based on optical properties, etching properties or other properties, and may not use one standard deviation to apply to all nature.
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.
本文參考作為理想化實施例的示意圖的截面圖來描述示例性實施例。因此,可以預期到作為例如製造技術及/或公差的結果的圖示的形狀變化。因此,本文所述的實施例不應被解釋為限於如本文所示的區域的特定形狀,而是包括例如由製造導致的形狀偏差。例如,示出或描述為平坦的區域通常可以具有粗糙及/或非線性特徵。此外,所示的銳角可以是圓的。因此,圖中所示的區域本質上是示意性的,並且它們的形狀不是旨在示出區域的精確形狀,並且不是旨在限制權利要求的範圍。Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
圖1A是依照本發明一實施例的感測裝置10的局部上視示意圖。圖1B是沿圖1A的剖面線A-A’所作的剖面示意圖。為了使圖式的表達較為簡潔,圖1A示意性繪示基板110、感測元件120、開關元件130、共用電極CM、掃描線SL以及資料線DL,並省略其他構件及膜層。FIG. 1A is a schematic partial top view of a
請同時參照圖1A至圖1B,感測裝置10包括:基板110;感測元件120,位於基板110上;開關元件130,位於感測元件120的一側;以及擋牆結構BW,電性連接感測元件120及開關元件130,其中,擋牆結構BW的牆面F大致平行於感測元件120的鄰近開關元件的側面121。1A to 1B, the
在本發明的一實施例的感測裝置10中,藉由設置擋牆結構BW來阻隔氫離子,且使擋牆結構BW的牆面F大致平行於感測元件120的鄰近開關元件的側面121,能夠有效防止氫離子進入半導體層,以免影響感測裝置的良率及可靠度。In the
以下,配合圖式,繼續說明感測裝置10的各個元件與膜層的實施方式,但本發明不以此為限。Hereinafter, with reference to the drawings, the implementation of each element and film layer of the
請同時參照圖1A及圖1B,在本實施例中,基板110可以是剛性基板,例如玻璃基板、石英基板或矽基板,但不限於此。在其他實施例中,基板110可以是可撓性基板,例如聚合物基板或塑膠基板。Please refer to FIG. 1A and FIG. 1B at the same time. In this embodiment, the
在本實施例中,感測裝置10可以包括陣列排列的多組感測元件120以及開關元件130。感測元件120例如是PIN二極體(PIN diode),用以將光能轉換成電訊號。開關元件130例如是金屬氧化物薄膜電晶體,用以讀取感測元件120測得的電訊號。In this embodiment, the
舉例而言,感測元件120可以設置於基板110之上,且感測元件120可以包括依序設置於基板110上的下電極BE、光電轉換層PN以及上電極TE。下電極BE可以設置於平坦層PL1的凹槽CA中,例如下電極BE可以位於凹槽CA的底面B1上,且上電極TE與下電極BE彼此電性獨立。上電極TE可以是光穿透式電極,舉例而言,上電極TE的材質可以包括銦錫氧化物(InSnO)、銦鋅氧化物(InZnO)、鋁鋅氧化物(AlZnO)、鋁銦氧化物(AlInO)、氧化銦(InO)、氧化鎵(GaO)、奈米碳管、奈米銀顆粒、厚度小於60奈米(nm)的金屬或合金、有機透明導電材料、或其它適合的透明導電材料。下電極BE的材質可以包括金屬,例如鉻(Cr)、金(Au)、銀(Ag)、銅(Cu)、錫(Sn)、鉛(Pb)、鉿(Hf)、鎢(W)、鉬(Mo)、釹(Nd)、鈦(Ti)、鉭(Ta)、鋁(Al)、鋅(Zn)、或上述金屬的任意組合之合金、或上述金屬及/或合金之疊層,但不限於此。下電極BE也可以包含其他導電材料,例如:金屬的氮化物、金屬的氧化物、金屬的氮氧化物、金屬與其它導電材料的堆疊層、或是其它具有導電性質之材料。For example, the
光電轉換層PN位於上電極TE與下電極BE之間,且光電轉換層PN可以吸收來自感測元件120上方的可見光,並產生對應的光電流。舉例而言,在一些實施例中,光電轉換層PN可以包括P型半導體圖案SP、本質半導體圖案SI以及N型半導體圖案SN,其中P型半導體圖案SP位於上電極TE與本質半導體圖案SI之間,且N型半導體圖案SN位於本質半導體圖案SI與下電極BE之間。在某些實施例中,本質半導體圖案SI例如包括本質非晶矽,N型半導體圖案SN例如包括摻雜磷(P)的非晶矽,P型半導體圖案SP例如包括摻雜硼(B)的非晶矽。The photoelectric conversion layer PN is located between the upper electrode TE and the lower electrode BE, and the photoelectric conversion layer PN can absorb visible light from above the
在一些實施例中,感測裝置10還可以包括平坦層PL2以及共用電極CM,其中平坦層PL2可以覆蓋感測元件120,共用電極CM可以設置於平坦層PL2上,且共用電極CM可以通過平坦層PL2中的通孔VA電性連接上電極TE。在某些實施例中,共用電極CM可以具有環形的輪廓,且共用電極CM可以重疊感測元件120的周緣,如此一來,共用電極CM可以將光反射回感測元件120,藉以提高感測裝置10的光利用率。共用電極CM的材質可以包括金屬、合金、金屬的氮化物、金屬的氧化物、金屬的氮氧化物、其它導電材料或前述材料中至少兩者之堆疊層。In some embodiments, the
開關元件130可以電性連接感測元件120,藉以讀取感測元件120測得的電訊號。舉例而言,在本實施例中,開關元件130可以設置於基板110之上,開關元件130可以包括半導體層130C、閘極130G、源極130S以及汲極130D,且源極130S電性連接感測元件120的下電極BE。The
具體而言,半導體層130C可以包括通道區Ac、源極區As以及汲極區Ad,其中通道區Ac重疊閘極130G,且通道區Ac連接源極區As與汲極區Ad。源極130S電性連接源極區As,且汲極130D電性連接汲極區Ad。另外,半導體層130C與基板110之間的間距D1可以小於感測元件120與基板110之間的間距D2。Specifically, the
感測裝置10還可以包括緩衝層BF以及絕緣層I1、I2以及平坦層PL1,其中緩衝層BF位於基板110與半導體層130C之間,以避免基板110中的雜質進入半導體層130C。絕緣層I1位於半導體層130C與閘極130G之間,絕緣層I2以及平坦層PL1位於源極130S以及汲極130D與閘極130G之間,且源極130S以及汲極130D分別通過絕緣層I1、I2以及平坦層PL1中的通孔V1、V2連接源極區As以及汲極區Ad。另外,感測裝置10還可以包括掃描線SL以及資料線DL,掃描線SL可以電性連接閘極130G,且資料線DL可電性連接汲極130D。The
半導體層130C的材質例如是金屬氧化物半導體材料,例如銦鋅氧化物(InZnO,IZO)、銦鎵鋅氧化物(InGaZnO,IGZO)、銦鎢氧化物(InWO,IWO)、銦鎢鋅氧化物(InWZnO,IWZO)、銦鋅錫氧化物(InZnSnO,IZTO)、銦鎵錫氧化物(InGaSnO,IGTO)或銦鎵鋅錫氧化物(InGaZnSnO,IGZTO),但本發明不以此為限。閘極130G、源極130S、汲極130D、掃描線SL以及資料線DL的材質可以包括金屬,例如鈦、鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鉭、鋁、鋅、或上述金屬的任意組合之合金、或上述金屬及/或合金之疊層,但不限於此。The material of the
在本實施例中,源極130S電性連接感測元件120的下電極BE,且源極130S與感測元件120的下電極BE可以屬於相同膜層。值得注意的是,感測元件120可以具有最鄰近開關元件130的側面121,其中側面121至少包括光電轉換層PN的側面,側面121可以在方向X-X’上延伸,且源極130S可以在大致平行於方向X-X’的方向Y-Y’上延伸而形成擋牆結構BW。換句話說,源極130S可以屬於擋牆結構BW的一部分,擋牆結構BW也可以電性連接感測元件120的下電極BE。在一些實施例中,擋牆結構BW可以實體連接下電極BE。擋牆結構BW的牆面F或中心軸可以大致垂直於基板110的上表面111,且牆面F可以在方向Y-Y’上延伸而阻擋於開關元件130的半導體層130C與感測元件120的光電轉換層PN之間。在一些實施例中,擋牆結構BW在牆面F的延伸方向Y-Y’上的長度Lb可以大於半導體層130C在方向Y-Y’上的寬度Wc。如此一來,在形成光電轉換層PN的過程中,擋牆結構BW能夠充當半導體層130C的屏蔽牆來阻擋氫離子擴散進入半導體層130C中,使得開關元件130的性能不受影響,從而確保感測裝置10具有提高的良率及改善的可靠度。In this embodiment, the
在一些實施例中,感測裝置10還可以包括輔助結構AW,輔助結構AW可以與源極130S以及下電極BE屬於相同膜層,且輔助結構AW可以電性連接源極130S與下電極BE。具體而言,輔助結構AW可以位於凹槽CA的側壁S1上,且輔助結構AW的延伸面與基板110的上表面111的夾角θ可以小於90度。輔助結構AW的第一端E1可以連接源極130S,輔助結構AW的第二端E2可以連接下電極BE,且第一端E1與基板110的間距D3大於第二端E2與基板110的間距D4。如此一來,輔助結構AW能夠充當光電轉換層PN與半導體層130C之間的第二道屏蔽牆,也就是說,擋牆結構BW以及輔助結構AW皆能夠阻擋氫離子擴散進入半導體層130C中,藉以確保開關元件130的性能不受影響。In some embodiments, the
在一些實施例中,感測裝置10還可以包括絕緣層I3、平坦層PL3以及波長轉換層WT,絕緣層I3、平坦層PL3以及波長轉換層WT可以依序設置於感測元件120以及開關元件130上方,以將來自圖1B上側的光線(例如X射線)轉換成可見光。舉例而言,波長轉換層WT可以藉由熱蒸鍍製程形成,且波長轉換層WT的材質可以包括碘化銫(Cesium Iodide,CsI)。In some embodiments, the
舉例而言,緩衝層BF以及絕緣層I1、I2、I3的材質可以選自無機材料,例如氧化矽、氮化矽、氮氧化矽、其它合適的材料或上述至少二種材料的堆疊層。平坦層PL1、PL2、PL3的材質可以包括透明的絕緣材料,例如有機材料、壓克力(acrylic)材料、矽氧烷(siloxane)材料、聚醯亞胺(polyimide)材料、環氧樹脂(epoxy)材料等,但本發明不限於此。For example, the material of the buffer layer BF and the insulating layers I1 , I2 , I3 can be selected from inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or stacked layers of at least two of the above materials. The materials of the planar layers PL1, PL2, and PL3 may include transparent insulating materials, such as organic materials, acrylic materials, siloxane materials, polyimide materials, epoxy resins, etc. ) materials, etc., but the present invention is not limited thereto.
在一些實施例中,感測裝置10還可以包括金屬反射層MR,金屬反射層MR可以藉由濺鍍的方式形成於波長轉換層WT的背離感測元件120的一側,以將可見光反射回光電轉換層PN。在一些實施例中,感測裝置10還可以包括光學膠層OA,光學膠層OA可以位於波長轉換層WT與感測元件120之間,且光學膠層OA的材質例如是壓克力膠。In some embodiments, the
以下,使用圖2至圖5B繼續說明本發明的其他實施例,並且,沿用圖1A至圖1B的實施例的元件標號與相關內容,其中,採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明,可參考圖1A至圖1B的實施例,在以下的說明中不再重述。In the following, other embodiments of the present invention are continued to be described using FIGS. 2 to 5B, and the component numbers and related contents of the embodiment in FIGS. Descriptions of the same technical contents are omitted. For the description of the omitted parts, reference may be made to the embodiment shown in FIG. 1A to FIG. 1B , which will not be repeated in the following description.
圖2是依照本發明一實施例的感測裝置20的局部上視示意圖。感測裝置20包括:基板110;感測元件120,位於基板110上;開關元件130,位於感測元件120的一側;以及擋牆結構BWa,電性連接感測元件120及開關元件130,其中,擋牆結構BWa的牆面Fa大致平行於感測元件120的鄰近開關元件的側面121。FIG. 2 is a schematic partial top view of a sensing device 20 according to an embodiment of the invention. The sensing device 20 includes: a
圖2所示的感測裝置20與如圖1A至圖1B所示的感測裝置10的主要差異在於:感測裝置20的擋牆結構BWa在牆面Fa的延伸方向Y-Y’上的長度Lba不小於感測元件120鄰近開關元件130的側面121在平行於方向Y-Y’的方向X-X’上的長度Ls。換句話說,感測裝置20的擋牆結構BWa的長度Lba等於或大於側面121的長度Ls。如此一來,對於開關元件130而言,擋牆結構BWa可以完全遮蔽感測元件120的側面121,藉以阻擋來自感測元件120的側面121的氫離子擴散進入開關元件130,從而確保感測裝置20具有提高的良率及改善的可靠度。The main difference between the sensing device 20 shown in FIG. 2 and the
圖3A是依照本發明一實施例的感測裝置30的局部上視示意圖。圖3B是沿圖3A的剖面線B-B’所作的剖面示意圖。感測裝置30包括:基板110;感測元件120,位於基板110上;開關元件130,位於感測元件120的一側;以及擋牆結構BW,電性連接感測元件120及開關元件130,其中,擋牆結構BW的牆面Fb大致平行於感測元件120的鄰近開關元件的側面121。FIG. 3A is a schematic partial top view of a
圖3A至圖3B所示的感測裝置30與如圖1A至圖1B所示的感測裝置10的主要差異在於:感測裝置30還包括導電氧化物層CO,且導電氧化物層CO可以層疊於擋牆結構BW上,藉以阻擋來自感測元件120的氫離子擴散進入開關元件130。The main difference between the
在一些實施例中,導電氧化物層CO還可以層疊於輔助結構AW上,用以阻擋來自感測元件120的氫離子擴散進入開關元件130。在某些實施例中,導電氧化物層CO還可以層疊於開關元件130的汲極130D上,且導電氧化物層CO還可以位於光電轉換層PN與下電極BE之間。也就是說,導電氧化物層CO可以層疊於形成擋牆結構BK、輔助結構AW、源極130S、汲極130D以及下電極BE的整個膜層上。In some embodiments, the conductive oxide layer CO can also be stacked on the auxiliary structure AW to block hydrogen ions from the
圖4A(a)至圖4E(b)是依照本發明一實施例的感測裝置40的製造方法的步驟流程的局部剖面示意圖,其中,圖4A(b)、圖4B(b)、圖4C(b)、圖4D(b)以及圖4E(b)分別是沿圖4A(a)、圖4B(a)、圖4C(a)、圖4D(a)以及圖4E(a)中的剖面線C-C’所作的剖面示意圖。以下,配合圖4A(a)至圖4E(b)說明感測裝置40的製造方法。4A(a) to 4E(b) are partial cross-sectional schematic diagrams of the steps of the manufacturing method of the
請同時參照圖4A(a)及圖4A(b),可以形成下電極BE於基板110上。舉例而言,下電極BE的形成方法可以包括以下步驟。首先,在基板110上形成毯覆的導體層(未繪示)。繼之,利用微影製程,在導體層上形成圖案化光阻(未繪示)。接著,利用圖案化光阻作為罩幕,來對導體層進行蝕刻製程,以形成下電極BE。之後,移除圖案化光阻。Please refer to FIG. 4A(a) and FIG. 4A(b) at the same time, the bottom electrode BE can be formed on the
請同時參照圖4B(a)及圖4B(b),接著,形成光電轉換層PN以及上電極TE於下電極BE上。舉例而言,光電轉換層PN以及上電極TE的形成方法可以包括以下步驟。首先,在下電極BE及基板110上形成毯覆的半導體疊層(未繪示),且在毯覆的半導體疊層上形成毯覆的透明導電層(未繪示)。半導體疊層可以包括例如依序形成於下電極BE上的N型半導體材料層、本質半導體材料層以及P型半導體材料層(未繪示)。繼之,利用微影製程,在毯覆的透明導電層上形成圖案化光阻(未繪示)。接著,利用圖案化光阻作為罩幕,來對毯覆的透明導電層進行濕式蝕刻製程,以形成上電極TE。接著,利用圖案化光阻作為罩幕,來對毯覆的半導體疊層進行乾式蝕刻製程,以形成光電轉換層PN,且光電轉換層PN可以包括P型半導體圖案SP、本質半導體圖案SI以及N型半導體圖案SN。之後,移除圖案化光阻,即完成感測元件420,且感測元件420包括上電極TE、光電轉換層PN以及下電極BE。Please refer to FIG. 4B(a) and FIG. 4B(b) at the same time. Next, the photoelectric conversion layer PN and the upper electrode TE are formed on the lower electrode BE. For example, the method for forming the photoelectric conversion layer PN and the upper electrode TE may include the following steps. First, a blanket semiconductor stack (not shown) is formed on the bottom electrode BE and the
在一些實施例中,光電轉換層PN還可以具有頂懸(overhead)及底切(undercut)的輪廓,藉以防止漏電。舉例而言,光電轉換層PN的P型半導體圖案SP的端部OH可以具有頂懸的輪廓,且光電轉換層PN的N型半導體圖案SN的端部UC可以具有底切的輪廓。In some embodiments, the photoelectric conversion layer PN may also have an overhang (overhead) and an undercut (undercut) profile, so as to prevent leakage. For example, the end OH of the P-type semiconductor pattern SP of the photoelectric conversion layer PN may have an overhang profile, and the end UC of the N-type semiconductor pattern SN of the photoelectric conversion layer PN may have an undercut profile.
在一些實施例中,還可以對上電極TE進行退火處理(Annealing)AN,以提高上電極TE的導電率。退火處理AN可以在介於約150℃至250℃之間的溫度(例如180℃、200℃或220℃)下進行,且退火處理AN的時間可以介於約30分鐘至180分鐘之間,例如80分鐘、120分鐘或150分鐘,但本發明不以此為限。值得注意的是,退火處理AN還能夠使殘餘的氫離子轉化成氫分子(H 2)而逸散。 In some embodiments, the upper electrode TE may also be annealed (Annealing) AN to improve the conductivity of the upper electrode TE. The annealing treatment AN may be performed at a temperature between about 150°C to 250°C (eg, 180°C, 200°C, or 220°C), and the time for the annealing treatment AN may be between about 30 minutes to 180 minutes, for example 80 minutes, 120 minutes or 150 minutes, but the present invention is not limited thereto. It is worth noting that annealing AN can also convert residual hydrogen ions into molecular hydrogen (H 2 ) and dissipate.
請同時參照圖4C(a)及圖4C(b),接著,形成具有通孔V3、V4的平坦層PL4於上電極TE、光電轉換層PN、下電極BE以及基板110上,且通孔V3可以露出下電極BE,通孔V4可以露出上電極TE。平坦層PL4的形成方法可以包括以下步驟。首先,利用化學氣相沉積法在感測元件420以及基板110之上形成毯覆的平坦材料層。平坦材料層的材質可以包括透明的絕緣材料,例如有機材料、壓克力(acrylic)材料、矽氧烷(siloxane)材料、聚醯亞胺(polyimide)材料、環氧樹脂(epoxy)材料等。接著,利用微影製程,在平坦材料層上形成圖案化光阻(未繪示)。繼之,利用圖案化光阻作為罩幕,來對平坦材料層進行蝕刻製程,以形成具有通孔V3、V4的平坦層PL4。之後,移除圖案化光阻。Please refer to FIG. 4C(a) and FIG. 4C(b) at the same time. Then, a flat layer PL4 with via holes V3 and V4 is formed on the upper electrode TE, the photoelectric conversion layer PN, the lower electrode BE and the
接著,形成源極430S、擋牆結構BWc以及共用電極CMc於平坦層PL4上,其中源極430S可以屬於擋牆結構BWc的一部分,且源極430S可以通過通孔V3電性連接下電極BE,共用電極CMc可以通過通孔V4電性連接上電極TE。源極430S、擋牆結構BWc以及共用電極CMc的形成方法可以包括以下步驟。首先,利用物理氣相沉積法在平坦層PL4上形成毯覆的導電層(未繪示)。接著,利用微影製程,在導電層上形成圖案化光阻(未繪示)。繼之,利用圖案化光阻作為罩幕,來對導電層進行蝕刻製程,以形成源極430S、擋牆結構BWc以及共用電極CMc。之後,移除圖案化光阻。換句話說,源極430S、擋牆結構BWc以及共用電極CMc可以屬於相同膜層。源極430S、擋牆結構BWc以及共用電極CMc的材質可以包括鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鈦、鉭、鋁、鋅、前述金屬的合金、或前述金屬及/或合金之堆疊層、或其他導電材料。Next, form the
請同時參照圖4D(a)及圖4D(b),接著,形成半導體層430C於平坦層PL4上,且半導體層430C的一端電性連接源極430S。半導體層430C的形成方法可以包括以下步驟。首先,利用化學氣相沉積法在平坦層PL4上形成半導體材料層(未繪示)。接著,利用微影製程,在半導體材料層上形成圖案化光阻(未繪示)。繼之,利用圖案化光阻作為罩幕,來對半導體材料層進行蝕刻製程,以形成半導體層430C。之後,移除圖案化光阻。在本實施例中,半導體層430C與基板110之間的間距D5可以大於感測元件420的上表面422(即上電極TE的上表面)與基板110之間的間距D6。換句話說,半導體層430C所在的水平面高於感測元件420所在的水平面,半導體層430C大致位於感測元件420的上方。Please refer to FIG. 4D(a) and FIG. 4D(b) at the same time. Next, a
接著,可以利用化學氣相沉積法形成毯覆的絕緣層I41於半導體層430C、源極430S、共用電極CMc以及平坦層PL4上。接著,形成閘極430G以及掃描線SL於絕緣層I41上,且閘極430G重疊半導體層430C。閘極430G以及掃描線SL的形成方法可以包括以下步驟。首先,利用物理氣相沉積法在絕緣層I41上形成毯覆的導電層(未繪示)。接著,利用微影製程,在導電層上形成圖案化光阻(未繪示)。繼之,利用圖案化光阻作為罩幕,來對導電層進行蝕刻製程,以形成閘極430G以及掃描線SL。之後,移除圖案化光阻。Next, a blanket insulating layer I41 may be formed on the
在一些實施例中,在形成閘極430G之後,還可以進行摻雜製程DP,且摻雜製程DP例如是氫電漿處理。摻雜製程DP可以利用閘極430G作為罩幕,來對半導體層430C進行摻雜。在摻雜製程DP之後,半導體層430C中重疊閘極430G的部分可以形成通道區Ac,且摻雜製程DP可以將氫元素植入半導體層430C中未重疊閘極430G的源極區As及汲極區Ad,使得源極區As以及汲極區Ad可具有較通道區Ac低的電阻,藉以提升源極區As以及汲極區Ad的載子遷移率。在一些實施例中,半導體層430C的源極區As可以重疊或連接源極430S,且源極區As能夠與源極430S形成歐姆(ohmic)接觸。類似地,半導體層430C的汲極區Ad也能夠與後續形成的汲極430D形成歐姆(ohmic)接觸。In some embodiments, after forming the
請同時參照圖4E(a)及圖4E(b),接著,形成毯覆的絕緣層I42於閘極430G以及絕緣層I41上,接著,於絕緣層I41、I42中形成通孔V5,以露出半導體層430C的汲極區Ad。絕緣層I41、I42的材質可以是氧化矽、氮化矽、氮氧化矽、其它合適的材料或上述至少二種材料的堆疊層。Please refer to Fig. 4E (a) and Fig. 4E (b) at the same time, then, form the insulating layer I42 of covering on
接著,形成汲極430D以及資料線DL於絕緣層I42上,且汲極430D可以通過通孔V5電性連接半導體層430C的汲極區Ad,即完成開關元件430,且開關元件430包括半導體層430C、閘極430G、源極430S以及汲極430D,其中源極430S與汲極430D屬於不同膜層。Next, the
在一些實施例中,還可以利用濺鍍製程於感測元件420以及開關元件430之上形成波長轉換層。在一些實施例中,在形成波長轉換層之前,還可以在感測元件420以及開關元件430上先形成平坦層,以提供用以形成波長轉換層的平坦表面。In some embodiments, a wavelength conversion layer may also be formed on the
值得注意的是,在本實施例中,半導體層430C是在形成光電轉換層PN之後才形成,也就是說,在形成光電轉換層PN時並不存在半導體層430C,因此可以排除在形成光電轉換層PN的過程中氫離子擴散進入半導體層430C的問題。另外,光電轉換層PN的上表面覆蓋有上電極TE,且上電極TE的材質可以包括容易吸入氫離子的金屬氧化物,例如銦鋅氧化物、鋁銦氧化物或鋁鋅氧化物等。此外,感測元件420的鄰近開關元件430的源極430S的側面421(主要包括光電轉換層PN的側面)可具有L形的輪廓,同時擋牆結構BWc可具有L形牆面Fc,使得牆面Fc的延伸方向可以大致平行於側面421的延伸方向。如此一來,在形成擋牆結構BWc之後的製程步驟期間,擋牆結構BWc以及上電極TE也能夠充當半導體層430C的屏蔽牆來阻止從光電轉換層PN釋出的氫離子擴散進入半導體層430C中,從而確保感測裝置40具有提高的良率及改善的可靠度。It is worth noting that in this embodiment, the
圖5A是依照本發明一實施例的感測裝置50的局部上視示意圖。圖5B是沿圖5A的剖面線D-D’所作的剖面示意圖。感測裝置50包括:基板110;感測元件層SS,位於基板110上,且包括多個感測元件520;波長轉換層WT,位於感測元件層SS的背離基板110的一側;以及開關元件層WW,位於感測元件層SS與波長轉換層WT之間,且包括多個開關元件530,其中多個開關元件530分別電性連接多個感測元件520的背離波長轉換層WT的一側。FIG. 5A is a schematic partial top view of a
在本實施例中,感測元件層SS可以包括位於基板110上的多個下電極BE、位於多個下電極BE上的N型半導體層LN、位於N型半導體層LN上的本質半導體層LI、位於本質半導體層LI上的P型半導體層LP以及位於P型半導體層LP上的多個上電極TE,其中多個上電極TE分別重疊多個下電極BE,且夾於每組相互重疊的上電極TE與下電極BE之間的部分N型半導體層LN、部分本質半導體層LI以及部分P型半導體層LP可以構成一個感測元件520的光電轉換層PN,而每組相互重疊的上電極TE與下電極BE以及夾於其間的光電轉換層PN則可以構成一個感測元件520。在一些實施例中,多個下電極BE以及多個上電極TE可以皆分別以陣列的方式排列於基板110之上,但不限於此。In this embodiment, the sensing element layer SS may include a plurality of lower electrodes BE located on the
感測裝置50的開關元件層WW大體上可以位於感測元件層SS之上,且平坦層PL5可以位於開關元件層WW與感測元件層SS之間。開關元件層WW可以包括多個源極530S、多個半導體層530C、多個閘極530G、多個汲極530D以及絕緣層I51、I52,其中多個半導體層530C以及多個源極530S位於平坦層PL5上,絕緣層I51位於多個半導體層530C以及多個源極530S與多個閘極530G之間,且絕緣層I52位於多個閘極530G與多個汲極530D之間。多個源極530S分別電性連接多個半導體層530C的源極區As。在一些實施例中,多個源極530S、多個半導體層530C、多個閘極530G、多個汲極530D可以皆分別以陣列的方式排列於基板110之上,但不限於此。絕緣層I51、I52的材質例如氧化矽、氮化矽、氮氧化矽、其它合適的材料或上述至少二種材料的堆疊層。The switching element layer WW of the
在本實施例中,感測裝置50的波長轉換層WT可以位於開關元件層WW之上,換句話說,開關元件層WW可以位於波長轉換層WT與感測元件層SS之間。在一些實施例中,平坦層PL5、P型半導體層LP、本質半導體層LI以及N型半導體層LN的疊層可以具有多個通孔V6,且多個通孔V6分別重疊多個下電極BE。如此一來,開關元件層WW的多個源極530S可以分別通過多個通孔V6電性連接至多個下電極BE,且下電極BE為感測元件520的背離波長轉換層WT的一側的電極。In this embodiment, the wavelength conversion layer WT of the
在一些實施例中,感測裝置50還可以包括共用電極CMd、掃描線SL以及資料線DL。舉例而言,共用電極CMd可以位於平坦層PL5上,且共用電極CMd可以通過平坦層PL5中的通孔V7電性連接上電極TE。在一些實施例中,共用電極CMd可以與源極530S屬於相同膜層。在一些實施例中,共用電極CMd可以具有環形的輪廓,且共用電極CMd可以大致上重疊感測元件520的周緣,藉以遮蔽來自圖5B上方的光。另外,掃描線SL可以電性連接閘極530G,且掃描線SL可與閘極530G屬於相同膜層。資料線DL可以電性連接汲極530D,且資料線DL可與汲極530D屬於相同膜層。In some embodiments, the
在一些實施例中,絕緣層I51、I52的疊層還可以具有多個通孔V8,且多個通孔V8可以分別重疊多個半導體層530C的汲極區Ad,使得多個汲極530D可以分別通過多個通孔V8電性連接多個半導體層530C的汲極區Ad。半導體層530C的通道區Ac可以重疊閘極530G,且通道區Ac可以位於源極區As與汲極區Ad之間。如此一來,電性連接至同一半導體層530C的源極530S及汲極530D以及鄰近的閘極530G可以構成一個開關元件530。In some embodiments, the stack of insulating layers I51 and I52 may also have a plurality of vias V8, and the plurality of vias V8 may respectively overlap the drain regions Ad of the plurality of semiconductor layers 530C, so that the plurality of
在一些實施例中,感測裝置50還可以包括具有多個開口OP的遮光層BM,且遮光層BM可以位於波長轉換層WT與開關元件層WW之間。具體而言,感測裝置50還可以包括平坦層PL6、PL7,其中平坦層PL6可以位於汲極530D以及絕緣層I52與遮光層BM之間,且平坦層PL7可以位於遮光層BM與波長轉換層WT之間。平坦層PL6、PL7的材質例如有機材料、壓克力(acrylic)材料、矽氧烷(siloxane)材料、聚醯亞胺(polyimide)材料、環氧樹脂(epoxy)材料等。遮光層BM可以遮擋來自圖5B上方的光,由於感測元件層SS中重疊遮光層BM的區域並不會有光電流通過,因此,可以將感測元件層SS中重疊遮光層BM的區域視為感測元件520之間的分隔區域,同時可以將感測元件層SS中重疊每一開口OP的區域視為一個感測元件520的區域。換句話說,遮光層BM的多個開口OP可以分別重疊感測元件層SS中的多個感測元件520。如此一來,感測元件層SS不需藉由蝕刻製程進行圖案化來形成多個感測元件520,因此能夠減輕或消除蝕刻製程所導致的漏電現象,從而改善感測裝置50的良率。In some embodiments, the
值得注意的是,在本實施例中,多個感測元件520的光電轉換層PN可以彼此實體連接,且多個通孔V6可以皆重疊遮光層BM,使得每一感測元件520可以位於多個通孔V6之間。另外,開關元件530的源極530S與波長轉換層WT之間的第一間距D7可以大於開關元件530的閘極530G與波長轉換層WT之間的第二間距D8,且閘極530G與波長轉換層WT之間的第二間距D8可以大於開關元件530的汲極530D與波長轉換層WT之間的第三間距D9。此外,在本實施例中,半導體層530C是在光電轉換層PN形成之後才形成,因此能夠排除在形成光電轉換層PN的過程中氫離子擴散進入半導體層530C的問題。It should be noted that, in this embodiment, the photoelectric conversion layers PN of the plurality of
綜上所述,本發明的感測裝置藉由設置擋牆結構來阻隔氫離子,能夠有效防止氫離子進入半導體層,使得感測裝置能夠具有良好的可靠度。另外,本發明的實施例的感測裝置還可以藉由設置輔助結構及/或導電氧化物層來增強阻擋氫離子進入半導體層的效果。再者,本發明的實施例的感測裝置還可以藉由先形成光電轉換層、後形成半導體層來排除在形成光電轉換層的過程中氫離子擴散進入半導體層的問題。此外,本發明的實施例的感測裝置還可以藉由以設置遮光層取代蝕刻製程來區分各個感測元件,因此能夠減輕或消除蝕刻製程造成的漏電現象,從而提高感測裝置的良率。To sum up, the sensing device of the present invention can effectively prevent the hydrogen ions from entering the semiconductor layer by setting the barrier structure to block the hydrogen ions, so that the sensing device can have good reliability. In addition, the sensing device according to the embodiment of the present invention can also enhance the effect of blocking hydrogen ions from entering the semiconductor layer by providing an auxiliary structure and/or a conductive oxide layer. Furthermore, the sensing device according to the embodiment of the present invention can also eliminate the problem of hydrogen ions diffusing into the semiconductor layer during the process of forming the photoelectric conversion layer by forming the photoelectric conversion layer first and then forming the semiconductor layer. In addition, the sensing device of the embodiment of the present invention can also distinguish each sensing element by disposing a light-shielding layer instead of an etching process, thereby reducing or eliminating the leakage phenomenon caused by the etching process, thereby improving the yield of the sensing device.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
10, 20, 30, 40, 50:感測裝置 110:基板 111:上表面 120, 420, 520:感測元件 121, 421:側面 130, 430, 530:開關元件 130C, 430C, 530C:半導體層 130D, 430D, 530D:汲極 130G, 430G, 530G:閘極 130S, 430S, 530S:源極 422:上表面 A-A’, B-B’, C-C’, D-D’:剖面線 Ac:通道區 Ad:汲極區 AN:退火處理 As:源極區 AW:輔助結構 B1:底面 BE:下電極 BF:緩衝層 BM:遮光層 BW, BWa, BWc:擋牆結構 CA:凹槽 CM, CMc, CMd:共用電極 CO:導電氧化物層 D1, D2, D3, D4, D5, D6:間距 D7:第一間距 D8:第二間距 D9:第三間距 DL:資料線 DP:摻雜製程 E1:第一端 E2:第二端 F, Fa, Fb, Fc:牆面 I1, I2, I3, I41, I42, I51, I52:絕緣層 Lb, Lba, Ls:長度 LI:本質半導體層 LN:N型半導體層 LP:P型半導體層 MR:金屬反射層 OA:光學膠層 OH:端部 OP:開口 PL1, PL2, PL3, PL4, PL5, PL6, PL7:平坦層 PN:光電轉換層 S1:側壁 SI:本質半導體圖案 SL:掃描線 SN:N型半導體圖案 SP:P型半導體圖案 SS:感測元件層 TE:上電極 UC:端部 V1, V2, V3, V4, V5, V6, V7, V8, VA:通孔 Wc:寬度 WT:波長轉換層 WW:開關元件層 X-X’, Y-Y’:方向 θ:夾角 10, 20, 30, 40, 50: sensing device 110: Substrate 111: upper surface 120, 420, 520: sensing element 121, 421: side 130, 430, 530: switching elements 130C, 430C, 530C: semiconductor layer 130D, 430D, 530D: drain 130G, 430G, 530G: gate 130S, 430S, 530S: source 422: upper surface A-A’, B-B’, C-C’, D-D’: hatching Ac: passage area Ad: Drain area AN: Annealing treatment As: source region AW: auxiliary structure B1: Bottom BE: Bottom electrode BF: buffer layer BM: shading layer BW, BWa, BWc: retaining wall structure CA: Groove CM, CMc, CMd: common electrode CO: conductive oxide layer D1, D2, D3, D4, D5, D6: Spacing D7: the first distance D8: second spacing D9: third spacing DL: data line DP: doping process E1: first end E2: second end F, Fa, Fb, Fc: Wall I1, I2, I3, I41, I42, I51, I52: insulating layer Lb, Lba, Ls: Length LI: Intrinsic semiconducting layer LN: N-type semiconductor layer LP: P-type semiconductor layer MR: metal reflective layer OA: optical adhesive layer OH: end OP: opening PL1, PL2, PL3, PL4, PL5, PL6, PL7: Flattened layers PN: photoelectric conversion layer S1: side wall SI: Intrinsic Semiconductor Pattern SL: scan line SN: N-type semiconductor pattern SP: P-type semiconductor pattern SS: Sensing element layer TE: upper electrode UC: end V1, V2, V3, V4, V5, V6, V7, V8, VA: Through hole Wc: width WT: wavelength conversion layer WW: switching element layer X-X’, Y-Y’: direction θ: included angle
圖1A是依照本發明一實施例的感測裝置10的局部上視示意圖。
圖1B是沿圖1A的剖面線A-A’所作的剖面示意圖。
圖2是依照本發明一實施例的感測裝置20的局部上視示意圖。
圖3A是依照本發明一實施例的感測裝置30的局部上視示意圖。
圖3B是沿圖3A的剖面線B-B’所作的剖面示意圖。
圖4A(a)至圖4E(b)是依照本發明一實施例的感測裝置40的製造方法的步驟流程的局部剖面示意圖,其中,圖4A(b)、圖4B(b)、圖4C(b)、圖4D(b)以及圖4E(b)分別是沿圖4A(a)、圖4B(a)、圖4C(a)、圖4D(a)以及圖4E(a)中的剖面線C-C’所作的剖面示意圖。
圖5A是依照本發明一實施例的感測裝置50的局部上視示意圖。
圖5B是沿圖5A的剖面線D-D’所作的剖面示意圖。
FIG. 1A is a schematic partial top view of a
10:感測裝置 10: Sensing device
110:基板 110: Substrate
120:感測元件 120: sensing element
121:側面 121: side
130:開關元件 130: switch element
130C:半導體層 130C: semiconductor layer
130D:汲極 130D: drain
130G:閘極 130G: Gate
130S:源極 130S: source
A-A’:剖面線 A-A': hatching
BW:擋牆結構 BW: retaining wall structure
CM:共用電極 CM: common electrode
DL:資料線 DL: data line
F:牆面 F: wall
Lb:長度 Lb: Length
SL:掃描線 SL: scan line
TE:上電極 TE: upper electrode
V1,V2,VA:通孔 V1, V2, VA: through hole
Wc:寬度 Wc: width
X-X’,Y-Y’:方向 X-X', Y-Y': Direction
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2022
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TW202332024A (en) | 2023-08-01 |
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