TW202332068A - Sensing device and fabricating method of the same - Google Patents

Abstract

A sensing device includes a substrate, a switching element, a sensing element and a common electrode. The switching element is disposed on the substrate and includes a source electrode. The sensing element is disposed at one side of the switching element and includes a lower electrode, a photoelectric conversion layer and an upper electrode. The lower electrode is electrically connected to the source electrode. The photoelectric conversion layer is disposed on the lower electrode. The upper electrode is disposed on the photoelectric conversion layer. The common electrode is electrically connected to the upper electrode and belongs to the same film layer as the source electrode. A fabricating method of a sensing device is also provided.

Description

Sensing device and manufacturing method thereof

The invention relates to a sensing device and a manufacturing method thereof.

Due to its excellent performance, light sensors have been widely used in fields such as security inspection, industrial inspection and medical diagnosis. For example, in medical diagnosis, X-ray sensors can be used to capture images of human chest, blood vessels, teeth, etc. Generally speaking, this type of sensor mainly includes thin film transistor (thin film transistor, TFT) and PIN diode (PIN diode), wherein PIN diode can convert light energy into electrical signal, and thin film transistor is Used to read the electrical signal measured by the PIN diode.

Traditionally, the manufacturing process for this type of sensor is to fabricate the PIN diode after the thin film transistor. Since thin film transistors and PIN diodes are manufactured individually one after the other, the number of masks in the manufacturing process is large, the manufacturing process steps are complicated and time-consuming. Therefore, how to integrate the manufacturing process of thin film transistors and PIN diodes is one of the most challenging research and development topics at present.

The invention provides a sensing device with a structure integrating a switching element and a sensing element.

The invention provides a sensing device with good reliability.

The invention provides a manufacturing method of a sensing device, which can integrate the manufacturing process of a switching element and a sensing element, simplify the manufacturing steps of the sensing device, and provide a sensing device with good reliability.

One embodiment of the present invention proposes a sensing device, comprising: a substrate; a switching element located on the substrate and including a source; a sensing element located on one side of the switching element and comprising: a lower electrode electrically connected to the source the photoelectric conversion layer is located on the lower electrode; the upper electrode is located on the photoelectric conversion layer; and the common electrode is electrically connected to the upper electrode and belongs to the same film layer as the source.

An embodiment of the present invention proposes a sensing device, comprising: a substrate; a switching element located on the substrate and comprising: a semiconductor layer; and a gate electrode surrounding the semiconductor layer; and a sensing element located on the substrate and comprising: an electrode; an upper electrode overlapping the lower electrode; and a photoelectric conversion layer located between the upper electrode and the lower electrode.

An embodiment of the present invention provides a method for manufacturing a sensing device, including: forming a semiconductor layer on a substrate; forming a first insulating layer on the semiconductor layer; forming a blanket conductive layer on the first insulating layer and the substrate; forming a blanketed semiconductor stack on the conductor layer; forming a blanketed transparent electrode layer on the semiconductor stack; patterning the transparent electrode layer to form an upper electrode; patterning the semiconductor stack to form a photoelectric conversion layer; and patterning the conductor layer to form the bottom electrode and top gate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" or meaning "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the existence of said features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more Existence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.

Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

The terms "about," "approximately," or "substantially" as used herein include stated values and those within ordinary skill in the art, taking into account the measurements in question and the specific amount of error associated with the measurements (i.e., limitations of the measurement system). The average value within an acceptable range of deviation from a specified value as determined by a human being. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" used herein may select a more acceptable range of deviation or standard deviation based on optical properties, etching properties or other properties, and may not use one standard deviation to apply to all nature.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

1A to 1G are partial cross-sectional schematic diagrams and partial top schematic diagrams of the steps of the manufacturing method of the sensing device 10 according to an embodiment of the present invention. Hereinafter, the manufacturing method of the sensing device 10 will be described with reference to FIG. 1A to FIG. 1G .

Referring to FIG. 1A , in some embodiments, the bottom gate BG and the scan line SL may be formed on the substrate 110 first. The substrate 110 may be a rigid substrate, such as a glass substrate, a quartz substrate or a silicon substrate, but is not limited thereto. In other embodiments, the substrate 110 may be a flexible substrate, such as a polymer substrate or a plastic substrate. Herein, the normal direction of the substrate 110 may be a direction Dz perpendicular to the surface 111 of the substrate 110 , and the direction Dz may be perpendicular to the direction Dx and the direction Dy.

For example, the method for forming the bottom gate BG and the scan line SL may include the following steps. First, a conductive layer (not shown) is formed on the substrate 110 . Then, a patterned photoresist (not shown) is formed on the conductive layer by using a lithography process. Next, the conductive layer is etched by using the patterned photoresist as a mask to form the bottom gate BG and the scan line SL. Afterwards, the patterned photoresist is removed.

For example, the material of the bottom gate BG and the scan line SL may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or the above Laminations of metals and/or alloys, but not limited thereto. The bottom gate BG and the scan line SL can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other materials with conductive properties .

Please refer to FIG. 1B(a). In this embodiment, a blanket insulating layer 120 can be formed on the substrate 110. The insulating layer 120 can be formed by chemical vapor deposition or other suitable methods to isolate the substrate 110. of impurities. In some embodiments, the insulating layer 120 may cover the bottom gate BG and the scan line SL to avoid unnecessary electrical connection. The material of the insulating layer 120 may include a transparent insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, organic polymer or a stack of the above materials, but the present invention is not limited thereto.

Next, referring to FIG. 1B(a) and FIG. 1B(b), a semiconductor layer CH is formed on the substrate 110 and the insulating layer 120 . In some embodiments, the semiconductor layer CH may partially overlap the bottom gate BG, and the orthographic projection of the semiconductor layer CH and the bottom gate BG on the substrate 110 may present a cross pattern. For example, the length Lc of the semiconductor layer CH in the direction Dx may be greater than the width Wg of the bottom gate BG in the direction Dx, and the width Wc of the semiconductor layer CH in the direction Dy may be smaller than the width Wg of the bottom gate BG in the direction Dy. length Lb, and the direction Dx is substantially perpendicular to the direction Dy, so that the orthographic projection of the two ends B1 and B2 of the bottom gate BG in the direction Dy on the substrate 110 is outside the orthographic projection of the semiconductor layer CH on the substrate 110 .

The method for forming the semiconductor layer CH may include the following steps: firstly, forming a blanket semiconductor material layer (not shown) on the insulating layer 120; then, forming a patterned photoresist (not shown) on the semiconductor material layer by using a lithography shown); then, use the patterned photoresist as a mask to perform an etching process on the semiconductor material layer to form the semiconductor layer CH; after that, remove the patterned photoresist.

The material of the semiconductor layer CH may include metal oxide semiconductor materials, for example: indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO, IZO), indium gallium oxide (InGaO, IGO), indium tin oxide (InSnO, ITO), indium gallium zinc tin oxide (InGaZnSnO, IGZTO), gallium zinc tin oxide (GaZnSnO, GZTO), gallium zinc oxide (GaZnO, GZO), zinc tin oxide (ZnSnO, ZTO) and indium At least one of tin zinc oxides (InSnZnO, ITZO), but not limited thereto.

Please refer to FIG. 1C(a), and then, form insulating layers 121, 131 on the substrate 110, wherein the insulating layer 121 can cover the bottom gate BG and the scanning line SL, the insulating layer 131 can cover the semiconductor layer CH, and the insulating layer 131 may overlap the insulating layer 121 on the scan line SL. The method for forming the insulating layers 121 and 131 may include the following steps. Firstly, a blanket insulating layer (not shown) is formed on the insulating layer 120 and the semiconductor layer CH. Then, a patterned photoresist (not shown) is formed on the blanket insulating layer by using a lithography process. Next, the blanket insulating layer and the insulating layer 120 are etched by using the patterned photoresist as a mask to form the insulating layers 121 and 131 . Afterwards, the patterned photoresist is removed. The above-mentioned blanket insulating layer can be formed by chemical vapor deposition or other suitable methods, and the material of the above-mentioned blanket insulating layer can include transparent insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, organic polymer or Lamination of the above materials, but the present invention is not limited thereto. In some embodiments, the insulating layers 121 and 131 can be formed in the same etching process, but not limited thereto.

Please refer to FIG. 1C(b), in some embodiments, the orthographic projections of the two ends B1 and B2 of the bottom gate BG in the direction Dy on the substrate 110 can be the orthographic projections of the insulating layers 121 and 131 on the substrate 110 In addition, in other words, the insulating layers 121 and 131 may not overlap and expose the two ends B1 and B2 of the bottom gate BG.

Please refer to FIG. 1D, and then, form a blanketed conductive layer 140 on the insulating layer 131 and the substrate 110, form a blanketed semiconductor stack 150 on the conductive layer 140, and form a blanketed transparent electrode layer 160 on the semiconductor stacked layer. 150 on. The conductor layer 140 , the semiconductor stack 150 and the transparent electrode layer 160 may be formed by chemical vapor deposition, physical vapor deposition or other suitable methods.

For example, the material of the conductor layer 140 may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or the above metals and/or alloys stacks, but not limited to this. The conductive layer 140 may also include other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

In some embodiments, the semiconductor stack 150 may include an N-type semiconductor material layer, an intrinsic semiconductor material layer, and a P-type semiconductor material layer sequentially formed on the conductor layer 140 . For example, the intrinsic semiconductor material layer is intrinsic amorphous silicon deposited by plasma enhanced chemical vapor deposition (PECVD) using silane (SiH ₄ ) and hydrogen (H ₂ ) as reactive gases. The N-type semiconductor material layer is, for example, phosphorus (P)-doped amorphous silicon formed by using phosphine (PH ₃ ), hydrogen (H ₂ ) and silane (SiH ₄ ) as reaction gases. The P-type semiconductor material layer is, for example, boron (B)-doped amorphous silicon formed by using trimethyl borate, hydrogen (H ₂ ) and silane (SiH ₄ ) as reaction gases, but the present invention is not limited thereto. .

The material of the transparent electrode layer 160 may include indium tin oxide, indium zinc oxide, aluminum zinc oxide (AlZO), aluminum indium oxide (AlInO), indium oxide (InO), gallium oxide (GaO), carbon nanotubes , nano silver particles, metals or alloys with a thickness less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials.

Referring to FIG. 1E , next, the transparent electrode layer 160 is patterned to form the upper electrode TE on the semiconductor stack 150 . In detail, patterning the transparent electrode layer 160 may include the following steps. First, a patterned photoresist (not shown) is formed on the transparent electrode layer 160 by using a photolithography process. Next, a wet etching process is performed on the transparent electrode layer 160 by using the patterned photoresist as a mask to form the upper electrode TE. The etchant used in the wet etching process is, for example, but not limited to oxalic acid or aluminate. Afterwards, the patterned photoresist is removed.

Next, the semiconductor stack 150 is patterned to form a photoelectric conversion layer PN. For example, patterning the semiconductor stack 150 may include the following steps. First, a patterned photoresist (not shown) is formed on the upper electrode TE and the semiconductor stack 150 by using a lithography process. Next, a dry etching process is performed on the semiconductor stack 150 by using the patterned photoresist as a mask to form the photoelectric conversion layer PN. The etching gas used in the dry etching process includes gases such as sulfur hexafluoride (SF ₆ ) and chlorine gas (Cl ₂ ), but is not limited thereto. Afterwards, the patterned photoresist is removed.

In some embodiments, the patterned transparent electrode layer 160 and the patterned semiconductor stack 150 may use the same photomask. Since the patterned transparent electrode layer 160 uses a wet etching process, during the wet etching process, the etchant will also remove the portion of the transparent electrode layer 160 below the edge of the patterned photoresist, so that the wet The size Wt of the top electrode TE formed after the etching process is smaller than the size of the patterned photoresist. In addition, since the patterned semiconductor stack 150 uses a dry etching process, the size Wp of the photoelectric conversion layer PN formed after the dry etching process will be similar to or equal to the size of the patterned photoresist, so that the size Wt of the upper electrode TE will be smaller than the size Wp of the photoelectric conversion layer PN.

It is worth noting that during the process of forming and patterning the semiconductor stack 150, the semiconductor layer CH is completely covered under the blanketed conductor layer 140, so that the blanketed conductor layer 140 can effectively block the reactive gas Hydrogen ions (H+) and the semiconductor layer CH are used to prevent the hydrogen ions from entering the semiconductor layer CH and affecting the properties of the semiconductor layer CH, thereby preventing the reliability of the sensing device 10 from being affected.

Referring to FIG. 1F(a), then, the conductive layer 140 is patterned to form the bottom electrode BE and the top gate TG. Patterning the conductor layer 140 may include the following steps. First, a patterned photoresist (not shown) is formed on the conductive layer 140 by using a lithography process. Next, the conductive layer 140 is etched by using the patterned photoresist as a mask to form the bottom electrode BE and the top gate TG. In other words, the bottom electrode BE and the top gate TG belong to the same film layer. Afterwards, the patterned photoresist is removed.

Referring to FIG. 1F(b), in some embodiments, the top gate TG can also extend down to the bottom gate along the two opposite sidewalls W31, W32 of the insulating layer 131 and the two opposite sidewalls W21, W22 of the insulating layer 121. The two ends B1 and B2 of BG enable the two ends T1 and T2 of the top gate TG to be physically connected to the two ends B1 and B2 of the bottom gate BG respectively to form a ring-shaped gate GE, and the gate GE can surround The central axis of the semiconductor layer CH and the gate GE may extend along the extending direction of the length Lc of the semiconductor layer CH (ie, the direction Dx). In some embodiments, the central axis of the gate GE may fall into the semiconductor layer CH. In some embodiments, the central axis of the gate GE may overlap the central axis of the semiconductor layer CH in the direction Dx.

In some embodiments, after forming the top gate TG, a doping process may also be performed. In the doping process, the top gate TG can be used as a mask to dope the semiconductor layer CH. After the doping process, the region overlapping the top gate TG in the semiconductor layer CH can become the channel region Cc, and the region not overlapping the top gate TG in the semiconductor layer CH can become the drain region C1 and the source region C2, and the drain Region C1 and source region C2 may have lower resistance than channel region Cc. For example, the doping process can implant hydrogen into the drain region C1 and the source region C2 of the semiconductor layer CH, so that the carrier mobility of the drain region C1 and the source region C2 of the semiconductor layer CH increases. In some embodiments, the doping process may be hydrogen plasma treatment. In some embodiments, the drain region C1 and the source region C2 of the semiconductor layer CH can respectively form ohmic contacts with the subsequently formed drain and source.

Referring to FIG. 1G , next, an insulating layer 170 is formed on the substrate 110 . The forming method of the insulating layer 170 may include the following steps. Firstly, a dielectric material layer (not shown) is formed on the substrate 110 by chemical vapor deposition or other suitable methods. Next, a patterned photoresist (not shown) is formed on the dielectric material layer by using a lithography process. Then, the dielectric material layer is etched by using the patterned photoresist as a mask to form the insulating layer 170 having the via holes V1 , V2 , V3 , and V4 . Afterwards, the patterned photoresist is removed. In this embodiment, the through holes V1 and V2 can further penetrate the insulating layer 131 to respectively expose the drain region C1 and the source region C2 of the semiconductor layer CH, and the through hole V3 can expose the bottom electrode BE, and the through hole V4 The upper electrode TE may be exposed.

Next, the drain electrode DE, the source electrode SE, the common electrode CM and the data line DL are formed on the insulating layer 170, wherein the drain electrode DE is electrically connected to the drain region C1 of the semiconductor layer CH through the via hole V1, and the source electrode SE is electrically connected to the drain electrode region C1 of the semiconductor layer CH through the via hole V1. The hole V2 is electrically connected to the source region C2 of the semiconductor layer CH, the source SE is also electrically connected to the lower electrode BE through the through hole V3, the common electrode CM is located on the upper electrode TE, and the common electrode CM is electrically connected through the through hole V4 Connect to top electrode TE. Since the common electrode CM, the drain electrode DE, the source electrode SE and the data line DL can be formed in the same process, the number of process masks can be reduced, thereby simplifying the process steps.

FIG. 1G is a schematic partial cross-sectional view of a sensing device 10 according to an embodiment of the invention. In this embodiment, the sensing device 10 may include: a substrate 110 , a switching element 180 , a sensing element 190 and a common electrode CM, and the switching element 180 , the sensing element 190 and the common electrode CM are all disposed on the substrate 110 . The sensing element 190 is, for example, a PIN diode (PIN diode), which is used to convert light energy into an electronic signal. The switching element 180 is, for example, a thin film transistor, and is used to read the signal detected by the sensing element 190 .

The switching element 180 includes at least a source SE. For example, in this embodiment, the switching element 180 may include a semiconductor layer CH, a source SE, a drain DE, and a top gate TG, wherein the insulating layer 121 is located between the semiconductor layer CH and the substrate 110, and the insulating layer 131 is located between Between the semiconductor layer CH and the top gate TG, the insulating layer 170 is located between the source SE and the drain DE and the top gate TG, and the insulating layers 131 and 170 are located between the source SE and the drain DE and the semiconductor layer CH, The drain DE is electrically connected to the drain region C1 of the semiconductor layer CH, and the source SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switching element 180 may be a top gate type thin film transistor.

In some embodiments, the switch element 180 may include a semiconductor layer CH, a source SE, a drain DE, a top gate TG, and a bottom gate BG, wherein the semiconductor layer CH is located between the bottom gate BG and the top gate TG, The insulating layer 121 is located between the bottom gate BG and the semiconductor layer CH, the insulating layer 131 is located between the semiconductor layer CH and the top gate TG, the insulating layer 170 is located between the source SE and the drain DE and the top gate TG, and is insulated The layers 131 and 170 are located between the source SE and the drain DE and the semiconductor layer CH, the semiconductor layer CH is located between the bottom gate BG and the top gate TG, and the drain DE is electrically connected to the drain region C1 of the semiconductor layer CH , the source SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switching element 180 may be a double gate thin film transistor.

In some embodiments, the switching element 180 may include a semiconductor layer CH, a source SE, a drain DE, and a bottom gate BG, wherein the insulating layer 121 is located between the bottom gate BG and the semiconductor layer CH, and the insulating layers 131 and 170 are located between Between the source SE, the drain DE and the semiconductor layer CH, the drain DE is electrically connected to the drain region C1 of the semiconductor layer CH, and the source SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switching element 180 may be a bottom gate thin film transistor.

In this embodiment, the sensing element 190 may be located on one side of the switching element 180, and the sensing element 190 may include an upper electrode TE, a lower electrode BE, and a photoelectric conversion layer PN, wherein the upper electrode TE overlaps the lower electrode BE, and the upper electrode TE and the bottom electrode BE are electrically independent from each other, and the photoelectric conversion layer PN is located between the top electrode TE and the bottom electrode BE; the bottom electrode BE is electrically connected to the source SE, and the bottom electrode BE and the top gate TG belong to the same film layer ; The upper electrode TE is electrically connected to the common electrode CM, and the common electrode CM and the source SE belong to the same film layer. In this way, the sensing device 10 can have a structure integrating the switching element 180 and the sensing element 190 .

In some embodiments, the photoelectric conversion layer PN is disposed on the lower electrode BE, and the photoelectric conversion layer PN may completely overlap the lower electrode BE. In other words, the orthographic projection of the photoelectric conversion layer PN on the substrate 110 may completely fall into the orthographic projection of the bottom electrode BE on the substrate 110 . In some embodiments, the distance S1 between the sidewall of the photoelectric conversion layer PN and the sidewall of the bottom electrode BE may be 2 μm to 5 μm, for example, about 3 μm or about 4 μm. In some embodiments, the upper electrode TE may completely overlap the photoelectric conversion layer PN. In other words, the orthographic projection of the upper electrode TE on the substrate 110 can completely fall into the orthographic projection of the photoelectric conversion layer PN on the substrate 110 . In some embodiments, the distance S2 between the sidewall of the upper electrode TE and the sidewall of the photoelectric conversion layer PN may be 0.5 μm to 3 μm, for example, about 1 μm or about 2 μm.

In some embodiments, the sensing device 10 may further include a scan line SL, the scan line SL may be electrically connected to the bottom gate BG, and the scan line SL and the bottom gate BG may belong to the same film layer. In addition, the sensing device 10 may further include a data line DL, which may be electrically connected to the drain DE, and the data line DL may belong to the same film layer as the source SE and the drain DE. In this way, there are at least insulating layers 121, 131, and 170 between the scan line SL and the data line DL, so the distance between the scan line SL and the data line DL at the intersection can be increased, thereby reducing the distance between the scan line SL and the data line DL. Parasitic capacitance, thereby improving the problem of electrostatic discharge (ESD). In some embodiments, in the normal direction Dz of the substrate 110, the distance S3 between the scan line SL and the data line DL is 3,000-12,000 Å, preferably 5,000-10,000 Å, such as about 6,000 Å or 8,000 Å, But the present invention is not limited thereto.

In the following, other embodiments of the present invention are continued to be described using FIGS. 2A to 2C , and the component numbers and related contents of the embodiment in FIGS. 1A to 1G are used, wherein the same or similar symbols are used to represent the same or similar components, And the description of the same technical content is omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and details are not repeated here.

FIG. 2A is a schematic partial top view of a sensing device 20 according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line A-A' of Fig. 2A. Fig. 2C is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A. In order to make the drawing more concise, the substrate 110 and the insulating layers 121 , 131 , 170 are omitted in FIG. 2A .

In this embodiment, the sensing device 20 may include: a substrate 110 , a switching element 280 , a sensing element 190 and a common electrode CM, and the switching element 280 , the sensing element 190 and the common electrode CM are all disposed on the substrate 110 . The sensing element 190 includes an upper electrode TE, a lower electrode BE and a photoelectric conversion layer PN, wherein the upper electrode TE overlaps the lower electrode BE, and the photoelectric conversion layer PN is located between the upper electrode TE and the lower electrode BE. The bottom electrode BE may be electrically connected to the source SE of the switch element 280 through, for example, the via hole V31 . The common electrode CM is located on the upper electrode TE, and the upper electrode TE may be electrically connected to the common electrode CM through, for example, the via hole V41.

The main difference between the sensing device 20 shown in FIGS. 2A to 2C and the sensing device 10 shown in FIG. 1G is that the switching element 280 of the sensing device 20 includes at least a semiconductor layer CH and a gate GE, and the gate GE surrounding the semiconductor layer CH.

For example, in this embodiment, the switch element 280 may include a semiconductor layer CH, a source SE, a drain DE and a gate GE, and the gate GE may include a top gate TG and a bottom gate BG. The insulating layers 121 and 131 wrap the semiconductor layer CH therebetween, and the insulating layer 121 is located between the bottom gate BG and the semiconductor layer CH, and the insulating layer 131 is located between the semiconductor layer CH and the top gate TG. The insulating layer 170 is located between the source SE and the drain DE and the top gate TG, and the insulating layers 131 and 170 are located between the source SE and the semiconductor layer CH and between the drain DE and the semiconductor layer CH. The region overlapping the top gate TG in the semiconductor layer CH is the channel region Cc, the region not overlapping the top gate TG in the semiconductor layer CH is the drain region C1 and the source region C2, and the channel region Cc connects the drain region C1 and the source The region C2, and the drain region C1 and the source region C2 may have lower resistance than the channel region Cc. The drain DE can be electrically connected to the drain region C1 through the through hole V11 , and the source SE can be electrically connected to the source region C2 through the through hole V21 .

Specifically, the semiconductor layer CH may have a length Lc along a direction Dx, the semiconductor layer CH has a width Wc along a direction Dy, and the direction Dx is substantially perpendicular to the direction Dy. The top gate TG is located on the insulating layer 131, the length Lt of the top gate TG in the direction Dy and the length Lb of the bottom gate BG in the direction Dy are both greater than the width Wc of the semiconductor layer CH, and the length Lb of the bottom gate BG is greater than the length Lt of the top gate TG, therefore, the top gate TG can extend along the direction Dy to cross both sides of the semiconductor layer CH, and the top gate TG can also extend along the two side walls of the insulating layers 121, 131 extending down to the bottom gate BG, so that the top gate TG is physically connected to the bottom gate BG to form a ring-shaped gate GE, and the top gate TG and the bottom gate BG surround the semiconductor layer CH. In this way, the gate GE can help prevent hydrogen ions in the reaction gas from entering the semiconductor layer CH during the formation of the photoelectric conversion layer PN, so that the sensing device 20 has good reliability. In addition, the ring gate GE can also increase the carrier mobility of the semiconductor layer CH, for example, increase the carrier mobility of the semiconductor layer CH by 2 times. In this way, the sensing device 20 can provide a higher frame rate, for example, provide high-frequency dynamic sensing images higher than 7 Hz.

In some embodiments, in the direction Dy, the distance S4 between the sidewall of the bottom gate BG and the sidewall of the top gate TG may be 0 to 3 μm, for example about 1 μm or about 2 μm. In some embodiments, the central axis of the ring gate GE may be located in the semiconductor layer CH.

In some embodiments, the top gate TG and the bottom gate BG have a width Wg in the direction Dx, and the width Wg may be 2 μm to 10 μm, such as 4 μm, 6 μm or 8 μm. In some embodiments, the minimum distance S5 between the orthographic projection of the top gate TG on the substrate 110 and the orthographic projection of the source SE on the substrate 110 may be 0 to 5 μm, preferably 1 μm to 3 μm, such as about 1.5 μm, 2μm or 2.5μm.

To sum up, the manufacturing method of the sensing device of the present invention forms the common electrode and the source electrode with the same film layer, and forms the bottom electrode and the top gate electrode with the same film layer, so the switching element and the sensing device can be integrated. The manufacturing process of the element enables the sensing device to have a structure integrating the switching element and the sensing element, and can reduce the number of process masks and simplify the process steps. Furthermore, the manufacturing method of the sensing device of the present invention uses the blanketed conductive layer to block hydrogen ions, which can effectively prevent hydrogen ions from entering the semiconductor layer, so as not to affect the reliability of the sensing device. In addition, the sensing device of the present invention has reduced scan line and data line parasitic capacitance, and thus can also improve ESD. In addition, the sensing device of the present invention also utilizes the ring gate to prevent hydrogen ions from entering the semiconductor layer, so that the sensing device can have good reliability.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 20: Sensing device 110: Substrate 111: surface 120, 121, 131, 170: insulation layer 140: conductor layer 150: Semiconductor stack 160: transparent electrode layer 180, 280: switching elements 190: sensing element A-A', B-B': hatching B1, B2, T1, T2: ends BE: Bottom electrode BG: bottom gate C1: drain area C2: source region Cc: channel area CH: semiconductor layer CM: common electrode DE: drain DL: data line Dx, Dy, Dz: directions GE: Gate Lb, Lc, Lt: Length PN: photoelectric conversion layer S1, S2, S3, S4: Spacing S5: Minimum spacing SE: source SL: scan line TE: upper electrode TG: top gate V1, V2, V3, V4: through holes V11, V21, V31, V41: Through hole W21, W22, W31, W32: side walls Wg, Wc: Width Wp, Wt: size

1A to FIG. 1G are partial cross-sectional schematic diagrams and partial top view schematic diagrams of the steps of the manufacturing method of the sensing device 10 according to an embodiment of the present invention, wherein FIG. 1G is a schematic diagram of the sensing device 10 according to an embodiment of the present invention. Partial cross-sectional schematic diagram. FIG. 2A is a schematic partial top view of a sensing device 20 according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line A-A' of Fig. 2A. Fig. 2C is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A.

10: Sensing device

110: Substrate

111: surface

121,131,170: insulating layer

180: switch element

190: sensing element

BE: Bottom electrode

BG: bottom gate

C1: drain area

C2: source region

Cc: channel area

CH: semiconductor layer

CM: common electrode

DE: drain

DL: data line

Dx, Dz: direction

PN: photoelectric conversion layer

S1, S2, S3: Spacing

SE: source

SL: scan line

TE: upper electrode

TG: top gate

V1, V2, V3, V4: through holes

Claims (19)

A sensing device comprising: Substrate; a switching element on the substrate and including a source; The sensing element is located on one side of the switching element and includes: a lower electrode electrically connected to the source; a photoelectric conversion layer located on the lower electrode; and an upper electrode located on the photoelectric conversion layer; and The common electrode is electrically connected to the upper electrode and belongs to the same film layer as the source. The sensing device according to claim 1, wherein the switching element further includes a top gate, and the top gate and the bottom electrode belong to the same film layer. The sensing device according to claim 2, wherein the switching element further includes a semiconductor layer and a bottom gate, and the semiconductor layer is located between the bottom gate and the top gate. The sensing device as claimed in claim 3, wherein the bottom gate and the top gate surround the semiconductor layer. The sensing device according to claim 1 further includes a data line, and the data line and the source electrode belong to the same film layer. The sensing device according to claim 5 further includes a scanning line, and the distance between the scanning line and the data line is 3,000-12,000 Å in the normal direction of the substrate. The sensing device according to claim 1, wherein the photoelectric conversion layer completely overlaps the lower electrode, and the upper electrode completely overlaps the photoelectric conversion layer. A sensing device comprising: Substrate; A switching element is located on the substrate and includes: a semiconductor layer; and a gate surrounding the semiconductor layer; and The sensing element is located on the substrate and includes: lower electrode; an upper electrode overlapping the lower electrode; and The photoelectric conversion layer is located between the upper electrode and the lower electrode. The sensing device as claimed in claim 8, wherein the gate includes a top gate and a bottom gate, and the top gate and the bottom electrode belong to the same film layer. The sensing device according to claim 9 further includes a scan line, and the scan line and the bottom gate belong to the same film layer. The sensing device as claimed in claim 8, wherein the switching element further includes a source, and the source is electrically connected to the semiconductor layer and the lower electrode. The sensing device according to claim 11, wherein the minimum distance between the orthographic projection of the gate on the substrate and the orthographic projection of the source on the substrate is 0 to 5 μm. The sensing device according to claim 11 further includes a common electrode electrically connected to the upper electrode and belonging to the same film layer as the source. A method of manufacturing a sensing device, comprising: forming a semiconductor layer on the substrate; forming a first insulating layer on the semiconductor layer; forming a blanket conductor layer on the first insulating layer and the substrate; forming a blanket semiconductor stack on the conductor layer; forming a blanket transparent electrode layer on the semiconductor stack; patterning the transparent electrode layer to form an upper electrode; patterning the semiconductor stack to form a photoelectric conversion layer; and The conductive layer is patterned to form a bottom electrode and a top gate. The method for manufacturing a sensing device according to claim 14, further comprising forming a bottom gate and a scan line on the substrate before forming the semiconductor layer. The method for manufacturing a sensing device as claimed in claim 15, wherein the top gate is physically connected to the bottom gate. The method for manufacturing a sensing device as claimed in claim 15, wherein the top gate and the bottom gate surround the semiconductor layer. The method for manufacturing a sensing device according to claim 14, further comprising forming a second insulating layer on the substrate after patterning the conductive layer, and a plurality of through holes in the second insulating layer Two ends of the semiconductor layer, the lower electrode and the upper electrode are respectively exposed. The method for manufacturing a sensing device according to claim 18, further comprising forming a source, a drain, a common electrode, and a data line on the second insulating layer after forming the second insulating layer, and the source The electrode is electrically connected to one end of the semiconductor layer and the lower electrode, the drain is electrically connected to the other end of the semiconductor layer, and the common electrode is electrically connected to the upper electrode.

Images