WO2022142430A1

WO2022142430A1 - Preparation method for flat panel detector

Info

Publication number: WO2022142430A1
Application number: PCT/CN2021/115934
Authority: WO
Inventors: 解海艇; 金利波
Original assignee: 上海奕瑞光电子科技股份有限公司
Priority date: 2020-12-28
Filing date: 2021-09-01
Publication date: 2022-07-07
Also published as: CN112736104A; CN112736104B

Abstract

The present invention provides a preparation method for a flat panel detector. A single or stacked metal isolation layer is used to isolate an AOS TFT, so that the damage to an amorphous oxide channel layer in the AOS TFT is avoided in the subsequent film forming process of a photodiode (PD), and the performance degradation of the amorphous oxide channel layer is avoided, and thus the quality and performance of the flat panel detector are improved. Impurity ions in a substrate can be reduced into a device by means of a buffer layer, and the influence of the stress of a thin film or the substrate on the device can be reduced. Two gate electrodes of the dual AOS TFT and a bottom electrode of the PD can be formed at the same time after the metal isolation layer is patterned once; the reserved metal isolation layer is directly used as the bottom electrode of the PD, which facilitates the reduction of the Lag value of the flat panel detector, the formed dual AOS TFT having the vertical structure is insensitive to the thin film stress in the flat panel detector, and the dynamic reading frame rate of the flat panel detector is improved.

Description

Preparation method of flat panel detector

technical field

The invention belongs to the field of flat panel detectors, and relates to a preparation method of a flat panel detector.

Background technique

Digital Radio Graphy (DR) is a new technology of X-ray photography developed in the 1990s. It has become the leading direction of digital X-ray photography technology, and has been recognized by clinical institutions and imaging experts all over the world. Its application in medical imaging diagnostic imaging, industrial flaw detection, security inspection and other fields is becoming more and more extensive. In the application of X-ray radiation imaging, the area of the flat panel detector is generally required to reach 43cm × 43cm. The design of the X-ray detector TFT panel has its function implementation played a big role.

In general, a flat panel detector is a detector that uses semiconductor technology to convert X-ray energy into electrical signals to generate X-ray images. The flat panel detector is composed of millions or even tens of millions of pixel unit circuits, which are generally composed of thin film transistors (TFTs) and photodiodes (PDs). The traditional flat panel detector is mainly an amorphous silicon flat panel detector, and its pixel unit circuit is composed of a-Si TFT and a-Si PD.

With the development of society, the requirements for TFT read rate are getting higher and higher. Compared with traditional a-Si TFT, amorphous oxide (AOS) TFT has higher field-effect mobility (about a-Si TFT). The advantages of Si TFT mobility are more than 10 times) and lower off-state current (fA level), which can be applied to the preparation of dynamic flat panel detectors with the advantages of high frame rate and low noise.

However, when fabricating a flat panel detector composed of AOS TFT and a-Si PD array, the a-Si PD array film formation process will adversely affect the AOS TFT, which will lead to the deterioration of the performance of the AOS TFT and reduce the product yield. .

Therefore, it is necessary to provide a preparation method of a flat panel detector.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a flat panel detector, which is used to solve the problem that the a-Si PD array film-forming process has an adverse effect on AOS TFTs when preparing a flat panel detector in the prior art. The problem of adversely affecting the performance of AOS TFTs.

In order to achieve the above purpose and other related purposes, the present invention provides a preparation method of a flat panel detector, comprising the following steps:

provide a substrate;

forming a buffer layer on the substrate;

forming a source electrode on the buffer layer;

forming a patterned insulating isolation layer and a drain electrode on the source electrode to expose part of the source electrode;

forming an amorphous oxide film, and patterning the amorphous oxide film to form a first amorphous oxide channel layer and a second amorphous oxide channel layer in contact with the source electrode and the drain electrode;

forming a gate insulating layer, the gate insulating layer covering the first amorphous oxide channel layer and the second amorphous oxide channel layer, and exposing part of the source electrode;

forming a metal isolation layer covering the gate insulating layer and the exposed source electrode;

forming a photodiode and a transparent top electrode on the metal isolation layer;

patterning the photodiode and transparent top electrode to expose a portion of the metal isolation layer;

patterning the metal isolation layer to form a first gate electrode and a second gate electrode to obtain a first TFT and a second TFT, and a bottom electrode of a photodiode;

forming a first protective layer covering the first TFT, the second TFT, the photodiode and the transparent top electrode;

patterning the first protective layer to form a common electrode through hole exposing the transparent top electrode;

forming a metal layer, patterning the metal layer, forming a common electrode and a light shielding layer, the light shielding layer is located above the first TFT and the second TFT, and the common electrode fills the common electrode through hole;

forming a second protective layer, the second protective layer covering the common electrode and the light shielding layer;

A scintillator layer is formed, and the scintillator layer covers the second protective layer.

Optionally, the buffer layer includes one or a combination of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer; The thickness range is

Optionally, the insulating isolation layer includes one or a combination of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer; the insulating isolation layer The thickness of the layer ranges from

Optionally, the source electrode includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; the thickness of the source electrode ranges from

The drain electrode includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; the thickness of the drain electrode is in the range of

Optionally, the amorphous oxide film includes one or a combination of a-IGZO layer, a-IZO layer, a-IGO layer, In ₂ O ₃ layer, ZnO layer, a-IZTO layer and AlZnO _x layer ; the thickness range of the amorphous oxide film is

Optionally, the gate insulating layer includes one or a combination of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer; the gate insulating layer The thickness of the layer ranges from

Optionally, the metal isolation layer includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal isolation layer is

The metal layer includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is

Optionally, the first protective layer includes one or a combination of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer; The thickness of a protective layer is in the range of

The second protective layer includes one or a combination of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer; The thickness range is

Optionally, the transparent top electrode includes an ITO layer; the thickness of the transparent top electrode is in the range of

Optionally, the scintillator layer includes one or a combination of a CsI layer, a GOS layer and a perovskite layer.

As mentioned above, the preparation method of the flat panel detector of the present invention has the following beneficial effects:

The invention adopts one-layer or stacked metal isolation layers to isolate the AOS TFT, which can avoid damage to the amorphous oxide channel layer in the AOS TFT in the subsequent process of preparing the photodiode film, and avoid the amorphous oxide. The performance of the channel layer is degraded, thereby improving the quality and performance of the flat panel detector; the buffer layer can reduce the entry of impurity ions in the substrate into the device, and can reduce the influence of the stress of the film or substrate on the device; in the metal isolation layer After one patterning, the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be formed at the same time, and directly using the remaining metal isolation layer as the bottom electrode of the PD is beneficial to reduce the Lag value of the flat panel detector, and the formed The dual AOS TFTs with vertical structure are insensitive to the film stress in the flat panel detector, which improves the dynamic reading frame rate of the flat panel detector.

Description of drawings

FIG. 1 is a schematic diagram of a manufacturing process flow diagram of a flat panel detector in an embodiment of the present invention.

FIG. 2 to FIG. 14 are schematic structural diagrams of each step of preparing a flat panel detector in the embodiment.

Component label description

110 Substrate

120 buffer layer

130 source electrode

140 insulation barrier

150 drain electrode

161 The first amorphous oxide channel layer

162 The second amorphous oxide channel layer

170 gate insulating layer

180 Metal isolation layer

181 first gate electrode

182 Second gate electrode

183 Bottom electrode of photodiode

190 photodiodes

111 Transparent top electrode

1111 Common electrode through hole

112 The first protective layer

1131 Common electrode

1132 shading layer

114 Second protective layer

115 scintillator layer

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below," "below," "below," "below," "above," "on," etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. In addition, when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between" means including both endpoints.

In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and the number of components in the actual implementation. For dimension drawing, the type, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complicated.

Referring to FIG. 1 to FIG. 14 , this embodiment provides a method for fabricating a flat panel detector. This embodiment uses a one-layer or stacked metal isolation layer to isolate the AOS TFT, which can avoid subsequent photodiode film formation processes. , causing damage to the amorphous oxide channel layer in the AOS TFT, avoiding the performance degradation of the amorphous oxide channel layer, thereby improving the quality and performance of the flat panel detector; the buffer layer can reduce the impurity ions in the substrate entering the device. and can reduce the influence of the stress of the film or the substrate on the device; after the metal isolation layer is patterned once, the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be simultaneously formed, and the remaining metal can be directly The isolation layer as the bottom electrode of the PD is beneficial to reduce the Lag value of the flat panel detector, and the dual AOS TFTs with vertical structure formed are not sensitive to the film stress in the flat panel detector, which improves the dynamic reading frame rate of the flat panel detector. .

The preparation method of the present embodiment will be further described below in conjunction with the accompanying drawings, specifically including:

Referring to FIG. 2 , a substrate 110 is provided first, and a buffer layer 120 is formed on the substrate 110 .

Specifically, the substrate 110 may include a glass substrate or a flexible PI, PET substrate, etc., but is not limited thereto. An insulating layer with one or more structures can be prepared by CVD, PVD or solution method to serve as the buffer layer 120, and the buffer layer 120 can include a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, and an AlO _x layer. layer, ZrO _x layer, TiO _x layer and organic insulating layer, one or a combination; the thickness range of the buffer layer 120 may be

like

and

Wait. The buffer layer 120 does not need to be patterned, which can reduce the entry of impurity ions in the substrate 110 into the device, and can reduce the influence of the stress of the film or the substrate on the device. The specific material, structure, thickness, and formation method of the buffer layer 120 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 3 , a source electrode 130 is formed on the buffer layer 120 .

Specifically, one or more layers of metal thin films can be deposited by PVD, and then the metal thin films can be patterned by dry or wet etching to form the source electrode 130. The source electrode 130 can include Mo layer, Al layer, AlNb layer, Cr layer, Cu layer, Ti layer and Nb layer or combination; the thickness range of the source electrode 130 may be

like

and

Wait. The specific material, structure, thickness, and forming method of the source electrode 130 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIGS. 4 and 5 , a patterned insulating isolation layer 140 is formed on the source electrode 130 , and a patterned drain electrode 150 is formed on the insulating isolation layer 140 to expose part of the source electrode 130 .

Specifically, referring to FIG. 4, the insulating isolation layer 140 may be prepared _by CVD, PVD or solution method, and the insulating isolation layer 140 may include a _SiOx layer, a _SiNx layer, a _SiOxNy layer, an _AlOx layer, a ZrO layer One or a combination of _x layer, TiO _x layer and organic insulating layer; the thickness of the insulating isolation layer 140 can be

like

and

Wait. The specific material, structure, thickness, and forming method of the insulating isolation layer 140 can be selected according to requirements, which are not excessively limited here. Next, one or more metal thin films can be deposited by PVD method to serve as the drain electrode 150 of the subsequent TFT. The drain electrode 150 can include a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, and a Ti layer. and one or a combination of Nb layers; the thickness range of the drain electrode 150 may be

like

and

Wait. The specific material, structure, thickness, and forming method of the drain electrode 150 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 5 , dry or wet etching is used to first obtain the patterned drain electrode 150 , and then obtain the patterned insulating isolation layer 140 to expose part of the source electrode 130 and facilitate subsequent electrical connect.

Next, referring to FIG. 6 , an amorphous oxide film is formed, and the amorphous oxide film is patterned to form a first amorphous oxide channel layer 161 and a first amorphous oxide channel layer 161 in contact with the source electrode 130 and the drain electrode 150 . Two amorphous oxide channel layers 162 .

Specifically, PVD method or solution method can be used to prepare one or more layers of the amorphous oxide film, and wet etching or dry etching method is used to pattern the amorphous oxide film to form the first An amorphous oxide channel layer 161 and a second amorphous oxide channel layer 162, wherein the amorphous oxide film may include a-IGZO layer, a-IZO layer, a-IGO layer, In ₂ O One or a combination of ₃ layers, ZnO layer, a-IZTO layer and AlZnO _x layer; the thickness range of the amorphous oxide film can be

like

and

and so on; it can be seen that the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 can be formed with the same material and the same thickness. The specific material, structure, thickness, and formation method of the amorphous oxide thin film can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 7 , a gate insulating layer 170 is formed, the gate insulating layer 170 covers the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 , and exposes part of the source electrode 130.

Specifically, one or more layers of gate insulating layer films may be prepared by CVD, PVD or solution method, and then patterned by dry or wet etching to form exposed portions of the source electrode 130 The gate insulating layer 170 of the TFT, the gate insulating layer 170 may include one of a SiO _x layer, a SiN _x layer, a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer kind or combination; the thickness range of the gate insulating layer 170 is

like

and

etc., the specific material, structure, thickness, and formation method of the gate insulating layer 170 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 8 , a metal isolation layer 180 is formed, the metal isolation layer 180 covers the gate insulating layer 170 and the exposed source electrode 130 , and a photodiode 190 and a transparent top are formed on the metal isolation layer 180 electrode 111 .

Specifically, PVD method can be used to deposit one or more layers of metal films, and then, the amorphous silicon PIN photodiode layer is prepared by CVD method on it, and finally the ITO electrode layer is prepared by PVD method, so as to form the stacked said Metal isolation layer 180 , photodiode 190 and transparent top electrode 111 . The metal isolation layer 180 may include one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal isolation layer 180 may be

like

and

etc., the specific material, structure, thickness, and formation method of the metal isolation layer 180 can be selected according to requirements, which are not excessively limited here. The transparent top electrode 111 can be an ITO layer, but not limited to, and the thickness of the transparent top electrode 111 can be

like

and

etc., the specific material, structure, thickness, and forming method of the transparent top electrode 111 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 9 , the photodiode 190 and the transparent top electrode 111 are patterned to expose part of the metal isolation layer 180 .

Specifically, dry etching or wet etching can be used to first pattern the ITO electrode layer to form the patterned transparent top electrode 111, and then pattern the amorphous silicon PIN photodiode layer. The photodiode 190 is formed patterned. Wherein, in the process of preparing the photodiode 190 and the transparent top electrode 111, due to the existence of the metal isolation layer 180, the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 161 of the TFT can be protected. The role of the crystalline oxide channel layer 162 is to prevent the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 from being affected by the deposition process of the photodiode 190 and avoid the TFT Deterioration of performance.

Next, referring to FIG. 10 , the metal isolation layer 180 is patterned to form a first gate electrode 181 and a second gate electrode 182 to obtain a first TFT and a second TFT, and the bottom electrode 183 of the photodiode 190 .

Specifically, the metal isolation layer 180 can be patterned by dry or wet etching, so that the first gate electrode 181 , the second gate electrode 182 and the photodiode 190 can be simultaneously formed by one patterning. The bottom electrode 183 of the photodiode 190 is directly used as the bottom electrode of the photodiode 190 to reduce the complexity of the process; and it is beneficial to reduce the Lag value of the flat panel detector; thus, the first TFT, The second TFT and PD.

Next, referring to FIG. 11 , a first protective layer 112 is formed, the first protective layer 112 covers the first TFT, the second TFT, the photodiode 190 and the transparent top electrode 111 ; and the first protective layer 112 is patterned , forming a common electrode through hole 1111 exposing the transparent top electrode 111 .

Specifically, one or more insulating layer films may be prepared by CVD, PVD or solution method to form the first protective layer 112, and the first protective layer 112 may include a _SiOx layer, a _SiNx layer, a SiOx layer, and a SiOx layer. _One or a combination of the _xNy layer, the _AlOx layer, the _ZrOx layer, the _TiOx layer and the organic insulating layer; to cover the photodiode 190 as a protective layer for the photodiode 190 . Then, it is patterned by wet or dry etching to form the common electrode through hole 1111 exposing part of the transparent top electrode 111 . The thickness range of the first protective layer 112 may be

like

and

etc., the specific material, structure, thickness, and formation method of the first protective layer 112 can be selected according to requirements, which are not excessively limited here.

Next, referring to FIG. 12, a metal layer is formed, and the metal layer is patterned to form a common electrode 1131 and a light shielding layer 1132, the light shielding layer 1132 is located above the first TFT and the second TFT, and the common electrode 1131 The common electrode through hole 1111 is filled.

Specifically, PVD method can be used to prepare a metal thin film with one or several layered structures to form the metal layer, and the metal layer can include one of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer. or a combination; the thickness of the metal layer can be

like

After that, the metal layer can be patterned to form the common electrode 1131 and the light shielding layer 1132, wherein the common electrode 1131 and the light shielding layer 1132 have the same plane, and have the same material and thickness. The material, thickness and formation method of the metal layer are not limited to this, and can be selected as required.

Next, referring to FIG. 13 , a second protective layer 114 is formed, and the second protective layer 114 covers the common electrode 1131 and the light shielding layer 1132 .

Specifically, CVD, PVD or solution method can be used to prepare an insulating layer with a one-layer or stacked-layer structure to form the second protective layer 114, wherein the second protective layer 114 can include a _SiOx layer, a _SiNx layer , one or a combination of a SiO _x N _y layer, an AlO _x layer, a ZrO _x layer, a TiO _x layer and an organic insulating layer. The thickness of the second protective layer 114 can be

like

etc., the material, thickness and formation method of the second protective layer 114 are not limited to this, and can be selected as required.

Next, referring to FIG. 14 , a scintillator layer 115 is formed, and the scintillator layer 115 covers the second protective layer 114 .

Specifically, the scintillator layer 115 may include one or a combination of a CsI layer, a GOS layer, and a perovskite layer, so as to convert X-rays into visible light through the scintillator layer 115 . The material, thickness and formation method of the scintillator layer 115 are not limited to this, and can be selected as required.

To sum up, the preparation method of the flat panel detector of the present invention adopts a single layer or a stacked metal isolation layer to isolate the AOS TFT, which can avoid the subsequent process of preparing the photodiode film formation. The oxide channel layer can cause damage to avoid the performance degradation of the amorphous oxide channel layer, thereby improving the quality and performance of the flat panel detector; the buffer layer can reduce the impurity ions in the substrate entering the device, and can reduce the film or lining The influence of the bottom stress on the device; after the metal isolation layer is patterned once, the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be simultaneously formed, and the remaining metal isolation layer is directly used as the bottom electrode of the PD. It is beneficial to reduce the Lag value of the flat panel detector, and the formed double AOS TFT with vertical structure is not sensitive to the film stress in the flat panel detector, and improves the dynamic reading frame rate of the flat panel detector.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims

A preparation method of a flat panel detector, characterized in that it comprises the following steps:

provide a substrate;

forming a buffer layer on the substrate;

forming a source electrode on the buffer layer;

forming a patterned insulating isolation layer and a drain electrode on the source electrode to expose part of the source electrode;

forming an amorphous oxide film, and patterning the amorphous oxide film to form a first amorphous oxide channel layer and a second amorphous oxide channel layer in contact with the source electrode and the drain electrode;

forming a gate insulating layer, the gate insulating layer covering the first amorphous oxide channel layer and the second amorphous oxide channel layer, and exposing part of the source electrode;

forming a metal isolation layer covering the gate insulating layer and the exposed source electrode;

forming a photodiode and a transparent top electrode on the metal isolation layer;

patterning the photodiode and transparent top electrode to expose a portion of the metal isolation layer;

patterning the metal isolation layer to form a first gate electrode and a second gate electrode to obtain a first TFT and a second TFT, and a bottom electrode of a photodiode;

forming a first protective layer covering the first TFT, the second TFT, the photodiode and the transparent top electrode;

patterning the first protective layer to form a common electrode through hole exposing the transparent top electrode;

forming a metal layer, patterning the metal layer, forming a common electrode and a light shielding layer, the light shielding layer is located above the first TFT and the second TFT, and the common electrode fills the common electrode through hole;

forming a second protective layer, the second protective layer covering the common electrode and the light shielding layer;

A scintillator layer is formed, and the scintillator layer covers the second protective layer.
The method for preparing a flat panel detector according to claim 1 , wherein the buffer layer comprises a SiOx layer, a SiNx layer, a SiOxNy layer, an AlOx layer, a ZrOx layer, a TiOx layer and an organic layer. One or a combination of insulating layers; the thickness of the buffer layer ranges from
The method for manufacturing a flat panel detector according to claim 1 , wherein the insulating isolation layer comprises a SiOx layer, a SiNx layer, a SiOxNy layer, an AlOx layer, a ZrOx layer, a TiOx layer and a One or a combination of organic insulating layers; the thickness of the insulating insulating layer ranges from
The method for preparing a flat panel detector according to claim 1, wherein the source electrode comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; The thickness of the source electrode is in the range of
The drain electrode includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; the thickness of the drain electrode is in the range of
The method for preparing a flat panel detector according to claim 1, wherein the amorphous oxide film comprises a-IGZO layer, a-IZO layer, a-IGO layer, In 2 O 3 layer, ZnO layer, One or a combination of a-IZTO layer and AlZnO x layer; the thickness of the amorphous oxide film is in the range of
The method for preparing a flat panel detector according to claim 1 , wherein the gate insulating layer comprises a SiOx layer, a SiNx layer, a SiOxNy layer, an AlOx layer, a ZrOx layer, a TiOx layer and a One or a combination of organic insulating layers; the thickness of the gate insulating layer ranges from
The method for manufacturing a flat panel detector according to claim 1, wherein the metal isolation layer comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the metal isolation layer thickness of
The metal layer includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is
The method for manufacturing a flat panel detector according to claim 1 , wherein the first protective layer comprises a SiOx layer, a SiNx layer, a SiOxNy layer, an AlOx layer, a ZrOx layer, and a TiOx layer and one or a combination of the organic insulating layer; the thickness of the first protective layer is in the range of
The second protective layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer; The thickness range is
The method for preparing a flat panel detector according to claim 1, wherein the transparent top electrode comprises an ITO layer; the thickness of the transparent top electrode is in the range of
The method for preparing a flat panel detector according to claim 1, wherein the scintillator layer comprises one or a combination of a CsI layer, a GOS layer and a perovskite layer.