JP2002270847A - Liquid crystal image display and manufacturing method semiconductor device for the image display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize lowering of the resistance of electrode wirings. SOLUTION: In the method of manufacture of an active matrix substrate having an inverse stagger structure TFT, after a gate electrode 11 which also acts as a scanning line has bean formed by the patterning process, a gate insulation film 30, a channel semiconductor layer 31 and a low resistance semiconductor layer are laminated. The channel semiconductor layer 31, low resistance semiconductor layer and gate insulation layer 30 are removed by the etching leaving a TFT forming region, and the scanning line 11 is exposed. A low resistance metal 71 is formed with the plating on the exposed scanning line 11, and moreover an organic insulation film 72 is formed by electrodeposition process. Next, a metal wiring 21 of three layers is formed on the low resistance semiconductor layer as the source/drain electrode. Thereafter, the metal wiring 21 is used as the mask for anode oxidation, to form an insulation film 66 on the low resistance semiconductor layer of an aperture and on a part of the channel semiconductor layer 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a color image display function, and more particularly to an active liquid crystal display.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of a large amount of television images and various image display devices on a commercial basis with 5 to 50 cm diagonal liquid crystal panels. ing. Further, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0003] These liquid crystal image display devices (liquid crystal panels)
Represents 200 to 1200 scanning lines and 200 to 16 signal lines
A matrix organization of about 00 lines is generally used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 31 shows a state in which a driving circuit is mounted on a liquid crystal panel. A driving signal is applied to one electrode terminal group 6 of scanning lines formed on one transparent insulating substrate constituting the liquid crystal panel 1, for example, a glass substrate 2. (Chip-On-Glass) that connects the semiconductor integrated circuit chip 3 that supplies the semiconductor chip 3 with a conductive adhesive.
s) Terminals of gold or solder-plated copper foil based on, for example, polyimide resin thin film (not shown)
To fix the TCP film 4 having the following characteristics to the electrode terminal group 5 of the signal line by pressing with a suitable adhesive containing a conductive medium.
An electric signal is supplied to the image display unit by a mounting means such as a (Tape-Carrier-Package) method. Here, for the sake of convenience, two mounting schemes are shown at the same time, but one of them is actually selected as appropriate.

[0005] Reference numerals 7 and 8 denote an image display portion located substantially at the center of the liquid crystal panel 1 and electrode terminals 5 and 6 for signal lines and scanning lines.
Between the terminal groups 5, 6
It is not necessary to be made of the same conductive material as that described above. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface.

FIG. 32 shows an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 31).
Is a scanning line, 12 (7 in FIG. 31) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all the liquid crystal cells 13 drawn by dotted lines is formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a storage capacitance line that is a common bus of the storage capacitance 15.

FIG. 33 is a sectional view of a main part of an image display section of the liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of resinous fibers, beads or columnar spacers (not shown). ) Is formed at a predetermined distance of about several μm, and the gap is defined by the glass substrate 9.
Is a closed space sealed with a sealing material made of an organic resin and a sealing material (both not shown) at the peripheral edge of the liquid crystal 17, and the liquid crystal 17 is filled in this closed space.

In order to realize a color display, an organic thin film layer having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is attached on the closed space side of the glass substrate 9. Color display function.
In that case, the glass substrate 9 is also called a color filter (Colo
The abbreviation rFilter is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials, and usually require two polarizing plates 19. Although not shown, a rear light source is arranged as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 located between the signal line 12 and the drain electrode 21 will be described later in detail. Colored layers 1 adjacent on color filter 9
8 and a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technology fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (referred to as an etch stop type). FIG. 34 is a plan view of a unit picture element of an active substrate (semiconductor device for an image display device) constituting a conventional liquid crystal panel. FIG. 35 is a cross-sectional view taken along line AA ′ of FIG. Will be briefly described below. The projection 50 formed on the scanning line 11
A region 51 where the pixel electrode 22 and the pixel electrode 22 overlap with each other with a gate insulating layer interposed therebetween (a hatched portion inclined downward to the right) forms the storage capacitor 15, but a detailed description thereof is omitted here.

First, as shown in FIG. 35 (a), an insulating substrate having high heat resistance, chemical resistance, and transparency has a thickness of 0.5 to 0.5 mm.
A glass substrate 2 having a thickness of about 1.1 mm, for example, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a product 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo, or the like, or an alloy or silicide thereof, a gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, AL (aluminum) is used as the material of the scanning line. At present, it is also a general technique to laminate with Cr, Ta, Mo or silicide thereof, or to add an oxide layer (AL2O3) to the surface of AL by anodic oxidation. In many cases.

Next, as shown in FIG. 35 (b), PCVD (Plasma assisted Chemical V
a first SiNx (silicon nitride) layer serving as a gate insulating layer and a first amorphous silicon (a-Si) layer serving as an insulated gate transistor channel containing almost no impurities by using an ap or deposition apparatus. And a second SiNx layer serving as an insulating layer for protecting the channel and three types of thin film layers, for example,
0.3-0.05-0.1μm film thickness
1, 32.

As a know-how technique, when forming a gate insulating layer, another type of insulating layer (for example, TaOx or SiO2) is used.
Etc. or laminated with AL2O3) mentioned above, or S
In many cases, yield improvement measures such as providing an iNx layer in two steps and providing a cleaning step in the middle thereof are performed, and the gate insulating layer is not limited to one type or a single layer.

Subsequently, the second amorphous SiNx layer on the gate 11 electrode is selectively made 32 ′ thinner than the gate electrode 11 by a fine processing technique to expose the first amorphous silicon layer 31 as 32 ′. Using a PCVD apparatus, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity
After being deposited with a thickness of about 0.05 μm, the first amorphous silicon layer 31 and the second amorphous silicon layer 33 are formed only on the vicinity of the gate electrode 11 as shown in FIG. The island 3
The gate insulating layer 30 is exposed, leaving the gate insulating layers 1 'and 33'.

Subsequently, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as PT, and the pixel electrode 22 is formed on the gate insulating layer 30 by a fine processing technique. Formed selectively.

Further, as shown in FIG. 35 (e), a selective opening 60 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display section necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 35 (f), a heat-resistant metal thin film layer 34 of, for example, Ti, Cr, Mo, etc.
An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a low-resistance wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by microfabrication technology and insulated including the pixel electrode 22. The drain wiring 21 of the gate type transistor and the source wiring 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 'between the source and drain electrodes is removed to expose the second SiNx layer 32', and the other regions are formed. Then, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the etching of the second amorphous silicon layer 33 'is automatically terminated due to the presence of the second SiNx layer 32' which is a protective layer of the channel. It is.

The source / drain wirings 12 and 21 are formed so as to partially overlap the gate 11 (several μm) so that the insulated gate transistor does not have an offset structure.
Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the mask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about. In addition, at the periphery of the image display unit, including the opening 60 on the scanning line 11, the signal line 12 and the wiring terminal electrode 6 at the same time as the signal line 12, or the wiring connecting the scanning line 11 and the scanning line side electrode terminal 6. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, a SiNx layer having a thickness of about 0.3 to 0.7 μm is applied to the entire surface of the glass substrate 2 by using a PCVD apparatus in the same manner as the gate insulating layer 30 to form a passivation insulating layer. 37, an opening 38 is formed on the pixel electrode 22 as shown in FIG.
Are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the scanning line electrode terminals 6 and the signal line electrode terminals 5 so that most of the electrode terminals are also exposed.

When the wiring resistance of the signal line 12 does not matter, the low-resistance wiring layer 35 made of AL is not always necessary. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is that one is to prevent the reduction of the effective voltage applied to the liquid crystal cell, and the other is that the film quality of the passivation insulating layer 37 is generally poor. This is for avoiding the accumulation of electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film formation temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The manufacturing process of the active substrate described above requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for LCD panel manufacturers in order to reduce the cost of LCD panels and respond to further increases in demand. It is becoming.

FIG. 36 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 37 is a cross-sectional view taken along the line AA 'of FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. The region 52 where the storage capacitance line 16 and the drain wiring 21 overlap with each other with the gate insulating layer interposed therebetween (the hatched portion falling to the right) forms the storage capacitance 15, but a detailed description thereof is omitted here.

First, similarly to the above, as shown in FIG. 37A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT. A metal layer is deposited, and a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by fine processing technology.

Next, as shown in FIG. 37B, a SiNx layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD apparatus, and a first channel serving as an insulated gate transistor channel containing almost no impurities. An amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are sequentially formed in a thickness of, for example, about 0.3-0.2-0.05 μm. 30, 31, and 33 are attached.

Then, as shown in FIG. 37C, the gate insulating layer 3 is formed on the gate electrode 11 by leaving the semiconductor layers composed of the first and second amorphous silicon layers in the form of islands 31 'and 33'.
Expose 0.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as T, for example, a Ti thin film layer 34 as a heat-resistant metal layer having a thickness of about 0.1 μm, an AL thin film layer 35 having a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer,
The drain wiring 21 of the insulated gate transistor and the source wiring 12 also serving as a signal line are selectively formed by a fine processing technique. This selective pattern formation is performed by using the photosensitive resin pattern used for forming the source / drain wiring as a mask, and forming the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', The first amorphous silicon layer 31 ′ is etched in order, and the first amorphous silicon layer 31 ′ is etched leaving about 0.05 to 0.1 μm, so that it is called a channel etch.

Subsequently, after the photosensitive resin pattern is removed, as shown in FIG. 37 (e), a transparent insulating layer is formed on the entire surface of the glass substrate 2 in the same manner as the gate insulating layer.
A passivation insulating layer 37 is formed by applying a SiNx layer having a thickness of about 0.3 μm using a VD device,
An opening 60 is formed at a position where the opening 62 and the electrode terminal 6 of the scanning line 11 are formed, thereby exposing a part of the scanning line 11. Although not shown, an opening is also formed on the position where the electrode terminal 5 of the signal line is formed to expose a part of the signal line 12.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as Then, the picture element electrode 22 is selectively formed to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 60 may be used as the electrode terminal 6, and the electrode terminal 6 ′ made of ITO is selectively formed on the passivation insulating layer 37 including the opening 60 as shown in the figure. It may be formed.

As described above, the five-mask process is one time in the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the step of forming an opening (contact) to a scanning line and the step of forming an opening to a pixel electrode and the step of forming a contact, which were required twice, have been streamlined once, thereby eliminating a total of two photo etching steps. Can be. Further, since the pixel electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a highly transparent resin thin film, for example.
If the pixel electrode 22 is formed to a thickness of 1.5 μm or more, even if the pixel electrode 22 overlaps with the scanning line 11 or the signal line 12, interference due to capacitance is small, and deterioration of image quality can be avoided. There are many advantages such as an improvement in the aperture ratio.

[0031]

SUMMARY OF THE INVENTION The production cost is reduced due to the improvement in productivity due to the increase in the size of the glass substrate.
In addition, the synergistic effect of reducing the parts and materials used as the production volume increases works, and the market for the liquid crystal panel continues to expand. The largest market at the moment is Note P
C and desktop monitors. Due to the rapid growth of mobile phones, small and medium-sized liquid crystal panels are also required for the display section of mobile terminal equipment, which is expected to grow at the same time. In addition to digital home appliances and conventional car navigation systems, small and medium-sized markets are expected to grow significantly.

It is a general principle that the larger the screen size of the liquid crystal panel or the higher the degree of definition, the lower the yield is. Product development is also active, C
Moves to replace RTs have also been in full swing.

Since it is a cumulative response type display element, the liquid crystal panel whose response time was difficult to be less than 16 mS was developed for a liquid crystal material, a new mode such as an OCB liquid crystal,
In addition, the response time has fallen below a few milliseconds due to the new development of an FS (field sequential) type liquid crystal panel that switches and displays the rear light source for each of R, G, and B in a time-sharing manner. The development of liquid crystal panels as substitutes for CRT is gaining momentum.

In these large-screen, high-definition, high-speed response liquid crystal panels, in addition to the above-mentioned high-speed liquid crystal, high-speed switching elements and low resistance of electrode wiring such as scanning lines and signal lines are indispensable technologies. That would not need to be explained.

The present invention has been made in view of the above-mentioned circumstances, and the above-described wiring material is now being replaced by aluminum, which has the lowest resistance, and gold, silver, and copper having lower resistance can be adopted. It is intended to solve these problems. As already mentioned, it is necessary to pursue further reduction in the number of manufacturing steps in order to realize a reduction in the price of liquid crystal panels and to respond to an increase in demand.

However, except for copper, gold and silver are precious metals and are expensive. If a vacuum film forming apparatus, particularly a sputter, is used as in the prior art, the inefficient use of the material is fatal and the cost is high. Since it is unavoidable, it is necessary to develop or adopt a new film forming method.

Further, silver and copper are very easily oxidized, and are liable to cause a problem in electrical contact with another conductive material. In addition, silver atoms are so mobile that they tend to migrate and lack substantial heat resistance. A disadvantage common to all of gold, silver, and copper is that the adhesion to the glass substrate is not good, and it is very easy to peel off. Since this property becomes a dust source even in the vacuum film forming apparatus, it is easily expected that the yield is hardly improved.

[0038]

According to the present invention, the scanning lines and the signal lines made of heat-resistant metal are plated with gold,
Selective growth of silver and copper improves adhesion and material utilization efficiency, and further improves oxidation resistance and heat resistance by forming an organic insulating layer by electrodeposition on this low-resistance metal layer. ing. Japanese Patent Laid-Open No. 4-30243 discloses a prior art for providing a channel protective layer to an insulated gate transistor.
No. 8 discloses a technique for converting a semiconductor layer containing impurities into a silicon oxide layer by anodic oxidation,
In order to effectively passivate only the drain wiring, a process is combined with an anodic oxidation technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in Japanese Patent Application Laid-Open No. 2-216129, which is a prior art. It is intended to realize the rationalization and the lowering of temperature. In order to further reduce the number of steps, the introduction of an organic insulating layer enables the step of islanding the semiconductor layer and the step of forming openings in the gate insulating layer to be rationalized. Further prior art, Japanese Patent Application 5-268
A streamlined process of forming a pixel electrode disclosed in Japanese Patent Publication No. 726 is adopted in conformity with the present invention.

The insulated gate transistor according to the first invention is of a bottom gate type, and is provided between channels and between a source and a source.
A low-resistance metal layer and an organic insulating layer are formed on the gate electrode except under the drain electrode.

The insulated gate transistor according to the second invention is of a top gate type, wherein a low resistance metal layer and an organic insulating layer are formed on a gate electrode.

According to a third aspect of the present invention, there is provided an insulated gate transistor having an insulating layer on a channel, and a low resistance metal layer and an organic insulating layer formed on source / drain electrodes.

With these structures, the basic material and structure of the insulated gate transistor are not changed, so that the risk involved in device development can be minimized and the resistance of the scanning lines and signal lines can be reduced. .

According to a fourth aspect of the present invention, there is provided a liquid crystal image display device, wherein a unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor has a two-dimensional structure. In a liquid crystal image display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a low-resistance metal layer is formed on a scanning line at least in an image display portion. An organic insulating layer is formed.

With this configuration, it is possible to obtain a liquid crystal image display device which can reduce the resistance of the scanning line and can respond to a large screen, high definition, and high speed response.

A liquid crystal image display device according to a fifth aspect of the present invention is a liquid crystal image display device comprising a two-dimensional unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to the drain of the insulated gate transistor. In a liquid crystal image display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, the liquid crystal display device has an insulating layer on the channel of the insulated gate transistor. A low-resistance metal layer and an organic insulating layer are formed on signal lines at least in the image display section.

With this configuration, the resistance of the signal line can be reduced, and a liquid crystal image display device capable of responding to a large screen, high definition, and high speed response can be obtained.

According to a sixth aspect of the present invention, there is provided a liquid crystal image display device, wherein a unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor has a two-dimensional structure. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, an insulated gate transistor comprising a heat-resistant metal layer on the insulating substrate A low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for the gate electrode in the channel formation region. A pair of impurities serving as a source / drain partially overlapping with the gate electrode are formed on the first semiconductor layer containing no impurity on the gate electrode through the gate insulating layer of at least one layer. It is formed no second semiconductor layer, a pair second semiconductor layer above can be anodized in an insulating substrate 1
A source (signal line) / drain wiring composed of at least one metal layer is formed, and a picture element electrode including the drain wiring is formed on the insulating substrate. , An anodic oxide layer is formed on the surface of the first semiconductor layer, and a silicon oxide layer containing no impurities and a silicon oxide layer containing impurities are formed on the first semiconductor layer between the source and drain wirings.

With this configuration, the number of photolithography steps is reduced, and a device can be manufactured using four photomasks. And the resistance of the scanning line, which is the main point of the present invention, is realized. Further, it is not necessary to cover the entire surface of the glass substrate with the passivation insulating layer as in the prior art, and the heat resistance of the insulated gate transistor does not become a problem. In addition, the insulating layer for protecting the channel is obtained by converting an amorphous silicon layer containing impurities into a silicon oxide layer by anodic oxidation, so that a thick amorphous silicon layer containing no impurities serving as a channel layer is formed. Eliminates the need.

The liquid crystal image display device according to the seventh aspect of the present invention provides a scanning line (and a storage capacitor line) also made of a heat-resistant metal layer on an insulating substrate and also serving as a gate electrode of an insulated gate transistor.
And a pixel electrode including the connection layer and a part of the connection layer, and a low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for the gate electrode in the channel formation region. And a second semiconductor layer containing a pair of impurities serving as a source / drain partially overlapping with the gate electrode on the first semiconductor layer containing no impurity on the gate electrode via at least one gate insulating layer. Is formed on the pair of second semiconductor layers and the insulating substrate, the source wiring and the drain wiring including a part of the connection layer are formed of one or more metal layers that can be anodized, and at least an image is formed. An anodized layer is formed on the surface of the source / drain wiring in the display portion, and a silicon oxide layer containing no impurities and a silicon oxide layer containing impurities are formed on the first semiconductor layer between the source / drain wirings. It is characterized by the following.

According to this configuration, the same effects as those of the liquid crystal image display device according to the sixth aspect of the invention can be obtained. Further, the configuration of the signal lines is slightly simplified but may be two layers.

The liquid crystal image display device according to the eighth aspect of the present invention provides a scanning line (and a storage capacitor line) also formed of a heat-resistant metal layer on an insulating substrate and also serving as a gate electrode of an insulated gate transistor.
And a pixel electrode are formed. A low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for a gate electrode in a channel formation region, and one or more gate insulating layers are interposed. A second semiconductor layer containing a pair of impurities, which partially overlaps the gate electrode and becomes a source / drain, is formed on the first semiconductor layer containing no impurities on the gate electrode, and a pair of second semiconductors is formed. A source wiring (signal line) and a drain wiring including a part of the picture element electrode are formed of one or more metal layers capable of being anodized on the layer and the insulating substrate, and at least the source / drain in the image display unit is formed. An anodic oxide layer is formed on a surface of the wiring, and a silicon oxide layer containing no impurity and a silicon oxide layer containing an impurity are formed on the first semiconductor layer between the source and drain wirings.

With this configuration, the same effect as that of the liquid crystal image display device according to the seventh aspect can be obtained.

The liquid crystal image display device according to the ninth aspect of the present invention provides a scanning line (and a storage capacitor line) also formed of a heat-resistant metal layer on an insulating substrate and also serving as a gate electrode of an insulated gate transistor.
Is formed, a low-resistance metal layer and an organic insulating layer are formed on the scanning lines (and the storage capacitor lines) except for the gate electrode in the channel formation region, and the gate electrode is formed on the gate electrode through one or more gate insulating layers. A second semiconductor layer containing a pair of impurities serving as a source / drain is formed on the first semiconductor layer containing no impurities so as to partially overlap with the gate electrode, and anodization is performed on the pair of second semiconductor layers. A source wiring (signal line) and a drain wiring made of one or more possible metal layers are formed, and a picture element electrode including a drain wiring is formed on an insulating substrate, except for at least a picture element electrode in an image display portion. An anodic oxide layer is formed on the surface of the source / drain wiring, and a silicon oxide layer containing no impurities and a silicon oxide layer containing impurities are formed on the first semiconductor layer between the source / drain wirings. Toss .

According to this configuration, the same effect as that of the liquid crystal image display device according to the sixth invention can be obtained.

The liquid crystal image display device according to the tenth aspect is
Similarly, a transparent conductive picture in which a transparent conductive layer and a heat-resistant metal layer are laminated on an insulating substrate, and a scanning line (and a storage capacitor line) also serving as a gate electrode of an insulated gate transistor and a heat-resistant metal layer are partially laminated. A low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for a gate electrode in a channel formation region, and a gate is formed via one or more gate insulating layers. A second semiconductor layer containing a pair of impurities serving as a source and a drain is formed on the first semiconductor layer containing no impurities on the electrode and partially overlaps with the gate electrode, and is formed on the pair of second semiconductor layers. A drain wiring including a laminated portion of a source wiring (signal line) and a heat-resistant metal layer of a transparent conductive picture element electrode formed on at least one metal layer capable of being anodized; Source and drain in the image display Anodized layer is formed on the surface of the wiring, wherein the silicon oxide layer including silicon oxide layer and the impurity containing no impurities in the first semiconductor layer between the source and drain lines are formed.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the seventh
The same effect as that of the liquid crystal image display device according to the invention is obtained,
Low resistance of the scanning line, which is the main point of the present invention, is realized.

The liquid crystal image display device according to the eleventh invention is
Similarly, a scanning line (and a storage capacitor line), which is also formed of a laminate of a transparent conductive layer and a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor, and a transparent conductive pixel electrode are formed on an insulating substrate, and a channel formation region is formed. A low-resistance metal layer and an organic insulating layer are formed on the scanning lines (and the storage capacitor lines) except for the gate electrode, and the first and second gate insulating layers do not contain impurities on the gate electrode. A second semiconductor layer containing a pair of impurities serving as a source and a drain is formed on the semiconductor layer so as to partially overlap with the gate electrode, and a source wiring (signal line) is formed on the pair of second semiconductor layers and the insulating substrate. Line) and the drain wiring including the transparent conductive picture element electrode
An anodic oxide layer is formed on at least the surface of the source / drain wiring in the image display section,
A silicon oxide layer containing no impurity and a silicon oxide layer containing an impurity are formed over the first semiconductor layer between the source and drain wirings.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the seventh
The same effect as that of the liquid crystal image display device according to the invention is obtained,
Not only is the main feature of the present invention that the resistance of the scanning line is reduced, but also the restrictions on the scanning line material are eased.

The liquid crystal image display device according to the twelfth invention is
Similarly, a scanning line (and a storage capacitor line) which is also made of a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor is formed on an insulating substrate. Except for the above, a low-resistance metal layer and an organic insulating layer are formed on a scanning line (and a storage capacitor line), and a first semiconductor layer containing no impurities is formed on a gate electrode through one or more gate insulating layers. A protective insulating layer formed narrower than the gate electrode over the first semiconductor layer; a second semiconductor layer containing impurities on the first semiconductor layer excluding the protective insulating layer; A source (signal line) / drain wiring made of a metal layer is formed on the semiconductor layer of the above, a picture element electrode including the drain wiring is formed on the insulating substrate, and a low resistance is formed on at least the source / drain wiring in the image display portion. Metal layer and organic insulating layer Is formed.

With this configuration, the number of photolithography steps can be reduced, and a device can be manufactured using four photomasks. A protective insulating layer is formed on the channel between the source and the drain in the same manner as in the conventional etch stop type to protect the channel. The layers are covered with layers to reduce the resistance, and an organic insulating layer is formed on these low-resistance metal layers for insulation. The signal lines are also covered with a low-resistance metal layer to reduce the resistance, and an organic insulating layer is also formed on these low-resistance metal layers to provide a passivation function.

A liquid crystal image display device according to a thirteenth invention is:
Similarly, a scanning line (and a storage capacitor line) which is also made of a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor is formed on an insulating substrate. Layer and an organic insulating layer are formed, a first semiconductor layer containing no impurities is formed on the gate electrode via one or more gate insulating layers, and the first semiconductor layer is thinner than the gate electrode on the first semiconductor layer. A protective insulating layer is formed, and a source (signal line) / drain wiring composed of a stack of a second semiconductor layer containing impurities and a metal layer is formed on the first semiconductor layer excluding the protective insulating layer and on the insulating substrate. And a pixel electrode including a drain wiring on the insulating substrate, and a low-resistance metal layer and an organic insulating layer formed on at least the source / drain wiring in the image display unit.

According to this configuration, the same effect as that of the liquid crystal image display device according to the eleventh aspect is obtained, and all the scanning lines are covered with the low-resistance metal layer and the organic insulating layer to reduce the resistance.

The liquid crystal image display device according to the fourteenth invention is
Similarly, a scanning line (and a storage capacitor line) which is also made of a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor is formed on an insulating substrate. A first semiconductor layer containing no impurities on the gate electrode through one or more gate insulating layers, and a source overlaps with the gate electrode and partially overlaps with the first semiconductor layer. A second semiconductor layer containing a pair of impurities serving as a drain is formed, a protective insulating layer narrower than the gate electrode is formed over the first semiconductor layer, and a second insulating layer is formed over the second semiconductor layer and the insulating substrate. A source (signal line) / drain wiring made of a metal layer is formed on the insulating substrate, and a picture element electrode including the drain wiring is formed on the insulating substrate. Insulating layer Wherein the but has been formed.

According to this configuration, the same effect as that of the liquid crystal image display device according to the twelfth invention can be obtained.

A liquid crystal image display device according to a fifteenth aspect of the present invention comprises:
A transparent conductive picture in which a scanning line (and a storage capacitor line), which is also formed of a transparent conductive layer and a heat-resistant metal layer on an insulating substrate and also serves as a gate electrode of an insulated gate transistor, and a heat-resistant metal layer are partially stacked. A low-resistance metal layer and an organic insulating layer are formed on scanning lines (and storage capacitor lines) except for a channel formation region, and at least two or more layers including a plasma protection layer are formed on the gate electrode. A first semiconductor layer that is wider than the gate electrode and does not contain impurities is formed via the gate insulating layer; a protective insulating layer that is narrower than the gate electrode is formed over the first semiconductor layer and partially overlaps the gate electrode; A second semiconductor layer containing a pair of impurities serving as a source and a drain is formed on the protective insulating layer and the first semiconductor layer, and a source made of a metal layer is formed on the second semiconductor layer and on the insulating substrate. Wiring (signal line And a drain wiring including a layered portion of a transparent conductive pixel electrode and a heat-resistant metal layer of a transparent conductive pixel electrode. It is characterized by having been done.

According to this configuration, the same effect as that of the liquid crystal image display device according to the twelfth invention can be obtained.

A liquid crystal image display device according to a sixteenth aspect of the present invention comprises:
Similarly, a scanning line (and a storage capacitor line), which is also formed of a laminate of a transparent conductive layer and a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor, and a transparent conductive pixel electrode are formed on an insulating substrate, and a channel formation region is formed. Except for the above, a low resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitance line), and the gate electrode is formed on the gate electrode through at least two or more gate insulating layers including a plasma protective layer. A first semiconductor layer that is wide and does not contain impurities is formed; a protective insulating layer is formed on the first semiconductor layer to be thinner than the gate electrode; A second layer containing a pair of impurities serving as a source and a drain on the layer;
Is formed on the second semiconductor layer and on the insulating substrate, a source wiring (signal line) made of a metal layer and a drain wiring including a part of the pixel electrode are formed at least in the image display portion. A low resistance metal layer and an organic insulating layer are formed on the source wiring (signal line).

According to this configuration, the same effect as that of the liquid crystal image display device according to the twelfth invention can be obtained, so that not only the main feature of the present invention is to reduce the resistance of the scanning line, but also the restriction on the scanning line material. Has been alleviated.

The liquid crystal image display device according to the seventeenth invention is
Similarly, a scanning line (and a storage capacitor line), which is also formed of a laminate of a transparent conductive layer and a heat-resistant metal layer and also serves as a gate electrode of an insulated gate transistor, and a transparent conductive pixel electrode are formed on an insulating substrate, and a channel formation region is formed. Except for the above, a low-resistance metal layer and an organic insulating layer are formed on a scanning line (and a storage capacitor line), and do not contain impurities through at least two or more gate insulating layers including a plasma protective layer on a gate electrode. A first semiconductor layer and a second semiconductor layer containing a pair of impurities serving as a source and a drain are formed in contact with the first semiconductor layer, and the protective insulating layer is thinner than the gate electrode over the first semiconductor layer. Are formed, a source wiring (signal line) made of a metal layer and a drain wiring including a part of the picture element electrode are formed on the second semiconductor layer and the insulating substrate, and at least the source wiring in the image display unit is formed. (Signal line) on Characterized in that the low-resistance metal layer and the organic insulating layer is formed.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the first
The same effects as those of the liquid crystal image display devices according to the inventions 2 to 15 can be obtained, and the resistance of the scanning line and the signal line, which is the main point of the invention, can be reduced.

The liquid crystal image display device according to the eighteenth aspect is
Similarly, an island-shaped semiconductor layer is formed on one main surface of an insulating substrate, and a first metal layer having an organic insulating layer on the surface thereof via a gate insulating layer on the semiconductor layer is formed by stacking a low-resistance metal layer. A scanning line also serving as a gate electrode is formed, a semiconductor layer into which impurities are implanted except under the gate electrode is used as a source / drain, and an interlayer insulating layer having an opening above the source / drain is formed. Including the opening in the second
A pixel electrode is formed including a source (signal line) / drain wiring and a drain wiring made of a metal layer having a low resistance on at least the source (signal line) wiring in the image display portion and the drain wiring excluding the pixel electrode. A metal layer and an organic insulating layer are formed.

With this configuration, the number of photolithography steps is reduced, and a device can be manufactured using five photomasks.

In a liquid crystal image display device using a top gate transistor as a switching element, the resistance of the scanning line and the signal line, which is the main point of the present invention, is realized.

The liquid crystal image display device according to the nineteenth aspect is
Similarly, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate, and a gate insulating layer is formed on the semiconductor layer. A scanning line also serving as an electrode is formed, a pixel electrode made of a transparent conductive layer is formed on one main surface of the insulating substrate via a gate insulating layer, and a semiconductor layer into which impurities are implanted except under the gate electrode is used as a source. An interlayer insulating layer having an opening on the source / drain and the pixel electrode is formed as a drain, and a signal line (source) including a second metal layer on the interlayer insulating layer and including an opening on the source; A low-resistance metal layer and an organic insulating layer are formed on at least the source line in the image display unit. And

With this configuration, the steps of forming the scanning lines and the picture element electrodes are rationalized, and the device can be manufactured with four photomasks.

The liquid crystal image display device according to the twentieth invention is
Similarly, an island-shaped semiconductor layer is formed on one main surface of an insulating substrate, and a first metal layer having an organic insulating thin film on the surface of the semiconductor layer with a gate insulating layer interposed therebetween is formed by laminating a low-resistance metal layer. A scanning line also serving as a gate electrode is formed.
An interlayer insulating layer having an opening on a source / drain is formed as a drain, and a signal line (source wiring) made of a transparent conductive layer including the opening and a drain wiring serving also as a pixel electrode are formed on the interlayer insulating layer. And a low-resistance metal layer and an organic insulating layer are formed on at least the source wiring in the image display unit.

With this configuration, the steps of forming signal lines and picture element electrodes are rationalized, and devices can be manufactured with four photomasks.

According to a twenty-first aspect, in the liquid crystal image display device according to the fourth to twentieth aspects, the low-resistance metal layer is made of gold, silver or copper.

With this configuration, it is possible to sufficiently reduce the resistance value of both the scanning line and the signal line, so that it is possible to easily cope with a large screen and a high definition, and also, it is possible to provide a liquid crystal image display device which is excellent in high-speed response. Is obtained.

A twenty-second invention is directed to a method of manufacturing a liquid crystal image display device according to the sixth invention, wherein a scanning line comprising a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor is provided. Forming a gate insulating layer, sequentially depositing at least one gate insulating layer, a first amorphous silicon layer containing no impurity and a second amorphous silicon layer containing an impurity, and a channel formation region. Exposing the insulating substrate by selectively removing the second and first amorphous silicon layers and the gate insulating layer except for the step of: exposing at least the exposed scanning lines and the gate electrodes in the image display unit; Forming a low-resistance metal layer and an organic insulating layer, and, after depositing at least one metal layer capable of being anodized, including a second amorphous silicon layer so as to partially overlap the gate electrode; Source on board (signal line)
A step of forming a drain wiring, a step of forming a pixel electrode including a drain wiring on an insulating substrate, and a step of forming a pixel electrode using the photosensitive resin pattern used for selective pattern formation of the pixel electrode as a mask. Anodizing the second amorphous silicon layer and a part of the first amorphous silicon layer between the source / drain wiring and the source / drain wiring while irradiating light while protecting. Features.

With this configuration, the scanning lines are covered with a low-resistance metal layer to reduce the resistance, and an organic insulating layer is formed on these low-resistance metal layers to be insulated. A silicon oxide layer containing impurities is formed on the channel between the source and the drain to protect the channel, and the surface of the source wiring (signal line) and the surface of the drain wiring excluding a region covered with the transparent conductive layer. Is anodized to form an insulating layer and has a passivation function.

A twenty-third invention is a method for manufacturing a liquid crystal image display device according to the seventh invention, wherein a gate electrode of an insulated gate transistor is formed on a main surface of an insulating substrate by a heat-resistant metal layer which can be anodized. Forming a scanning line also serving as a connection layer, and sequentially covering one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities. And exposing the insulating substrate by selectively removing the second and first amorphous silicon layers and the gate insulating layer except for the channel forming region, and exposing at least the exposed portion in the image display portion. Forming a low-resistance metal layer and an organic insulating layer on a scanning line and a gate electrode, and depositing one or more anodically oxidizable metal layers so that the gate electrode partially overlaps the insulating substrate. Source distribution including the second amorphous silicon layer (A signal line) and a step of forming a drain wiring including a part of the connection layer; a step of forming a pixel electrode including a part of the connection layer on an insulating substrate; The second amorphous silicon layer and the first amorphous layer between the source / drain wiring and the source / drain wiring are irradiated while irradiating light while protecting the picture element electrodes using the photosensitive resin pattern used as a mask as a mask. Anodizing a part of the silicon layer.

According to this structure, the same effect as that of the manufacturing method according to the twenty-second invention can be obtained.

A twenty-fourth invention is a method for manufacturing a liquid crystal image display device according to the eighth invention, wherein a scanning line comprising a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor is provided. Forming a gate insulating layer, sequentially depositing at least one gate insulating layer, a first amorphous silicon layer containing no impurity and a second amorphous silicon layer containing an impurity, and a channel formation region. Exposing the insulating substrate except for selectively leaving the second and first amorphous silicon layers and the gate insulating layer, except that the low level is formed on at least the exposed scanning lines and gate electrodes in the image display unit. Forming a resistive metal layer and an organic insulating layer, forming a pixel electrode on the insulating substrate, and applying one or more anodically oxidizable metal layers;
Forming a source wiring (signal line) including the second amorphous silicon layer and a drain wiring including a part of the pixel electrode on the insulating substrate so as to partially overlap the gate electrode; Anodizing the second amorphous silicon layer between the source / drain wiring and the source / drain wiring and part of the first amorphous silicon layer during irradiation.

According to this structure, the same effect as the manufacturing method according to the twenty-second invention can be obtained.

A twenty-fifth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the ninth aspect, wherein the scanning line is formed of a heat-resistant metal layer on one main surface of an insulating substrate and also serves as a gate electrode of an insulated gate transistor. Forming, sequentially depositing one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities, Forming a source (signal line) / drain wiring on the second amorphous silicon layer so as to partially overlap with the gate electrode after depositing at least one metal layer;
Exposing the insulating substrate by selectively removing the second and first amorphous silicon layers and the gate insulating layer except for the channel formation region and under the source (signal line) / drain wiring;
Forming a low-resistance metal layer and an organic insulating thin layer on at least the exposed scanning lines and gate electrodes in the image display unit; forming a pixel electrode including a drain wiring on an insulating substrate; The photosensitive resin pattern used for the selective pattern formation of the pixel electrodes is used as a mask to protect the pixel electrodes while irradiating light while the source / drain wiring and the source / drain wiring are formed.
Anodizing the second amorphous silicon layer between the drain wirings and a part of the first amorphous silicon layer.

According to this structure, the same effect as that of the manufacturing method according to the twenty-second invention can be obtained.

A twenty-sixth invention is directed to a method for manufacturing a liquid crystal image display device according to the tenth invention, which comprises laminating a transparent conductive layer and a heat-resistant metal layer on one principal surface of an insulating substrate. Forming a scan line also serving as a gate electrode of a transistor and a pseudo picture element electrode; a plasma protection layer, a gate insulating layer, a first amorphous silicon layer containing no impurity, and a second amorphous silicon containing an impurity A step of sequentially depositing a silicon layer and a step of exposing the insulating substrate by selectively removing the second and first amorphous silicon layers, the gate insulating layer, and the plasma protection layer except for the channel formation region Forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit; and attaching one or more anodizable metal layers to the insulating substrate. Second so that it partially overlaps the gate Forming a source wiring (signal line) including the amorphous silicon layer and a drain wiring including a part of the pseudo picture element electrode, removing the heat-resistant metal layer on the pseudo picture element electrode, Anodizing the second amorphous silicon layer between the source / drain wiring and the source / drain wiring and a part of the first amorphous silicon layer while irradiating the first amorphous silicon layer.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the second
The same effect as the method of manufacturing a semiconductor device for an image display device according to any one of the inventions 2 to 25 is obtained, and a reduction in resistance of the scanning line, which is the main point of the present invention, is realized.

A twenty-seventh aspect of the present invention relates to the method for manufacturing a liquid crystal image display device according to the eleventh aspect, comprising a laminated structure of a transparent conductive layer and a heat-resistant metal layer on one principal surface of an insulating substrate. Forming a scan line also serving as a gate electrode of the transistor and a pseudo picture element electrode; a plasma protection layer, a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon containing impurities A step of sequentially depositing a silicon layer and a step of exposing the insulating substrate by selectively removing the second and first amorphous silicon layers, the gate insulating layer, and the plasma protection layer except for the channel formation region Removing the heat-resistant metal layer on the pseudo-picture element electrode to expose the picture element electrode; and forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and the gate electrode in the image display unit. Forming process and one layer that can be anodized After depositing the upper metal layer, a source wiring (signal line) including the second amorphous silicon layer and a drain wiring including a part of the picture element electrode are formed on the insulating substrate so as to partially overlap the gate. And a step of anodizing the second amorphous silicon layer and a part of the first amorphous silicon layer between the source / drain wiring and the source / drain wiring while irradiating light. It is characterized by having.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the second
The same effect as the method of manufacturing a semiconductor device for an image display device according to any one of the inventions 2 to 25 is obtained, and a reduction in resistance of the scanning line, which is the main point of the present invention, is realized.

Further, the restriction on the scanning wire is eased.

A twenty-eighth invention is a method for manufacturing a liquid crystal image display device according to the twelfth invention, wherein the scanning line is formed of a heat-resistant metal layer on one main surface of an insulating substrate and also serves as a gate electrode of an insulated gate transistor. Forming a lift-off layer after sequentially depositing at least one gate insulating layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer; and forming a gate on the gate electrode. Exposing the first amorphous silicon layer while selectively leaving the lift-off layer and the protective insulating layer thinner than the electrode; and forming the second amorphous silicon layer and the second metal layer containing impurities. A step of selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer; and a step of removing the second semiconductor layer and the second metal layer on the insulating substrate. Source (signal line) consisting of a laminate with a metal layer Forming a rain line and selectively removing the first amorphous silicon layer and the gate insulating layer except for between the source / drain lines and under the source / drain lines to expose the insulating substrate; Forming a low-resistance metal layer and an organic insulating layer on the exposed scanning lines and the gate electrode in the display unit, forming a pixel electrode including a drain wiring on the insulating substrate, Forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring excluding the picture element electrode in the image display unit using the photosensitive resin pattern used for the selective pattern formation as a mask. It is characterized by.

With this configuration, the resistance of the scanning line and the signal line can be reduced except for the intersection between the scanning line and the signal line. Also, the insulated gate transistor has a protective insulating layer, and wiring passivation by an organic insulating layer is also formed on the signal line, so there is no need to cover the entire surface of the glass substrate with the passivation insulating layer. The heat resistance of the transistor does not become a problem.

A twenty-ninth aspect of the present invention is the method of manufacturing a liquid crystal image display device according to the thirteenth aspect, wherein the scanning line is formed of a heat-resistant metal layer on one main surface of an insulating substrate and also serves as a gate electrode of an insulated gate transistor. Forming, forming a lift-off layer after sequentially depositing one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a protective insulating layer; and forming a gate on the lift-off layer. A step of selectively forming a photosensitive resin pattern narrower than the electrodes; and a step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, and the gate insulating layer using the photosensitive resin pattern as a mask to form an insulating substrate. The step of exposing, the step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and the step of sequentially exposing the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask Exposing the first semiconductor layer to partially expose the first semiconductor layer, forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit, and removing impurities. A step of depositing a second amorphous silicon layer and a second metal layer including the second semiconductor layer and the second metal layer on the lift-off layer while removing the lift-off layer. Forming a source (signal line) / drain wiring composed of a stack of a second semiconductor layer and a second metal layer on the insulating substrate; and forming a pixel electrode including the drain wiring on the insulating substrate. Forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring excluding the picture element electrodes in the image display portion using the photosensitive resin pattern used for the selective pattern formation of the picture element electrodes as a mask. And a step of forming And wherein the door.

According to this structure, the same effect as that of the method of manufacturing a semiconductor device for an image display device according to the twenty-third aspect is obtained. Further, all the scanning lines are covered with a low-resistance metal layer and an organic insulating layer and have a low resistance. Has been

A thirtieth invention is directed to a method of manufacturing a liquid crystal image display device according to the fourteenth invention, wherein a scanning line comprising a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor is provided. Forming, forming a lift-off layer after sequentially depositing one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a protective insulating layer; and forming a gate on the lift-off layer. A step of selectively forming a photosensitive resin pattern narrower than the electrodes; and a step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, and the gate insulating layer using the photosensitive resin pattern as a mask to form an insulating substrate. The step of exposing, the step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and the step of sequentially exposing the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask Engraving to partially expose the first semiconductor layer; implanting impurities into the first semiconductor layer using the lift-off layer as a mask to change the quality into a second semiconductor layer; Forming a low-resistance metal layer and an organic insulating layer on a scanning line and a gate electrode, forming a second metal layer, removing the lift-off layer, and removing the second metal layer on the lift-off layer. A step of selectively removing a layer, a step of forming a source (signal line) / drain wiring made of a second metal layer on an insulating substrate, and a step of forming a pixel electrode including a drain wiring on the insulating substrate And forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring excluding the pixel electrodes in the image display portion using the photosensitive resin pattern used for the selective pattern formation of the pixel electrodes as a mask. Forming process Characterized in that it has a.

According to this structure, the same effect as that of the method for manufacturing a semiconductor device for an image display device according to the twenty-ninth aspect is obtained.

A thirty-first aspect is a method of manufacturing a liquid crystal image display device according to the fifteenth aspect, comprising a laminated structure of a transparent conductive layer and a heat-resistant metal layer on one main surface of an insulating substrate. Forming a scan line also serving as a gate electrode of a transistor and a pseudo pixel electrode; and forming at least two gate insulating layers including a plasma protective layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer. Sequentially exposing, a step of exposing the first amorphous silicon layer while leaving the protective insulating layer on the gate electrode narrower than the gate electrode, and a step of exposing the second amorphous silicon Depositing a layer, selectively removing the second and first amorphous silicon layers, the plasma protection layer, and the gate insulating layer except for a channel formation region to expose a scan line; Exposed scanning lines in the image display Forming a low-resistance metal layer and an organic insulating layer on the gate electrode; and partially covering the protective insulating layer on the insulating substrate, including the second amorphous silicon layer, after the second metal layer is deposited. Forming a source wiring made of the second metal layer and a drain wiring including a part of the pseudo picture element electrode, and removing the second amorphous silicon layer between the source and drain wirings. Removing the heat-resistant metal layer on the pseudo-picture element electrode to expose the picture element electrode; and forming a low-resistance metal layer and an organic insulating layer on at least the source wiring in the image display unit. Features.

According to this configuration, the same effect as that of the method for manufacturing a semiconductor device for an image display device according to the twenty-ninth aspect is obtained.

A thirty-second aspect of the invention is a method of manufacturing a liquid crystal image display device according to the sixteenth aspect of the present invention, which comprises laminating a transparent conductive layer and a heat-resistant metal layer on one main surface on an insulating substrate. Forming a scanning line also serving as a gate electrode of the transistor and a pseudo picture element electrode; and forming two or more gate insulating layers including a plasma protective layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer. Sequentially exposing, a step of exposing the first amorphous silicon layer while leaving the protective insulating layer on the gate electrode narrower than the gate electrode, and a step of exposing the second amorphous silicon A step of depositing a layer, and selectively removing the second and first amorphous silicon layers, the plasma protection layer and the gate insulating layer except for the channel formation region, thereby forming a scanning line and a pseudo pixel electrode. Exposing process and heat-resistant metal layer on pseudo pixel electrode Removing, exposing the pixel electrodes, forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and the gate electrodes in the image display unit, and covering the second metal layer. After the deposition, a source wiring made of the second metal layer and a drain wiring containing a part of the pixel electrode are formed on the insulating substrate including the second amorphous silicon layer so as to partially overlap the protective insulating layer. Performing a step of removing the second amorphous silicon layer between the source and drain wirings, and forming at least a low-resistance metal layer and an organic insulating layer on the source wirings in the image display unit. It is characterized by.

According to this configuration, the same effect as that of the method for manufacturing a semiconductor device for an image display device according to the twenty-ninth aspect is obtained. Further, restrictions on the scanning wire are eased.

A thirty-third invention is a method for manufacturing a liquid crystal image display device according to the seventeenth invention, which comprises laminating a transparent conductive layer and a heat-resistant metal layer on one principal surface of an insulating substrate. Forming a scan line also serving as a gate electrode of the transistor and a pseudo pixel electrode; and sequentially depositing a plasma protective layer, a gate insulating layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer. A step of applying a lift-off layer, a step of selectively forming a photosensitive resin pattern narrower than the gate electrode on the lift-off layer, a step of using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Exposing the insulating substrate by sequentially etching the layer, the gate insulating layer and the plasma protective layer; removing the heat-resistant metal layer on the pseudo-pixel electrode to expose the pixel electrode; Film reduction Exposing the lift-off layer and partially exposing the first semiconductor layer by sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Implanting impurities into the first semiconductor layer using the lift-off layer as a mask,
Transforming into a semiconductor layer, forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit, and applying a second metal layer And selectively removing the second metal layer on the lift-off layer together with the removal of the lift-off layer, and forming a part of the source (signal line) wiring and the pixel electrode made of the second metal layer on the insulating substrate. And a step of forming a low-resistance metal layer and an organic insulating layer on at least the source wiring in the image display unit.

With this configuration, the rationalization of the process is further promoted, the number of photolithography steps is further reduced, and the device can be manufactured with three photomasks. And the second
The same effects as those of the method for manufacturing a semiconductor device for an image display device according to any one of the inventions 8 to 32 are obtained, and the resistance of the scanning line and the signal line, which is the main point of the present invention, is realized.

A thirty-fourth invention is a method for manufacturing a liquid crystal image display device according to the eighteenth invention, wherein a step of depositing an amorphous silicon layer on at least one main surface of the insulating substrate, A step of reducing hydrogen contained in a silicon layer, a step of polycrystallizing an amorphous silicon layer by laser irradiation, a step of forming a polycrystalline silicon layer in an island shape, and a step of forming a gate insulating layer on an insulating substrate. Exposing the polycrystalline silicon layer by selectively leaving the gate insulating layer and the first metal layer corresponding to the scanning line also serving as the gate electrode after depositing the first metal layer, and at least in the image display portion. Forming a low resistance metal layer and an organic insulating layer on the scan line, irradiating (implanting) impurities to form a source / drain, and forming an interlayer insulating layer having a pair of openings on the source / drain. The step of applying and the second metal including the opening Forming a source (signal line) / drain wiring comprising: forming a pixel electrode including a drain wiring on an interlayer insulating layer; and a photosensitive resin used for selective pattern formation of the element electrode. Forming a low-resistance metal layer and an organic insulating layer on the source / drain wiring excluding at least the picture element electrodes in the image display unit using the pattern as a mask.

According to this structure, the resistance of the scanning line and the signal line, which is the main point of the present invention, is also realized in a liquid crystal image display device using a top gate insulated gate transistor as a switching element.

A thirty-fifth invention is a method for manufacturing a liquid crystal image display device according to the nineteenth invention, which comprises a step of depositing an amorphous silicon layer on at least one principal surface of an insulating substrate; A step of reducing hydrogen contained in a silicon layer, a step of polycrystallizing an amorphous silicon layer by laser irradiation, a step of forming a polycrystalline silicon layer in an island shape, and a step of forming a gate insulating layer on an insulating substrate. Exposing the polycrystalline silicon layer by selectively leaving the gate insulating layer and the transparent conductive layer corresponding to the scanning line also serving as the gate electrode and the pixel electrode after depositing the transparent conductive layer and A step of forming a low-resistance metal layer and an organic insulating layer on a scanning line in a display unit, and irradiating (implanting) impurities
Forming a source / drain by applying a second metal layer, forming an interlayer insulating layer having a pair of openings on the source / drain and an opening on the pixel electrode, Forming a source wiring (signal line) including the opening, a drain wiring including an opening on the drain and a part of the picture element electrode, and forming a low-resistance metal on at least the source wiring in the image display unit. Forming a layer and an organic insulating layer.

With this configuration, not only are the resistances of the scanning lines and the signal lines reduced, but also the rationalization of the process of forming the scanning lines and the pixel electrodes is combined with the rationalization of the four photomasks. Enables device fabrication.

A thirty-sixth invention is a method for manufacturing a liquid crystal image display device according to the twentieth invention, comprising the steps of: depositing an amorphous silicon layer on at least one main surface of the insulating substrate; A step of reducing hydrogen contained in a silicon layer, a step of polycrystallizing an amorphous silicon layer by laser irradiation, a step of forming a polycrystalline silicon layer in an island shape, and a step of forming a gate insulating layer on an insulating substrate. Exposing the polycrystalline silicon layer by selectively leaving the gate insulating layer and the first metal layer corresponding to the scanning line also serving as the gate electrode after depositing the first metal layer, and at least in the image display portion. Forming a low resistance metal layer and an organic insulating layer on the scan line, irradiating (implanting) impurities to form a source / drain, and forming an interlayer insulating layer having a pair of openings on the source / drain. Deposition process and transparent conductive including opening Forming a drain wiring also serves as the pixel electrode and become more source wiring (signal line), characterized in that a step of forming at least a low-resistance metal layer over the source wiring and the organic insulating layer.

With this configuration, not only the reduction in the resistance of the scanning lines and the signal lines is realized, but also the rationalization of the process of forming the signal lines and the pixel electrodes is combined with the rationalization of the four photomasks. Enables device fabrication.

A thirty-seventh aspect is the method for manufacturing a liquid crystal image display device according to the twenty-second to thirty-sixth aspects, wherein the low-resistance metal layer is formed by plating using gold, silver or copper.

With this configuration, the resistance of the scanning line and the signal line can be sufficiently reduced without using a vacuum film forming apparatus and an etching apparatus. Is realized. Similarly, the plating apparatus differs from the vacuum film forming apparatus and the dry type etching apparatus in that the source of dust particles does not exist, so that the yield is improved.

[0113]

(Embodiment 1) Embodiment 1 of the present invention
(Corresponding to the first to third aspects of the present invention) shows the basic configuration of an insulated gate transistor serving as a skeleton of the present invention. .

The first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor device (active substrate) for an image display device according to a first embodiment of the present invention, and FIG. 2 is a view showing a manufacturing process on lines AA ′ and BB ′ in FIG. FIG. Similarly, the second embodiment is shown in FIGS. 3 and 4, the third embodiment is shown in FIGS. 5 and 6, and hereinafter, the fifteenth embodiment is shown in FIGS. 28 and 30 in plan view of the active substrate. And a sectional view of a manufacturing process. Parts having the same functions as those of the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In the first embodiment of the present invention, that is, in the method of manufacturing an active substrate according to the present invention, first, as shown in FIG. A first metal layer having a thickness of about 0.1 μm is deposited by using an apparatus, and a gate electrode 11 serving also as a scanning line is formed by a fine processing technique.
(And the common capacitance line 16) are selectively formed. As described later, since a low-resistance metal layer is formed on the scanning line 11, it is not necessary to form the first metal layer thickly. Increasing the leakage current requires a film thickness to be avoided.

As described in the conventional example, C having high heat resistance is used.
It is desirable to use r, Ta, Mo, etc., or an alloy or silicide thereof.

Next, as shown in FIG. 2 (b), a first SiNx (silicon nitride) layer serving as a gate insulating layer was formed on the entire surface of the glass A first amorphous silicon layer serving as a channel of a transistor, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers, for example, 0.3-0.1-0.05 The layers are sequentially deposited to a thickness of about μm to obtain 30, 31, and 33. As described above, one of the features of the present invention is that the first amorphous silicon layer 31 can be thinner than the conventional one.

Subsequently, as shown in FIG. 2C, at least the transistor formation region 102 (and the storage capacitor line 16
Except for the upper storage capacitor forming region 103), the second and first amorphous silicon layers 33 and 31 and the gate insulating layer 30 are selectively removed to expose the glass substrate 2. In this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using gas.

In the present invention, the islanding step of the semiconductor layer is performed by simultaneous etching of the semiconductor layer and the gate insulating layer from the viewpoint of reducing the number of steps. Irradiation light causes light leakage of the insulated gate transistor, which hinders operation. In addition, when a semiconductor layer exists on the scanning line 11, there is a high possibility that a parasitic transistor is formed or a stray capacitance fluctuates. Then, as a result of removing an unnecessary semiconductor layer on the scanning line 11, a part (tip portion) 105 of the gate electrode and the scanning line 11 are exposed.

In the present invention, a low-resistance metal layer, specifically, gold, silver, or copper is formed on the scanning lines 11 by plating, utilizing the fact that the scanning lines 11 are exposed. The film thickness is determined by the screen size and definition of the liquid crystal image display device and the required response speed (time constant) of the scanning line 11.
Care must be taken because the short circuit occurs between the channel semiconductor layer 31 'and the channel semiconductor layer 31'. For plating, sodium cyanide, silver nitrate, copper sulfate, etc. are used as electrolytes, respectively. However, since sodium cyanide is highly toxic, the use of a recently developed non-cyanide-based electrolyte is recommended. Although not shown, the above-described low-resistance metal plate is used as an anode, and the scanning line 11 is used as a cathode. A thin film layer 71 of a low resistance metal is formed. A design matter to be noted in plating is that all the scanning lines 11 (and the storage capacitor lines 16) must be electrically connected in parallel or in series (in the case of series, it is necessary to pay attention to the voltage drop due to plating current). There is. For this purpose, as shown in FIG. 38, a wiring path 83 (84) for connecting the scanning lines 11 (storage capacitor lines 16) in parallel is provided, and the leading end of the wiring path 83 (84) is connected at the periphery of the glass substrate. It is convenient to use the terminal 85 (86). Naturally, when the scanning line 11 and the storage capacitor line 16 are formed simultaneously on the same surface, the connection terminals 85 and 86 are short-circuited. Note that this electrical connection may be hindered not only in the electrical inspection of the active substrate 2 but also in the actual operation of the liquid crystal image display device unless the connection is released somewhere in the subsequent manufacturing process and the scanning lines 11 are not separated one by one. It goes without saying that there is. However, in general, it is not necessary to release the connection of the storage capacitor line 16.

The low-resistance metal layer formed by plating is not necessarily required on all of the scanning lines 11. When the low-resistance metal layer 71 is made of silver or copper, the electrode terminals 6 or the scanning lines on which the electrode terminals 6 are formed are formed. Only on a part of 11 rather chemical resistance,
From the viewpoint of oxidation resistance and the like, the conventional first metal layer is desirable. In such a case, it is recommended to use a later-described selective in-substrate electrochemical treatment apparatus.

Even if the resistance of the scanning line 11 is reduced by plating, a direct current bias is applied between the scanning line 11 and the counter electrode 14 in the liquid crystal panel state. A direct current flows through the liquid crystal, and the liquid crystal device not only has a strong flicker, but also has a property of deteriorating the liquid crystal and becoming brown when used for a long time. Therefore, an important point of the present invention is that an organic insulating layer 72 is further formed on the scanning line 11 by an electrodeposition method so that a direct current does not flow. Among materials that can be formed by electrodeposition as an organic insulating layer that can secure the insulating properties required for a device, polyamic acid is used as described in Literature, C 112 vol. 12, No. 12, 1992. Add salt to 0.
When a solution containing about 01% is used as an electrodeposition solution and a + (plus) potential is applied to the scanning line 11 to perform electrodeposition, as shown in FIG. The polyimide layer 72 can be selectively formed. The electrodeposition voltage is about several volts, and the thickness of the polyimide layer 72 is adjusted to the gate insulating layer 30 '.
It is easy to set the thickness to about 0.3 μm, which is the same as that of. The polyimide resin is a resin having high heat resistance similarly to the acrylic resin.
A heat treatment of up to 300 ° C. for several minutes to several tens of minutes may be performed to increase the insulation properties and chemical resistance of the polyimide layer 72. Since the composition is governed by the composition, the heating conditions may be determined experimentally. In this electrodeposition step, no polyimide layer is formed on the second amorphous silicon layer 33 ′, and conversely, the gate insulating layer 30 ′ on the gate electrode 11 and the first
A pinhole penetrating through the amorphous silicon layer 31 'and the second amorphous silicon layer 33'
Even if 1 is filled with plating, since it is further covered with the organic insulating layer 72, a secondary effect of reducing interlayer short-circuit between the gate electrode 11, the signal line 12, and the drain wiring 21 also occurs.

However, the organic insulating layer 72 is connected to the scanning line 1
If the electrode terminal 6 is formed on the area where the one electrode terminal 6 is formed, the number of steps cannot be reduced. Therefore, it is necessary to cover the area with an appropriate means. For example, since selective electrodeposition using a photosensitive resin pattern as a mask causes an increase in the number of manufacturing steps, basically, selective electrochemical deposition in a substrate disclosed in Japanese Patent Application No. The adoption of a processing device is reasonable. As shown in FIG. 39, the chemical processing apparatus holds the glass substrate 2 on a horizontal substrate stage 90 and has an insulating frame-shaped or square-shaped container 92 in which an O-ring 91 made of resin is embedded at one end. Is pressed against the glass substrate 2, a chemical solution 93 is injected into the frame-shaped container 92, and a current is supplied from the DC power supply 95 between the electrode plate 94 fixed to the vertically movable support rod 97 and the conductive pattern on the glass substrate 2. This is an apparatus for performing an electrochemical treatment by applying a DC voltage via a total 96. In FIG. 39, a terminal 97 for connecting the scanning lines 11 in parallel is formed in order to electrodeposit the scanning lines 11 of the four-sided devices. A state is shown in which a potential is applied to the terminal 97 and a + (plus) potential is applied to each surface. As described above, the sizes of the frame-shaped container 92 and the O-ring 91 are appropriately set, and a plurality of electrode lines to be electrodeposited (the scanning lines 11 or the common capacitance lines 16 or the pixel in the case of the IPS type liquid crystal panel). The terminal 97 on which the counter electrode formed at a predetermined distance from the electrode is bundled, or a mechanism for electrically bundling the electrode wire is provided on the outer peripheral side of the frame-shaped container 92 so that the glass substrate 2
The inside can be selectively electrodeposited. That is, the organic insulating layer 72 can be selectively formed only on the exposed scanning lines 11 in the image display section or up to the vicinity of the electrode terminals 6, and on the exposed scanning lines 11 in the region of the scanning lines 11 where the electrode terminals 6 are formed. Can be treated so as to prevent the formation of the organic insulating thin film 72. As a mechanism for electrically bundling the electrode wires, for example, as in the liquid crystal panel mounting process, an appropriate conductive metal plate 42 is connected to an ACF (anisotropic conductive thin film) 4 serving as a conductive medium.
A method of pressing a part of the scanning line 11 exposed through the line 3 is adopted, and a + (plus) potential is applied to the conductive metal plate 42 from the DC power supply 95 and a − (minus) potential is applied to the electrode plate 94 from the DC power supply. FIG. 39 simultaneously illustrates an example of performing the electrodeposition.

As described above, the organic insulating layer (polyimide) 72 is selectively formed on at least the exposed scanning lines 11 in the image display section, and subsequently, as shown in FIG. Using a film apparatus, a heat-resistant metal thin film layer 34 of, for example, Ti, Ta or the like as an anodically oxidizable heat-resistant metal layer having a film thickness of about 0.1 μm, and a 0.3 mm-thick film as a low-resistance wiring layer.
An AL thin film layer 35 of about μm and a heat-resistant metal thin film layer 36 of Ta or the like as an anodically oxidizable intermediate conductive layer of about 0.1 μm in thickness are sequentially deposited. Then, these three metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique to form a drain wiring (electrode) of an insulated gate transistor.
21 and the signal line 12 also serving as a source wiring (electrode) are selectively formed. In selectively forming the source / drain wirings 12 and 21, the etching of the second amorphous silicon layer 33 ′ containing impurities and the first amorphous silicon layer 31 ′ containing no impurities are performed in the conventional manner. Not required. One storage electrode 55 for forming a storage capacitor is formed on the storage capacitor line 16 simultaneously with the formation of the source / drain wirings 12 and 21. Further, it is also possible to form the scanning line electrode terminals 6 including the scanning lines 11 exposed in a region outside the image display section. Alternatively, here, the electrode terminal 6 is not formed,
A transparent conductive electrode terminal 6 'may be formed in a subsequent step.

Further, as shown in FIG. 2 (g), the entire surface of the glass substrate 2 was processed to a thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide) and a pixel electrode 22 on the glass substrate 2 including a part of the drain wiring 21 by a fine processing technique.
Are formed selectively. Then, using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrodes 22 as a mask, the source / drain wirings 12 and 2 are irradiated with light.
1 is anodized to form an oxide layer on the source / drain wirings 12 and 21 and
A portion of the second amorphous silicon layer 33 'containing impurities and a portion of the first amorphous silicon layer 31' containing no impurities exposed between the portions 21 are anodized to form a silicon oxide layer as an insulating layer. (SiO2) 66 and 67 are formed.

Ta is formed on the upper surfaces of the source / drain wirings 12 and 21, and T is formed on the side surfaces of the source / drain wirings 12 and 21.
a, AL, Ti (or Ta) laminate is exposed,
By anodization, Ta is tantalum pentoxide (Ta2O5) 68 as an insulating layer, and AL is alumina (AL2O3) as an insulating layer.
69, Ti changes to titanium oxide (TiO2) 70 which is a semiconductor. Titanium oxide (TiO2) 70 is not an insulating layer, but its thickness is extremely small, so there is no problem in passivation. It should be noted that it lacks the ability to absorb surface oxide and facilitate ohmic contact.

Second amorphous silicon layer 3 containing impurities
3 'increases the leakage current of the insulated gate transistor unless the insulating layer is completely formed in the thickness direction. Therefore, performing anodization while irradiating light is an important point in the anodization step. This is because the second amorphous silicon layer 33 ′ containing impurities changes from the surface in contact with the chemical conversion solution to the silicon oxide layer 66, but as the anodic oxidation proceeds, the second amorphous silicon layer Layer 3
This is because the film thickness of 3 ′ decreases, and it becomes impossible to flow a current sufficient to anodize the second amorphous silicon layer 33 ′ containing impurities and the drain wiring 21. When anodic oxidation is performed while irradiating light, the first non-impurity-free first amorphous silicon layer 33 ′ in contact with the second
Can be changed from a high resistance state in which almost no current flows due to the photoelectric effect to a low resistance state in which a necessary current can flow. More specifically, if the leakage current of the insulated gate transistor exceeds μA by irradiating a sufficiently strong light of about 10,000 lux, calculation is made from the area of the channel between the source / drain wirings 12 and 21 and the area of the drain wiring 21. Thus, current density for obtaining good film quality can be obtained by anodic oxidation of about 10 mA / cm2.

The second amorphous silicon layer 33 'containing impurities is anodized to form a silicon oxide layer (Si
O2) 1 from formation voltage over 100V enough to transform to 66
A portion of the first amorphous silicon layer 31 ′ containing no impurity (10) that is in contact with the impurity-containing silicon oxide layer (SiO ₂ ) 66 formed by setting the formation voltage high to about 0V.
Silicon oxide layer (Si
By transforming into O ₂ ) 67, the electrical purity of the channel is increased, and the electrical isolation between the source / drain wirings 12 and 21 can be completed. That is, the OFF current of the insulated gate transistor is sufficiently reduced, and a high ON / OFF ratio is obtained.

Tantalum pentoxide (Ta) formed by anodic oxidation
₂ O ₅ ) 68, alumina (AL ₂ O ₃ ) 69, titanium oxide (TiO ₂ )
2) The film thickness of each oxide layer 70 is sufficient to be about 0.1 to 0.2 μm for the passivation of the wiring, and the applied voltage is likewise over 100 V by using a chemical such as ethylene glycol. A point to be noted in anodic oxidation of the source / drain wirings 12 and 21 is that all the signal lines 12 need to be formed electrically in parallel or in series. If not released, it goes without saying that not only the electrical inspection of the active substrate 2 but also the actual operation of the liquid crystal display device is hindered. If the signal lines 12 are not connected in series or in parallel,
A mechanism for bundling electrode terminals like a selective electrochemical device in a substrate, for example, a mechanism for pressing a metal electrode to a plurality of electrode terminals via an anisotropic conductive rubber is required.

The reason that the pixel electrode 22 is covered with the photosensitive resin pattern 65 is not only that the pixel electrode 22 does not need to be anodized, but also that the formation current flowing to the drain wiring 21 via the insulated gate transistor is not limited. This is because it is not necessary to secure the value larger than necessary. Note that the electrode terminals 6 of the scanning lines 11 are electrically floating (neutral) during anodization.
Therefore, no anodized layer is formed. By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the electrode terminal 5 in a region outside the image display unit as shown in FIG. In a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the source / drain wirings 12 and
It is not possible to selectively anodize the electrode 21, and the electrode terminal 5 ′ made of a transparent conductive layer is formed including the signal line 12 in a region outside the image display unit as shown separately.
This configuration is the same as the connection form between the picture element electrode 22 and the drain wiring 21 shown in FIG.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 (semiconductor device for an image display device) as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the first embodiment of the present invention is completed. Regarding the configuration of the storage capacitor 15, the storage capacitor line 16
The storage electrode 55 and the storage capacitance line 16 formed simultaneously with the source / drain wirings 12 and 21 are formed on the gate insulating layer 3.
FIG. 1 illustrates an example in which an amorphous silicon layer 31 ′ containing no impurities and an impurity-free amorphous silicon layer 31 ′ is interposed therebetween. However, the present invention is not limited to this, and a thin film layer including the gate insulating layer 30 may be interposed between the pixel electrode 22 and the preceding scanning line 11. Further, other configurations are possible, but detailed description is omitted.

(Embodiment 2) Embodiment 2 of the present invention will be described with reference to FIGS. In the second embodiment, it is possible to form the source / drain wiring into a two-layer structure by introducing a new connection layer for the connection between the pixel electrode and the drain electrode. In the method for manufacturing an active substrate according to the twenty-third aspect, first, as shown in FIG. 4A, a film thickness of 0.1 mm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT (sputtering). Ta or a silicide of Cr, Ta, Mo, or the like is selected as the first metal layer that can be anodized to about μm. Since the connection layer is also anodized as described later, it is necessary to avoid Mo and W in which at least the anodized layer is easily dissolved by a water-soluble and weak chemical. Therefore, the gate electrode 11 also serving as a scanning line and the connection layer 80 are selectively formed by depositing Ta or the like by a fine processing technique.

Next, as shown in FIG. 4B, a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD apparatus, and an insulated gate type containing almost no impurities. A first amorphous silicon layer serving as a channel of the transistor, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers, for example, 0.3-0.1-0.05 The layers are sequentially deposited to a thickness of about μm to form 30, 31, 33.

Subsequently, as shown in FIG. 4C, at least the transistor formation region 102 (and the storage capacitor line 16
Except for the upper storage capacitor forming region 103), the second and first amorphous silicon layers 33 and 31 and the gate insulating layer 30 are selectively removed to expose the glass substrate 2. As described above, since a plurality of types of thin films are etched in this step, it is reasonable to adopt dry etching using gas.

Then, a low-resistance metal layer 71 is formed by plating on the exposed scanning lines 11 and the gate electrodes 105 as shown in FIG. 4D, and subsequently, as shown in FIG. The organic insulating thin film 72 is formed by electrodeposition. At this time, since the connection layer 80 is electrically isolated and floating, the low resistance metal layer and the organic insulating layer are not formed on the connection layer 80.

Thereafter, as shown in FIG.
Using a vacuum film forming apparatus such as this, a heat-resistant metal thin film layer of, for example, Ti, Ta, etc. having a thickness of about 0.1 μm and an AL thin-film layer having a thickness of about 0.3 μm as a low-resistance wiring layer are sequentially covered. To wear. Then, these two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and the signal line 12 also serving as the source wiring of the insulated gate transistor and the drain wiring 21 including a part of the connection layer 80 are formed. Are formed selectively. At the same time as the formation of the source / drain wirings 12 and 21, the electrode terminals 6 of the scanning lines including the scanning lines 11 exposed in the region outside the image display unit are formed at the same time.

Subsequently, as shown in FIG.
(Sputtering) using a vacuum film-forming device such as 0.1-0.2μ
ITO (Indium-Tin-Oxide) as a transparent conductive layer of about m
Is formed over the entire surface, and the pixel electrode 22 is selectively formed on the glass substrate 2 including a part of the connection layer 80 by a fine processing technique.

Subsequently, the source / drain wirings 12 and 21 are anodically oxidized while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the picture element electrodes 22 as a mask to form an oxide layer and Anodizing a portion of the second amorphous silicon layer 33 'containing impurities and a portion of the first amorphous silicon layer 31' containing no impurities, which are exposed between the drain wirings 12 and 21; Then, silicon oxide layers (SiO2) 66 and 67 are formed. A layer of AL and Ti is exposed on the upper surfaces of the source / drain wirings 12 and 21, and AL and Ti are exposed on side surfaces of the source / drain wirings 12 and 21. AL is an insulating layer of alumina (AL 2 O 3) 69 by anodic oxidation. Ti is a semiconductor titanium oxide (T
Transforms to iO2) 70. Further, since the anodic oxide layer is also formed on the surface of the connection layer 80 which is not covered with the drain wiring 21 and the pixel electrode 22, the connection layer 80 is also made of an anodizable metal layer or a silicide layer as described above. It is desirable to form it.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the electrode terminal 5 in a region outside the image display section as shown in FIG. Alternatively, the connection layer 80 'may be used as an electrode terminal without interposing a transparent conductive layer. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer is formed to include a part of the connection layer 80 ′ in a region outside the image display unit. This configuration is the same as the connection form between the picture element electrode 22 and the connection layer 80 shown in FIG. Finally, the photosensitive resin pattern 65
To remove the active substrate 2 as shown in FIG.
Completed as The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the second embodiment of the present invention. If it is not necessary to lower the resistance of the signal line 12, the source / drain wirings 12 and 21 can be made of a slightly thicker heat-resistant metal 34 'alone. In that case, the connection layer 80 is interposed. Significance is lost, and the first and second embodiments are substantially identical.

The insulated gate transistor having a different structure can be obtained by performing the main manufacturing process of the islanding process of the semiconductor layer, the forming process of the source / drain wiring, and the forming process of the picture element electrode before and after. This will be described below as third and fourth embodiments.

(Embodiment 3) Embodiment 3 of the present invention will be described with reference to FIGS. In the third embodiment, that is, the method for manufacturing an active substrate according to the twenty-fourth invention,
The step of islanding the semiconductor layer and the gate insulating layer shown in FIG.
The same manufacturing process as in the first embodiment proceeds up to the process of forming the low-resistance metal layer 71 and the organic insulating thin film 72 thereon. Subsequently, as shown in FIG. 6 (f), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm was formed using a vacuum film forming apparatus such as SPT.
TO (Indium-Tin-Oxide) is applied to the entire surface, and the pixel electrodes 22 are selectively formed on the glass substrate 2 by a fine processing technique.

Subsequently, as shown in FIG.
Using a vacuum film-forming apparatus such as T, a heat-resistant metal thin film layer 34 of, for example, Ti or Ta as a heat-resistant metal layer having a thickness of about 0.1 μm, and an AL thin film layer 3 having a thickness of about 0.3 μm as a low-resistance wiring layer.
5 are sequentially applied. Then, these two layers are sequentially etched using a photosensitive resin pattern 65 by a fine processing technique to form a signal line 12 also serving as a source wiring of an insulated gate transistor.
And the drain wiring 21 including a part of the picture element electrode 22 are selectively formed. As for the configuration of the scanning line electrode terminal, the electrode terminal 6 ′ made of a transparent conductive layer may be formed when the pixel electrode 22 is formed.
The electrode terminals 6 of the scanning lines including the scanning lines 11 exposed in the region outside the image display unit may be formed simultaneously with the formation of the electrodes 2 and 21.

Finally, as shown in FIG. 6 (h), while irradiating light, the source / drain wirings 12 and 21 are anodized to form an oxide layer on the surface thereof, and between the source / drain wirings 12 and 21. Second containing impurities exposed to
The amorphous silicon layer 33 'and a part of the first amorphous silicon layer 31' containing no impurities are anodized to form silicon oxide layers (SiO2) 66, 67 as insulating layers. By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the electrode terminal 5 in a region outside the image display unit as shown in FIG. Otherwise, as shown separately, the signal line 12 is formed including a part of the electrode terminal 5 ′ made of a transparent conductive layer in a region outside the image display unit. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain electrode 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the third embodiment of the present invention is completed.

In the third embodiment, the source
Although the drain wirings 12 and 21 can be composed of two layers of a heat-resistant metal layer and an aluminum alloy layer,
Drain wirings 12 and 21 and second amorphous silicon layer 3
Since the pixel electrode 22 electrically connected to the drain wiring 21 is also exposed during the anodic oxidation of 3 ′, the pixel electrode 22
Is also greatly anodized at the same time as the first and second embodiments. For this reason, depending on the film quality of the transparent conductive layer constituting the picture element electrode 22, the resistance may increase due to anodic oxidation. In such a case, the film forming conditions of the transparent conductive layer are appropriately changed to make the film quality oxygen-deficient. Although it is necessary, the anodic oxidation does not reduce the transparency of the transparent conductive layer. Further, a current for anodizing the drain wiring 21 and the pixel electrode 22 is also supplied through the channel of the insulated gate transistor. However, since the area of the pixel electrode 22 is large, a large formation current or a long formation time is required. Is required, and no matter how strong external light is irradiated, the resistance of the channel part becomes an obstacle,
It is difficult to form an alumina layer having the same film quality and thickness as the source wiring 12 on the drain wiring 21 only by extending the formation time. However, even if the alumina layer formed on the drain wiring 21 is somewhat incomplete, reliability that does not hinder practical use is often obtained. This is because the drive signal applied to the liquid crystal cell is basically an alternating current, and there is little DC voltage component between the counter electrode 14 and the source / drain 12, 21 wiring. In particular, applying a compensation voltage that does not cause flicker (DC voltage) between the drain wiring 21 and the counter electrode 14 is a basic concept of electric driving of an active liquid crystal panel.

When the second amorphous silicon layer 33 'containing impurities is anodized to be transformed into a silicon oxide layer (SiO ₂ ) 66 as an insulating layer, a silicon oxide film having a uniform thickness in the channel direction is formed. It is desirable that the layer (SiO ₂ ) 66 be formed. However, from the viewpoint of separation of the source and the drain, it is difficult to make the anodic oxidation reach the first amorphous silicon layer 31 ′ in a region closer to the signal line 12. Because it is simple, it is possible to evaluate an insulated gate transistor by measuring the OFF (leak) current of the insulated gate transistor even if a silicon oxide layer (SiO ₂ ) 66 with an uneven thickness is formed in the channel direction. It is. The same can be said for the passivation ability of the channel portion, which can be evaluated by a reliability test result as a single insulated gate transistor or a liquid crystal image display device.

(Embodiment 4) Embodiment 4 of the present invention will be described with reference to FIGS. In the fourth embodiment, that is, the method for manufacturing an active substrate according to the twenty-fifth invention,
The steps up to the step of forming the second semiconductor layer 33 containing impurities shown in FIG. 8B are performed in the same manufacturing steps as in the first embodiment. Thereafter, as shown in FIG. 8C, a heat-resistant metal thin film layer 3 of, for example, Ti, Ta or the like is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT.
4 and AL having a thickness of about 0.3 μm as a low-resistance wiring layer.
The thin film layer 35 is further coated with a heat-resistant metal thin film layer 36 of Ta or the like in order as an anodically oxidizable intermediate conductive layer having a thickness of about 0.1 μm. Then, these three metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique to form a signal line 12 also serving as a drain wiring 21 and a source wiring of the insulated gate transistor into a second amorphous silicon layer 33. Formed selectively on top. At this time, the storage electrode 5 is simultaneously placed on the storage capacitor line 16.
5 is formed.

Subsequently, as shown in FIG. 8D, the transistor forming region 102 (and the region near the storage electrode 55) are formed.
Except for 3), the second and first amorphous silicon layers 33, 31
And the gate insulating layer 30 are selectively removed to remove the glass substrate 2
To expose. In this step, the source / drain wirings 12 and 21 function as a mask, and the second and first amorphous silicon layers 3 under the source / drain wirings 12 and 21 are formed.
3 ', 31' and the gate insulating layer 30 'are not removed. Then, as shown in FIG. 8E, a low-resistance metal layer 71 is formed on the exposed scanning line 11 and the gate electrode 105 by plating, and an organic insulating layer 72 is formed by electrodeposition.

Subsequently, as shown in FIG.
Using a vacuum film-forming apparatus such as T, ITO (Indium-Tin-Oxide) is applied over the entire surface as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm, and a part of the drain wiring 21 is included by a fine processing technique. The picture element electrode 22 is selectively formed on the glass substrate 2. At the same time as the formation of the picture element electrode 22, the scanning line electrode terminal 6 'including the scanning line 11 exposed in the region outside the image display section is also formed at the same time. Then, using the photosensitive resin pattern 65 used for selective pattern formation of the picture element electrode 22 as a mask, the source / drain wiring 1 is irradiated while irradiating light.
2, 21 are anodized to form an insulating layer on the surface thereof, and a second amorphous silicon layer 33 'containing impurities exposed between the source / drain wirings 12 and 21 and a first amorphous silicon layer 33' containing no impurities are formed. Of the amorphous silicon layer 31 'is anodized to form a silicon oxide layer (SiO ₂ ) 66 as an insulating layer,
67 is formed.

Ta is formed on the upper surfaces of the source / drain wirings 12 and 21, and T is formed on the side surfaces of the source / drain wirings 12 and 21.
The stack of a, AL, and Ti is exposed, and Ta is an insulating layer of tantalum pentoxide (Ta ₂ O ₅ ) 68,
AL is an alumina (AL ₂ O ₃ ) 69 which is an insulating layer, and Ti is a titanium oxide (TiO ₂ ) 70 which is a semiconductor. In addition, the first layer including impurities exposed on the side
A silicon oxide layer (SiO ₂ ) 66 and a silicon oxide layer (SiO ₂ ) 67, which are oxide layers, are formed on the first amorphous silicon layer 33 ′ and the second amorphous silicon layer 31 ′ containing no impurities, respectively. Is done. If the selective anodic oxidation in the glass substrate 2 is performed, as shown in FIG.
2 can be used as the electrode terminal 5. Otherwise, as shown separately, the electrode terminal 5 ′ made of the transparent conductive layer is formed including a part of the signal line 12 in a region outside the image display unit. This configuration is the same as the connection between the picture element electrode 22 and the drain wiring 21 shown in FIG. Finally, the photosensitive resin pattern 65 is removed and FIG.
The active substrate 2 is completed as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the fourth embodiment of the present invention is completed.

(Embodiment 5) Embodiment 5 of the present invention will be described with reference to FIGS. In the fifth embodiment, in addition to the rationalization of the step of forming the islands in the semiconductor layer and the step of forming the openings in the gate insulating layer, the formation of the pixel electrodes and the formation of the scanning lines are simultaneously performed, thereby further reducing the manufacturing steps. I have. In the method for manufacturing an active substrate according to the twenty-sixth aspect, first, as shown in FIG. 10A, a film thickness of about 0.1 μm is formed on one main surface of a glass substrate 2 using a vacuum film forming apparatus such as SPT. The transparent conductive layer 81 is made of, for example, ITO (Indium-Tin-Oxi).
de) and a first metal layer 82 having a film thickness of about 0.1 μm having high heat resistance and preferably anodizable Ta or C
A silicide of r, Ta, Mo or the like is sequentially deposited, and a gate electrode 11 also serving as a scanning line formed by laminating a transparent conductive layer 81 'and a first metal layer 82' and a pseudo picture element electrode 75 by a fine processing technique. Are formed selectively. In order to improve the dielectric strength between the signal line and the drain electrode via the gate insulating layer and increase the yield, it is desirable to control the taper of the cross section of these electrodes by dry etching.

Next, a transparent insulating layer serving as a plasma protective layer, for example, TaOx or SiO ₂ is deposited on the entire surface of the glass substrate 2 to a thickness of about 0.1 μm to form 76. This plasma protective layer 76 is used to deposit the gate electrode 1 when SiNx is deposited by a subsequent PCVD apparatus.
1 and the transparent conductive layer 81 ′ exposed at the edge of the pseudo picture element electrode 75 are required to prevent reduction in the film quality of SiNx due to reduction. 9962
Please refer to Japanese Patent Publication No.

After the plasma protective layer 76 is applied,
As shown in (b), as in the other embodiments, a first SiNx (silicon nitride) layer serving as a gate insulating layer using a PCVD apparatus, and a first SiNx (silicon nitride) layer serving as a channel of an insulated gate transistor containing almost no impurities. Amorphous silicon (a-Si)
Layer and a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor and three types of thin film layers are sequentially deposited in a thickness of, for example, about 0.3-0.1-0.05 μm. 30, 31, and 33.

Thereafter, as shown in FIG. 10C, the second and first amorphous silicon layers 33 and 31 are removed except for the transistor forming region 102 (and the storage capacitor forming region 104 on the scanning line 11). , Gate insulating layer 30 and plasma protection layer 76
And the glass substrate 2 and the pseudo pixel electrode 75
And expose. Then, as shown in FIG. 10D, a low-resistance metal layer 71 is formed on the exposed scanning line 11 and the gate electrode 105 by plating, and an organic insulating layer 72 is formed by electrodeposition. At this time, since the pseudo-pixel electrode 75 is electrically isolated and floating, the low-resistance metal layer and the organic insulating layer are not formed on the pseudo-pixel electrode 75.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as T, a heat-resistant metal thin film layer 34 of, for example, Ti, Ta, etc.
Then, an AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a low-resistance wiring layer. Then, these two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and the signal line 12 also serving as the source electrode of the insulated gate transistor and the drain wiring including a part of the pseudo pixel electrode 75 are formed. 2
1 is selectively formed. At this time, the storage electrode 55 and the electrode terminal 6 are simultaneously formed. Further, by using the photosensitive resin pattern used for the selective pattern formation as a mask, the first metal layer 82 'on the pseudo picture element electrode 75 is removed to expose most of the transparent conductive layer 81', thereby forming the picture element electrode. 22 are formed.

Finally, as shown in FIG. 10F, while irradiating light, the source / drain wirings 12 and 21 are anodized to form an insulating layer on the surface thereof, and the source / drain wirings 12 and 21 are formed between them. Anodized portions of the second amorphous silicon layer 33 'containing impurities and the first amorphous silicon layer 31' containing no impurities are anodized to form a silicon oxide layer (SiO ₂ ) Form 66 and 67. By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the electrode terminal 5 in a region outside the image display unit as shown in FIG. Otherwise, as shown separately, in the region outside the image display unit, the signal line 12 is formed to include a part of the electrode terminal 5 ′ made of a transparent conductive layer via the first metal layer 82 ′. Become. This configuration is shown in FIG.
This is the same as the connection form between the picture element electrode 22 and the drain wiring 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, thereby completing the fifth embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, the source / drain wiring 1 is placed on the scanning line 11 including the picture element electrode 22.
The storage electrode 55 and the scanning line 11 formed simultaneously with the storage electrodes 2 and 21
FIG. 9 shows an example in which a plasma protective layer 76 ′, a gate insulating layer 30 ′, an amorphous silicon layer 31 ′ containing no impurities, and an amorphous silicon layer 33 ′ containing impurities are included.
Is exemplified. Storage capacitance 15 using storage capacitance line 16
However, since the scanning lines 11 and the pixel electrodes 22 are formed at the same time, when the common capacitance line 16 is arranged, the pixel electrode 22 is divided into two parts by the storage capacitance line 16 up and down. Please note. The configuration of the storage capacitor 15 is not limited to these, and other configurations are possible, but detailed description is omitted.

In the fifth embodiment, similarly to the third embodiment, the source / drain wirings 12 and 21 can be composed of two layers of a heat-resistant metal layer and an aluminum alloy layer. Since the anodized layer becomes slightly thinner and the leakage current of the insulated gate type tends to increase, the above-described consideration is required.

After the source / drain wirings 12 and 21 are formed, the first metal layer 82 'on the pseudo picture element electrode 75 must be removed.
If the thickness of the amorphous silicon layer 33 'containing impurities between the layers 21 is reduced and the thickness of the amorphous silicon layer 31' containing no impurities is also reduced, the effect on the transistor characteristics is large, so the first metal layer 82 ' Is important, and there is a high possibility that the material of the first metal layer 82 'is restricted. So the sixth
In the fifth embodiment, the above-mentioned restriction is lifted by a slight change in the manufacturing process of the fifth embodiment.

Embodiment 6 Embodiment 6 of the present invention will be described with reference to FIGS. In the sixth embodiment, that is, in the method of manufacturing an active substrate according to the twenty-seventh aspect, as shown in FIG. 12C, the transistor formation region 102 (and the storage capacitance formation region 104 on the scanning line 11) as shown in FIG.
Except that the second and first amorphous silicon layers 33 and 31, the gate insulating layer 30 and the plasma protection layer 76 are selectively removed to expose the glass substrate 2 and the pseudo pixel electrode 75. The same manufacturing process as that of the fifth embodiment is performed, and the first metal layer 82 'is continuously removed using the photosensitive resin pattern used for the selective pattern formation to expose the transparent conductive layer 81'. As a result, the transparent conductive picture element electrode 22 is exposed on the insulating substrate 2.

Thereafter, the photosensitive resin pattern is removed, and as shown in FIG. 12D, the low-resistance metal layer 71 by plating and the organic insulating layer by electrodeposition are formed on the exposed scanning lines 11 and gate electrode electrodes 105. 72 is formed. At this time, since the pixel electrode 22 is electrically isolated and floating, the low resistance metal layer and the organic insulating thin layer are not formed on the pixel electrode 22.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as T, a heat-resistant metal thin film layer 34 of, for example, Ti, Ta or the like is formed as a heat-resistant metal layer having a thickness of about 0.1 μm.
Then, an AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a low-resistance wiring layer. The two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and the signal line 12 also serving as the source electrode of the insulated gate transistor and the drain wiring 21 including a part of the pixel electrode 22 are formed. Are selectively formed.

Finally, as shown in FIG. 12F, while irradiating light, the source / drain wirings 12 and 21 are anodized to form an insulating layer on the surface thereof, and the source / drain wirings 12 and 21 are formed between them. Anodized portions of the second amorphous silicon layer 33 'containing impurities and the first amorphous silicon layer 31' containing no impurities are anodized to form a silicon oxide layer (SiO ₂ ) Form 66 and 67. By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the electrode terminal 5 in a region outside the image display unit as shown in FIG. Otherwise, as shown separately, the signal line 12 is formed including a part of the electrode terminal 5 ′ made of a transparent conductive layer in a region outside the image display unit. This configuration corresponds to the picture element electrode 2 shown in FIG.
2 and the drain wiring 21 are connected in the same manner. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the sixth embodiment of the present invention. As described above, in the sixth embodiment, when the first metal layer 82 'on the pseudo pixel electrode 75 is removed, the thin film in the other region is covered with the photosensitive resin, so that the selectivity becomes a problem. In addition, the first metal layer 82 'is not exposed at the time of anodic oxidation of the source / drain wiring, so that it is not necessary to be anodic oxidizable. In other words, the limitation as the scanning line material is only heat resistance. I have.

In the above-described embodiment, since the source / drain wiring of the channel-etch type insulated gate transistor and the channel surface are simultaneously anodized, the reduction of the resistance of the source / drain wiring can be achieved by any method other than increasing the film thickness. An increase in the number of manufacturing steps is inevitable. Therefore, in the following embodiments, an insulated gate transistor having an insulating layer on a channel is employed to reduce the resistance of the source / drain wiring. Of course, an insulating layer for protecting the channel may be formed on the channel surface of the channel-etched insulated-gate transistor by any method or means. However, in the present invention, an etch-stop insulating film having a channel protective layer from the beginning is provided. The gate type transistor will be mainly described.

(Embodiment 7) Embodiment 7 of the present invention will be described with reference to FIGS. In the seventh embodiment, that is, in the method for manufacturing an active substrate according to the twenty-eighth invention, a glass substrate having a thickness of about 0.5 to 1.1 mm as an insulating substrate as shown in FIG. 2 using a vacuum film forming apparatus such as SPT (sputtering).
As the first metal layer of about μm, for example, Cr, Ta, Mo
The gate electrode 11 (and the storage capacitor line 16) also serving as a scanning line is selectively formed by a fine processing technique by applying an alloy or silicide thereof.

Next, as shown in FIG.
Using a D device, a first SiNx (silicon nitride) layer serving as a gate insulating layer, and a first amorphous silicon (aS
i) The second SiN which becomes the insulating layer for protecting the layer and the channel
The x layer and the three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32. further,
For example, a film thickness of 0.2 μm
A Mo (molybdenum) layer 40 is deposited.

Subsequently, the gate electrode 1 is formed by a fine processing technique.
The lift-off layer 40 and the protective layer 32 on the gate electrode 1
The width of the first amorphous silicon layer 31 is reduced to 40 'and 32' by selectively leaving the first amorphous silicon layer 31 thinner than that of FIG.
As shown in FIG. 3C, an amorphous silicon layer 33 containing, for example, phosphorus and having a thickness of about 0.05 μm is formed as a second semiconductor layer containing impurities using a PCVD apparatus, and SPT is used as a source (signal line) / drain electrode material. Using a device, for example, a film thickness of 0.1 μm
A second metal thin film 34 of Ti, Ta, Cr or the like is applied on the entire surface. Then, the combined thickness of the protective insulating layer 32 ′ and the lift-off layer 40 ′ is 0.3 μm, which is thicker than the lamination of the amorphous silicon layer 33 and the Ti thin film 34. Is likely to cause disconnection at the edge of the lift-off layer 40 '. Thereafter, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 'disappears as shown in FIG. Amorphous silicon layer 33 containing Ti and Ti thin film 3
4 is selectively lifted off (peeled off) to expose the second SiNx 32 'as a protective layer.

Subsequently, as shown in FIG. 14E, the amorphous silicon layer 31 'containing no impurities and the phosphorus-containing amorphous A pair of source (signal line) / drain wirings 12 and 2 composed of a stack of a silicon layer 33 'and a Ti thin film 34'
1 is selectively formed, but at this time, it is necessary to leave the protective layer 32 'while leaving the photosensitive resin pattern between the source (signal line) and the drain wiring 12, 21 (on the second SiNx 32'). And a storage electrode 55 is provided on the storage capacitor line 16.
To form Source (signal line) / drain wiring 12, 2
During the formation of the first and second storage layers 1, the scanning lines 11 and the storage capacitance lines 16 are formed by over-etching the amorphous silicon layer 33 'or changing the etching material (gas).
The amorphous silicon layer 31 containing no impurity and the gate insulating layer 30 are removed to expose the scanning line 11 and the storage capacitor line 16.

Thereafter, plating is applied to the first metal layer 85 exposed at a part of the peripheral portion of the glass substrate 2 shown in FIG. 38 in an electrolytic solution while applying a DC negative (−) potential from a clip or the like. Then, as shown in FIG. 14F, the low-resistance metal layer 71 is formed on the surface of the scanning line 11 and the gate electrode 105 which are exposed at least up to the inside of the image display portion or the vicinity of the formation region of the electrode terminal 6. As described above, when the thickness exceeds the thickness of the gate insulating layer 30 ', the first amorphous silicon layer 31' comes into contact with the film.
Subsequently, as shown in FIG. 14G, an organic insulating layer 72 (polyimide layer) is formed with a thickness of about 0.5 μm on the low-resistance metal layer 71 which is also exposed to the vicinity of the formation region of the electrode terminal 6. .

Further, as shown in FIG. 14 (h), the entire surface of the glass substrate 2 is coated with a film using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide) and a pixel electrode 2 on a glass substrate 2 including a part of a drain wiring 21 by a fine processing technique.
2 is selectively formed.

At this time, a transparent conductive electrode terminal 6 'including the scanning line 11 exposed outside the image display portion is also formed at the same time. Then, using the photosensitive resin pattern 65 used for the selective pattern formation of the pixel electrodes 22 as a mask, FIG.
As shown in (i), the low resistance metal layer 73 is formed on the source (signal line) / drain wirings 12 and 21 by plating, but it is not necessary to form the low resistance metal layer on the drain wiring 21. In fact, if plating is performed in a dark place, the amount of plating formed on the drain wiring 21 by the leakage current of the insulated gate transistor is insignificant. A plating layer is formed.
There is no restriction on the direction in which the thickness of the low-resistance metal layer on the source (signal line) / drain wirings 12 and 21 increases, and the low-resistance metal layer 73 having a thickness of, for example, about 0.3 μm is formed. Then, an organic insulating layer 74 (polyimide layer) having a thickness of about 0.2 μm is formed by electrodeposition on the low resistance metal layer 73 exposed at least up to the inside of the image display portion or the vicinity of the electrode terminal 5 formation region while irradiating light. Form. Since the electrodeposition is performed while irradiating light, the leakage current of the insulated gate transistor easily increases, and the organic insulating layer 74 having the same thickness as the signal line 12 is formed on the drain wiring 21. Since the non-conductive photosensitive resin pattern 65 exists on the pixel electrode 22, the formation of the low-resistance metal layer and the organic insulating layer can be prevented.

When the selective electrodeposition in the glass substrate 2 is performed, as shown in FIG. 13, a part of the signal line 12 whose surface is a low-resistance metal layer in a region outside the image display portion is connected to an electrode terminal. 5 can be set. Of course, if plating is selectively performed in the substrate, a part of the signal line 12 becomes the electrode terminal 5 due to the lamination of the amorphous silicon layer 33 'and the Ti thin film 34'. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer in the area outside the image display unit is connected to the signal line 12.
Will be formed. This configuration is shown in FIG.
This is the same as the connection form between the picture element electrode 22 and the drain wiring 21 shown in (i). Then, as shown in FIG. 14 (j), the active substrate 2 obtained by removing the photosensitive resin pattern 65 and a color filter are bonded to form a liquid crystal panel, and the seventh embodiment of the present invention is completed. I do. Regarding the configuration of the storage capacitor 15, the storage electrode 55 and the storage capacitor line 16 formed simultaneously with the source / drain wirings 12 and 21 on the storage capacitor line 16 are composed of the gate insulating layer 30 ′ and the amorphous silicon FIG. 13 shows an example in which a structure is formed via a layer 31 'and an amorphous silicon layer 33' containing impurities.
However, the configuration of the storage capacitor 15 is not limited to this, and may be configured via a thin film layer including the gate insulating layer 30 between the pixel electrode 22 and the preceding scanning line 11. good. Further, other configurations are possible, but detailed description is omitted.

Eighth Embodiment An eighth embodiment of the present invention will be described with reference to FIGS. In the seventh embodiment, the resistance of the scanning line 11 is not reduced at the intersection of the scanning line 11 and the signal line 12. Therefore, the eighth embodiment is such that a manufacturing process is performed such that the scanning lines 11 are exposed before the signal lines 12 are formed. In the active substrate manufacturing method according to the twenty-ninth aspect, the lift-off is performed on the protective layer 32. Until a Mo (molybdenum) layer 40 having a thickness of, for example, about 0.2 μm is applied as a layer, the process proceeds in the same manufacturing process as in the seventh embodiment.

Thereafter, as shown in FIG. 16C, a photosensitive resin pattern 41 slightly thinner than the gate electrode 11 is formed on the lift-off layer 40 on the transistor formation region by a fine processing technique, for example, to a thickness of about 2 μm. To form selectively. Then, using the photosensitive resin pattern 41 as a mask, the molybdenum layer 40, the protective insulating layer 32, the first amorphous silicon layer 31, and the gate insulating layer 30 are sequentially etched to expose the scanning lines 11 and the storage capacitor lines 16, 40 ', 3 respectively
2 ′, 31 ′, 30 ′ are formed. Also in this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using gas, and it is preferable to control the taper of the cross section of the multilayer film.

Subsequently, the film thickness of the photosensitive resin pattern 41 is reduced by, for example, about 0.5 μm to 41 ′ by a treatment in an oxygen gas plasma or the like, and then, as shown in FIG. Using the 41 ′ as a mask, the molybdenum layer 40 ′ and the protective insulating layer 32 ′ are etched to partially expose the first amorphous silicon layer 31 ′ (about 0.5 μm on one side). In order to enhance the lift-off function of the molybdenum layer 40 ″ after the etching, the molybdenum layer 40 ′ is etched by RIE having a strong anisotropy so that its cross-sectional shape stands sharply.
It is necessary to adopt a (Reactive-Ion-Etch) type dry etch.

Thereafter, the photosensitive resin pattern 41 ′ is removed, and then, as shown in FIG. 38, the first metal layer 85 (and 86) exposed at a part of the peripheral portion of the glass substrate 2 is removed. Plating is performed in an electrolytic solution while applying a DC negative (−) potential from a clip or the like, and the exposed scanning line 11 and gate electrode 105 (and storage capacitor line 1) are exposed as shown in FIG.
A low resistance metal layer 71 having a thickness of about 0.2 μm is formed on the surface of 6). Then, as shown in FIG. 16F, an organic insulating layer 72 (polyimide layer) having a thickness of about 0.5 μm is formed on the low resistance metal layer 71 which is exposed at least up to the inside of the image display portion or the vicinity of the electrode terminal 6 formation region. It is formed with a thickness. (Similarly, an organic insulating layer is also formed on the low resistance metal layer on the storage capacitor line 16).

Further, as shown in FIG. 16G, an amorphous silicon layer 33 containing, for example, phosphorus and having a thickness of about 0.05 μm is formed as a second semiconductor layer containing impurities by using a PCVD apparatus.
Then, using a SPT device as a source (signal line) / drain electrode material, a second metal thin film 34 of, for example, Ti, Ta, Cr or the like having a thickness of about 0.1 μm is applied to the entire surface. Thereafter, when the insulating substrate 2 is left in an aqueous solution of hydrogen peroxide containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 "disappears and the molybdenum layer 40" as shown in FIG. Amorphous silicon layer 33 containing phosphorus and Ti thin film 3
4 is a second protective layer which is selectively lifted off (peeled off).
Of SiNx32 ″ is exposed.

Subsequently, as shown in FIG. 16 (i), the amorphous silicon layer 31 'containing no impurity on the gate electrode 11 and the amorphous A pair of source (signal line) / drain wirings 12 and 21 composed of a stack of a silicon layer 33 'and a Ti thin film 34' are selectively formed.

Further, as shown in FIG. 16 (j), the entire surface of the glass substrate 2 is coated with a film using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide) and a pixel electrode 2 on a glass substrate 2 including a part of a drain wiring 21 by a fine processing technique.
2 is selectively formed.

At this time, a transparent conductive electrode terminal 6 'including the scanning line 11 exposed outside the image display portion is also formed at the same time. Then, as shown in FIG. 16 (k), the photosensitive resin pattern 6 used for selective pattern formation of the picture element electrode 22 is formed.
5 is again used as a mask, and the source (signal line)
A low resistance metal layer 73 is formed on the drain wirings 12 and 21. Then, while irradiating the light, the organic insulating layer 74 (polyimide) is deposited by electrodeposition while irradiating the light on the low resistance metal layer 73 on the signal line 12 which is exposed at least to the inside of the image display portion or the vicinity of the electrode terminal 5 formation region. Layer) is formed with a thickness of about 0.2 μm.

When selective electrodeposition within the glass substrate 2 is performed, as shown in FIG. 15, a part of the signal line 12 whose surface is the low-resistance metal layer 73 in the region outside the image display portion is connected to the electrode terminal. 5 can be set. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer is formed including the signal line 12 in a region outside the image display unit. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain wiring 21 shown in FIG. And FIG.
As shown in (l), the active substrate 2 obtained by removing the photosensitive resin pattern 65 and a color filter are bonded to form a liquid crystal panel, thereby completing the eighth embodiment of the present invention. Regarding the configuration of the storage capacitor 15, FIG. 15 illustrates an example in which the pixel electrode 22 and the storage capacitor line 16 are configured via the organic insulating layer 72 formed on the storage capacitor line 16. The configuration of the storage capacitor 15 is not limited to this, and it may be configured via a thin film layer including an appropriate insulating layer between the pixel electrode 22 and the preceding scanning line 11,
Other configurations are possible, but detailed description is omitted. Further, as in the other embodiments, the electrode terminals 6 of the scanning lines can be made of a source / drain wiring material instead of a transparent conductive layer.

(Embodiment 9) Embodiment 9 of the present invention will be described with reference to FIGS. It is also possible to obtain a semiconductor device for an image display device having a different configuration by replacing some steps with the eighth embodiment, and this will be described as a ninth embodiment. In the method for manufacturing an active substrate according to the thirtieth aspect, an organic insulating layer 72 (polyimide layer) having a thickness of about 0.5 μm is formed on a low-resistance metal layer 71 that is exposed at least up to the inside of an image display portion or the vicinity of a region where electrode terminals 6 are formed. The same manufacturing process as in the eighth embodiment proceeds until the film is formed with the thickness. Thereafter, as shown in FIG. 18F, the exposed first amorphous silicon layer 31 'is ion-implanted or irradiated into the exposed first amorphous silicon layer 31' using the lift-off layer 40 "as a mask. It is converted to an amorphous silicon layer 33 '.

Then, as shown in FIG. 18 (g), using a SPT device as a source (signal line) / drain electrode material, for example, a second film of Ti, Ta, Cr or the like having a film thickness of about 0.1 μm is formed.
Is deposited on the entire surface of the glass substrate 2.

Subsequently, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia,
As shown in FIG. 18H, the molybdenum layer 40 "disappears, and the Ti thin film 34 on the molybdenum layer 40" is selectively lifted off (peeled off), so that the second S layer serving as a protective layer is formed.
The iNx32 "is exposed. The feature of the ninth embodiment is that the lift-off is facilitated because only the thin Ti thin film 34 exists on the lift-off layer 40" as compared with the eighth embodiment.

Then, as shown in FIG. 18I, a Ti thin film 34 ′ is formed on the amorphous silicon layer 33 ′ containing impurities on the gate electrode 11 and on the insulating substrate 2 by the fine processing technique.
A pair of source (signal lines) / drain lines 12,
21 are selectively formed. At this time, the electrode terminal 6 made of a Ti thin film may be formed at the same time as including the scanning line 11 exposed outside the image display unit, or as in the eighth embodiment, the electrode terminal 6 may be transparent when a subsequent pixel electrode is formed. A conductive picture element electrode 6 'may be formed.

Further, as shown in FIG. 18 (j), the entire surface of the glass substrate 2 is formed using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide) and a pixel electrode 2 on a glass substrate 2 including a part of a drain wiring 21 by a fine processing technique.
2 is selectively formed.

Thereafter, as shown in FIG. 18 (k), using the photosensitive resin pattern 65 used for selective pattern formation of the picture element electrode 22 as a mask, the source (signal line) / drain wiring 12 is again plated by plating. , 21 are formed with a low-resistance metal layer 73. Then, while irradiating light, the organic insulating layer 74 (polyimide layer) is deposited to about 0.2 μm on the low resistance metal layer 73 on the signal line 12 which is exposed at least up to the inside of the image display portion or the vicinity of the electrode terminal 5 formation region. It is formed with a film thickness of.

By performing selective electrodeposition in the glass substrate 2, as shown in FIG. 17, a part of the signal line 12 whose surface is a low-resistance metal layer in a region outside the image display portion is connected to the electrode terminal 5.
It can be. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer is formed including the signal line 12 in a region outside the image display unit. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain wiring 21 shown in FIG. Finally, FIG.
As shown in (5), the active substrate 2 obtained by removing the photosensitive resin pattern 65 and a color filter are bonded to form a liquid crystal panel, thereby completing the ninth embodiment of the present invention.

In the seventh to ninth embodiments, the step of forming the islands of the semiconductor layer is rationalized. However, like the fifth to sixth embodiments, the step of forming the scanning lines and the pixel electrodes is rationalized. This is also possible, and will be described as tenth to twelfth embodiments.

(Embodiment 10) Embodiment 1 of the present invention
0 will be described with reference to FIGS. In the tenth embodiment, that is, in the method of manufacturing an active substrate according to the thirty-first invention, first, as shown in FIG. 20A, a scan comprising a stack of a transparent conductive layer 81 'and a first metal layer 82'. The gate electrode 11 also serving as a line and the pseudo picture element electrode 75 are selectively formed, and the plasma protection layer 76 is deposited on the entire surface.

Thereafter, a first SiNx (silicon nitride) layer serving as a gate insulating layer and a first amorphous silicon (a-Si) serving as a channel of an insulated gate transistor containing almost no impurities are formed by using a PCVD apparatus. A second SiNx layer serving as an insulating layer for protecting the layer and the channel, and three types of thin film layers are sequentially deposited in a thickness of, for example, about 0.3-0.05-0.1 μm.
31, 32.

Subsequently, the gate electrode 1 is formed by a fine processing technique.
The first amorphous silicon layer 31 is exposed by leaving the protective layer 32 on the first layer 32 selectively thinner than the gate electrode 11 to form a second layer 32 ', and as shown in FIG. Using a PCVD apparatus, an amorphous silicon layer 33 containing, for example, phosphorus and having a thickness of about 0.05 μm is deposited over the entire surface.

Thereafter, as shown in FIG. 20C, the transistor formation region 102 (and the storage capacitor formation region 10).
Except for 4), the second and first amorphous silicon layers 33, 31
And the gate insulating layer 30 and the plasma protection layer 76 are selectively removed to expose the glass substrate 2. And FIG.
As shown in (d), on the exposed scanning line 11 and the gate electrode 105, a low-resistance metal layer 71 is formed by plating and an organic insulating layer 72 is formed by electrodeposition. At this time, the pseudo picture element electrode 75
Is isolated and electrically floating, so that the low resistance metal layer and the organic insulating layer are not formed on the pseudo picture element electrode 75.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as T, a heat-resistant metal thin film layer 34 of, for example, Ti, Ta or the like is deposited as a heat-resistant metal layer having a thickness of about 0.1 μm. Then, the signal line 12, which also includes the second amorphous silicon layer 33 ′ and is made of the Ti thin film layer 34 ′ and also serves as a source wiring, is formed on the insulating substrate 2 by a microfabrication technique so as to partially overlap the protective insulating layer 32 ′. The drain wiring 21 and a part of the pixel electrode 75 are selectively formed. At this time, the electrode terminals 6 made of a Ti thin film including the scanning lines 11 exposed outside the image display unit are formed at the same time. Further, by using the photosensitive resin pattern used for the selective pattern formation as a mask, the first metal layer 82 'on the pseudo picture element electrode 75 is removed to expose most of the transparent conductive layer 81', thereby forming the picture element electrode. 22 are formed.

Subsequently, after removing the photosensitive resin pattern, a low-resistance metal layer 73 is formed on the signal line 12 by plating in a dark place as shown in FIG. Then, an organic insulating layer 74 (polyimide layer) is electrodeposited on the low-resistance metal layer 73 on the signal line 12 which is exposed at least up to the inside of the image display section or the vicinity of the electrode terminal 5 formation area in a dark place.
Is formed with a thickness of about 0.2 μm.

When selective electrodeposition within the glass substrate 2 is performed, as shown in FIG. 19, a portion of the signal line 12 whose surface is a low resistance metal layer is
It can be. Otherwise, as shown separately, the signal line 12 is connected to the first metal layer 8 in an area outside the image display unit.
It is formed to include a part of the electrode terminal 5 'made of a transparent conductive layer via 2'. This configuration is shown in FIG.
Is the same as the connection form between the picture element electrode 22 and the drain wiring 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel,
The tenth embodiment of the present invention is completed.

In the tenth embodiment, the first metal layer 82 'on the pseudo picture element electrode 75 must be removed after the formation of the source / drain wirings 12, 21 as in the fifth embodiment. At this time, since the protective layer 32 'made of SiNx between the source / drain wirings 12 and 21 is thin, the thickness is reduced, and if the amorphous silicon layer 31' containing no impurity which is a channel is exposed, the reliability of the transistor characteristics is improved. Is impaired. To avoid this, the selectivity between the protective layer 32 'and the first metal layer 82' is important, and the first metal layer 8 '
There is a high possibility that the material of 2 ′ is restricted. Therefore, in the eleventh embodiment, the above restriction is not lifted by a slight change in the manufacturing process of the tenth embodiment.

(Embodiment 11) Embodiment 1 of the present invention
1 will be described with reference to FIGS. In the method of manufacturing an active substrate according to the thirty-second aspect, as shown in FIG. 22C, the second and first amorphous silicon layers except for the transistor forming region 102 (and the storage capacitor forming region 104) are formed. 33, 31, gate insulating layer 30, and plasma protection layer 76
The same manufacturing process as in the tenth embodiment is performed until the glass substrate 2 is exposed by selectively removing the glass substrate 2. The first metal layer 82 'is subsequently removed by using the photosensitive resin pattern used for the selective pattern formation, and the transparent conductive layer 8 is formed.
Expose 1 '. As a result, the transparent conductive scanning lines 11 and the pixel electrodes 22 are exposed on the insulating substrate 2.

Thereafter, the photosensitive resin pattern is removed, and as shown in FIG. 22D, a low resistance metal layer 71 by plating and an organic insulating layer 72 by electrodeposition are formed on the exposed scanning lines 11 and gate electrodes 105. To form At this time, the pixel electrode 22
Is isolated and electrically floating, so that a low resistance metal layer and an organic insulating layer are not formed on the pixel electrode 22.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as T, a heat-resistant metal thin film layer 34 of, for example, Ti, Ta or the like is deposited as a heat-resistant metal layer having a thickness of about 0.1 μm. Then, the signal line 12 composed of a Ti thin film layer 34 ′ and also serving as a source wiring is formed on the insulating substrate 2 including the second amorphous silicon layer 33 ′ so as to partially overlap with the protective insulating layer 32 ′ by a fine processing technique. The drain wiring 21 and a part of the elementary electrode 22 are selectively formed.

Subsequently, as shown in FIG. 22F, a low-resistance metal layer 73 is formed on the signal line 12 by plating in a dark place. Then, the organic insulating layer 7 is electrodeposited on the low-resistance metal layer 73 on the signal line 12 which is also exposed at least up to the inside of the image display portion or the vicinity of the electrode terminal 5 formation region in a dark place.
4 (polyimide layer) is formed with a thickness of about 0.2 μm.

If the selective electrodeposition in the glass substrate 2 is performed, a part of the signal line 12 whose surface is a low-resistance metal layer in a region outside the image display portion is connected to the electrode terminal 5 as shown in FIG.
It can be. Otherwise, as shown separately, the signal line 12 is formed including the electrode terminal 5 'made of a transparent conductive layer in a region outside the image display unit. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain wiring 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the eleventh embodiment of the present invention.

(Embodiment 12) Embodiment 12 of the present invention
Will be described with reference to FIGS. In the twelfth embodiment which is the most streamlined process, that is, in the active substrate manufacturing method according to the thirty-third invention, first, FIG.
As shown in (a), a transparent conductive layer 81 ′ is formed on an insulating substrate 2.
The gate electrode 11 also serving as a scanning line and a pseudo picture element electrode 75, which are formed by laminating the first metal layer 82 'and the first metal layer 82', are selectively formed.

Thereafter, as shown in FIG. 24B, a plasma protection layer 76 is deposited on the entire surface, and a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed by using a PCVD apparatus, and almost all impurities are contained. A first amorphous silicon (a-Si) layer serving as a channel of an insulated gate transistor, and a second SiNx layer serving as an insulating layer for protecting the channel, and three types of thin film layers, for example, 0.3-0.05- The layers are sequentially deposited at a film thickness of about 0.1 μm to obtain 30, 31, and 32. Further, a Mo (molybdenum) layer 40 having a thickness of about 0.2 μm, for example, is deposited on the protective layer 32 as a lift-off layer.

Then, as shown in FIG. 24C, a photosensitive resin pattern 41 slightly narrower than the gate electrode 11 is formed on the lift-off layer 40 on the gate electrode 11 by a fine processing technique, for example, to a thickness of about 2 μm. To form selectively. Then, using the photosensitive resin pattern 41 as a mask, the molybdenum layer 40, the protective insulating layer 32, the first amorphous silicon layer 31, and the gate insulating layer 30 are sequentially etched to expose the scanning lines 11 and 40 ', 32, respectively. ', 31' and 30 '. Further, using the photosensitive resin pattern used for the selective pattern formation, the first metal layer 82 'is successively removed to expose the transparent conductive layer 81'. As a result, the transparent conductive picture element electrode 22 is exposed on the insulating substrate 2.

Subsequently, the film thickness of the photosensitive resin pattern 41 is reduced by, for example, about 0.5 μm to 41 ′ by a treatment in an oxygen gas plasma or the like, and then the photosensitive resin pattern 41 is formed as shown in FIG. Using the pattern 41 'as a mask, the molybdenum layer 40' and the protective insulating layer 32 'are etched and
The first amorphous silicon layer 31 ′ is partially exposed (about 0.5 μm on one side) to 0 ″ and 32 ″.

Subsequently, the photosensitive resin pattern 41 '
Then, the transparent conductive layer 85 exposed at a part of the periphery of the glass substrate 2 shown in FIG. 38 is plated in an electrolytic solution while applying a DC (-) potential from a clip or the like. The scanning line 11 exposed as shown in FIG.
And a low-resistance metal layer 71 is formed on the surface of the gate electrode 105. Then, an organic insulating layer 72 (polyimide layer) is formed with a thickness of about 0.3 μm on the low resistance metal layer 71 exposed at least up to the inside of the image display portion or the vicinity of the formation region of the electrode terminal 6.

Furthermore, although not shown, the lift-off layer 4
The exposed first amorphous silicon layer 31 'is converted into a second amorphous silicon layer 33' containing impurities by ion-implanting or irradiating the exposed first amorphous silicon layer 31 'with 0 "as a mask.

Then, as shown in FIG. 24 (f), using a SPT device as a source (signal line) / drain wiring material, for example, a second film of Ti, Ta, Cr or the like having a film thickness of about 0.1 μm is formed.
Is deposited on the entire surface. Thereafter, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 "disappears and the Ti on the molybdenum layer 40" disappears as shown in FIG. The thin film 34 is selectively lifted off (peeled off) to expose the second SiNx 32 ″ serving as a protective layer.

Subsequently, as shown in FIG. 24H, a Ti thin film 3 is formed on the amorphous silicon layer 33 ′ containing impurities on the gate electrode 11 and on the insulating substrate 2 by the fine processing technique.
4 ′ source wiring (signal line) 12 and picture element electrode 22
And the drain wiring 21 is selectively formed to include a part of the drain wiring 21. At this time, the scanning line 1 including a part of the pixel electrode 22
The storage electrode 55 is formed in the storage capacitor formation region on the storage capacitor 1.

Further, as shown in FIG. 24I, a low-resistance metal layer 7 is formed on at least the signal line 12 by plating in a dark place.
Form 3 Then, an organic insulating layer 74 (polyimide layer) having a thickness of about 0.2 μm is formed by electrodeposition on the low-resistance metal layer 73 on the signal line 12 which is exposed at least to the inside of the image display portion or the vicinity of the electrode terminal 5 in a dark place. It is formed with a film thickness.

If selective electrodeposition within the glass substrate 2 is performed, a part of the signal line 12 whose surface is a low-resistance metal layer in a region outside the image display portion is connected to the electrode terminal 5 as shown in FIG.
It can be. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer in a region outside the image display unit is formed to be included in a part of the signal line 12. This configuration is the same as the connection form between the picture element electrode 22 and the drain wiring 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the twelfth embodiment of the present invention. Regarding the configuration of the storage capacitor 15, the source / drain wiring 1
The storage electrode 55 and the scanning line 11 formed simultaneously with the storage electrodes 2 and 21
FIG. 23 illustrates an example in which the storage capacitor 15 is configured via the organic insulating layer 72. However, the configuration of the storage capacitor 15 is not limited to these, and other configurations are possible. Omitted.

In the first to twelfth embodiments, a bottom gate type insulated gate transistor is used as a switching element. However, a top gate type insulated gate transistor can be used. This will be described as an embodiment.

(Embodiment 13) Embodiment 1 of the present invention
3 will be described with reference to FIGS. In the thirteenth embodiment, that is, in the method for manufacturing an active substrate according to the thirty-fourth invention, first, although not shown, the insulating transparent substrate 2 having excellent transparency, heat resistance, and chemical resistance is manufactured by Corning as described above. On one main surface of trade name 1737, SiO2 or SiNx having a thickness of about 0.3 μm is applied as an alkali blocking layer. After that, an amorphous silicon layer having a thickness of about 0.05 μm is deposited using a PCVD apparatus, and the content of hydrogen is reduced by heating. Then, the amorphous silicon layer is crystallized by irradiation with an excimer laser. Of course, an excimer laser may be irradiated after forming amorphous silicon or microcrystalline silicon by sputtering using no silicon, for example, silicon as a target. Then, as shown in FIG. 26A, the crystallized low-temperature polysilicon, which is crystallized, is selectively removed and left in an island shape 100 on the glass substrate 2.

Next, a substrate heating temperature of 400 to 50 is formed as the gate insulating layer 30 by CVD or TEOS-PCVD.
At about 0 ° C., SiO 2 having a thickness of about 0.1 μm and a first metal layer 82 serving as a gate metal layer, for example, M having a thickness of about 0.1 μm
After the oW alloy is applied over the entire surface, as shown in FIG. 26B, MoW and SiO2 are etched by a fine processing technique corresponding to the pattern of the scanning line 11 (and the common capacitance line 16) to form a low-temperature poly. The silicon 100 is exposed.

Then, for example, as shown in FIG. 38, the first metal layer 8 exposed at a part of the peripheral portion of the glass substrate 2
Plating is performed in an electrolytic solution while applying a DC negative (−) potential from a clip or the like to 5 to form a low-resistance metal layer 71 with a thickness of about 0.3 μm on the exposed scanning line 11 (gate electrode). Subsequently, as shown in FIG. 26C, an organic insulating layer 72 (polyimide layer) is formed on the low-resistance metal layer 71 to a thickness of about 0.2 μm by electrodeposition. Of course, these thin films can be formed by using an in-substrate selective chemical treatment apparatus or by using an appropriate mask in a usual manner, and limiting these thin films to the vicinity of the electrode terminal 6 formation region as necessary. It is.

Thereafter, although not shown, phosphorus or boron is implanted into the low-temperature polysilicon 100 as an impurity by ion implantation or ion irradiation using the gate electrode 11 as a mask to form the source / drain 10 of the insulated gate transistor.
1, 102 are formed. Since the low-resistance metal layer 71 and the organic insulating layer 72 are formed on the gate electrode 11 and the pattern width is slightly widened (about 0.2 to 0.4 μm), the widened portion functions as a mask for ion implantation, It is possible to form a region with less or no ion implantation than the source / drain 101, 102 (LDD structure or offset structure).

Subsequently, as shown in FIG. 26D, for example, SiO.sub.2 having a thickness of about 0.3 .mu.m is deposited as the interlayer insulating layer 200 by the above-described method, and is formed on the source / drain 101 and 102 by the fine processing technique. A pair of openings 103 and 104 are formed. At the same time, the scanning line 1 is set in an area outside the image display unit.
An opening 60 is also formed on 1 to expose a part of the scanning line 11. It goes without saying that the organic insulating layer 72 may be etched following the etching of the interlayer insulating layer 200. Further, it is also possible to adopt a heat-resistant photosensitive acrylic resin as the interlayer insulating layer 200 and to form it to have a thickness of 1 μm or more to flatten the surface of the insulating substrate 2.

Subsequently, as shown in FIG. 26E, a heat-resistant metal thin film of, for example, Ti, Ta, Cr or the like having a thickness of about 0.1 μm is deposited as a source / drain electrode material by using a film forming apparatus such as sputtering. After that, source (signal line) / drain wirings 12 and 21 including a pair of openings 103 and 104 are formed by a fine processing technique. At this time, at the same time, the electrode terminals 6 made of a heat-resistant metal thin film including the exposed scanning lines 11 in the opening 60 outside the image display unit are formed.

Further, as shown in FIG.
After depositing ITO, which is a transparent conductive layer of about 0.1 to 0.2 μm, using a film forming apparatus such as sputtering, the pixel electrode 22 including the drain wiring 21 is formed on the insulating substrate 2 by fine processing technology.
Are formed selectively. Then, using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrodes 22 as a mask, at least the source (signal line) 1 is again plated.
A low-resistance metal layer 73 having a thickness of, for example, about 0.2 μm is formed on the substrate 2. However, if plating is performed while irradiating light, the leakage current of the insulated gate transistor easily increases, and the signal A low resistance metal layer 73 having the same thickness as the line 12 is formed. Subsequently, the organic insulating layer 74 (polyimide layer) is deposited by electrodeposition on the low-resistance metal layer 73 on the source / drain wirings 12 and 21 which are exposed at least up to the inside of the image display portion or the vicinity of the electrode terminal 5 while irradiating light. Is formed with a thickness of about 0.3 μm.

When the selective electrodeposition in the glass substrate 2 is performed, as shown in FIG. 25, a part of the signal line 12 whose surface is a low-resistance metal layer is
It can be. Otherwise, as shown separately, the electrode terminal 5 ′ made of a transparent conductive layer is formed including the signal line 12 in a region outside the image display unit. This configuration is the same as the connection configuration between the picture element electrode 22 and the drain wiring 21 shown in FIG. Finally, FIG.
As shown in (g), the active substrate 2 obtained by removing the photosensitive resin pattern 65 and a color filter are bonded to form a liquid crystal panel, thereby completing the thirteenth embodiment of the present invention. I do. Regarding the configuration of the storage capacitor 15, an example in which the pixel electrode 22 and the scanning line 11 are configured via an organic insulating layer 72 formed on the scanning line 11 is shown in FIG.
5, the configuration of the storage capacitor 15 is not limited to this, and the pixel electrode 22 and the storage capacitor line 16 may be configured via the organic insulating layer 72. Further, other configurations are possible, but detailed description is omitted.

The manufacturing process can be reduced even in a liquid crystal image display device using a bottom-gate insulated gate transistor. The fourteenth embodiment is an embodiment in which the process of forming the pixel electrodes and the scanning lines is rationalized. An embodiment in which the process of forming the pixel electrodes and the signal lines is rationalized will be described below as a fifteenth embodiment.

(Embodiment 14) Embodiment 14 of the present invention
Will be described with reference to FIGS. In the fourteenth embodiment, that is, in the method for manufacturing an active substrate according to the thirty-fifth invention, the same manufacturing as the thirteenth embodiment is performed until the island-shaped low-temperature polysilicon 100 is formed and the gate insulating layer 30 is formed on the entire surface. Proceed with the process. After that, a transparent conductive layer 81 having a film thickness of about 0.1 μm, which becomes a scanning line and a pixel electrode, is deposited on the entire surface, and then the pattern of the scanning line 11 (and the common capacitance line 16) is changed as shown in FIG. The low-temperature polysilicon 100 is exposed by etching the transparent conductive layer 81 and the gate insulating layer 30 by a fine processing technique corresponding to the pixel electrode 22.

For example, the transparent conductive layer 85 exposed at a part of the peripheral portion of the glass substrate 2 shown in FIG. 38 is plated in an electrolytic solution while applying a DC (-) potential from a clip or the like. , Exposed scanning line 11 (gate electrode)
A low resistance metal layer 71 is formed thereon. Continuing with FIG.
As shown in (c), an organic insulating layer 72 (polyimide layer) is formed on the low-resistance metal layer 71 by electrodeposition with a thickness of about 0.2 μm. At this time, the pixel electrode 22 is electrically isolated, and the low resistance metal layer and the organic insulating layer are not formed on the pixel electrode 22.

Thereafter, although not shown, phosphorus or boron is implanted as impurities into the low-temperature polysilicon 100 by ion implantation or ion irradiation using the gate electrode 11 as a mask to form the source / drain 10 of the insulated gate transistor.
1, 102 are formed.

Subsequently, as shown in FIG. 28 (d), for example, SiO 2 having a thickness of about 0.2 μm is applied as the interlayer insulating layer 200 by the above-mentioned manufacturing method, and is formed on the source / drain 101 and 102 by the fine processing technique. A pair of openings 103 and 104 are formed. At this time, an opening 60 is formed on the scanning line 11 in a region outside the image display unit to expose a part of the scanning line 11 and, at the same time, an opening 38 is formed on the pixel electrode 22 to form the pixel electrode 22. However, it is also possible to form an opening 64 also on the electrode terminal 5 'made of a transparent electrode to expose most of the electrode terminal 5'.

Subsequently, as shown in FIG. 28 (e), a heat-resistant metal thin film having a thickness of, for example, about 0.1 μm is deposited as a source / drain electrode material by using a film forming apparatus such as sputtering, and then subjected to fine processing technology. The source line 12 including the opening 103 on the source, the opening 104 on the drain, and the drain line 21 including a part of the pixel electrode 22 are formed. At this time, at the same time, the electrode terminals 6 made of a heat-resistant metal thin film including the exposed scanning lines 11 in the opening 60 outside the image display unit.
To form

Then, as shown in FIG. 28F, a low-resistance metal layer 73 having a thickness of, for example, about 0.2 μm is formed on the source (signal line) 12 by plating in a dark place. Further, the organic insulating layer 74 (polyimide layer) is deposited by electrodeposition on the low resistance metal layer 73 on the source (signal line) 12 which is exposed at least up to the inside of the image display section or the vicinity of the electrode terminal 5 formation area in a dark place. It is formed with a thickness of about μm. The reason for performing these treatments in a dark place is to prevent the formation of a low-resistance metal, which is an opaque material, on the exposed picture element electrodes 22 to prevent the transmittance from lowering. Elementary electrode 2
This is for preventing a decrease in the effective voltage formed on the liquid crystal cell 2 and applied to the liquid crystal cell. However, if the organic insulating layer is minute, for example, several hundreds of degrees, it can be easily removed by processing with oxygen plasma, and if the organic insulating layer 74 formed on the source (signal line) 12 is formed thicker. good.

When selective electrodeposition within the glass substrate 2 is performed, as shown in FIG. 27, a part of the signal line 12 whose surface is a low-resistance metal layer is
It can be. Alternatively, as shown separately, in a region outside the image display unit, the signal line 12 is formed to include the electrode terminal 5 ′ made of a transparent conductive layer in the opening 64 formed in the interlayer insulating layer. This configuration is the same as the connection between the picture element electrode 22 and the drain wiring 21 shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel,
The fourteenth embodiment of the present invention is completed.

(Embodiment 15) Embodiment 1 of the present invention
5 will be described with reference to FIGS. In the fifteenth embodiment, that is, in the method for manufacturing an active substrate according to the thirty-sixth invention, as shown in FIG.
The same manufacturing steps as in the thirteenth embodiment are performed until a pair of openings 103 and 104 are formed on the source / drain 101 and 102 by depositing over the entire surface.

Subsequently, as shown in FIG. 30E, as the source / drain electrode material and the pixel electrode material, for example,
After depositing ITO, which is a transparent conductive layer having a thickness of about 0.1 μm, using a vacuum film forming apparatus such as sputtering, the source wiring 12 including the opening 103 on the source and the opening 104 on the drain are formed by fine processing technology. And the drain wiring 21 also serving as the pixel electrode 22 is formed. At this time, an electrode terminal 6 ′ made of a transparent conductive layer is formed at the same time, including the scanning line 11 exposed in the opening 60 outside the image display unit.

Then, as shown in FIG. 30 (f), a low-resistance metal layer 73 having a thickness of, for example, about 0.2 μm is formed on the signal line 12 by plating in a dark place. An organic insulating layer 74 (polyimide layer) having a thickness of about 0.2 μm is formed by electrodeposition on the low resistance metal layer 73 on the signal line 12 which is exposed in the display section or near the region where the electrode terminal 5 is formed.

If the selective electrodeposition in the glass substrate 2 is performed, as shown in FIG. 29, the surface of the glass substrate 2 is not covered by the signal line 12 or the transparent conductive layer whose surface is the low-resistance metal layer 73 outside the image display section. A part of the signal line 12 can be used as the electrode terminal 5. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel,
The fifteenth embodiment of the present invention is completed.

[0233]

As described above, according to the liquid crystal image display device of the present invention, the silicon oxide layer containing impurities for protecting the channel portion of the insulated gate transistor and the pentaoxide for protecting the source / drain wiring are provided. An anodized layer of a metal layer capable of being anodized such as a tantalum or aluminum oxide layer is formed at the same time by anodization and is insulated, so that the number of manufacturing steps is not increased. This is a special feature from the viewpoint of cost reduction.

Next, neither the above passivation nor the passivation for forming the organic insulating layer on the source / drain wiring by electrodeposition involves an extra heating step, so that an insulated gate transistor using an amorphous silicon layer as a semiconductor layer. Does not require excessive heat resistance. In other words, the effect of preventing the electrical performance from being deteriorated by the passivation is obtained.

Further, the isolation of the amorphous silicon layer containing a pair of impurities serving as the source / drain of the insulated gate transistor is performed by an electrochemical method of transforming the amorphous silicon layer containing the impurities by anodic oxidation. Therefore, there is no possibility that the electrical characteristics of the insulated gate transistor are degraded due to damage during etching of the channel semiconductor layer as in the related art, and an amorphous silicon layer containing no impurity serving as a channel is optimally formed. Since the film can be formed with the film thickness reduced, the operation rate of the PCVD apparatus and the particle generation state can be significantly improved.

In addition, the step of islanding the semiconductor layer and the step of forming an opening in the gate insulating layer can be performed simultaneously by introducing an organic insulating layer by electrodeposition. By rationalizing the simultaneous formation of the electrodes and the scanning lines, the number of photolithography steps can be further reduced compared to the conventional five times, and excellent effects such as reduction in manufacturing costs are promoted.

The reduction of resistance by plating on the exposed scanning lines and signal lines can be performed at low cost because no vacuum film forming apparatus and vacuum etching apparatus are used, and the yield is high because no particles are generated. In addition, it is necessary to promote the early realization of a large-screen, high-definition, high-speed response liquid crystal image display device.

As is clear from the above description, the requirement of the present invention is that an amorphous silicon layer containing impurities by using anodically oxidizable source / drain wiring material in a channel-etch type insulated gate transistor. At the same time, the surface of the source / drain wiring was anodized to form an insulating layer, and the low-resistance metal layer and the organic insulating layer were placed on the source wiring in the etch stop type and top gate type insulated gate transistors. The point is that the low resistance metal layer and the organic insulating layer are formed in a self-alignment manner on the scanning line exposed during the manufacturing process. In addition, a new means for realizing an LDD or offset structure for reducing a leak current in an insulated gate transistor using low-temperature polysilicon as a semiconductor material is proposed.

With respect to structures and members other than those described above, semiconductor devices for image display devices having different materials and film thicknesses of picture element electrodes, gate insulating layers, and the like, or differences in manufacturing methods thereof are also included in the scope of the present invention. The IP is controlled by applying a horizontal electric field to the liquid crystal between the pixel electrode and the counter electrode formed at a predetermined distance on the same substrate.
The present invention can be easily applied to an S (In-Plain-Switching) type liquid crystal panel. In addition, the usefulness of the present invention is not only in a reflective liquid crystal image display device in which a pixel electrode is made of a metal layer, but also in a transflective liquid crystal image display device in which a pixel electrode has a transparent electrode and a metal reflective electrode. It is clear that the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon, but may be microcrystalline silicon, polycrystalline silicon, a mixed crystal thereof, or another semiconductor material. .

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for an image display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the first embodiment of the present invention;

FIG. 3 is a plan view of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor device for an image display device according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the third embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor device for an image display device according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor device for an image display device according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the seventh embodiment of the present invention.

FIG. 15 is a plan view of a semiconductor device for an image display device according to an eighth embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the eighth embodiment of the present invention.

FIG. 17 is a plan view of a semiconductor device for an image display device according to a ninth embodiment of the present invention;

FIG. 18 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the ninth embodiment of the present invention.

FIG. 19 is a plan view of a semiconductor device for an image display device according to a tenth embodiment of the present invention.

FIG. 20 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the tenth embodiment of the present invention.

FIG. 21 is a plan view of a semiconductor device for an image display device according to an eleventh embodiment of the present invention.

FIG. 22 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the eleventh embodiment of the present invention.

FIG. 23 is a plan view of a semiconductor device for an image display device according to a twelfth embodiment of the present invention.

FIG. 24 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the twelfth embodiment of the present invention.

FIG. 25 is a plan view of a semiconductor device for an image display device according to a thirteenth embodiment of the present invention.

FIG. 26 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the thirteenth embodiment of the present invention;

FIG. 27 is a plan view of a semiconductor device for an image display device according to a fourteenth embodiment of the present invention.

FIG. 28 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the fourteenth embodiment of the present invention;

FIG. 29 is a plan view of a semiconductor device for an image display device according to a fifteenth embodiment of the present invention;

FIG. 30 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the fifteenth embodiment of the present invention;

FIG. 31 is a perspective view showing a mounted state of a liquid crystal panel.

FIG. 32 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 33 is a sectional view of a conventional liquid crystal panel.

FIG. 34 is a plan view of a conventional active substrate.

FIG. 35 is a sectional view of a manufacturing process of a conventional active substrate.

FIG. 36 is a plan view of a streamlined active substrate.

FIG. 37 is a sectional view of a manufacturing process of a streamlined active substrate.

FIG. 38 is a diagram showing a pattern arrangement in which scanning lines (storage capacitor lines) are connected in parallel;

FIG. 39 is a diagram showing an outline of an in-substrate selective electrochemical treatment apparatus.

[Explanation of symbols]

Reference Signs List 1 liquid crystal panel 2 active substrate (glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 electrode terminal 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line (gate wiring, gate electrode) 12 signal line (Source wiring, source electrode) 16 Storage capacitance line 17 Liquid crystal 21 Drain wiring (electrode) 22 (Transparent conductive) picture element electrode 30 Gate insulating layer 31 (First) amorphous silicon layer containing no impurity 33 Impurity Including (second) amorphous silicon layer 34-35 (anodically oxidizable) heat-resistant metal layer, low-resistance metal layer (AL), intermediate conductive layer 37 passivation insulating layer 38 (passivating insulating layer on picture element electrode Opening (formed) 40 Lift-off layer 60 Opening (on scan line) 65 Photosensitive resin pattern (for pixel electrode formation) Layers 66 and 67 (including and not including impurities) silicon oxide layers 68 to 705 tantalum oxide (Ta2O5), alumina (Al2
O3), titanium oxide (TiO2) 71, 73 organic insulating layer 72, 74 low-resistance metal layer 76 <v plasma protective layer 80 (anodically oxidizable) connection layer 81 transparent conductive layer 82 first metal layer (gate metal layer) 92) frame-shaped or square-shaped container 93 chemical solution (chemical solution or electrodeposition solution or plating solution) 94 cathode plate 95 DC power supply 98 impurity ion 100 (island-like) low-temperature polysilicon 101, 102 source / drain 200 interlayer insulating layer

Continued on the front page F-term (reference) 2H091 FA02Y GA08 GA13 LA12 MA10 2H092 GA40 GA49 JA25 JA26 JA37 JA41 JB57 KB24 MA08 MA14 MA24 NA27 PA01 PA03 PA08 5C094 AA43 BA03 BA43 CA19 DA15 EA04 EA07 EB02 FB12 FB15 FB18 DD01 DD02 DD14 EE02 EE04 EE05 EE06 EE07 EE14 EE37 EE41 EE44 EE48 FF02 FF03 FF09 FF29 FF30 GG02 GG13 PP GG15 GG25 GG43 GG45 HJ01 HJ12 HJ14 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN

Claims (38)

[Claims] 1. A bottom-gate insulated gate transistor in which a low-resistance metal layer and an organic insulating layer are formed on a gate electrode except for a channel formation region. 2. A top-gate insulated gate transistor in which a low-resistance metal layer and an organic insulating layer are formed on a gate electrode. 3. An insulated gate transistor having an insulating layer on a channel and a low resistance metal layer and an organic insulating layer formed on source / drain electrodes. 4. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a low-resistance metal layer and an organic layer are formed on at least scanning lines (and storage capacitance lines) in the image display unit. A liquid crystal image display device comprising: an insulating layer; 5. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, an insulating layer is provided on a channel of the insulated gate transistor and at least a signal line is provided in the image display unit A liquid crystal image display device, wherein a low resistance metal layer and an organic insulating layer are formed on the substrate. 6. An insulating substrate in which unit picture elements each having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) A low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for the gate electrode in the channel formation region, and one or more gate insulating layers are interposed. And a second semiconductor layer containing a pair of impurities that partially overlaps the gate electrode and becomes a source / drain on the first semiconductor layer containing no impurity on the gate electrode.
A source (signal line) / drain wiring made of one or more anodizable metal layers is formed on the pair of second semiconductor layers and on the insulating substrate; and on the insulating substrate. A picture element electrode including the drain wiring is formed on the surface of the source / drain wiring except at least the picture element electrode in the image display unit; A liquid crystal image display device, wherein a silicon oxide layer containing no impurities and a silicon oxide layer containing impurities are formed over a semiconductor layer. 7. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) A pixel electrode including the connection layer and a part of the connection layer, and a low-resistance metal layer on the scanning line (and the storage capacitance line) except for the gate electrode in the channel formation region. An organic insulating layer is formed, and the source / drain is partially overlapped with the gate electrode on the first semiconductor layer containing no impurity on the gate electrode via at least one gate insulating layer. Second containing a pair of impurities
A source wiring and a drain wiring including a part of the connection layer are formed of one or more metal layers on the pair of second semiconductor layers and the insulating substrate, the drain wiring including a part of the connection layer. An anodic oxide layer is formed on at least a surface of the source / drain wiring in the image display unit; and a silicon oxide layer containing no impurities and a silicon oxide containing impurities on the first semiconductor layer between the source / drain wirings A liquid crystal image display device comprising: a liquid crystal image display device; 8. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface thereof and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) And a storage capacitor line) and a pixel electrode. A low-resistance metal layer and an organic insulating layer are formed on a scanning line (and a storage capacitor line) except for a gate electrode in a channel formation region. A second semiconductor layer containing a pair of impurities that partially overlaps the gate electrode and becomes a source and a drain on the first semiconductor layer containing no impurity on the gate electrode via the gate insulating layer;
A source line (signal line) and a drain line including a part of a pixel electrode and an anodically oxidizable layer are formed on the pair of second semiconductor layers and the insulating substrate. An anodic oxide layer is formed on at least the surface of the source / drain wiring in the image display unit; and a silicon oxide layer containing no impurity on the first semiconductor layer between the source / drain wiring and an impurity A liquid crystal image display device comprising: a silicon oxide layer containing: 9. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) A low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for the gate electrode in the channel formation region, and one or more gate insulating layers are interposed. And a second semiconductor layer containing a pair of impurities that partially overlaps the gate electrode and becomes a source / drain on the first semiconductor layer containing no impurity on the gate electrode.
A source wiring (signal line) and a drain wiring made of one or more metal layers that can be anodized are formed on the pair of second semiconductor layers, and the drain wiring is formed on an insulating substrate. A anodic oxide layer is formed on the surface of the source / drain wiring except at least the picture element electrode in the image display portion; and on the first semiconductor layer between the source / drain wiring A liquid crystal image display device, wherein a silicon oxide layer containing no impurities and a silicon oxide layer containing impurities are formed. 10. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter opposed to the insulating substrate, a liquid crystal display device comprising: a transparent conductive layer and a heat-resistant metal layer on the insulating substrate; A scanning line (and a storage capacitor line) also serving as a gate electrode and a transparent conductive picture element electrode in which the heat-resistant metal layer is partially laminated are formed. A low-resistance metal layer and an organic insulating layer are formed on the capacitor line, and a gate electrode is formed on the first semiconductor layer containing no impurity on the gate electrode via at least one gate insulating layer. Including a pair of impurities that partially overlap with
And a drain including the laminated portion of the source wiring (signal line) and the heat-resistant metal layer of the transparent conductive picture element electrode on the pair of second semiconductor layers and the insulating substrate. Anodizable with wiring 1
An anodized layer formed on at least the surface of the source / drain wiring in the image display unit; and a silicon oxide layer containing no impurities on the first semiconductor layer between the source / drain wiring. And a silicon oxide layer containing impurities is formed. 11. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter opposed to the insulating substrate, a liquid crystal display device comprising: a transparent conductive layer and a heat-resistant metal layer laminated on the insulating substrate; A scanning line (and storage capacitor line) also serving as a gate electrode and a transparent conductive picture element electrode are formed, and a low-resistance metal layer and an organic material An insulating layer is formed, and the source / drain is partially overlapped with the gate electrode on the first semiconductor layer containing no impurity on the gate electrode via at least one gate insulating layer. Second containing a pair of impurities
A source line (signal line) and a drain line including a transparent conductive picture element electrode on the pair of second semiconductor layers and the insulating substrate, the drain line including an anodizable layer An anodized layer formed at least on the surface of the source / drain wiring in the image display unit; and a silicon oxide layer containing no impurities on the first semiconductor layer between the source / drain wiring. A liquid crystal image display device, comprising a silicon oxide layer containing impurities. 12. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix, In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) And a low-resistance metal layer and an organic insulating layer on the scanning lines (and the storage capacitance lines) except for the intersections of the channel forming region, the scanning lines (and the storage capacitance lines) and the signal lines. Is formed, a first semiconductor layer containing no impurity is formed on the gate electrode via one or more gate insulating layers, and the first semiconductor layer is formed on the first semiconductor layer more than the gate electrode. A thin protective insulating layer is formed, a second semiconductor layer containing impurities is formed on the first semiconductor layer excluding the protective insulating layer, and a source (signal line) made of a metal layer is formed on the second semiconductor layer. A) forming a drain wiring, forming a picture element electrode including the drain wiring on an insulating substrate, and forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring in the image display unit; A liquid crystal image display device. 13. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) And a storage capacitor line), a low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for a channel formation region, and one or more gate insulating layers are formed on the gate electrode. A first semiconductor layer containing no impurities is formed via the first semiconductor layer; a protective insulating layer narrower than the gate electrode is formed on the first semiconductor layer; A source (signal line) / drain wiring composed of a stack of a second semiconductor layer containing impurities and a metal layer formed on the first semiconductor layer and the insulating substrate, and including the drain wiring on the insulating substrate A liquid crystal image display device comprising: a pixel electrode; and a low-resistance metal layer and an organic insulating layer formed on at least the source / drain wiring in the image display unit. 14. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line (made of a heat-resistant metal layer on the insulating substrate and also serving as a gate electrode of an insulated gate transistor) And a storage capacitor line), a low-resistance metal layer and an organic insulating layer are formed on the scanning line (and the storage capacitor line) except for a channel formation region, and one or more gate insulating layers are formed on the gate electrode. Through the first semiconductor layer containing no impurity and the second semiconductor including a pair of impurities which are in contact with the first semiconductor layer and partially overlap the gate electrode to become a source / drain. A conductive layer, a protective insulating layer formed narrower than the gate electrode on the first semiconductor layer, and a source (signal line) formed of a metal layer on the second semiconductor layer and the insulating substrate. A) forming a drain wiring, forming a picture element electrode including the drain wiring on an insulating substrate, and forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring in the image display unit; A liquid crystal image display device. 15. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter opposed to the insulating substrate, a liquid crystal display device comprising: a transparent conductive layer and a heat-resistant metal layer laminated on the insulating substrate; A scanning line (and a storage capacitor line) also serving as a gate electrode and a transparent conductive picture element electrode in which the heat-resistant metal layer is partially laminated are formed, and a scanning line (and a storage capacitor line) excluding a channel forming region. A low-resistance metal layer and an organic insulating layer are formed thereon;
A first semiconductor layer that is wider than the gate electrode and contains no impurities is formed via the gate insulating layer of at least one layer, and a protective insulating layer that is narrower than the gate electrode is formed on the first semiconductor layer; And a second semiconductor layer containing a pair of impurities serving as a source and a drain is formed on the protective insulating layer and the first semiconductor layer on the protective insulating layer and the first semiconductor layer, and on the second semiconductor layer and the insulating substrate. A drain wiring is formed including the laminated portion of the source wiring (signal line) made of a metal layer and the heat-resistant metal layer of the transparent conductive picture element electrode, at least on the source wiring (signal line) in the image display section. A liquid crystal image display device, further comprising a low resistance metal layer and an organic insulating layer formed thereon. 16. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter opposed to the insulating substrate, a liquid crystal display device comprising: a transparent conductive layer and a heat-resistant metal layer laminated on the insulating substrate; A scanning line (and a storage capacitor line) also serving as a gate electrode and a transparent conductive picture element electrode are formed, and a low-resistance metal layer, an organic insulating layer, and the like are formed on the scanning line (and the storage capacitor line) except for a channel formation region. And at least 2 including a plasma protection layer on the gate electrode
A first semiconductor layer that is wider than the gate electrode and does not contain impurities is formed via at least one gate insulating layer;
A protective insulating layer formed narrower than the gate electrode over the semiconductor layer, and a second layer including a pair of impurities serving as a source / drain on the protective insulating layer and the first semiconductor layer so as to partially overlap with the gate electrode; A source line (signal line) made of a metal layer and a drain line including a part of the picture element electrode are formed on the second semiconductor layer and the insulating substrate; A liquid crystal image display device, wherein a low resistance metal layer and an organic insulating layer are formed on the source wiring (signal line) in a display unit. 17. An insulating substrate in which unit picture elements each having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between a transparent insulating substrate or a color filter opposed to the insulating substrate, a liquid crystal display device comprising: a transparent conductive layer and a heat-resistant metal layer on the insulating substrate; A scanning line (and a storage capacitor line) also serving as a gate electrode and a transparent conductive picture element electrode are formed, and a low-resistance metal layer, an organic insulating layer, and the like are formed on the scanning line (and the storage capacitor line) except for a channel formation region. And at least 2 including a plasma protection layer on the gate electrode
Forming a first semiconductor layer containing no impurity through a gate insulating layer of at least one layer and a second semiconductor layer containing a pair of impurities serving as a source and a drain in contact with the first semiconductor layer; A protective insulating layer formed narrower than the gate electrode on the first semiconductor layer; a source line (signal line) made of a metal layer and one of the picture element electrodes on the second semiconductor layer and the insulating substrate; A liquid crystal image display device comprising: a drain wiring including a portion; a low resistance metal layer and an organic insulating layer formed at least on the source wiring (signal line) in the image display section. 18. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate; A scanning line which is also formed by laminating a first metal layer having an organic insulating layer on the surface thereof and a low-resistance metal layer via a gate insulating layer and also serves as a gate electrode is formed, and impurities are implanted except under the gate electrode. A semiconductor layer formed as a source / drain; an interlayer insulating layer having an opening formed on the source / drain; and a second metal layer including the opening on the interlayer insulating layer. A picture element electrode is formed including a source (signal line) / drain wiring and the drain wiring, and a low-resistance metal is formed on at least the source (signal line) wiring in the image display portion and the drain wiring excluding the picture element electrode. A semiconductor device for a display device, comprising a layer and an organic insulating layer. 19. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate; A scanning line, which also comprises a transparent conductive layer having an organic insulating layer on its surface and a low-resistance metal layer, and also serves as a gate electrode, is formed on the main surface of the insulating substrate. A pixel electrode made of a transparent conductive layer is formed through the semiconductor layer, and a semiconductor layer into which impurities are implanted except for a portion under the gate electrode is used as a source / drain, and on the source / drain and on the pixel electrode An interlayer insulating layer having an opening is formed on the interlayer insulating layer. The second metal layer is formed on the interlayer insulating layer, including the opening on the source, the opening on the signal line (source wiring) and the drain, and one of the pixel electrodes. A semiconductor device for a display device, wherein a drain wiring including a portion is formed, and a low-resistance metal layer and an organic insulating layer are formed at least on the source wiring in the image display portion. 20. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate; A scanning line which is also formed by laminating a first metal layer having an organic insulating layer on the surface thereof and a low-resistance metal layer via a gate insulating layer and also serves as a gate electrode is formed, and impurities are implanted except under the gate electrode. A semiconductor layer formed as a source / drain, an interlayer insulating layer having an opening on the source / drain is formed, and a transparent conductive layer including the opening is formed on the interlayer insulating layer. And a drain line serving also as a pixel electrode, and a low-resistance metal layer and an organic insulating layer are formed at least on the source line in the image display unit. apparatus. 21. The liquid crystal image display device according to claim 4, wherein the low resistance metal layer is made of gold, silver or copper. 22. A step of forming a scan line made of a heat-resistant metal layer on one main surface of an insulating substrate and also serving as a gate electrode of an insulated gate transistor, and forming at least one gate insulating layer and a first impurity-free layer. Sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, and forming the second and first amorphous silicon layers and the gate insulating layer except for a channel formation region. Selectively removing and exposing the insulating substrate; forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit; Forming a source (signal line) / drain wiring on an insulating substrate including a second amorphous silicon layer so as to partially overlap with the gate electrode after depositing the metal layer of at least one layer; To form a pixel electrode including drain wiring And irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask.
Anodizing the second amorphous silicon layer between the drain wiring and the source / drain wiring and a part of the first amorphous silicon layer. 23. A step of forming a scanning line and a connection layer, which are made of a heat-resistant metal layer capable of being anodized and serve also as a gate electrode of an insulated gate transistor, on one main surface of an insulating substrate;
A step of sequentially depositing at least a gate insulating layer, a first amorphous silicon layer containing no impurity, and a second amorphous silicon layer containing an impurity; (1) selectively removing the amorphous silicon layer and the gate insulating layer to expose the insulating substrate; and forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit. Forming one or more anodically oxidizable metal layers, and then forming a source wiring (signal line) including a second amorphous silicon layer on the insulating substrate so as to partially overlap the gate electrode. Forming a drain line including a line) and a part of the connection layer; forming a pixel electrode including a part of the connection layer on an insulating substrate; and selectively patterning the pixel electrode. Pixel electrodes using the photosensitive resin pattern used for formation as a mask Anodizing the second amorphous silicon layer and a part of the first amorphous silicon layer between the source / drain wiring and the source / drain wiring while irradiating light while protecting the image. Method for manufacturing semiconductor device for device. 24. A step of forming a scan line made of a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor; and forming at least one gate insulating layer and a first impurity-free layer. Sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, and forming the second and first amorphous silicon layers and the gate insulating layer except for a channel formation region. Selectively exposing the insulating substrate, leaving a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit; Forming an electrode and, after depositing at least one metal layer capable of being anodized, including a second amorphous silicon layer on the insulating substrate so as to partially overlap the gate electrode; ) And the drain wiring including a part of the pixel electrode Forming and a second step between the source / drain wiring and the source / drain wiring while irradiating light.
Anodizing the amorphous silicon layer and a part of the first amorphous silicon layer. 25. A step of forming a scan line made of a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor; and forming at least one gate insulating layer and a first impurity-free layer. Sequentially depositing an amorphous silicon layer and a second amorphous silicon layer containing impurities, and depositing one or more metal layers capable of being anodized so as to partially overlap the gate electrode. Forming a source (signal line) / drain wiring on the second amorphous silicon layer; and forming a second and first amorphous layers except for a channel formation region and below the source (signal line) / drain wiring. Selectively removing the silicon layer and the gate insulating layer to expose the insulating substrate, and forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and the gate electrodes in the image display unit Process, including the drain wiring on the insulating substrate Forming a pixel electrode by irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for selective pattern formation of the pixel electrode as a mask. Anodizing a second amorphous silicon layer between wirings and a part of the first amorphous silicon layer. 26. A step of forming a scan line and a pseudo picture element electrode which are formed by laminating a transparent conductive layer and a heat-resistant metal layer on one main surface on an insulating substrate and also serve as a gate electrode of an insulated gate transistor; A step of sequentially depositing a plasma protective layer, a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities; Exposing the insulating substrate by selectively removing the first amorphous silicon layer, the gate insulating layer, and the plasma protection layer; and providing a low resistance on at least the exposed scanning lines and the gate electrodes in the image display unit. A step of forming a metal layer and an organic insulating layer; and, after depositing at least one metal layer capable of being anodized, including a second amorphous silicon layer on the insulating substrate so as to partially overlap the gate. Source wiring (signal line) and part of pseudo picture element electrode Forming a drain wiring including: a step of removing the heat-resistant metal layer on the pseudo-picture element electrode; and irradiating light with the source / drain wiring and the source / drain wiring.
Anodizing a second amorphous silicon layer between drain wirings and a part of the first amorphous silicon layer. 27. A step of forming a scan line and a pseudo picture element electrode which are formed by laminating a transparent conductive layer and a heat-resistant metal layer on one principal surface on an insulating substrate and also serve as a gate electrode of an insulated gate transistor; A step of sequentially depositing a plasma protective layer, a gate insulating layer, a first amorphous silicon layer containing no impurities, and a second amorphous silicon layer containing impurities; A step of selectively removing the first amorphous silicon layer, the gate insulating layer, and the plasma protection layer to expose the insulating substrate; and a step of removing the heat-resistant metal layer on the pseudo-pixel electrode to expose the pixel electrode. Forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and the gate electrodes in the image display unit;
After depositing at least one metal layer, a source wiring (signal line) including a second amorphous silicon layer and a drain wiring including a part of a pixel electrode are formed on the insulating substrate so as to partially overlap the gate. Forming a second amorphous silicon layer and a portion of the first amorphous silicon layer between the source / drain wiring and the source / drain wiring while irradiating the light with light. A method for manufacturing a semiconductor device for an image display device, comprising: 28. A step of forming a scan line made of a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor; and forming at least one gate insulating layer and a first impurity-free layer. Depositing a lift-off layer after sequentially depositing an amorphous silicon layer and a protective insulating layer, and selectively removing the lift-off layer and the protective insulating layer narrower than the gate electrode on the gate electrode. Exposing the first amorphous silicon layer, depositing a second amorphous silicon layer containing impurities and a second metal layer, and removing the lift-off layer and forming a second layer on the lift-off layer. Semiconductor layer and second
Selectively removing the metal layer of (a) and (b), forming a source (signal line) / drain wiring composed of a stack of a second semiconductor layer and a second metal layer on the insulating substrate, and
Except between drain wiring and below source / drain wiring
Exposing the insulating substrate by selectively removing the amorphous silicon layer and the gate insulating layer, and a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit. Forming a pixel electrode including a drain wiring on an insulating substrate, at least in the image display portion using the photosensitive resin pattern used for selective pattern formation of the pixel electrode as a mask Forming a low-resistance metal layer and an organic insulating layer on the source / drain wiring excluding the picture element electrode. 29. A step of forming a scan line made of a heat-resistant metal layer on one main surface of an insulating substrate and also serving as a gate electrode of an insulated gate transistor; and forming at least one gate insulating layer and a first impurity-free layer. Applying a lift-off layer after sequentially applying an amorphous silicon layer and a protective insulating layer, and selectively forming a photosensitive resin pattern narrower than a gate electrode on the lift-off layer; A step of exposing the insulating substrate by sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, and the gate insulating layer using the photosensitive resin pattern as a mask, and reducing the photosensitive resin pattern to form a lift-off layer. Partially exposing the first semiconductor layer by partially etching the lift-off layer and the protective insulating layer sequentially using the photosensitive resin pattern having the reduced film thickness as a mask; Forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and the gate electrodes in the image display unit; and forming a second amorphous silicon layer and a second metal layer containing impurities. And selectively removing the second semiconductor layer and the second metal layer on the lift-off layer together with the removal of the lift-off layer; and removing the second semiconductor layer and the second metal layer on the insulating substrate. Forming a source (signal line) / drain wiring composed of a laminate with a metal layer, forming a picture element electrode including a drain wiring on an insulating substrate, and selectively forming a pattern of the picture element electrode Forming a low-resistance metal layer and an organic insulating layer on at least the source / drain wiring except for the picture element electrodes in the image display unit using the photosensitive resin pattern used as a mask as a mask. Manufacturing method. 30. A step of forming a scanning line made of a heat-resistant metal layer on one main surface on an insulating substrate and also serving as a gate electrode of an insulated gate transistor; and forming at least one gate insulating layer and a first impurity-free layer. Applying a lift-off layer after sequentially applying an amorphous silicon layer and a protective insulating layer, and selectively forming a photosensitive resin pattern narrower than a gate electrode on the lift-off layer; A step of exposing the insulating substrate by sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, and the gate insulating layer using the photosensitive resin pattern as a mask, and reducing the photosensitive resin pattern to form a lift-off layer. Partially exposing the first semiconductor layer by sequentially etching the lift-off layer and the protective insulating layer using the photosensitive resin pattern having a reduced film thickness as a mask; Implanting impurities into the first semiconductor layer using the shift-off layer as a mask to transform the first semiconductor layer into a second semiconductor layer; and forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit. Forming a second metal layer, applying a second metal layer, selectively removing the second metal layer on the lift-off layer together with removing the lift-off layer, and forming a second metal layer on the insulating substrate. Forming a source (signal line) / drain wiring composed of a metal layer of the above, forming a pixel electrode including a drain wiring on an insulating substrate, and forming a selective pattern of the pixel electrode. Forming a low-resistance metal layer and an organic insulating layer on source / drain wiring excluding at least picture element electrodes in an image display portion using the photosensitive resin pattern as a mask. . 31. A step of forming a scan line and a pseudo picture element electrode which are formed by laminating a transparent conductive layer and a heat-resistant metal layer on one main surface on an insulating substrate and also serve as a gate electrode of an insulated gate transistor; Sequentially depositing two or more gate insulating layers including a plasma protective layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer; and forming the protective insulating layer on the gate electrode more than the gate electrode. A step of exposing the first amorphous silicon layer while leaving it thin, a step of depositing a second amorphous silicon layer containing impurities on the entire surface, and a step of exposing the second and first layers except for the channel formation region. Selectively removing the amorphous silicon layer and the plasma protection layer and the gate insulating layer to expose the scanning line; and forming a low-resistance metal layer on at least the exposed scanning line and the gate electrode in the image display unit. Forming an organic insulating layer and a second step. After the metal layer is deposited, the signal line (source wiring) and the pseudo pixel electrode made of the second metal layer are formed on the insulating substrate including the second amorphous silicon layer so as to partially overlap with the protective insulating layer. Forming a drain wiring including a portion, a step of removing a second amorphous silicon layer between source and drain wirings, and removing a heat-resistant metal layer on a pseudo pixel electrode to form a pixel electrode. A method for manufacturing a semiconductor device for an image display device, comprising: a step of exposing; and a step of forming a low-resistance metal layer and an organic insulating layer at least on a source wiring in an image display unit. 32. A step of forming a scan line and a pseudo picture element electrode which are formed by laminating a transparent conductive layer and a heat-resistant metal layer on one main surface of an insulating substrate and also serve as a gate electrode of an insulated gate transistor; Sequentially depositing two or more gate insulating layers including a plasma protective layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer; and forming the protective insulating layer on the gate electrode more than the gate electrode. A step of exposing the first amorphous silicon layer while leaving it thin, a step of depositing a second amorphous silicon layer containing impurities on the entire surface, and a step of exposing the second and first layers except for the channel formation region. Selectively removing the amorphous silicon layer and the plasma protection layer and the gate insulating layer to expose the scanning lines and the pseudo pixel electrodes; and removing the heat-resistant metal layer on the pseudo pixel electrodes to remove the pixels. A step of exposing the electrodes, and at least exposing the electrodes in the image display section. Forming a low-resistance metal layer and an organic insulating layer on the scanning line and the gate electrode, and applying a second insulating layer on the insulating substrate including the second amorphous silicon layer after depositing the second metal layer. Forming a signal line (source wiring) made of a second metal layer and a drain wiring including a part of a pixel electrode so as to partially overlap the layer, and forming a second amorphous layer between the source and drain wirings A method for manufacturing a semiconductor device for an image display device, comprising: a step of removing a porous silicon layer; and a step of forming a low-resistance metal layer and an organic insulating layer at least on a source wiring in an image display unit. 33. A step of forming a scan line and a pseudo picture element electrode which are formed by laminating a transparent conductive layer and a heat-resistant metal layer on one main surface of an insulating substrate and also serve as a gate electrode of an insulated gate transistor; Depositing a lift-off layer after sequentially depositing at least two gate insulating layers including a plasma protective layer, a first amorphous silicon layer containing no impurity, and a protective insulating layer; and forming a gate on the lift-off layer. Selectively forming a photosensitive resin pattern narrower than the electrode; and sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the plasma protective layer using the photosensitive resin pattern as a mask. Exposing the insulating substrate, removing the heat-resistant metal layer on the pseudo-pixel electrode to expose the pixel electrode, and reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer. Engineering A step of sequentially etching the lift-off layer and the protective insulating layer using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer; Implanting impurities into the semiconductor layer to transform into a second semiconductor layer, and forming a low-resistance metal layer and an organic insulating layer on at least the exposed scanning lines and gate electrodes in the image display unit; A step of applying a second metal layer, a step of selectively removing the second metal layer on the lift-off layer together with the removal of the lift-off layer, and a step of forming a signal line of the second metal layer on an insulating substrate ( An image display device comprising: a step of forming a drain wiring including a part of a pixel electrode and a pixel electrode; and a step of forming a low-resistance metal layer and an organic insulating layer at least on a source wiring in an image display unit. Of semiconductor devices for manufacturing Law. 34. A step of depositing an amorphous silicon layer on at least one principal surface of an insulating substrate; a step of reducing hydrogen contained in the amorphous silicon layer; Forming a polycrystalline silicon layer in a polycrystalline silicon layer, forming the polycrystalline silicon layer in an island shape, and depositing a gate insulating layer and a first metal layer on an insulating substrate, and then forming a scanning line also serving as a gate electrode. Exposing the polycrystalline silicon layer while selectively leaving the gate insulating layer and the first metal layer corresponding to the step of forming a low-resistance metal layer and an organic insulating layer on at least scanning lines in an image display unit. Forming a source / drain by irradiating (implanting) an impurity; depositing an interlayer insulating layer having a pair of openings on the source / drain; and forming a second metal including the opening. Source (signal line) and drain wiring Forming a picture element electrode including a drain wiring on an interlayer insulating layer; and using a photosensitive resin pattern used for selective pattern formation of the picture element electrode as a mask at least a picture in an image display portion. Forming a low-resistance metal layer and an organic insulating layer on the source / drain wiring excluding the elementary electrodes. 35. A step of depositing an amorphous silicon layer on at least one main surface of an insulating substrate; a step of reducing hydrogen contained in the amorphous silicon layer; Forming a polycrystalline silicon layer in a polycrystalline silicon layer, forming the polycrystalline silicon layer in an island shape, depositing a gate insulating layer and a transparent conductive layer on an insulating substrate, and forming a scanning line and a gate electrode. Exposing the polycrystalline silicon layer by selectively leaving the gate insulating layer and the transparent conductive layer corresponding to the elementary electrodes, and forming a low-resistance metal layer and an organic insulating layer on at least scanning lines in the image display unit Process and irradiate (implant) impurities
Forming a source / drain by depositing an interlayer insulating layer having a pair of openings on the source / drain and an opening on the picture element electrode; and forming the source / drain comprising a second metal layer. Forming a signal line (source wiring) including the upper opening, a drain wiring including the opening on the drain and a part of the pixel electrode, and forming a low-resistance on at least the source wiring in the image display unit. A method for manufacturing a semiconductor device for an image display device, comprising: forming a metal layer and an organic insulating layer. 36. A step of depositing an amorphous silicon layer on at least one principal surface of an insulating substrate; a step of reducing hydrogen contained in the amorphous silicon layer; Forming a polycrystalline silicon layer in a polycrystalline silicon layer, forming the polycrystalline silicon layer in an island shape, and depositing a gate insulating layer and a first metal layer on an insulating substrate, and then forming a scanning line also serving as a gate electrode. Exposing the polycrystalline silicon layer while selectively leaving the gate insulating layer and the first metal layer corresponding to the step of forming a low-resistance metal layer and an organic insulating layer on at least scanning lines in an image display unit. Forming a source / drain by irradiating (implanting) an impurity; depositing an interlayer insulating layer having a pair of openings on the source / drain; Signal line (source wiring) and pixel electrode Forming a drain wiring, a method of manufacturing a semiconductor device for an image display apparatus and a step of forming at least a low-resistance metal layer over the source wiring and the organic insulating layer. 37. The low-resistance metal layer is formed by plating using gold, silver or copper.
37. The method for manufacturing a semiconductor device for an image display device according to any one of items 36 to 36. 38. The insulated gate transistor according to claim 1, wherein the low resistance metal layer is made of gold, silver or copper.