JP2005157016A - Liquid crystal display and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a manufacturing margin is reduced and yield is reduced when channel length is shortened in a manufacturing method in which the number of conventional manufacturing steps is reduced. <P>SOLUTION: A four mask process and a three mask process of a TN type liquid crystal display and an IPS type liquid crystal display are constructed by combination of a new technology wherein a semiconductor layer is formed first and then a scanning line forming process and a contact forming process are rationalized by introducing a halftone exposure technology, a new technology wherein a protective layer forming process is rationalized by introducing the halftone exposure technology to an anodic oxidation process of a source/drain wiring which is a well-known technology and a rationalization technology for simultaneously forming a pixel electrode and a scanning line which is a well-known technology. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device.

With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, and the like, television images and various image display devices are provided in large quantities on a commercial basis in 5 to 50 cm diagonal liquid crystal display devices. Further, color display is easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, so-called active liquid crystal panels in which switching elements are built in for each picture element have little crosstalk, fast response speed, and an image having a high contrast ratio.

 These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 300 to 1600 signal lines, but recently, a large screen is required to cope with an increase in display capacity. And high definition are progressing simultaneously.

FIG. 18 shows a state of mounting on a liquid crystal panel, and a semiconductor integrated circuit for supplying a drive signal to an electrode terminal group 5 of a scanning line formed on one transparent insulating substrate, for example, a glass substrate 2, constituting the liquid crystal panel 1. A COG (Chip-On-Glass) system in which the chip 3 is connected using a conductive adhesive, or a copper foil terminal (not shown) based on, for example, a polyimide resin thin film and plated with gold or solder. An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) system in which the TCP film 4 is fixed to the electrode terminal group 6 of the signal line by pressing with an appropriate adhesive containing a conductive medium. The Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.

Wiring paths 7 and 8 connect the pixels in the image display unit located almost at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 of the scanning lines and signal lines, and are not necessarily the same as the electrode terminal groups 5 and 6. It is not necessary to be made of a conductive material. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

  FIG. 19 shows an equivalent circuit diagram of an active liquid crystal display device in which an insulated gate transistor 10 is arranged for each picture element as a switching element, 11 (7 in FIG. 18) is a scanning line, and 12 (8 in FIG. 18) is a signal. A line 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn with solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is the main electrode facing the other glass substrate 9. It is formed on the surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

  FIG. 20 is a cross-sectional view of the main part of the image display unit of the liquid crystal display device, and the two glass substrates 2 and 9 constituting the liquid crystal panel 1 are columnar spacers formed on resinous fibers, beads, or color filters 9. Are formed at a predetermined distance of about several μm by a spacer material (not shown) such as a sealing material made of an organic resin and a sealing material (both shown in FIG. The liquid crystal 17 is filled in this closed space.

  In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is also called a color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use a TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.

The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. It is a technology that is fixed as a so-called black matrix (Black Matrix abbreviation is BM).

Here, a structure and a manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently widely used, and one of them called etch stop type is introduced as a conventional example. With the introduction of the dry etch technology, the number of photomasks that were originally required to be about eight is reduced to five at the present time, greatly contributing to the reduction of process costs. FIG. 21 is a plan view of unit picture elements of an active substrate (semiconductor device for display device) that constitutes a conventional liquid crystal panel, on the lines AA ′, BB ′, and CC ′ of FIG. FIG. 22 shows a cross-sectional view of this, and the manufacturing process will be briefly described below.

First, as shown in FIGS. 21A and 22A, a glass substrate 2 having a thickness of about 0.5 to 1.1 mm as an insulating substrate having high heat resistance, chemical resistance, and transparency, for example, Corning. A first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of a product name 1737 manufactured by the company using a vacuum film-forming apparatus such as SPT (sputtering), and fine processing technology is used. The scanning line 11 that also serves as the gate electrode 11A and the storage capacitor line 16 are selectively formed. The scanning line material is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and conductivity, but generally a metal or alloy having high heat resistance such as Cr, Ta, MoW alloy is used. Is done.

  It is reasonable to use AL (aluminum) as the scanning line material to reduce the resistance value of the scanning line in response to the increase in the screen size and resolution of the liquid crystal panel. Since it is low, it is a common technique to stack with Cr, Ta, Mo or their silicides as mentioned above, or to add an oxide layer (Al 2 O 3) by anodic oxidation on the surface of AL. That is, the scanning line 11 is composed of one or more metal layers.

Next, a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma sieve fluid) apparatus, and a first serving as a channel of an insulated gate transistor containing almost no impurities. The amorphous silicon (a-Si) layer 31, the second SiNx layer 32 serving as an insulating layer for protecting the channel, and three kinds of thin film layers are, for example, about 0.3 to 0.05 μm. Sequentially deposited by film thickness, the second SiNx layer on the gate electrode 11A is selectively left narrower than the gate electrode 11A by microfabrication technology as shown in FIGS. 21 (b) and 22 (b). Thus, the first amorphous silicon layer 31 is exposed as the channel protective layer 32D.

Subsequently, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface using a PCVD apparatus in a thickness of, for example, about 0.05 μm, and then FIG. 21C and FIG. ) Using a vacuum film-forming apparatus such as SPT, a heat-resistant metal thin film layer 34 of Ti, Cr, Mo or the like as a heat-resistant metal layer having a film thickness of about 0.1 μm and a film thickness of 0 as a low-resistance wiring layer Then, an AL thin film layer 35 having a thickness of about 3 μm and a Ti thin film layer 36, for example, are sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. , 35A and 36A, the drain electrode 21 of the insulated gate transistor and the signal line 12 also serving as the source electrode are selectively formed. In this selective pattern formation, the Ti thin film layer 36, the AL thin film layer 35, and the Ti thin film layer 34 are sequentially etched using the photosensitive resin pattern used for forming the source / drain wiring as a mask, and then the source / drain electrodes 12, The second amorphous silicon layer 33 between the two regions 21 is removed to expose the second SiNx layer 32D, and the first amorphous silicon layer 31 is also removed in other regions to form the gate insulating layer 30. Made by exposing. As described above, since the second SiNx layer 32D serving as a channel protective layer exists and the etching of the second amorphous silicon layer 33 is automatically terminated, this manufacturing method is called an etch stop.

  The source / drain electrodes 12 and 21 are formed to partially overlap (several μm) in plan with the etch stop layer 32D so that the insulated gate transistor does not have an offset structure. Since this overlap is electrically acting as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the photomask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about 2 μm.

Further, after removing the photosensitive resin pattern, a SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus in the same manner as the gate insulating layer. As the insulating layer 37, as shown in FIGS. 21D and 22D, the passivation insulating layer 37 is selectively removed by a microfabrication technique, an opening 62 is formed on the drain electrode 21, and an image display unit. In the outer region, an opening 63 is formed on the position where the electrode terminal 5 of the scanning line 11 is formed, and an opening 64 is formed on the position where the electrode terminal 6 of the signal line 12 is formed, so that the drain electrode 21 and the scanning line are formed. 11 and a part of the signal line 12 are exposed. An opening 65 is formed on the storage capacitor line 16 (electrode pattern in which the storage capacitor lines are bundled in parallel) to expose a part of the storage capacitor line 16.

Finally, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIGS. 21 (e) and 22 (e), the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening 62 by a microfabrication technique, and the active substrate 2 is completed. A part of the exposed scanning line 11 in the opening 63 may be used as the electrode terminal 5 and a part of the exposed signal line 12 in the opening 64 may be used as the electrode terminal 6. As shown in FIG. The electrode terminals 5A and 6A made of ITO may be selectively formed on the passivation insulating layer 37 including 63 and 64, but normally the transparent conductive short-circuit line 40 connecting the electrode terminals 5A and 6A is also provided. Formed simultaneously. The reason is that although not shown, the resistance between the electrode terminals 5A and 6A and the short-circuit line 40 can be increased in resistance by increasing the resistance by forming an elongated stripe. Similarly, an electrode terminal to the storage capacitor line 16 is formed including the opening 65.

When the wiring resistance of the signal line 12 does not become a problem, the low resistance wiring layer 35 made of AL is not necessarily required. In this case, the source / drain wiring 12 can be selected by selecting a heat-resistant metal material such as Cr, Ta, and Mo. , 21 can be simplified by forming a single layer. As described above, it is important that the source / drain wiring is a refractory metal layer to ensure electrical connection with the second amorphous silicon layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example. In FIG. 21C, the storage capacitor 15 is formed by a region 50 (shaded portion to the right) where the storage capacitor line 16 and the drain electrode 21 overlap with each other through the gate insulating layer 30. Detailed description is omitted.
JP-A-7-74368

Although the detailed process of the five-mask process described above is omitted, it was obtained as a result of streamlining the semiconductor layer islanding process and reducing the contact formation process once. The photomask, which has been reduced to 5 at the present time due to the introduction of dry etching technology, has greatly contributed to the reduction of process costs. In order to reduce the production cost of the liquid crystal display device, it is a well-known development target that it is effective to reduce the process cost in the manufacturing process of the active substrate and the member cost in the panel assembly process and the module mounting process. In order to lower the process cost, there are a process reduction that shortens the process and a cheap process development or replacement with a process. Here, the process is reduced to a four-mask process where an active substrate can be obtained with four photomasks. An example will be described. The four-mask process reduces the number of photo-etching steps by introducing halftone exposure technology. FIG. 23 is a plan view of unit picture elements of an active substrate corresponding to the four-mask process. FIG. FIG. 24 is a cross-sectional view taken along the lines AA ′, BB ′, and CC ′ of FIG. As already described, two types of insulated gate transistors are currently widely used. Here, a channel-etched insulated gate transistor is used.

First, a first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, as in the five-mask process. As shown in FIGS. 23A and 24A, the scanning line 11 and the storage capacitor line 16 that also serve as the gate electrode 11A are selectively formed by a fine processing technique.

Next, a SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that contains almost no impurities and becomes a channel of an insulated gate transistor, and contains impurities. The second amorphous silicon layer 33 that becomes the source / drain of the insulated gate transistor and the three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm. Subsequently, using a vacuum film forming apparatus such as SPT, for example, a Ti thin film layer 34 as a heat resistant metal layer having a thickness of about 0.1 μm, and an AL thin film layer 35 as a low resistance wiring layer having a thickness of about 0.3 μm, For example, a Ti thin film layer 36, that is, a source / drain wiring material is sequentially deposited as an intermediate conductive layer of about 0.1 μm, and the drain electrode 21 of the insulated gate transistor and the signal line 12 also serving as the source electrode are selected by microfabrication technology. In this selective pattern formation, the film of the channel formation region 80B (shaded portion) between the source and drain is formed by a halftone exposure technique as shown in FIGS. 23 (b) and 24 (b). For example, photosensitive resin patterns 80A and 80B having a thickness of 1.5 μm and thinner than the film thickness of 3 μm of the source / drain wiring formation regions 80A (12) and 80A (21) are formed. The point of formation is a major feature.

Since the photosensitive resin patterns 80A and 80B usually use a positive photosensitive resin for the production of a substrate for a liquid crystal display device, the source / drain wiring formation region 80A is black, that is, a Cr thin film is formed. The channel region 80B is gray, for example, a line and space Cr pattern having a width of about 0.5 to 1 μm is formed, and the other region may be white, that is, a photomask from which the Cr thin film is removed may be used. . In the gray area, the line-and-space is not resolved because the resolving power of the exposure machine is insufficient, and it is possible to transmit about half of the photomask irradiation light from the lamp light source. According to the remaining film characteristics, photosensitive resin patterns 80A and 80B having a cross-sectional shape as shown in FIG. 24B can be obtained.

With the photosensitive resin patterns 80A and 80B as masks, as shown in FIG. 24B, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first non-crystalline layer 33 are used. After sequentially etching the crystalline silicon layer 31 to expose the gate insulating layer 30, as shown in FIGS. 23C and 24C, the photosensitive resin pattern 80A, When the film thickness of 80B is reduced from 3 μm to 1.5 μm or more, for example, the photosensitive resin pattern 80B disappears and the channel region is exposed, and 80C (12) and 80C (21) are formed only on the source / drain wiring formation region. Can leave. Therefore, the Ti thin film layer, the AL thin film layer, the Ti thin film layer, and the second amorphous film between the source and drain wirings (channel formation region) are again formed using the photosensitive resin patterns 80C (12) and 80C (21) whose thickness has been reduced. The porous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. Since the source / drain wiring is formed by etching the metal layer and etching the first amorphous silicon layer 31A leaving about 0.05 to 0.1 μm, an insulated gate type obtained by such a manufacturing method is used. The transistor is called a channel etch. In the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension, and the reason will be described later.

Further, after the photosensitive resin patterns 80C (12) and 80C (21) having been reduced in thickness are removed, the glass substrate 2 is formed as shown in FIGS. 23 (d) and 24 (d) as in the five-mask process. A SiNx layer having a thickness of about 0.3 μm is deposited as a transparent insulating layer on the entire surface to form a passivation insulating layer 37, and in regions where the electrode terminals of the drain electrode 21, the scanning line 11, and the signal line 12 are formed, respectively. Openings 62, 63, 64 are formed, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed to expose a part of the scanning line, and the passivation insulating layer in the openings 62, 64 is exposed. 37 is removed to expose part of the drain electrode 21 and part of the signal line.

Finally, for example, ITO or IZO was deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, and the results are shown in FIGS. 23 (e) and 24 (e). As described above, the transparent conductive picture element electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by the fine processing technique to complete the active substrate 2. In this case, transparent conductive electrode terminals 5A and 6A made of ITO are selectively formed on the passivation insulating layer 37 including the openings 63 and 64.

  In this way, in the five-mask process and the four-mask process, the contact formation process to the drain electrode 21 and the scanning line 11 is performed at the same time. Therefore, the thickness of the insulating layer in the openings 62 and 63 corresponding to them is determined. The types are different. The passivation insulating layer 37 has a lower film forming temperature and inferior film quality compared to the gate insulating layer 30, and the etching rate with a hydrofluoric acid-based etching solution is several thousand liters / minute and several hundreds liters / minute, which is one digit. In contrast, the cross-sectional shape of the opening 62 on the drain electrode 21 employs dry etching using a fluorine-based gas for the reason that too much etching occurs at the top and the hole diameter cannot be controlled.

Even if dry etching is employed, since the opening 62 on the drain electrode 21 is only the passivation insulating layer 37, over-etching is unavoidable as compared with the opening 63 on the scanning line 11. Depending on the material, The intermediate conductive layer 36A may be reduced in thickness by the etching gas. In removing the photosensitive resin pattern after the etching, the surface of the photosensitive resin pattern is first scraped by about 0.1 to 0.3 μm by oxygen plasma ashing in order to remove the polymer on the fluorinated surface. In general, chemical treatment using an organic stripping solution such as Tokyo Ohka stripping solution 106 is performed, but the intermediate conductive layer 36A is reduced in thickness and the underlying aluminum layer 35A is exposed. If so, AL2O3, which is an insulator, is formed on the surface of the aluminum layer 35A by the oxygen plasma ashing treatment, and ohmic contact with the pixel electrode 22 cannot be obtained. Thus, the thickness of the intermediate conductive layer 36A is set to be as thick as, for example, 0.2 μm so that the film can be reduced. Alternatively, when the openings 62 to 65 are formed, it is possible to avoid the formation of the pixel electrode 22 after removing the aluminum layer 35A and exposing the thin film layer 34A which is the underlying heat-resistant metal layer. There is also an advantage that the intermediate conductive layer 36A is unnecessary from the beginning.

However, if the in-plane uniformity of the film thickness of these thin films is not good in the former measure, this approach does not necessarily work effectively, and the same is true when the in-plane uniformity of the etching speed is not good. is there. The latter measure eliminates the need for the intermediate conductive layer 36A, but the number of steps for removing the aluminum layer 35A increases, and if the cross section control of the opening 62 is insufficient, the pixel electrode 22 may be disconnected. .

In addition, the channel forming process applied in the four-mask process selectively removes the source / drain wiring material between the source / drain wirings 12 and 21 and the semiconductor layer containing impurities, so that the insulated gate transistor is turned on. This is a step of determining the length of the channel (4 to 6 μm in the current mass-produced product) that greatly affects the characteristics. This variation in the channel length greatly changes the ON current value of the insulated gate transistor, and therefore, strict manufacturing control is usually required. Strength and pattern accuracy of photomask (especially line & space dimensions), photosensitive resin coating thickness, photosensitive resin phenomenon treatment, and the amount of photosensitive resin film reduction in the etching process, etc. In combination with the in-plane uniformity of these quantities, it is not always possible to produce products stably at a high yield, and even more stringent manufacturing management is required than conventional manufacturing management, and it can be said that it is at a highly completed level. There is no current situation. In particular, when the channel length is 6 μm or less, the influence of the pattern size generated with a decrease in the film thickness of the resist pattern is large, and this tendency becomes remarkable.

The present invention has been made in view of the current situation, and not only avoids the troubles in forming contacts common to the conventional 5-mask process and 4-mask process, but also adopts a halftone exposure technique with a large manufacturing margin. Thus, the manufacturing process can be reduced. In addition, it is clear that there is a need to pursue further reductions in the number of manufacturing processes in order to reduce the price of liquid crystal panels and respond to the increase in demand. The value of the present invention is further enhanced by providing a technique for simplifying the process or reducing the cost.

In the present invention, first, a semiconductor layer is formed, and then halftone exposure technology is applied to a scanning line forming process in which pattern accuracy control is easy and a contact forming process for electrical connection to the scanning line. This reduces the number of manufacturing processes. Then, in order to effectively passivate only the source / drain wiring, it is combined with an anodic oxidation technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in Japanese Patent Laid-Open No. 2-216129 which is a prior art. The aim is to achieve rationalization of processes and low temperatures. Furthermore, a streamlined pixel electrode forming process disclosed in Japanese Patent Application Laid-Open No. 8-136951, which is a prior art, is adopted in conformity with the present invention. In order to further reduce the process, the halftone exposure technique is applied to the formation of the anodic oxide layer of the source / drain wiring, thereby rationalizing the electrode terminal protective layer forming process.
JP-A-2-216129 JP-A-8-136951

The liquid crystal display device according to claim 1 is connected to at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring on one main surface. A first transparent insulating substrate in which unit pixel elements each having a pixel electrode are arranged in a two-dimensional matrix; and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In a liquid crystal display device in which liquid crystal is filled in between,
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
Source (signal line) / drain wiring comprising one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and the opening. Similarly, the electrode terminal of the scanning line is formed,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the area overlapping the pixel electrode of the drain wiring and the electrode terminal area of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, the gate insulating layer is formed with the same pattern width as the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. . This is a structural feature common to the liquid crystal display device of the present invention. A transparent conductive pixel electrode is formed on a glass substrate, and a silicon oxide layer is formed on the channel between the source and drain to protect the channel and an insulating anode is formed on the surface of the signal line and drain wiring. Since a tantalum pentoxide (Ta 2 O 5) or aluminum oxide (Al 2 O 3) that is an oxide layer is formed to provide a passivation function, it is not necessary to deposit the passivation insulating layer on the entire surface of the glass substrate, and the heat resistance of the insulated gate transistor No longer becomes a problem. Thus, a TN liquid crystal display device having a transparent conductive electrode terminal is obtained.

The liquid crystal display device according to claim 2 is also provided with a scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, and transparent conductive material. Sex pixel electrode is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more anodizable metal layers including a heat-resistant metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer Also on the first transparent insulating substrate and on part of the pixel electrode, the drain wiring, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line comprising a part of the signal line Formed,
An anodic oxidation layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, a transparent conductive pixel electrode is formed on the glass substrate, and a silicon oxide layer is formed on the channel between the source and drain to protect the channel and the surface of the source / drain wiring is insulated. The tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), which is an anodized layer, is formed to provide a passivation function, and the same effect as the liquid crystal display device according to claim 1 can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

The liquid crystal display device according to claim 3 is a scanning line that is formed of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate, and has an insulating layer on its side surface. , Transparent conductive pixel electrode and signal line electrode terminal are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent insulating layer serving as the electrode terminal of the scanning line is exposed by removing the gate insulating layer and the first metal layer in the opening. ,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A passivation insulating layer having openings on the pixel electrodes and on the scanning line and signal line electrode terminals is formed on the first transparent insulating substrate.

With this configuration, a transparent conductive pixel electrode is formed at the same time as the scanning line, so it is automatically formed on the glass substrate, and a conventional passivation insulating layer is formed on the active substrate to form the channel of the insulated gate transistor. And source / drain wiring are protected. Thus, a TN liquid crystal display device having a transparent conductive electrode terminal is obtained.

5. The liquid crystal display device according to claim 4, wherein the scanning line is formed of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate, and has an insulating layer on its side surface. A transparent conductive pixel electrode having a first metal layer laminated on its periphery, and a transparent conductive signal line electrode terminal having a first metal layer laminated on its periphery,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent insulating layer serving as the electrode terminal of the scanning line is exposed by removing the gate insulating layer and the first metal layer in the opening. ,
One or more second metals including a refractory metal layer on the second semiconductor layer, on the first transparent insulating substrate, and on a part of the first metal layer around the electrode terminal of the signal line. Similarly, a drain wiring is formed on the source wiring (signal line) composed of layers, on the second semiconductor layer, on the first transparent insulating substrate, and on a part of the first metal layer around the pixel electrode. And
A passivation insulating layer having openings on the transparent conductive pixel electrodes and on the electrode terminals of the transparent conductive scanning lines and signal lines is formed on the first transparent insulating substrate. Features.

With this configuration, a transparent conductive pixel electrode is formed at the same time as the scanning line, so it is automatically formed on the glass substrate, and a conventional passivation insulating layer is formed on the active substrate to form the channel of the insulated gate transistor. And source / drain wiring are protected. A TN type liquid crystal display device having a transparent conductive electrode terminal can be obtained, but the structural difference from the liquid crystal display device according to claim 3 is very small.

The liquid crystal display device according to claim 5 is a scanning line that is formed of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate, and has an insulating layer on its side surface. A transparent conductive pixel electrode is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the gate insulating layer and the first metal layer in the opening are removed to expose the transparent conductive layer that is part of the scanning line. ,
A source wiring (signal line) made of one or more anodizable metal layers including a heat-resistant metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer Also on the first transparent insulating substrate and on part of the pixel electrode, the drain wiring, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line comprising a part of the signal line Formed,
An anodic oxidation layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate, and a silicon oxide layer is formed on the channel between the source and drain to protect the channel. 2. The liquid crystal display device according to claim 1, wherein tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), which is an insulating anodic oxide layer, is formed on the surfaces of the signal line and the drain wiring to provide a passivation function. The same effect can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

The liquid crystal display device according to claim 6, wherein at least one insulated gate transistor, a scanning line that also serves as a gate electrode of the insulated gate transistor, and a signal line that also serves as a source line are provided on one main surface; A first transparent insulating substrate in which unit picture elements each having a picture element electrode connected to a drain and a counter electrode formed at a predetermined distance from the picture element electrode are arranged in a two-dimensional matrix; In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter facing the first transparent insulating substrate,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display unit,
A passivation insulating layer having openings on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate.

With this configuration, the pixel electrode and the counter electrode are formed on a glass substrate, and a conventional passivation insulating layer is formed on the active substrate to provide a channel, source wiring (signal line) and drain wiring (picture) of the insulated gate transistor. Elementary electrode) is protected. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

The liquid crystal display device according to claim 7 is provided with a scanning line and a counter electrode, each having at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface. Formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; The electrode terminal of the scanning line, including the opening, and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display unit are formed,
An anodized layer is formed on the source / drain wiring except on the electrode terminal of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a silicon oxide layer is formed on the channel between the source and drain to protect the channel, and the surface of the signal line and drain wiring (picture element electrode) Since tantalum pentoxide (Ta 2 O 5) or aluminum oxide (Al 2 O 3), which is an insulating anodic oxide layer, is formed, and a gate insulating layer is formed on the counter electrode to provide a passivation function. The same effect as the liquid crystal display device described in (1) can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

8. The liquid crystal image display device according to claim 8, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. A liquid crystal display device according to claim 5, claim 6 and claim 7. With this configuration, an organic insulating layer can be formed on the side surface of the scanning line by electrodeposition regardless of the material and configuration of the scanning line, and the scanning line forming process and the contact forming process can be performed using halftone exposure technology. It is possible to process continuously with one photomask.

The liquid crystal image display device according to claim 9, wherein the first metal layer is made of an anodizable metal layer, and the insulating layer formed on the side surface of the scanning line is an anodized layer. A liquid crystal display device according to claim 2, claim 6, and claim 7. With this configuration, an insulating layer can be formed on the side surface of the scanning line by anodic oxidation, and the scanning line forming process and the contact forming process are successively processed with a single photomask using a halftone exposure technique. Things will be possible.

A method of manufacturing a liquid crystal display device according to claim 1, wherein the step of forming the semiconductor layer, the formation of the scanning line, and the formation of the contact are processed using the same photomask by a halftone exposure technique. And a step of forming a source / drain wiring, and a step of anodizing the source / drain wiring simultaneously with the formation of the transparent conductive pixel electrode.

With this configuration, the scanning line forming process and the contact forming process necessary for electrical connection to the scanning line can be processed using a single photomask, and the number of photolithography steps can be reduced. Moreover, the contact is formed in a self-aligned manner with the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. This is a manufacturing characteristic common to the liquid crystal display device of the present invention. In addition, since the silicon oxide layer is formed on the channel between the source and drain to protect the channel by anodizing the source / drain wiring when the pixel electrode is formed, the manufacturing process does not require the formation of a passivation insulating layer. As a result of the reduction, a TN liquid crystal display device can be manufactured using four photomasks.

11. A method of manufacturing a liquid crystal display device according to claim 2, wherein the step of forming the semiconductor layer, the formation of the scanning line, and the formation of the contact are processed using the same photomask by a halftone exposure technique. A step of forming a transparent conductive pixel electrode, a step of forming source / drain wiring using a halftone exposure technique, and anodizing the source / drain wiring and the channel of the insulated gate transistor It is characterized by that.

With this configuration, it is possible to simultaneously reduce the number of photo-etching processes in which the scanning line forming process and the contact forming process are performed using a single photomask. In addition, since the silicon oxide layer is formed on the channel between the source and drain to protect the channel by anodizing the source / drain wiring when forming the source / drain wiring, the manufacturing process eliminates the need for forming a passivation insulating layer. As a result, a TN liquid crystal display device can be manufactured using four photomasks.

Claim 12 is a method of manufacturing a liquid crystal display device according to claim 3, wherein a step of forming a semiconductor layer, formation of a scanning line composed of a laminate of a transparent conductive layer and a first metal layer, and formation of a contact are formed. Process using the same photomask by halftone exposure technology, removing the first metal layer in the contact to form a transparent conductive layer when forming the contact, and forming source / drain wiring And a step of forming a passivation insulating layer.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. A reduction in the number of photolithography steps can be realized at the same time, and a TN type liquid crystal display device can be manufactured using four photomasks.

Claim 13 is a method of manufacturing a liquid crystal display device according to claim 4, wherein the step of forming a semiconductor layer, the formation of a scanning line composed of a laminate of a transparent conductive layer and a first metal layer, and contact formation A process of forming the half-tone exposure technique using the same photomask, a process of forming source / drain wirings, a passivation insulating layer, and a first metal layer when forming an opening in the passivation insulating layer It has the process of removing.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. A reduction in the number of photolithography steps can be realized at the same time, and a TN type liquid crystal display device can be manufactured using four photomasks.

14. A method of manufacturing a liquid crystal display device according to claim 5, wherein a step of forming a semiconductor layer, formation of a scanning line composed of a laminate of a transparent conductive layer and a first metal layer, and formation of a contact are formed. A half-tone exposure technique using the same photomask, a step of removing the first metal layer in the contact to form a transparent conductive layer during contact formation, and a source using the half-tone exposure technique A step of forming the drain wiring and anodizing the source / drain wiring and the channel of the insulated gate transistor is characterized.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. In addition, since the silicon oxide layer is formed on the channel between the source and drain to protect the channel by anodizing the source / drain wiring when forming the source / drain wiring, the manufacturing process eliminates the need for forming a passivation insulating layer. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

15. A method of manufacturing a liquid crystal display device according to claim 6, wherein the step of forming the semiconductor layer, the formation of the scanning line and the counter electrode, and the formation of the contact are performed using the same photomask by halftone exposure technology And a process of forming a pixel electrode also serving as a signal line and a drain wiring, and a process of forming a passivation insulating layer.

With this configuration, it is possible to reduce the number of photo-etching steps in which the scanning line and counter electrode forming process and the contact forming process are performed using one photomask, and an IPS type liquid crystal using four photomasks. A display device can be manufactured.

16. A method of manufacturing a liquid crystal display device according to claim 7, wherein the step of forming the semiconductor layer, the formation of the scanning line and the counter electrode, and the formation of the contact are performed using the same photomask by a halftone exposure technique. And a step of forming a pixel electrode also serving as a source line and a drain line using a halftone exposure technique and anodizing a source / drain line and a channel of an insulated gate transistor. It is characterized by that.

With this configuration, it is possible to reduce the number of photo-etching steps in which the scanning line and counter electrode forming step and the contact forming step are processed using a single photomask. In addition, a silicon oxide layer is formed on the channel between the source and drain to protect the channel by anodizing the source / drain wiring when forming the pixel electrode that also functions as the source wiring and the drain wiring. As a result of reducing the number of manufacturing steps that do not require the formation of an insulating layer, an IPS liquid crystal display device can be manufactured using three photomasks.

In some liquid crystal display devices described in the present invention, since a silicon oxide layer is formed on the channel by anodization, the source / drain wiring made of an anodizable metal layer is anodized simultaneously with the channel and insulated on the surface. By forming the layer, the active substrate is given a passivation function. Therefore, no special heating step is involved in the production of the active substrate constituting the liquid crystal display device, and the insulated gate transistor having the amorphous silicon layer as the semiconductor layer does not require excessive heat resistance. In other words, an effect of not causing deterioration of electrical performance by forming a passivation is added. In addition, when anodizing the source / drain wiring, it is possible to selectively protect the scanning line and signal line electrode terminals by introducing a halftone exposure technique, and the effect of preventing an increase in the number of photolithography steps can be obtained. It is done.

The semiconductor layer can be formed first, and then the scanning line forming process and the contact forming process for electrical connection to the scanning line can be processed with a single photomask by introducing halftone exposure technology. The reduction in the leveling process is the main point of the present invention. By forming an organic insulating layer or an anodized layer on the side surface of the exposed scanning line, it is possible to cross the scanning line and the signal line. Is born.

  In addition, the introduction of pseudo-picture element electrodes, combined with rationalization such as processing of picture element electrodes and scanning lines with a single photomask, can further reduce the number of photo-etching steps from the conventional five times to four or more. A liquid crystal display device can be manufactured using three photomasks, and the industrial value is extremely large from the viewpoint of cost reduction of the liquid crystal display device. Moreover, since the pattern accuracy of these processes is not so high, the production control is also facilitated by not greatly affecting the yield and quality.

In the IPS type liquid crystal display device according to Example 7, the electric field generated between the counter electrode and the pixel electrode is applied to the gate insulating layer on the counter electrode, the liquid crystal layer, and the anodized layer of the pixel electrode. The advantage that the display image is not easily burned out without the presence of a defective passivation insulating layer with many defects is not to be overlooked. This is because the anodic oxide layer of the drain wiring (picture element electrode) functions as a high resistance layer rather than an insulating layer, so that charge accumulation does not occur.

As is clear from the above description, the requirement of the present invention is that the semiconductor layer is formed first in the production of the active substrate, and then the scanning line (and counter electrode) forming process and the contact forming process are performed by halftone exposure. The introduction of technology makes it possible to process with a single photomask and the organic insulating layer or anodic oxide layer, which is an insulating layer, is formed on the side surface of the exposed scanning line (and the counter electrode). It is obvious that the difference in the material of the pixel electrode, the gate insulating layer, and the like, and the manufacturing method of the display device semiconductor device or the manufacturing method thereof belong to the category of the present invention. The usefulness of the present invention does not change even in a liquid crystal display device using LCD and a reflective liquid crystal display device, and the semiconductor layer of the insulated gate transistor is also limited to amorphous silicon. Ikoto is also apparent.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor device for display device (active substrate) according to Embodiment 1 of the present invention, and FIG. 2 is on the AA ′ line, the BB ′ line, and the CC ′ line in FIG. Sectional drawing of a manufacturing process is shown. Similarly, Example 2 is shown in FIGS. 3 and 4, Example 3 is shown in FIGS. 5 and 6, Example 4 is shown in FIGS. 7 and 8, Example 5 is shown in FIGS. 9 and 10, and Example 6 is shown in FIGS. 12, Example 7 shows a plan view of an active substrate and a sectional view of a manufacturing process in FIGS. 13 and 14, respectively. In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

In Example 1, as in the conventional example, first, a first metal layer 92 having a thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, Cr, A refractory metal such as Ta or Mo or an alloy or silicide thereof is deposited. As will be clarified in the following description, in the present invention, when an organic insulating layer is selected as the insulating layer formed on the side surface of the scanning line, there is almost no restriction caused by the scanning line material, but it is formed on the side surface of the scanning line. When an anodic oxide layer is selected as an insulating layer, it is necessary that the anodic oxide layer has an insulating property. In that case, considering that Ta alone has high resistance and AL alone has poor heat resistance. In order to reduce the resistance of the scanning line, the scanning line is composed of a single layer structure such as AL (Zr, Ta, Nd) alloy having high heat resistance or AL / Ta, Ta / AL / Ta, AL / AL (Ta , Zr, Nd) and other laminated structures can be selected. AL (Ta, Zr, Nd) means an AL alloy having high heat resistance to which Ta, Zr, Nd or the like of several percent or less is added.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a source A second amorphous silicon layer 33 containing impurities serving as a drain and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.1-0.05 μm, and a fine processing technique Thus, as shown in FIGS. 1A and 2A, a semiconductor layer region formed by stacking the second amorphous silicon layer 33A and the first amorphous silicon layer 31A is selectively formed. Then, the gate insulating layer 30 is exposed.

Subsequently, as shown in FIGS. 1B and 2B, the thickness of the openings 63A and 65A as the contact formation region 81B is 1 μm, for example, and the region 81A corresponding to the scanning line 11 and the storage capacitor line 16 The photosensitive resin patterns 81A and 81B thinner than 2 μm above are formed by a halftone exposure technique, and the gate insulating layer 30 and the first metal layer 92 are selectively removed using the photosensitive resin patterns 81A and 81B as a mask. The glass substrate 2 is exposed. Since the size of the contact is usually 10 μm or more, which is comparable to that of the electrode terminal, it is easy to produce a photomask for forming 81B (halftone region) and to control the accuracy of the finished dimensions. It is reasonable to set the pattern width of the photosensitive resin pattern 81A by setting the pattern width slightly larger than the semiconductor layer region formed by the lamination of the second amorphous silicon layer 33A and the first amorphous silicon layer 31A. However, there is a problem that the size of the insulated gate transistor is slightly increased. On the contrary, even when the pattern width of the photosensitive resin pattern 81A is set by slightly reducing the pattern width from the semiconductor layer region formed by the above-described lamination, the above-described process is performed when the gate insulating layer 30 and the first metal layer 92 are etched. Since the semiconductor layer formed of the stacked layer serves as a mask and the semiconductor layer is etched and the cross-sectional shape thereof is tapered, the semiconductor layer formed of the stacked layer has a pattern width larger than that of the gate insulating layer 30A and the gate electrode 11A. Is slightly smaller.

Subsequently, when the photosensitive resin patterns 81A and 81B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 81B disappears and the openings are opened as shown in FIGS. The gate insulating layers 30A and 30B in the portions 63A and 65A are exposed, and the photosensitive resin pattern 81C reduced in thickness on the scanning line 11 and the storage capacitor line 16 can be left as it is. Since the photosensitive resin pattern 81C (black region), that is, the pattern width of the gate electrode 11A is obtained by adding the mask alignment accuracy to the dimension between the source and drain wires, the alignment accuracy between the source and drain wires is 4 to 6 μm. When it is set to ± 3 μm, the minimum is 10 to 12 μm, and the dimensional accuracy is not severe. Also, the pattern width of the scanning line 11 and the storage capacitor line 16 is usually set to 10 μm or more because of the resistance value. However, in the present invention, unlike the conventional example, since the scanning line is formed after the formation of the semiconductor layer, the semiconductor layer is formed with the same or slightly narrow width as the gate electrode 11A, so that the resist pattern is converted during conversion from the resist pattern 81A to 81C. If the film is isotropically reduced by 1 μm, not only will the size be reduced by 2 μm, but the mask alignment accuracy during subsequent source / drain wiring formation will be reduced by 1 μm to ± 2 μm. Will be tough. Therefore, in the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension. Specifically, an RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) method having a high density plasma source, and a TCP (Transfer Coupled Plasma) method oxygen plasma treatment are more desirable. Alternatively, it is desirable to take a process measure by designing a large pattern dimension of the resist pattern 81A in advance in consideration of the dimensional change amount of the resist pattern.

Thereafter, as shown in FIG. 2C, an insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 15, electrodeposition or anodization is performed on the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the storage capacitor line 16 is similar, but not shown here) in parallel. A connection pattern 78 for applying a potential is sometimes required, and a film-forming region 79 using an appropriate mask means for the amorphous silicon layers 31 and 33 and the silicon nitride layer 30 by plasma CVD is located inside the connection pattern 78. It is limited and at least the connection pattern 78 needs to be exposed. Using connection means such as a hook clip having a sharp cutting edge in the connection pattern 78, the photosensitive resin pattern 81C (78) on the connection pattern 78 is pierced, and a + (plus) potential is applied to the scanning line 11 so that ethylene glycol is the main component. When the glass substrate 2 is infiltrated into the chemical conversion solution to be anodized, if the scanning line 11 is an AL-based alloy, for example, alumina (AL2O3) having a film thickness of 0.3 μm at a chemical conversion voltage of 200 V is formed. The In the case of electrodeposition, as shown in the literature, Monthly “Polymer Processing” November 2002 issue, a pendant carboxyl group-containing polyimide electrodeposition solution is used and the electrodeposition voltage number is 0.3 μm. A polyimide resin layer having a film thickness is formed. It should be noted that the insulating layer is formed on the exposed side surfaces of the scanning line 11 and the storage capacitor line 16, as long as at least some of the scanning lines 11 are not deserialized in the subsequent manufacturing process. It goes without saying that not only the inspection but also the actual operation as a liquid crystal display device is hindered. As the releasing means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but a detailed description is omitted.
Monthly “Polymer Processing” November 2002 issue

After the formation of the insulating layer 76, the gate insulating layers 30A and 30B in the openings 63A and 65A are selectively used with the photosensitive resin pattern 81C reduced in thickness as shown in FIGS. 1D and 2D as a mask. And a part 73 of the scanning line 11 and a part 75 of the storage capacitor line 16 are exposed.

After removing the reduced photosensitive resin pattern 81C, in the source / drain wiring formation process, an anodic heat-resistant metal layer having a film thickness of about 0.1 μm is formed using, for example, Ti, Ta using a vacuum film forming apparatus such as SPT. A thin film layer 34 having a thickness of approximately 0.3 μm, an AL thin film layer 35 having a thickness of approximately 0.3 μm, and an intermediate conductive layer having a thickness of approximately 0.1 μm, which is also anodizable, such as Ta A thin film layer 36 is deposited sequentially. Then, the source / drain wiring material composed of these three layers of thin films is sequentially etched using a photosensitive resin pattern by a fine processing technique to expose the gate insulating layers 30A and 30B, and FIGS. 1 (e) and 2 (e). ), The signal line 12 which also serves as the drain electrode 21 and the source electrode of the insulated gate transistor formed by stacking 34A, 35A and 36A is selectively formed. Etching of the second amorphous silicon layer 33A containing impurities and the first amorphous silicon layer 31A containing no impurities is unnecessary. It goes without saying that the source / drain wirings 12 and 21 are formed so as to partially overlap the gate electrode 11A (semiconductor layer 33A) because they do not become inoperable due to offset. Usually, in order to avoid side effects associated with the battery action, the electrode terminal 5 of the scanning line is formed at the same time including the part 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12, 21. Since the terminal 5 is not essential, the transparent conductive electrode terminal 5A may be directly formed in a subsequent process. Similarly, although the number including the part 75 of the storage capacitor line 16 is not given, an electrode terminal of the storage capacitor line 16 is also formed, but this is omitted in the following description. As the configuration of the source / drain wirings 12 and 21, it is reasonable to simplify the Ta / single layer if the restriction of the resistance value is loose, and the AL alloy to which Nd is added reduces the chemical potential and reduces the alkaline solution. In this case, the intermediate conductive layer 36 is not required, and the stacked structure of the source / drain wirings 12 and 21 can be made into a two-layer structure. The configuration of the wirings 12 and 21 is slightly simplified. This is the same even when IZO is used instead of ITO which is a transparent conductive layer.

After the formation of the source / drain wirings 12 and 21, for example, ITO is deposited on the entire surface of the glass substrate 2 as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIG. 1 (f) and FIG. 2 (f), the pixel electrode 22 is selectively formed on the glass substrate 2 including a part of the intermediate conductive layer 36A of the drain electrode 21 by a fine processing technique. At this time, a transparent conductive layer pattern is also formed on the electrode terminal 5 of the scanning line and the electrode terminal 6 which is a part of the signal line in a region outside the image display unit to form the transparent conductive electrode terminals 5A and 6A. . As described above, the electrode terminal 5 may not be formed, and at this time, the electrode terminal 5A may be formed directly including the opening 63A. Here, as in the conventional example, a transparent conductive short-circuit line 40 is provided, and the resistance between the electrode terminals 5A and 6A and the short-circuit line 40 is increased in a strip shape to increase the resistance, thereby providing a high resistance against static electricity. Yes.

Subsequently, as shown in FIGS. 1 (g) and 2 (g), the source / drain wirings 12, while irradiating light with the photosensitive resin pattern 83A used for the selective pattern formation of the pixel electrode 22 as a mask 21 is anodized to form an oxide layer on the surface thereof and the first amorphous silicon adjacent to the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 in the thickness direction A part of the layer 31A is anodized to form a silicon oxide layer 66 containing impurities, which is an insulating layer, and a silicon oxide layer (not shown) containing no impurities. At this time, the electrode terminals 5A and 6A are protected by the photosensitive resin patterns 83B and 83C. Ta is exposed on the upper surface of the source / drain wirings 12 and 21, and a stacked layer of Ta, AL and Ti is exposed on the side surface. The layer is changed to alumina or aluminum oxide (AL2O3) 69, and Ta is changed to tantalum pentoxide (Ta2O5) 70 which is an insulating layer. Although the titanium oxide layer 68 is not an insulating layer, the film thickness is extremely thin and the exposed area is small, so that there is no problem in terms of passivation. However, it is desirable that the refractory metal thin film layer 34A is also selected from Ta. However, it is necessary to pay attention to the characteristic that Ta, unlike Ti, lacks the function of absorbing the underlying surface oxide layer and facilitating ohmic contact.

If the second amorphous silicon layer 33A containing impurities between the channels is not completely insulated in the thickness direction, the leakage current of the insulated gate transistor is increased. Therefore, it is also disclosed in the preceding example that anodizing while irradiating light is an important point in the anodizing process. Specifically, when the leakage current of the insulated gate transistor exceeds μA by irradiating with sufficiently strong light of about 10,000 lux, the calculation is made from the area of the channel portion between the source / drain wirings 12 and 21 and the drain electrode 21. The current density for obtaining good film quality can be obtained by anodization of about 10 mA / cm 2.

Further, the second amorphous silicon layer 33A containing impurities is formed by anodizing and setting the formation voltage higher than about 100V, which is sufficient to transform the silicon oxide layer 66, which is an insulating layer, into an insulating layer. By changing the part of the first amorphous silicon layer 31A not containing impurities (about 100 mm) in contact with the silicon oxide layer 66 containing impurities into a silicon oxide layer (not shown) containing no impurities, The electrical purity is increased, and the electrical separation between the source / drain wirings 12 and 21 can be made complete. That is, the OFF current of the insulated gate transistor is sufficiently reduced to obtain a high ON / OFF ratio.

The thickness of each tantalum pentoxide 70, alumina 69, titanium oxide 68, and silicon oxide layer 66 formed by anodic oxidation is sufficient to be about 0.1 to 0.2 μm as a passivation insulating layer. The applied voltage is also realized at over 100V using a chemical conversion solution such as Although not shown, all signal lines 12 need to be formed electrically in parallel or in series, although not shown in the drawings, in some of the subsequent manufacturing steps. Needless to say, if this series-parallel is not canceled, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal display device is hindered. As the releasing means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but a detailed description is omitted.

Covering the pixel electrode 22 with the photosensitive resin pattern 83A not only does not require the anodization of the pixel electrode 22, but also causes an excessive formation current to flow to the drain electrode 21 via the insulated gate transistor. This is because it is not necessary to secure a large amount.

Finally, the photosensitive resin patterns 83A to 83D are removed to complete the active substrate 2 (display device semiconductor device) as shown in FIGS. 1 (h) and 2 (h). The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 1 of the present invention is completed. With respect to the configuration of the storage capacitor 15, the storage capacitor line 16 and the pixel electrode 22 are planarly overlapped via the gate insulating layer 30B as shown in FIG. However, the configuration of the storage capacitor 15 is not limited to this, and an insulating layer including the gate insulating layer 30A is interposed between the pixel electrode 22 and the preceding scanning line 11. It may be configured. Although other configurations are possible, detailed description thereof is omitted. As shown in FIG. 1 (h), a static conductive layer 40 is disposed on the outer periphery of the active substrate 2, and the transparent conductive layer pattern 40 is connected to the transparent conductive electrode terminals 5A and 6A. However, since the opening forming process is provided in the gate insulating layers 30A and 30B, other countermeasures against static electricity are easy.

In the first embodiment, the anodic oxide layer 69 (12) is formed only on the signal line 12 and the pixel electrode 22 is exposed while maintaining conductivity. However, the reason why sufficient reliability can be obtained is the liquid crystal. The drive signal applied to the cell is basically alternating current, and the counter electrode 14 has a DC voltage component between the counter electrode 14 and the pixel electrode 22 formed on the counter surface of the color filter so that the DC voltage component is reduced. Since the voltage is adjusted at the time of image inspection (flicker reduction adjustment), therefore, it is based on the basic principle that an insulating layer should be formed so that a direct current component does not flow only on the signal line 12.

In the first embodiment, a semiconductor layer of an insulated gate transistor is first formed, and then a halftone is formed on a layer with low pattern accuracy such as a scanning line forming step and a contact (opening) forming step for electrical connection to the scanning line. Apply photolithographic technology to reduce photo-etching process, after forming source / drain wiring, simultaneously with transparent conductive pixel electrode, source / drain wiring and channel are anodized and insulating layer on the surface The active substrate is fabricated with four photomasks by providing passivation, but a similar active substrate is fabricated even if the pixel electrode forming step and the source / drain wiring forming step are interchanged. Since this is possible, this will be described as a second embodiment.

In the second embodiment, as shown in FIGS. 3D and 4D, the contact formation process, that is, the gate insulating layers 30A and 30B in the openings 63A and 65A are selectively etched, and the scanning lines 11 are respectively formed. The same manufacturing process as in the first embodiment is performed until a part 73 of the storage capacitor and a part 75 of the storage capacitor line 16 are exposed. The film thickness of the first amorphous silicon layer 31 may be as thin as 0.1 μm here.

Subsequently, for example, ITO is deposited on the entire surface of the glass substrate 2 as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, and FIGS. As shown in e), the pixel electrodes 22 are selectively formed on the glass substrate 2 by a fine processing technique. At this time, the electrode terminal 55A of the scanning line including the electrode terminal 6A of the signal line and the part 73 of the scanning line is simultaneously formed in the region outside the image display portion. Also here, as in the conventional example, a transparent conductive short-circuit line 40 is provided, and between the electrode terminals 5A, 6A and the short-circuit line 40 is formed in an elongated stripe shape, so that the resistance is increased and the resistance against static electricity is increased. However, the electrode terminal 5A for the scanning line and the electrode terminal 6A for the signal line are not indispensable constituent elements, and can be omitted.

In the source / drain wiring formation process, a heat-resistant metal layer having a film thickness of about 0.1 μm and a thin film layer 34 of, for example, Ti, Ta, and the like, and a film thickness of about 0.3 μm, using a vacuum film forming apparatus such as SPT. Similarly, the AL thin film layer 35 is sequentially deposited as a low resistance wiring layer that can be anodized. Then, the source / drain wiring material composed of these two layers of thin films is sequentially etched using a photosensitive resin pattern 87 by a fine processing technique to expose the gate insulating layers 30A and 30B, and FIG. 3 (f) and FIG. As shown in f), the signal line 12 including the part of the pixel electrode 22 and selectively serving as the source wiring as well as the drain electrode 21 of the insulated gate transistor formed by stacking 34A and 35A is selectively formed. The scanning line electrode terminal 5A (including the signal line electrode terminal 6A) including the scanning line electrode terminal 5A or the scanning line part 73 exposed simultaneously with the formation of the drain wirings 12 and 21 is provided. A part of the electrode terminal 6 is also formed. Etching of the second amorphous silicon layer 33A containing impurities and the first amorphous silicon layer 31A containing no impurities is unnecessary. At this time, the photosensitive resin is thicker than the thickness of the region 87A (black region) on the electrode terminals 5 and 6 is 3 μm and the thickness of the region 87B (halftone region) on the source / drain wirings 12 and 21 is 1.5 μm. It is an important feature of the second embodiment that the patterns 87A and 87B are formed by the halftone exposure technique.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 is exposed, and the photosensitive resin pattern 87C having a reduced thickness on the electrode terminals 5 and 6 can be left as it is. Even if the pattern width of the photosensitive resin pattern 87C is reduced by the oxygen plasma treatment, an anodic oxide layer is formed around the pixel electrode 22 and the electrode terminals 5 and 6 that also serve as a drain electrode having a large pattern size. It is a remarkable feature that there is almost no influence on the electrical characteristics, yield and quality. As shown in FIGS. 3G and 4G, the source / drain wirings 12 and 21 are anodized while irradiating light in the same manner as in the first embodiment using the photosensitive resin pattern 87C with a reduced thickness as a mask. Part of the first amorphous silicon layer 31A adjacent to the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 and in the thickness direction. Is anodized to form a silicon oxide layer 66 containing impurities as an insulating layer and a silicon oxide layer (not shown) containing no impurities.

After the anodic oxidation, the photosensitive resin pattern 87C is removed, and as shown in FIGS. 3 (h) and 4 (h), electrode terminals comprising low resistance metal layers 35A and 35C having an anodic oxide layer formed on the side surfaces thereof. 6 and 5 are exposed. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 2 of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the first embodiment.

In Example 1 and Example 2, the source / drain wiring forming process and the transparent conductive pixel electrode forming process are independent, and an active substrate is manufactured using four photomasks. By processing the formation of the scanning line with one photomask, it is possible to further reduce the number of processes and produce an active substrate with four and three photomasks. This will be described as Example 4 and Example 5.

In Example 3, first, as a transparent conductive layer 91 having a film thickness of about 0.1 to 0.2 μm on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, ITO and a film thickness of 0.1 to A first metal layer 92 of about 0.3 μm is deposited. As will be clarified in the following description, in Examples 3 to 5, since the scanning line is formed of a laminate of a transparent conductive layer and a metal layer, an anodic oxidation requires that an insulating layer be formed on the side surface of the scanning line. Impossible. Therefore, since an organic insulating layer is formed by electrodeposition on the insulating layer, a high melting point such as Cr, Ta, Mo or the like is used as the first metal layer that does not cause a battery reaction with the transparent conductive layer ITO as the scanning line material. A metal or an alloy or silicide thereof is selected. If AL is used to reduce resistance, a single layer of heat-resistant AL (Nd) alloy is the simplest, and then Ta / AL (Zr, Hf) and Ta / Al / The Ta stack and configuration are complicated.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a source A second amorphous silicon layer 33 containing impurities serving as a drain and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm, and a fine processing technique Thus, as shown in FIGS. 5A and 6A, a semiconductor layer region formed by stacking the second amorphous silicon layer 33A and the first amorphous silicon layer 31A is selectively formed. Then, the gate insulating layer 30 is exposed.

Subsequently, as shown in FIGS. 5B and 6B, the film thickness of the region 82A on the scanning line 11 which also serves as the gate electrode 11A is 2 μm, for example, and the transparent conductive layer 91B and the first metal layer 92B A pseudo picture element electrode 93 made of a laminate of the above, a pseudo electrode terminal 94 made of a laminate of the transparent conductive layer 91A and the first metal layer 92A, and a pseudo electrode made of a laminate of the transparent conductive layer 91C and the first metal layer 92C. Photosensitive resin patterns 82A and 82B thicker than 1 μm in thickness of the photosensitive resin pattern 82B corresponding to the terminal 95 are formed by a halftone exposure technique, and the gate insulating layer 30 and the first insulating film 30 are formed using the photosensitive resin patterns 82A and 82B as a mask. In addition to the metal layer 92, the transparent conductive layer 91 is also sequentially removed to expose the glass substrate 2.

Thus, after obtaining a multilayer film pattern corresponding to the scanning line 11, which also serves as the gate electrode 11A, the pseudo picture element electrode 93, and the pseudo electrode terminals 94, 95, the photosensitive resin is subsequently applied by ashing means such as oxygen plasma. When the film thickness of the patterns 82A and 82B is reduced by 1 μm or more, the photosensitive resin pattern 82B disappears as shown in FIGS. 5C and 6C, and the pseudo picture element electrode 93 and the pseudo electrode terminals 94 and 95 are over. The photosensitive resin pattern 82 </ b> C whose thickness is reduced only on the scanning line 11 can be left as it is, while the gate insulating layers 30 </ b> A to 30 </ b> C are exposed. As described above, in the oxygen plasma treatment, it is desirable to increase the anisotropy and suppress the change in the pattern dimension so that the mask alignment accuracy in the subsequent source / drain wiring forming process is not lowered. Alternatively, the pattern dimension of the resist pattern 82A may be designed to be large in advance in consideration of the dimensional change amount of the resist pattern.

Subsequently, as shown in FIG. 6C, an organic insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, the connection pattern 78 shown in FIG. 16 is cut through the photosensitive resin pattern 82C (78) on the connection pattern 78 using connection means such as a hook clip having a sharp cutting edge, and a + (plus) potential is applied to the scanning line 11. However, depending on the composition of the electrodeposition liquid, a-(minus) potential may be applied. For example, a polyimide resin layer having a film thickness of 0.3 μm at an electrodeposition voltage number V is formed as the organic insulating layer. Since the pseudo picture element electrode 93 is electrically isolated, the organic insulating layer 76 is not formed around the pseudo picture element electrode 93.

Subsequently, as shown in FIGS. 5D and 6D, the gate insulating layers 30A to 30C and the first metal layers 92A to 92C are sequentially removed by using the photosensitive resin pattern 82C with a reduced thickness as a mask. When the layers 91A to 91C are exposed, an electrode terminal 5A for the scanning line, a pixel electrode 22 and an electrode terminal 6A for the signal line, each of which is made of a transparent conductive layer, are obtained.

After removing the photosensitive resin pattern 82C, in the source / drain wiring formation process, a thin film layer 34 such as Ti or Ta is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer having a thickness of about 0.3 μm. An insulated gate transistor comprising a laminate of 34A and 35A including a part of the pixel electrode 22 as shown in FIGS. 5 (e) and 6 (e) using a photosensitive resin pattern by microfabrication technology. The drain electrode 21 and the signal line 12 including a part of the electrode terminal 6A of the signal line and also serving as the source electrode are selectively formed to expose the gate insulating layer 30A. The amorphous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched while leaving about 0.05 to 0.1 μm. It will be understood that the electrode terminal 5A for the scanning line and the electrode terminal 6A for the signal line are exposed on the glass substrate 2 after the etching of the source / drain wirings 12 and 21 as in the case of the pixel electrode 22. . The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW alloy or the like if the resistance value is loosely restricted.

After the formation of the source / drain wirings 12, 21, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus. As shown in FIGS. 5 (f) and 6 (f), openings 38, 63 and 64 are formed on the transparent conductive pixel electrode 22 and the transparent conductive electrode terminals 5A and 6A, respectively. The passivation insulating layer in each opening is selectively removed to expose most of the picture element electrode 22 and the electrode terminals 5A and 6A.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 3 of the present invention is completed. With respect to the configuration of the storage capacitor 15, as shown in FIG. 5 (f), the storage electrode 72 formed including a part of the pixel electrode 22 at the same time as the source / drain wirings 12, 21 and the scanning line 11 in the previous stage. Although an example is shown in which the protrusions provided are overlapped in a planar manner via the gate insulating layer 30A (downward slanted line portion 52), the configuration of the storage capacitor 15 is limited to this. Instead, as in the first embodiment, an insulating layer including the gate insulating layer 30B may be interposed between the storage capacitor line 16 formed simultaneously with the scanning line 11 and the pixel electrode 22. The static electricity countermeasure wire 40 is the same as in the first and second embodiments.

In Example 3, the electrode terminal of the scanning line and the electrode terminal of the signal line are both formed of a transparent conductive layer, but the same metal as the source / drain wiring material is formed on the transparent conductive electrode terminal 5A which is a part of the scanning line. The electrode terminal 5 and the signal line 12 may be partly made of the same metal electrode terminal 6 as the source / drain wiring material, and pattern design may be performed as necessary.

In Example 3, the transparent conductive pixel electrode 22 is exposed on the glass substrate 2 when the contact is formed. Therefore, if a pinhole is generated in the heat-resistant metal layer 34 when the source / drain wirings 12 and 21 are formed, the low-resistance metal layer 35 is formed. In the case where aluminum is used, alkaline developer causes a battery reaction between aluminum and ITO, which is a transparent conductive layer, through a pinhole in the development process of the photosensitive resin for forming the source / drain wirings 12 and 21. It is known that ITO disappears. In order to avoid this battery effect, material measures such as adopting IZO instead of ITO or adding several percent of niobium (Nd) to aluminum are effective, but in Example 4 described below, it is transparent. By making the time when the conductive layer is exposed at the end of the manufacturing process, it is possible to cope with a process that avoids a chemical reaction between aluminum and ITO.

In the fourth embodiment, as shown in FIGS. 7C and 8C, the pseudo picture element electrode 93 and the gate insulating layers 30A to 30C on the pseudo electrode terminals 94 and 95 are exposed and only on the scanning line 11. The process proceeds in the same manufacturing process as in Example 3 until the reduced photosensitive resin pattern 82C is left as it is, and the organic insulating layer 76 is formed on the side surface of the gate electrode 11A.

Subsequently, as shown in FIGS. 7D and 8D, the gate insulating layers 30A to 30C are removed using the photosensitive resin pattern 82C with a reduced thickness as a mask to expose the first metal layers 92A to 92C. A pseudo electrode terminal 94 for the scanning line, a pseudo pixel electrode 93, and a pseudo electrode terminal 95 for the signal line are obtained.

After removing the photosensitive resin pattern 82C, in the source / drain wiring formation process, a thin film layer 34 such as Ti or Ta is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer having a thickness of about 0.3 μm. Then, using a photosensitive resin pattern by a microfabrication technique, as shown in FIGS. 7 (e) and 8 (e), an insulated gate type including a part of the pseudo picture element electrode 93 and a laminate of 34A and 35A. The gate insulating layer 30A is exposed by selectively selecting the signal line 12 that also includes a part of the drain electrode 21 of the transistor and the pseudo electrode terminal 95 of the signal line and also serves as the source electrode. The second amorphous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. The pseudo electrode terminal 94 of the scanning line and the pseudo electrode terminal 95 of the signal line may be formed exposed on the glass substrate 2 after the etching of the source / drain wirings 12 and 21 is completed, similarly to the pseudo pixel electrode 93. It will be understood. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW or the like if the resistance value is loosely restricted.

After the formation of the source / drain wirings 12 and 21, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer by using a PCVD apparatus. 7 (f) and FIG. 8 (f), openings 38, 63,... On the pseudo picture element electrode 93, on the scanning line pseudo electrode terminal 94 and on the signal line pseudo electrode terminal 95, respectively. 64, and selectively removing the passivation insulating layer and the first metal layers 92A to 92C in the respective openings so that most of the transparent conductive pixel electrode 22 and the transparent conductive electrode terminals 5A and 6A are formed. Exposed.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 4 of the present invention is completed. Regarding the configuration of the storage capacitor 15, as shown in FIG. 7F, the storage electrode 72 formed including a part of the pseudo-pixel electrode 93 simultaneously with the source / drain wirings 12 and 21, and the scanning line 11 in the previous stage. An example (lower right oblique line portion 52) configured by planarly overlapping the protruding portion provided on the gate insulating layer 30A is illustrated.

In Example 3 and Example 4, the scanning line forming process and the contact forming process are processed with a single photomask by the halftone exposure technique to promote the reduction of the manufacturing process. Since conventional SiNx is used, four photomasks are required for manufacturing the active substrate. Instead of the passivation using SiNx, a metal thin film capable of anodization is used for the source / drain wiring material as in Example 2, and an insulating anodic oxidation layer is formed by anodic oxidation when forming the source / drain wiring. It is possible to form passivation of source / drain wiring, and in channel-etched insulated gate transistors, it is also possible to form a silicon oxide layer on the surface of the channel and form the passivation of the channel. Since the reduction of the number of etching steps is also promoted, this will be described as Example 5.

In the fifth embodiment, the second amorphous silicon layers 33A to 33C and the first amorphous silicon are formed using the photosensitive resin pattern 82C whose thickness is reduced as shown in FIGS. 9D and 10D. The layers 31A to 31C, the gate insulating layers 30A to 30C, and the first metal layers 92A to 92C are sequentially removed to expose the transparent conductive layers 91A to 91C. Until the electrode 22 and the electrode terminal 6A of the signal line are obtained, the manufacturing process proceeds in substantially the same manner as in the third embodiment. However, the electrode terminal 6A (pseudo electrode terminal 95) is not necessarily required for the reason described later, and the first amorphous silicon layer 31 may be formed as thin as 0.1 μm.

Subsequently, in the source / drain wiring formation process, a heat-resistant metal layer having a thickness of about 0.1 μm, for example, a thin film layer 34 of Ti, Ta, etc., and a film thickness of 0. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer of about 3 μm that can also be anodized. Then, the source / drain wiring material composed of these two thin films is sequentially etched using the photosensitive resin patterns 87A and 87B by a fine processing technique to expose the gate insulating layer 30A, and FIG. 9 (e) and FIG. As shown in e), the drain electrode 21 of the insulated gate transistor including a part of the pixel electrode 22 and a stacked layer of 34A and 35A and the signal line 12 also serving as the source wiring are selectively formed, and the source / drain is formed. Simultaneously with the formation of the wirings 12 and 21, an electrode terminal 6 including a part 5A of the scanning line exposed and a part of the signal line and the electrode terminal 5 of the scanning line is also formed. That is, the pseudo electrode terminal 95 is not necessarily required as in the fourth embodiment. Note that the etching of the second amorphous silicon layer 33A containing impurities and the first amorphous silicon layer 31A containing no impurities is unnecessary. At this time, similar to the second embodiment, the photosensitive resin pattern 87A having a film thickness of the region 87A on the electrode terminals 5 and 6 is 3 μm and thicker than the film thickness 1.5 μm of the region 87B on the source / drain wirings 12 and 21, for example. It is an important feature of the fifth embodiment that 87B is formed by a halftone exposure technique. The minimum dimension of 87A corresponding to the electrode terminals 5 and 6 is as large as several tens of μm, and the photomask manufacturing and the finished dimension management are extremely easy. However, the minimum dimension of the region 87B corresponding to the signal line 12 is 4 to 8 μm. Since the dimensional accuracy is relatively high, a thin pattern is required as the halftone area. However, as described in the conventional example, the source / drain wirings 12 and 21 of the present invention are compared with the single exposure processing and the etching processing twice as compared with the source / drain wirings 12 and 21 formed by one exposure processing. Since it is formed by a single etching process, there are few factors that cause fluctuations in the pattern width, and the dimension management of the source / drain wirings 12 and 21 and the dimension management of the channel length between the source / drain wirings 12 and 21, that is, the channel length are conventional. Pattern accuracy is easier to manage than halftone exposure technology.

After the formation of the source / drain wirings 12, 21, when the photosensitive resin patterns 87A, 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C whose film is reduced only on the electrode terminals 5 and 6 can be left as it is. Even if the pattern width of the photosensitive resin pattern 87C is reduced by the oxygen plasma treatment, only an anodic oxide layer is formed around the electrode terminals 5 and 6 having a large pattern size, so that the electrical characteristics and yield of the liquid crystal display device are obtained. It is a remarkable feature that it has almost no influence on quality. Then, while irradiating light using the photosensitive resin pattern 87C as a mask, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 9 (f) and 10 (f). At the same time, a part of the first amorphous silicon layer 31A adjacent to the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 in the thickness direction is anodized to form an insulating layer. A silicon oxide layer 66 containing impurities and a silicon oxide layer (not shown) containing no impurities are formed.

When the photosensitive resin pattern 87C is removed after the anodic oxidation is finished, as shown in FIGS. 9 (g) and 10 (g), the electrode terminal 5 made of the low resistance thin film layer 35A having the anodic oxide layer formed on the side surface thereof is shown. 6 is exposed. The side surface of the electrode terminal 5 of the scanning line has a thickness of the anodized layer formed on the side surface as compared with the electrode terminal 6 of the signal line because an anodizing current flows through the high resistance short circuit line 40 (91C) for static electricity countermeasures. Please understand that is thin. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 5 of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the third embodiment.

In the fifth embodiment, the drain electrode 21 is electrically connected during the anodic oxidation of the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 and the source / drain wirings 12 and 21, as described above. Since the pixel electrode 22 is also exposed, the pixel electrode 22 is also anodized at the same time. For this reason, depending on the film quality of the transparent conductive layer constituting the pixel electrode 22, the resistance value may be increased by anodic oxidation. In this case, the film forming conditions of the transparent conductive layer are changed as appropriate to obtain a film quality lacking oxygen. Although necessary, the transparency of the transparent conductive layer does not decrease due to anodic oxidation. In addition, a current for anodizing the drain electrode 21, the pixel electrode 22, and the storage electrode 72 is also supplied through the channel of the insulated gate transistor. However, since the area of the pixel electrode 22 is large, a large formation current or Anodization layer 69 having a film quality and a film thickness equivalent to those on signal line 12 is formed on drain electrode 21 and storage electrode 72 on the drain electrode 21 and storage electrode 72, regardless of how much external light is irradiated. It is difficult to cope with the formation of only by extending the formation time. However, even if the anodic oxide layer 69 formed on the drain wiring 21 is somewhat incomplete, reliability that does not hinder practical use is often obtained. This is because, as described above, it is basically sufficient to form an insulating layer so that a direct current component does not flow only on the signal line 12.

In the fifth embodiment, the electrode terminals 5 and 6 are made of the same metal material as that of the signal line 12. However, the pseudo electrode terminals 94 and 95 are introduced as in the third embodiment to make the signal line 12 transparent electrode terminal 6A. It is easy to provide the transparent conductive electrode terminals 5A and 6A. In this case, it is not necessary to employ the halftone exposure technique for forming the source / drain wiring, but it is necessary to pay attention to an increase in the resistance value of the transparent conductive electrode terminals 5A and 6A. The transparent conductive layer pattern connecting the transparent conductive pattern 6A (91C) formed under the part 5A of the scanning line and the signal line 12 and the short-circuit line 40 is formed into an elongated linear shape, thereby generating static electricity. High resistance wiring can be used as a countermeasure, but of course, countermeasures against static electricity using other conductive members are possible.

The liquid crystal display device described above uses a TN type liquid crystal cell. However, a horizontal electric field is generated between a pair of counter electrodes and a pixel electrode formed at a predetermined distance from the pixel electrode. The process reduction proposed in the present invention is also useful in a liquid crystal display device of an IPS (In-Plain-Switting) system to be controlled, and will be described in the following examples.

In Example 6, as in the conventional example, first, a first metal layer 92 having a thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, Cr, Ta, Mo or the like or an alloy or silicide thereof is deposited. Further, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, The second amorphous silicon layer 33 containing impurities serving as a drain and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm, and fine processing technology is used. As shown in FIGS. 11A and 12A, a semiconductor layer region formed by stacking the second amorphous silicon layer 33A and the first amorphous silicon layer 31A is selectively formed. The gate insulating layer 30 is exposed.

Next, as shown in FIGS. 11B and 12B, the openings 63A and 65A, which are the contact formation regions 84B, have a film thickness of 1 μm, for example, and the scanning lines 11 and storage capacitor lines that also serve as the gate electrodes 11A The photosensitive resin patterns 84A and 84B having a film thickness of less than 2 μm on the region 84A corresponding to the counter electrode 16 which also serves as the counter electrode 16 are formed by the halftone exposure technique, and the gate insulating layer 30 and the first insulating film 30 are formed using the photosensitive resin patterns 84A and 84B as a mask. The glass layer 2 is exposed by sequentially removing the metal layers.

Subsequently, when the photosensitive resin patterns 84A and 84B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 84B disappears as shown in FIGS. 11 (c) and 12 (c). Thus, the gate insulating layers 30A and 30B are exposed in the openings 63A and 65A, respectively, and the photosensitive resin pattern 84C reduced in thickness on the scanning line 11 and the counter electrode 16 can be left as it is.

Subsequently, as shown in FIG. 11C, an insulating layer 76 is formed on the side surfaces of the gate electrode 11 </ b> A and the counter electrode 16. For this purpose, as shown in FIG. 17, the potential of the electrode 77 during electrodeposition or anodic oxidation at the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the counter electrode 16 is the same but is not shown here) in parallel. A connection pattern 78 is required to provide the film, and a film-forming region 79 using an appropriate mask means of the amorphous silicon layers 31 and 33 and the silicon nitride layers 30 and 32 by plasma CVD is located inside the connection pattern 78. It is limited, and at least the connection pattern 78 needs to be exposed. The connecting pattern 78 is cut through the photosensitive resin pattern 84C (78) on the connecting pattern 78 using connecting means such as a hook clip having a sharp edge, and an electric potential is applied to the scanning line 11 to perform electrodeposition or anodic oxidation, and an insulating layer In 76, either an organic insulating layer or an anodized layer is formed.

Further, as shown in FIGS. 11D and 12D, the gate insulating layers 30A and 30B in the openings 63A and 65A are etched using the reduced photosensitive resin pattern 84C as a mask, respectively. Part 73 and part 75 of the counter electrode 16 are exposed.

After the photosensitive resin pattern 84C is removed, a heat-resistant metal thin film layer such as Ti or Ta is formed as a heat-resistant metal layer having a film thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT in the source / drain wiring formation process. 34 and an AL thin film layer 35 are sequentially deposited as a low resistance wiring layer having a thickness of about 0.3 μm. Then, as shown in FIGS. 11 (e) and 12 (e), the source / drain wiring material made of these two layers of thin films is sequentially etched using a photosensitive resin pattern by a microfabrication technique, and 34A and 35A. The signal line 12 that also serves as the source wiring and the drain electrode 21 of the insulated gate transistor that becomes the pixel electrode is selectively formed. Here, as in the conventional example, the second amorphous silicon layer 33A and The first amorphous silicon layer 31A is sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. In addition, at the same time as the formation of the source / drain wirings 12, 21, the electrode terminal 5 of the scanning line and a part of the signal line 12 are included in the region outside the image display part, including the part 73 of the scanning line 11 in the opening 63 A. The electrode terminal 6 is also formed at the same time. Also here, the configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, Mo or the like if the resistance value is loosely restricted.

After the source / drain wirings 12 and 21 are formed, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as in the conventional five-mask process. Then, a passivation insulating layer 37 is formed, and openings 63 and 64 are selectively formed on the electrode terminals 5 and 6 of the scanning line 11 and the signal line 12 as shown in FIGS. 11 (f) and 12 (f). As a result, most of the electrode terminals 5 and 6 are exposed to complete the active substrate 2.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 6 of the present invention is completed. As is apparent from the above description, the IPS liquid crystal display device does not require the transparent conductive pixel electrode 22 on the acti substrate 2, and therefore the intermediate conductive layer 36 A on the source / drain wiring is also unnecessary. Regarding the configuration of the product capacitor 15, an example in which the counter electrode (storage capacitor line) 16 and the picture element electrode (drain electrode) 21 are configured via the gate insulating layer 30B (lower right oblique line portion 50) is shown in FIG. However, the configuration of the storage capacitor 15 is not limited to this, and the storage capacitor 15 is configured via an insulating layer including the gate insulating layer 30A between the pixel electrode 21 and the preceding scanning line 11. Also good. In FIG. 11 (f), a countermeasure against static electricity is particularly applicable, in which the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line are connected by a high-resistance member, for example, an insulated gate transistor or an elongated conductive line in an OFF state. Although not shown, since an opening 63A is provided and a step of exposing a portion 73 of the scanning line 11 is provided, it is easy to take measures against static electricity using a high-resistance part.

  In the sixth embodiment, the silicon nitride layer (SiNx) produced by using the PCVD apparatus is employed for the passivation of the active substrate 2 as in the conventional example, so that there are few process changes in the existing mass production factory and the introduction is easy. Although the merit is great, the process can be further reduced and the cost can be reduced by applying a passivation technique by anodic oxidation of the source / drain wiring as in the second and fifth embodiments. explain.

In Example 7, the gate insulating layers 30A and 30B in the openings 63A and 65A are etched by using the photosensitive resin pattern 84C with a reduced thickness as shown in FIGS. 13D and 14D, respectively. The manufacturing process proceeds in substantially the same manner as in the sixth embodiment until a part 73 of the scanning line 11 and a part 75 of the counter electrode 16 are exposed. However, the first amorphous silicon layer 31 may be formed as thin as 0.1 μm.

Subsequently, in the process of forming the source / drain wirings 12 and 21, a heat-resistant metal thin film layer 34 such as Ti or Ta is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. Then, the AL thin film layer 35 is sequentially deposited as a low-resistance wiring layer having a thickness of about 0.3 μm and also capable of anodization. Then, as shown in FIGS. 13 (e) and 14 (e), the source / drain wiring material composed of these two layers of thin films is sequentially etched using the photosensitive resin patterns 87A and 87B by a microfabrication technique. And the signal line 12 that also serves as the source electrode and the drain electrode 21 of the insulated gate transistor, which is a stacked pixel layer and 35A. Etching of the second amorphous silicon layer 33A containing impurities and the first amorphous silicon layer 31A containing no impurities is unnecessary. Simultaneously with the formation of the source / drain wirings 12, 21, the electrode terminal 5 of the scanning line and the electrode terminal 6 including a part of the signal line including the part 73 of the scanning line 11 in the opening 63 A are formed simultaneously. Sometimes, as in Example 5, the regions 87A (5) and 87A (6) on the electrode terminals 5 and 6 have a film thickness of 3 μm, for example, and regions 87B (12) and 87B (21 The photosensitive resin patterns 87A and 87B thicker than 1.5 μm are formed by a halftone exposure technique.

  After the formation of the source / drain wirings 12, 21, when the photosensitive resin patterns 87A, 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 are exposed, and the photosensitive resin patterns 87C (5) and 87C (6) whose thickness is reduced only on the electrode terminals 5 and 6 can be left as they are. Therefore, as shown in FIGS. 13 (f) and 14 (f), the source / drain wirings 12 and 21 are anodized while irradiating light using the photosensitive resin patterns 87C (5) and 87C (6) as a mask. Anodized layers 69 and 68 are formed on the surface, and a part of the second amorphous silicon layer 33A and the first amorphous silicon layer 31A exposed between the source / drain wirings 12 and 21 are formed. Anodization is performed to form a silicon oxide layer 66 containing impurities as an insulating layer and a silicon oxide layer (not shown) containing no impurities.

After the anodic oxidation, the photosensitive resin patterns 87C (5) and 87C (6) are removed to form the low resistance thin film layers 35A and 35C as shown in FIGS. 13 (g) and 14 (g). The electrode terminal 5 and the electrode terminal 6 are exposed. Anodized layers 69 and 68 are formed on the side surface of the electrode terminal 6 of the signal line 12 similarly to the signal line 12, but the anodized layer is not formed on the side surface of the electrode terminal 5 of the scanning line. Please be careful. This is because the scanning line electrode terminal 5 is anodized independently, and as in Example 5, the scanning line electrode terminal 5 and the signal line electrode terminal 6 are connected with a resistive member to prevent static electricity. When anodized, a slight amount of an anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line. As the resistive member, in the case of the IPS liquid crystal display device, a transparent conductive layer is unnecessary, and therefore any one of the scanning line material, the signal line material, and the semiconductor layer is necessary. However, the opening 63A for connection to the scanning line 11 There are no restrictions on which one to select because they exist, but a detailed description is omitted. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 7 of the present invention is completed. With respect to the configuration of the storage capacitor 15, an example in which the counter electrode (storage capacitor line) 16 and the pixel electrode (drain electrode) 21 are configured via the gate insulating layer 30B (lower right oblique line portion 50) is shown in FIG. ).

Plan view of a semiconductor device for a display device according to Example 1 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 1 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 2 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 2 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 3 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 3 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 4 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 4 of this invention. Plan view of display device semiconductor device according to embodiment 5 of the present invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 5 of this invention. Plan view of a semiconductor device for a display device according to Example 6 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 6 of this invention. Plan view of a semiconductor device for a display device according to Example 7 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 7 of this invention. Arrangement diagram of connection pattern for forming insulating layer in Example 1 and Example 2 Arrangement of connection pattern for forming insulating layer in Example 3, Example 4 and Example 5 Arrangement of connection pattern for forming insulating layer in Example 6 and Example 7 The perspective view which shows the mounting state of a liquid crystal panel Equivalent circuit diagram of LCD panel Sectional view of a conventional LCD panel Plan view of conventional active substrate Cross-sectional view of manufacturing process of conventional active substrate Plan view of streamlined active substrate Streamlined manufacturing process of active substrate

Explanation of symbols

1: Liquid crystal panel 2: Active substrate (glass substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: Scanning line electrode terminal 6: Signal line electrode terminal 9: Color filter (opposing glass substrate)
10: Insulated gate transistor 11: Scanning line 11A: (Gate wiring, gate electrode)
12: Signal line (source wiring, source electrode)
16: Storage capacitor line (counter electrode in IPS type)
17: Liquid crystal
19: Polarizing plate 20: Alignment film 21: Drain electrode (pixel electrode in IPS liquid crystal display device)
22: (transparent conductive) picture element electrode 30, 30A, 30B, 30C: gate insulating layer (first SiNx layer)
31, 31A, 31B, 31C: first amorphous silicon layer (without impurities) 32, 32A, 32B, 32C: second SiNx layer 32D: channel protective insulating layer (etch stop layer)
33, 33A, 33B, 33C: second amorphous silicon layer (including impurities) 34, 34A: refractory metal layer (anodizable) 35, 35A: low resistance metal layer (AL) )
36, 36A: (Anodically oxidizable) intermediate conductive layer 37: Passivation insulating layer 50, 51, 52: Storage capacitor formation region 62: Opening (on the drain electrode) 63, 63A: Opening (on the scanning line) 64 64A: Opening (on the signal line) 65, 65A: Opening (on the counter electrode) 66: Silicon oxide layer containing impurities 68: Anodized layer (titanium oxide, TiO 2)
69: Anodized layer (alumina, Al2O3)
70: Anodized layer (tantalum pentoxide, Ta2O5)
72: Storage electrode 73: Part of the scanning line 75: Part of the storage capacitor line 76: Insulating layer formed on the side surface of the scanning line 81A, 81B, 82A, 82B, 84A, 84B, 87A, 87B
: Photosensitive resin pattern (formed by halftone exposure) 83A: Photosensitive resin pattern (ordinary for pixel electrode formation) 91: Transparent conductive layer 92: First metal layer

Claims (16)

Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
Source (signal line) / drain wiring comprising one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and the opening. Similarly, the electrode terminal of the scanning line is formed,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the area overlapping the pixel electrode of the drain wiring and the electrode terminal area of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more anodizable metal layers including a heat-resistant metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer Also on the first transparent insulating substrate and on part of the pixel electrode, the drain wiring, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line comprising a part of the signal line Formed,
An anodic oxidation layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface; a transparent conductive pixel electrode; and a signal line Electrode terminals are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent insulating layer serving as the electrode terminal of the scanning line is exposed by removing the gate insulating layer and the first metal layer in the opening. ,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A liquid crystal display device, wherein a passivation insulating layer having openings on the pixel electrodes and on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, and a first metal layer on the periphery thereof. The transparent conductive picture element electrode and the electrode terminal of the transparent conductive signal line formed by laminating the first metal layer on the periphery thereof are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent insulating layer serving as the electrode terminal of the scanning line is exposed by removing the gate insulating layer and the first metal layer in the opening. ,
One or more second metals including a refractory metal layer on the second semiconductor layer, on the first transparent insulating substrate, and on a part of the first metal layer around the electrode terminal of the signal line. Similarly, a drain wiring is formed on the source wiring (signal line) composed of layers, on the second semiconductor layer, on the first transparent insulating substrate, and on a part of the first metal layer around the pixel electrode. And
A passivation insulating layer having openings on the transparent conductive pixel electrodes and on the electrode terminals of the transparent conductive scanning lines and signal lines is formed on the first transparent insulating substrate. A characteristic liquid crystal display device. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the gate insulating layer and the first metal layer in the opening are removed to expose the transparent conductive layer that is part of the scanning line. ,
A source wiring (signal line) made of one or more anodizable metal layers including a heat-resistant metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer Also on the first transparent insulating substrate and on part of the pixel electrode, the drain wiring, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line comprising a part of the signal line Formed,
An anodic oxidation layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the electrode terminal of the scanning line including the opening, and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display unit,
A liquid crystal display device, wherein a passivation insulating layer having openings on electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer that does not contain impurities slightly smaller than the gate insulating layer is formed in an island shape over the gate insulating layer on the gate electrode,
A second semiconductor layer including a pair of impurities is formed on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; The electrode terminal of the scanning line, including the opening, and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display unit are formed,
An anodized layer is formed on the source / drain wiring except on the electrode terminal of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. 8. The insulating layer formed on the side surface of the scanning line is an organic insulating layer, wherein the insulating layer is an organic insulating layer. Liquid crystal display device. The claim 1, claim 2, claim 6, and claim 7, wherein the first metal layer is made of an anodizable metal layer and the insulating layer formed on the side surface of the scanning line is an anodized layer. A liquid crystal display device according to 1. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching at least the gate insulating layer and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer in the contact formation region; and
Forming an insulating layer on a side surface of the scanning line;
Etching the gate insulating layer of the contact region using the photosensitive resin pattern having a reduced thickness as a mask to expose a part of the scanning line; and
After depositing one or more anodizable metal layers including a refractory metal layer, the source layer (signal line) is selectively removed by microfabrication technology so as to partially overlap the gate electrode. A step of forming an electrode terminal of the scanning line including a part of the scanning line;
A transparent conductive pixel electrode on the first transparent insulating substrate and a part of the drain wiring, a transparent conductive electrode terminal on the signal line in a region outside the image display unit, and an electrode terminal of the scanning line Forming a transparent conductive electrode terminal thereon;
Source / drain wiring and source / drain wiring while protecting the transparent conductive pixel electrode and transparent conductive electrode terminal using the photosensitive resin pattern used for selective pattern formation of the pixel electrode and electrode terminal as a mask A method for manufacturing a liquid crystal display device, comprising a step of anodizing an amorphous silicon layer therebetween. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching at least the gate insulating layer and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer in the contact formation region; and
Forming an insulating layer on a side surface of the scanning line;
Etching the gate insulating layer of the contact region using the photosensitive resin pattern having a reduced thickness as a mask to expose a part of the scanning line; and
Forming at least a transparent conductive pixel electrode on the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, a source wiring (signal line) so as to partially overlap the gate electrode, and a drain wiring including a part of the pixel electrode, And corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, on the electrode terminal of the scanning line and the signal line. Forming a photosensitive resin pattern whose film thickness is thicker than other regions;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and scanning and signal line electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring;
A method of manufacturing a liquid crystal display device comprising a step of anodizing a source / drain wiring and an amorphous silicon layer between the source / drain wiring while protecting the electrode terminal. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, the film thickness on the electrode terminal forming area of the scanning line and the signal line in the area outside the image display part and the image display part is larger than that in the other areas Forming a thin photosensitive resin pattern,
Etching at least the gate insulating layer, the first metal layer, and the transparent conductive layer sequentially using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line;
Forming an insulating layer on a side surface of the scanning line;
The transparent conductive picture element is etched by etching the gate insulating layer and the first metal layer on the picture element electrode, the scanning line, and the electrode terminal of the signal line using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the electrode and the electrode terminal of the transparent conductive scanning line and the electrode terminal of the signal line;
After depositing one or more second metal layers including the refractory metal layer, the second metal layer and the second amorphous silicon layer are selectively removed by a microfabrication technique to partially remove the gate electrode Forming a source wiring (signal line) including a part of the electrode terminal of the signal line so as to overlap, and forming a drain wiring also including a part of the pixel electrode;
Forming a passivation insulating layer having openings on the transparent conductive picture element electrodes and on the electrode terminals of the transparent conductive scanning lines and signal lines on the first transparent insulating substrate; Manufacturing method. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, the film thickness on the electrode terminal forming area of the scanning line and the signal line in the area outside the image display part and the image display part is larger than that in the other areas Forming a thin photosensitive resin pattern,
Etching at least the gate insulating layer, the first metal layer, and the transparent conductive layer sequentially using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line;
Forming an insulating layer on a side surface of the scanning line;
The transparent conductive layer and the first metal layer are stacked by etching the gate insulating layer on the picture element electrode and on the electrode terminal of the scanning line and the signal line using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the pseudo picture element electrode and the pseudo electrode terminal of the scanning line and the signal line,
After depositing one or more second metal layers including the refractory metal layer, the second metal layer and the second amorphous silicon layer are selectively removed by a microfabrication technique to partially remove the gate electrode Forming a source wiring (signal line) including a part of the pseudo electrode terminal of the signal line so as to overlap, and forming a drain wiring also including a part of the pseudo pixel electrode;
Forming a passivation insulating layer having an opening on the pseudo-pixel electrode and the pseudo-electrode terminal on the first transparent insulating substrate;
A method for manufacturing a liquid crystal display device, comprising a step of removing the first metal layer in the opening. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, with a thinner film thickness on the contact formation area of the scanning line on the pixel electrode and in the area outside the image display area than other areas. Forming, and
Etching at least the gate insulating layer, the first metal layer, and the transparent conductive layer sequentially using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer on the pixel electrode and the contact formation region of the scanning line;
Forming an insulating layer on a side surface of the scanning line;
The transparent conductive pixel electrode and the scanning line are etched by etching the gate insulating layer and the first metal layer on the pixel electrode, the contact region of the scanning line, using the photosensitive resin pattern having the reduced thickness as a mask. A step of exposing a portion of
After depositing one or more anodizable metal layers including a refractory metal layer, a source wiring (signal line) so as to partially overlap the gate electrode, and a drain wiring including a part of the pixel electrode, And corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, on the electrode terminal of the scanning line and the signal line. Forming a photosensitive resin pattern whose film thickness is thicker than other regions;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and scanning and signal line electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring;
A method of manufacturing a liquid crystal display device comprising a step of anodizing a source / drain wiring and an amorphous silicon layer between the source / drain wiring while protecting the electrode terminal. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching at least the gate insulating layer and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer in the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the gate insulating layer of the contact region using the photosensitive resin pattern having a reduced thickness as a mask to expose a part of the scanning line; and
After depositing one or more second metal layers including the refractory metal layer, the second metal layer and the second amorphous silicon layer are selectively removed by a microfabrication technique to partially remove the gate electrode A source line (signal line) / drain line (pixel electrode) so as to overlap, an electrode terminal of the scan line including a part of the scan line, and a signal composed of a part of the signal line in an area outside the image display unit Forming a wire electrode terminal;
A method for manufacturing a liquid crystal display device, comprising: forming a passivation insulating layer having openings on electrode terminals of scanning lines and signal lines on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
Forming a second amorphous silicon layer and a first amorphous silicon layer in an island shape in the semiconductor layer formation region to expose the gate insulating layer;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching at least the gate insulating layer and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the gate insulating layer in the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the gate insulating layer of the contact region using the photosensitive resin pattern having a reduced thickness as a mask to expose a part of the scanning line; and
After depositing one or more anodizable metal layers including a refractory metal layer, a source wiring (signal line) / drain wiring (pixel electrode) and one of the scanning lines so as to partially overlap the gate electrode Forming a photosensitive resin pattern including a portion corresponding to the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line, the film thickness on the electrode terminal being thicker than other regions; ,
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and scanning and signal line electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring;
A method of manufacturing a liquid crystal display device comprising a step of anodizing a source / drain wiring and an amorphous silicon layer between the source / drain wiring while protecting the electrode terminal.

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