JP2002229480A - Display device, liquid crystal display device and semiconductor device for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a matrix type display device. SOLUTION: The display part of the matrix type display device is formed by cutting some wirings in intersection parts of wirings of scanning lines and signal lines or the like and in intersection parts of power source lines and other wirings and, also, connection lines connecting the cut wirings with a gate insulating layer or an interlayer insulating layer and other kinds of insulating layers are formed in the display part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having an image display function, particularly to an active liquid crystal display device or an organic EL display device.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of a large amount of television images and various image display devices on a commercial basis with 5 to 50 cm diagonal liquid crystal panels. ing. Further, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0003] These liquid crystal image display devices (liquid crystal panels)
Represents 200 to 1200 scanning lines and 200 to 16 signal lines
A matrix organization of about 00 lines is generally used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 10 shows a state of mounting on a liquid crystal panel.
A semiconductor integrated circuit chip 3 for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, a group of scanning line terminal electrodes 6 formed on a glass substrate 2, is connected using a conductive adhesive. Or a COG (Chip-On-Glass) method, for example, based on a polyimide resin thin film and having a terminal (not shown) of copper foil plated with gold or solder.
A TCP (Tape-Ca) in which the CP film 4 is fixed to the group of terminal electrodes 5 of the signal lines by pressing with an appropriate adhesive containing a conductive medium.
An electrical signal is supplied to the image display unit by mounting means such as a rrier-package method. Here, for the sake of convenience, two mounting methods are shown simultaneously, but in practice, either method is appropriately selected.

[0005] Reference numerals 7 and 8 denote an image display portion located substantially at the center of the liquid crystal panel 1 and terminal electrodes 5 and 6 of signal lines and scanning lines.
Between the terminal electrode groups 5, 6
It is not necessary to be made of the same conductive material as that described above. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface.

FIG. 11 is an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 10).
Is a scanning line, 12 (7 in FIG. 10) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the common electrodes 14 common to all the liquid crystal cells 13 drawn by dotted lines are formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus (storage capacitor line) of the storage capacitor 15.

FIG. 12 is a sectional view of a main part of an image display section of a liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a spacer material (not shown) such as resin fibers or beads. Is formed at a predetermined distance of about several μm, and the gap is sealed at the periphery of the glass substrate 9 with a sealing material made of an organic resin and a sealing material (neither is shown). It is a closed space, and the liquid crystal 17 is filled in this closed space.

In order to realize a color display, an organic thin film having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the glass substrate 9. Since a color display function is provided, in this case, the glass substrate 9 is also called a color filter (Color
The Filter abbreviation is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element.
At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials.
Usually, two polarizing plates 19 are required. Although not shown, a rear light source is disposed as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described later in detail. Colored layers 1 adjacent on color filter 9
8 and a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technology fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (referred to as an etch stop type). FIG. 13 is a plan view of a unit picture element of an active substrate (semiconductor device for an image display device) constituting a conventional liquid crystal panel. FIG. 14 is a cross-sectional view taken along line AA ′ of FIG. Is briefly described below. The projection 50 formed on the scanning line 11
A region 51 where the pixel electrode 22 and the pixel electrode 22 overlap with each other with a gate insulating layer interposed therebetween (a hatched portion inclined downward to the right) forms the storage capacitor 15, but a detailed description thereof is omitted here.

First, as shown in FIG. 14 (a), an insulating substrate having high heat resistance, chemical resistance, and transparency has a thickness of 0.5 to 0.5 mm.
A glass substrate 2 having a thickness of about 1.1 mm, for example, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a product 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo, or the like, or an alloy or silicide thereof, a gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, it is reasonable to use AL (aluminum) as the material of the scanning line. However, AL alone has low heat resistance. Therefore, Cr, T
Lamination with a, Mo or silicide thereof, or addition of an oxide layer (AL ₂ O ₃ ) by anodic oxidation on the surface of AL is currently a general technique. That is,
The scanning line 11 includes one or more metal layers.

Next, as shown in FIG. 14B, a first SiN _x (silicon nitride) layer serving as a gate insulating layer and an insulating gate are formed on the entire surface of the glass substrate 2 by using a PCVD (Plasma Thievey) apparatus. An amorphous silicon (a-Si) layer containing almost no impurities as a first semiconductor layer serving as a channel of a _p- type transistor, and a second SiN _x layer serving as an insulating layer for protecting a channel, and three types of thin film layers. , For example, 0.3-0.0
30, 31, 32 by sequentially depositing with a film thickness of about 5-0.1 μm
And

Subsequently, the second amorphous SiN _x layer on the gate 11 is selectively left narrower than the gate 11 by a fine processing technique to expose the first amorphous silicon layer 31 as 32 ′. Is used to form an amorphous silicon layer 33 containing, for example, phosphorus as an impurity as a second semiconductor layer serving as a source / drain of an insulated gate transistor, for example, at 0.05 μm.
After being deposited with a film thickness of the order of, the first amorphous silicon layer 31 is formed only on the vicinity of the gate 11 as shown in FIG.
And the second amorphous silicon layer 33 are formed into island shapes 31 ′, 33 ′.
And the gate insulating layer 30 is exposed.

Subsequently, as shown in FIG.
As a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as PT, for example, ITO (Indium-Tin-Oxide)
And the picture element electrode 22 is selectively formed on the gate insulating layer 30 by a fine processing technique.

Further, as shown in FIG. 14E, a selective opening 63 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display section necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 14 (f), a heat-resistant metal thin film layer 34 of, for example, Ti, Cr, Mo, etc.
An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a low-resistance wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by microfabrication technology and insulated including the pixel electrode 22. The drain electrode 21 of the gate type transistor and the source electrode 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 ′ between the source and drain electrodes is removed to expose the second SiN _x layer 32 ′, In the region, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the second SiN _x layer 32 ′ serving as a channel protection layer is present and the etching of the second amorphous silicon layer 33 ′ is automatically completed. It is.

The source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 (several μm) so that the insulated gate transistor does not have an offset structure.
Since this overlap acts electrically as a parasitic capacitance, the smaller the better, the better. It is about 2 μm. In addition, at the periphery of the image display unit, including the opening 63 on the scanning line 11, the signal line 12 and the scanning line side terminal electrode 6 simultaneously with the signal line 12, or the wiring connecting the scanning line 11 and the scanning line side terminal electrode 6. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, an SiN _x layer having a thickness of about 0.3 to 0.7 μm is applied as a transparent insulating layer on the entire surface of the glass substrate 2 by using a PCVD apparatus in the same manner as the gate insulating layer 30 so as to passivate. As shown in FIG. 14 (g), an opening 38 is formed on the pixel electrode 22 to form a layer 37.
Are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines, and most of the terminal electrodes are also exposed.

If the wiring resistance of the signal line 12 is not a problem, the low-resistance wiring layer 35 made of AL is not always necessary. In this case, if a heat-resistant metal material such as Cr, Ta, or Mo is selected, the source and the wiring can be used. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is, firstly, to prevent a decrease in the effective voltage applied to the liquid crystal cell, and secondly, because the film quality of the passivation insulating layer 37 is generally poor, This is for avoiding the accumulation of the electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film forming temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The above-described active substrate manufacturing process requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for liquid crystal panel manufacturers in order to realize lower prices for liquid crystal panels and respond to further increases in demand. I've been.

FIG. 15 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 16 is a cross-sectional view taken along the line AA 'in FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. A region 52 where the storage capacitance line 16 and the drain electrode 21 overlap each other with the gate insulating layer 30 interposed therebetween (a hatched portion falling to the right) forms the storage capacitance 15, but a detailed description thereof is omitted here. .

First, similarly to the conventional example, as shown in FIG. 16A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a glass substrate 2 by using a vacuum film forming apparatus such as SPT. And a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by a fine processing technique.

Next, as shown in FIG. 16B, an SiN _x layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 using a PCVD apparatus, and a SiN _x layer containing almost no impurities and serving as a channel of an insulated gate transistor is formed. A first amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are formed in a thickness of, for example, about 0.3-0.2-0.05 μm. They are sequentially deposited to form 30, 31, 33.

Then, as shown in FIG. 16C, the gate insulating layer 30 is formed on the gate 11 by leaving the semiconductor layers made of the first and second amorphous silicon layers in the form of islands 31 'and 33'. Exposed.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as PT, for example, a Ti thin film layer 34 as a heat-resistant metal layer with a thickness of about 0.1 μm, an AL thin film layer 35 with a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm-thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer, and the drain electrode 21 of the insulated gate transistor and the source electrode 12 also serving as a signal line are selectively formed by a fine processing technique. This selective patterning is
Using the photosensitive resin pattern used for forming the drain wiring as a mask, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', and the first amorphous silicon layer 31' Are sequentially etched, and the first amorphous silicon layer 31 'is etched by leaving about 0.05 to 0.1 .mu.m, so that it is called a channel etch.

After the photosensitive resin pattern is further removed, as shown in FIG. 16E, a transparent insulating layer is formed on the entire surface of the glass substrate 2 by PCVD in the same manner as the gate insulating layer.
A passivation insulating layer 37 is formed by depositing a SiN _x layer having a thickness of about 0.3 μm using an apparatus, and an opening is formed on the drain electrode 21 at a position where the opening 62 and the terminal electrode 6 of the scanning line 11 are formed. 63 is formed to form the drain electrode 21 and the scanning line 1
Expose a portion of 1. Although not shown, an opening 64 is also formed on the position where the terminal electrode 5 of the signal line is formed to expose a part of the signal line 12.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as The pixel electrode 22 is selectively formed on the substrate to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 63 may be used as the terminal electrode 6,
As illustrated, the terminal electrode 6 ′ made of ITO may be selectively formed on the passivation insulating layer 37 including the opening 63.

As described above, the five-mask process is performed once by the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the process of forming an opening (contact) to a scanning line and the process of forming an opening to a pixel electrode and the process of forming a contact, which were required twice, have been streamlined once. Can be. Further, since the pixel electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a transparent resin thin film, for example, for 1.5 times.
If the pixel electrode 22 is formed thicker than μm, even if the pixel electrode 22 overlaps the scanning line 11 or the signal line 12, interference due to capacitance is small, and deterioration of image quality can be avoided, so that the pixel electrode 22 can be formed large. There are many advantages such as an improvement in the aperture ratio.

[0030]

The power consumption of the above-mentioned transmission type liquid crystal panel includes the power consumption of the driving semiconductor integrated circuit on the scanning line side and the signal line side, the power consumption of the back light source, and the power consumption of the scanning line side. This is the sum of the power consumption of a control semiconductor integrated circuit (generally called a controller) that sends a control signal to the drive semiconductor integrated circuit on the signal line side.

The power consumption of the driving semiconductor integrated circuits on the scanning line side and the signal line side is determined by the capacitance and the driving voltage of the scanning line and the signal line, which are the loads, that is, the power accompanying the charging and discharging of the capacitance.
Although it largely depends on the screen size and definition of the liquid crystal panel, generally speaking, it is clear that the smaller the capacitance component of the scanning line and the signal line, the smaller the capacitance component.

As described above, the source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 in a plane so that the insulated gate transistor does not have an offset structure. Since this overlap acts electrically as a parasitic capacitance, the smaller the better, the better. It is about 2 μm. Rather, the thickness is preferably about 3 μm from the viewpoint of manufacturing margin during mass production. However, at present, a self-aligned insulated gate transistor such as a single crystal silicon device has not been realized or fixed for various reasons. . In addition, no particular attention has been paid to an approach for reducing a parasitic capacitance caused by a plane crossing of a scanning line and a signal line.

The present invention has been made in view of the above-mentioned circumstances, and it is intended that a parasitic capacitance formed between a scanning line or a signal line and a power supply line or other wiring crossing the scanning line or the signal line, and further, that the scanning line and the signal line cross each other. It is an object to reduce power consumption of a display device by reducing parasitic capacitance generated by the display device.

[0034]

According to the present invention, one of the wirings is provided at a crossing of two kinds of wirings such as a power supply line or other wiring intersecting a scanning line or a signal line, or an intersection of two kinds of wirings such as a scanning line and a signal line. Separate and add another insulating layer to a gate insulating layer or an interlayer insulating layer that constitutes an insulated gate transistor that is a switching element, and form connection lines connecting the separated wirings on the two or more insulating layers. By doing so, the insulating layer at the intersection is formed thick.

According to the display device of the present invention, at least one switching insulated gate transistor, a scanning line also serving as a gate and a source also serving as a source of the switching insulated gate transistor, and a drain are provided on one main surface. An insulating substrate and a display medium in which unit picture elements having a connected storage capacitor, a driving insulated gate transistor, and a display electrode connected to the drain of the driving insulated gate transistor are arranged in a two-dimensional matrix; In the display device, one of the scan line and the signal line is divided at the intersection of the scan line and the signal line, and the scan line or the signal line is separated through the gate insulating layer or the interlayer insulating layer of the switching insulated gate transistor and another insulating layer. And a first connection line for connecting any of the divided scanning lines or signal lines is formed. .

According to this configuration, at the intersection of the scanning line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and is formed between the scanning line and the signal line. Parasitic capacitance is reduced. As a result, the power consumption of any of the driving circuits for driving the scanning lines and the signal lines is reduced.

In the display device according to the second aspect, either the power supply line or the signal line is divided at the intersection of the power supply line and the signal line which also serves as the source of the driving insulated gate transistor substantially parallel to the scanning line. A second connection line for connecting the divided power supply line or signal line via a gate insulating layer or an interlayer insulating layer of the switching insulated gate transistor and another insulating layer is formed. I do.

With this configuration, at the intersection of the power supply line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the signal line decreases. As a result, the power consumption of the driving circuit for driving the signal line is also reduced.

In the display device according to the third aspect, either the power supply line or the scanning line is divided at the intersection of the power supply line and the scanning line, which also serves as the source of the driving insulated gate transistor substantially parallel to the signal line. A third connection line for connecting the separated power supply line or scan line via a gate insulating layer or an interlayer insulating layer of the switching insulated gate transistor and another insulating layer. I do.

With this configuration, at the intersection of the power supply line and the scanning line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the scanning line decreases. As a result, the power consumption of the driving circuit for driving the scanning lines is also reduced.

A display device according to a fourth aspect is the display device according to the first aspect, further comprising a second or third connection line in addition to the first connection line.

With this configuration, the thickness of the insulating layer that insulates and separates these electrode lines at the intersection between the scanning line and the signal line and at the intersection between the power supply line and the scanning line or the signal line can be increased. As a result, the parasitic capacitance of the scanning line and the signal line is further reduced. As a result, the power consumption of the driving circuit for driving the scanning lines and the signal lines is further reduced.

A display device according to a fifth aspect is characterized in that the switching insulated gate transistor and the driving insulated gate transistor are the same.

This configuration is applied to a display device that requires only a small amount of power to drive a display medium, and corresponds to, for example, a liquid crystal display device.

According to a sixth aspect of the present invention, there is provided a liquid crystal display device having at least one insulated gate transistor on one principal surface, a scanning line also serving as a gate and a signal line also serving as a source, and a drain of the switching insulated gate transistor. Liquid crystal display device in which a liquid crystal is filled between an insulating substrate in which unit picture elements each having a patterned pixel electrode are arranged in a two-dimensional matrix, and a transparent insulating substrate or a color filter facing the insulating substrate. In the above, either the scanning line or the signal line is divided at the intersection of the scanning line and the signal line, and the divided scanning line is separated via a gate insulating layer or an interlayer insulating layer of an insulated gate transistor and another insulating layer. Alternatively, a first connection line for connecting any of the signal lines is formed.

According to this configuration, at the intersection of the scanning line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and is formed between the scanning line and the signal line. Parasitic capacitance is reduced. As a result, the power consumption of any of the driving circuits for driving the scanning lines and the signal lines is reduced.

According to a seventh aspect of the present invention, in the liquid crystal display device, either the common capacitance line or the signal line is divided at the intersection of the common capacitance line and the signal line which are also substantially parallel to the scanning line, and the gate of the insulated gate transistor is separated. A second connection line for connecting any of the divided common capacitance lines or signal lines via an insulating layer or an interlayer insulating layer and another insulating layer is formed.

With this configuration, at the intersection of the common capacitance line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the signal line decreases. As a result, the power consumption of the driving circuit for driving the signal line is also reduced.

In the liquid crystal display device according to the present invention, either the common capacitance line or the scanning line is divided at the intersection of the common capacitance line and the scanning line which are also substantially parallel to the signal line, and the gate of the insulated gate transistor is separated. A third connection line for connecting any of the divided common capacitance lines or the scanning lines via an insulating layer or an interlayer insulating layer and another insulating layer is formed.

With this configuration, at the intersection of the common capacitance line and the scanning line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the scanning line decreases. As a result, the power consumption of the driving circuit for driving the scanning lines is also reduced.

The liquid crystal display device according to the ninth aspect has the second or third connection line in addition to the first connection line.

With this configuration, the thickness of the insulating layer that insulates and separates these electrode lines at the intersection between the scanning line and the signal line and at the intersection between the common capacitance line and the scanning line or the signal line can be increased. As a result, the parasitic capacitance of the scanning line and the signal line is further reduced. As a result, the power consumption of the driving circuit for driving the scanning lines and the signal lines is further reduced.

According to a tenth aspect of the present invention, in the semiconductor device for a display device, a scanning line which is formed of one or more metal layers and also serves as a gate of an insulated gate transistor is formed on one main surface of the insulating substrate, and is formed on the gate. A first semiconductor layer containing no impurity is formed in an island shape through one or more gate insulating layers, and a second semiconductor layer is formed on the first semiconductor layer so as to overlap with the gate and contain an impurity. Are formed as a source / drain, on the second semiconductor layer, a drain electrode and a source (signal line) electrode separated except on a scanning line are formed of one or more metal layers, and the separated source (signal A passivation insulating layer having a pair of first openings on both ends of the electrode and a second opening on the drain electrode, including a second opening on the passivation insulating layer; Pixel electrode and Characterized in that the connecting line connecting the first of the shed source (signal line) include openings electrode pairs are formed.

According to this configuration, any of the divided electrode lines at the intersection of the scanning line and the signal line is connected by a connection layer formed on a stack of a gate insulating layer and a passivation insulating layer, and is connected to the scanning line. It is possible to reduce the parasitic capacitance between the signal lines.

The display device semiconductor device according to the eleventh aspect is the display device semiconductor device according to the tenth aspect, wherein the picture element electrode and the connection line are formed simultaneously by the same member.

According to this configuration, a semiconductor device for a display device can be obtained without increasing the cost because the number of manufacturing steps does not increase when any of the divided connection lines is formed, and the power consumption of the display device is reduced.

According to a twelfth aspect of the present invention, in the semiconductor device for a display device, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate.
A gate made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer with a gate insulating layer interposed therebetween. The semiconductor layer into which impurities are implanted except under the gate is used as a source / drain. An interlayer insulating layer having an opening is formed on the drain, and a drain electrode and a source (signal line) electrode separated except on a scanning line are formed on the interlayer insulating layer including the opening, and the source ( A passivation insulating layer having a pair of first openings and a second opening on the drain electrode is formed at both ends of the signal line) electrode, and includes a second opening on the passivation insulating layer. And a connection line for connecting the divided source (signal line) electrode including the pair of first openings is formed.

According to this structure, at the intersection of the scanning line and the signal line, any one of the divided electrode lines is connected by a connection line formed on a stack of an interlayer insulating layer and a passivation insulating layer, and is connected to the scanning line. It is possible to reduce the parasitic capacitance between the signal lines.

According to a thirteenth aspect of the present invention, there is provided the semiconductor device for a display device according to the twelfth aspect, wherein the picture element electrode and the connection line are formed simultaneously by the same member.

According to this configuration, a semiconductor device for a display device can be obtained without increasing the cost since the number of manufacturing steps is not increased in forming any divided connection line, and the power consumption of the display device is reduced.

[0061]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 6 show equivalent circuit diagrams of display devices according to first to ninth embodiments of the present invention, and FIG. 7 is a plan view of a semiconductor device for a display device according to a tenth embodiment of the present invention. Is shown. Similarly, the twelfth embodiment is a plan view of an active substrate (semiconductor device for a display device) and a cross-sectional view of a manufacturing process taken along line AA 'in FIG. 8 and FIG. 9, respectively. Parts having the same functions as those of the conventional example are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the display device according to the first embodiment of the present invention, that is, as shown in the equivalent circuit diagram of FIG. 1, a switching device is provided at each intersection of the scanning line 11 and the signal line 12. The storage capacitor 15 and the gate of the driving insulated gate transistor 40 are connected to the insulated gate transistor 10 and the drain of the transistor.
A display medium 41 composed of a light emitting element is connected. The storage capacitor 15 is necessary to turn on the insulated gate transistor 40 for driving during the holding time (Japanese Patent Laid-Open No. 6-32).
No. 5869).

Reference numerals 42 and 43 denote power supply lines for supplying and recovering electric power for driving the display medium. The power supply line (+ potential) 42 common to the sources of all the insulated gate transistors 40 for driving is 42. And a conductive path formed on the insulating substrate. On the other hand, a feedback line (ground line, earth line) 43 for a current flowing through the light emitting element 41, which is formed of a conductive thin film layer formed on the organic EL light emitting thin film and is common to all the light emitting elements 41, is shown in Japanese Patent Application Laid-Open No. H8 (1996) -8. -234683).

It is a known technique that the scanning lines 11 and the signal lines 12 are insulated and separated by at least one or more types of insulating layers. The insulating layers constitute the switching or driving insulated gate transistor 10. Storage capacitance 15 in addition to the gate insulating layer, interlayer insulating layer, and passivation insulating layer
Are appropriately selected and used from the insulators and the like constituting the above. Usually, one kind is selected from these insulating layers, and generally, a gate insulating layer or an interlayer insulating layer of the insulated gate transistor 10 is employed.

Therefore, at the intersection 71 between the scanning line 11 and the signal line 12, an insulating layer at the intersection 71 is added to the gate insulating or interlayer insulating layer, for example, a passivation insulating layer is laminated and the scanning line 11 and the signal line 12 are stacked. 12 is divided, an opening is formed in the laminated insulating layer, and any divided wiring is connected by another conductive thin film (first connection line). As the other conductive thin film, for example, an electrode forming a storage capacitor or an electrode forming a display element can be selected.

As a result, at the intersection 71 between the scanning line 11 and the signal line 12, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection of the scanning line 11 and the signal line 12 is reduced.

In the second embodiment of the present invention, that is, in the display device according to the second aspect, as shown in the equivalent circuit diagram of FIG. At the intersection 72 between the power supply line 42 also serving as the source and the signal line 12 of the switching insulated gate transistor 10, an insulating layer at the intersection 72 is added to the gate insulating layer or the interlayer insulating layer, and a passivation insulating layer is laminated, for example. At the same time, one of the signal line 12 and the power supply line 42 is cut off, an opening is formed in the laminated insulating layer, and any of the split wirings is connected by another conductive thin film (second connection line). Is what you do.

As a result, at the intersection 72 between the signal line 12 and the power supply line 42, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection between the signal line 12 and the power supply line 42 is reduced.

As in the second embodiment, the power supply line 42 also serving as the source of the driving insulated gate transistor 40 is connected to the scanning line 11 of the switching insulated gate transistor 10.
When the display is arranged in parallel, when the screen size of the display device is large, the potential drop of the power line 42 becomes large.
If no bypass is provided in 2, the displayed image will be dark. Therefore, when the screen size is large, it is a general design matter to arrange the power supply line 42 in parallel with the signal line 12.

In the display device according to the third embodiment of the present invention, that is, as shown in the equivalent circuit diagram of FIG. 3, the driving insulated gate transistor 40 substantially parallel to the signal line 12 is provided. At the intersection 73 between the power supply line 42 also serving as the source and the scanning line 11 of the switching insulated gate transistor 10, an insulating layer at the intersection 73 is added to the gate insulation or interlayer insulation layer, and a passivation insulation layer is laminated, for example. At the same time, any one of the scanning line 11 and the power supply line 42 is divided, an opening is formed in the laminated insulating layer, and any divided wiring is connected by another conductive thin film (third connection line). Is what you do.

As a result, at the intersection 73 between the scanning line 11 and the power supply line 42, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection between the scanning line 11 and the power supply line 42 is reduced.

In the display device according to the fourth embodiment of the present invention, that is, not shown, a second or third connection line is added to the first connection line, although not shown. It is intended to reduce the load on the scanning lines and the signal lines to the maximum, thereby suppressing power consumption.

The display device according to the fifth embodiment of the present invention, that is, the display device described in claim 5, drives the display medium so that the switching insulated gate transistor can also serve as the driving insulated gate transistor. The present invention is applied to a display device with low power, and specifically, a liquid crystal display device using liquid crystal as a display medium corresponds thereto.

In the sixth embodiment of the present invention, that is, in the liquid crystal display device according to the sixth aspect, as shown in the equivalent circuit diagram of FIG. 4, accumulation between the preceding scanning line 11 and the pixel electrode is performed. In the active liquid crystal display device having the capacitance 15, the switching insulated gate transistor 10
At the intersection 71 between the scanning line 11 and the signal line 12, the insulating layer at the intersection 71 is added to the gate insulating layer or the interlayer insulating layer, for example, a passivation insulating layer is laminated, Any one of these is divided, and an opening is formed in the laminated insulating layer, and any of the divided wirings is connected by another conductive thin film (first connection line). For example, a transparent conductive layer or the like can be selected as an electrode forming a storage capacitor or an electrode forming a display element.

As a result, at the intersection 71 between the scanning line 11 and the signal line 12, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection of the scanning line 11 and the signal line 12 is reduced.

In the display device according to the seventh embodiment of the present invention, that is, as shown in the equivalent circuit diagram of FIG. 5, the storage capacitor 15 is connected between the storage capacitor line 16 and the pixel electrode. In the active type liquid crystal display device, the insulating layer at the intersection 72 between the signal line 12 and the storage capacitor line 16 substantially parallel to the scanning line 11 of the switching insulated gate transistor 10 is gate-insulated. For example, a passivation insulating layer is laminated in addition to the layer 4 or the interlayer insulating layer, and the signal line 12 and the storage capacitor line 16 are stacked.
Is formed, an opening is formed in the laminated insulating layer, and any of the divided wirings is connected by another conductive thin film (second connection line).

As a result, at the intersection 72 between the signal line 12 and the storage capacitance line 16, the insulating layer at the intersection becomes thicker, so that the parasitic capacitance caused by the intersection of the signal line 12 and the storage capacitance line 16 is reduced. I do.

According to the eighth embodiment of the present invention, that is, in the display device according to the eighth aspect, as shown in the equivalent circuit diagram of FIG. 6, the storage capacitor 15 is connected between the storage capacitor line 16 and the pixel electrode. In the active type liquid crystal display device having the structure (1), at the intersection 73 between the storage capacitor line 16 and the scanning line 11 substantially parallel to the signal line 12 of the switching insulated gate transistor 10, the insulating layer at the intersection 73 is subjected to the gate insulation. In addition to laminating a passivation insulating layer in addition to the layer or the interlayer insulating layer, any one of the scanning line 11 and the storage capacitor line 16 is divided, and any one of the divided insulating layers is formed by forming an opening in the laminated insulating layer. Are connected by another conductive thin film (third connection line).

As a result, at the intersection 73 between the scanning line 11 and the storage capacitance line 16, the insulating layer at the intersection is thickened, so that the parasitic capacitance caused by the intersection of the scanning line 11 and the storage capacitance line 16 is reduced. I do.

In the ninth embodiment of the present invention, that is, in the liquid crystal display device according to the ninth aspect, although not shown, a second or third connection layer is added to the first connection layer. Thus, the load on the scanning lines and signal lines is reduced as much as possible to suppress the power consumption.

FIG. 7 is a plan view of a tenth embodiment of the present invention, that is, a unit pixel of a semiconductor device for a display device according to the present invention. In manufacturing the transmission type liquid crystal display device by the streamlined five-mask process shown in FIG.
The signal line 12 is divided at the intersection with the scanning line 11 to form 12 ′, and the signal line 1 separated from the drain electrode 21 is formed.
A passivation insulating layer 37 having openings 62 and 61 at both ends of 2 ′ is formed, and the pixel electrode 22 including the opening 62 and the first connection line 70 including the pair of openings 61 are transparent. It is formed using a conductive layer.

According to this configuration, the scanning line 11 and the connection line 70 which is a part of the signal line intersect with each other via the insulating layer composed of the gate insulating layer 30 and the passivation insulating layer 37. Obviously, the parasitic capacitance decreases as the thickness of the insulating layer increases. Either an etch-stop type is used for the insulated gate transistor 10 and a flattening resin layer made of highly transparent acrylic resin is used for the passivation insulating layer 37, or the passivation insulating layer 37 is used.
When a flattening resin layer made of highly transparent acrylic resin is further laminated in addition to
m, the parasitic capacitance value is further reduced, and another parasitic capacitance, for example, the transparent conductive layer 14 on the color filter 9 opposed to the signal line 12 becomes the alignment film 20 and the liquid crystal 1.
7, the parasitic capacitance can be reduced to the same level as that of the parasitic capacitance constituted by the first and second elements.

As described in claim 11, there is no increase in the number of manufacturing steps, and the parasitic capacitance formed by the scanning lines 11 and the signal lines 12 can be greatly reduced only by changing the mask for manufacturing the active substrate 2. As a result, the effect of two birds per stone can be obtained for a liquid crystal panel for a mobile phone or the like, which has strict regulations on power consumption.

The connection line 70 has a length of at most about 10% when viewed from the entire length of the signal line 12, but when a conductive foreign substance is mixed in the liquid crystal cell, a so-called opposing short circuit is caused. Therefore, an appropriate insulating layer should preferably be formed on the surface of the substrate, but otherwise the display image is not particularly deteriorated under normal operating conditions. Is not allowed, it is reasonable to simultaneously form the transparent picture element electrode 22 (reflection electrode) and the connection line 70 with the transparent conductive layer (metal layer) as illustrated.

FIG. 8 is a plan view of a twelfth embodiment of the present invention, that is, a unit pixel of a semiconductor device for a display device according to the present invention. Different from the tenth embodiment, an insulated gate transistor 10 using so-called low-temperature polysilicon for a semiconductor layer is used for a switching element, and a manufacturing process cross section taken along line AA ′ of FIG. 8 with reference to FIG. The figure will be described.

First, although not shown, as described above, the insulating transparent substrate 2 having excellent transparency, heat resistance, and chemical resistance has a film thickness as an alkali blocking layer on one main surface of 1737 (trade name, manufactured by Corning Incorporated). Deposit SiO ₂ or SiN _x of about 0.3 μm. Thereafter, an amorphous silicon layer having a thickness of about 0.05 μm is deposited using a PCVD apparatus, and the content of hydrogen is reduced by heating. Then, the amorphous silicon layer is crystallized by irradiating an excimer laser. . Then, the so-called low-temperature polysilicon which has been crystallized as shown in FIG. 9A is selectively removed to leave 80 on the glass substrate 2 in an island shape.

Next, SiO ₂ having a thickness of about 0.1 μm at a substrate heating temperature of about 500 ° C. and a MoW alloy having a thickness of about 0.3 μm to be a gate metal layer are formed on the entire surface by CVD or TEOS-PCVD as the gate insulating layer 30. After the deposition, as shown in FIG. 9B, the gate 11 (and the common capacitance line 1
6) MoW and Si by fine processing technology corresponding to the pattern
The low temperature polysilicon 80 is exposed by etching with O ₂ . Then, although not shown, phosphorus is implanted as impurities into the low-temperature polysilicon 80 by ion implantation or ion irradiation using the gate 11 as a mask to form the source / drain 81 and 82 of the insulated gate transistor.

Subsequently, as shown in FIG. 9C, for example, SiO ₂ having a thickness of about 0.2 μm is applied as the interlayer insulating layer 83 by the above-mentioned manufacturing method, and is formed on the source / drain 81 and 82 by the fine processing technique. Are formed with a pair of openings 84 and 85.

Subsequently, as shown in FIG. 9D, for example, a film having a thickness of 0.1 / 0.3 / 0.1 μm
After a layer of Ti / Al / Ti or the like having a thickness of about m is deposited by using a film forming apparatus such as sputtering, the source (signal line) / drain wiring 12 '' including a pair of openings 84 and 85 by a fine processing technique. , 21. At this time, the signal line 12 ″ is divided at the intersection with the scanning line 11, as shown in FIG.

Further, as shown in FIG. 9E, as the passivation insulating layer 37, for example, a SiO.sub.
_{2 is applied} by the above-described manufacturing method, and the opening 62 and the divided signal line 1 are formed on the drain electrode 21 by a fine processing technique.
A pair of openings 61 is formed on both ends of 2 ″.

Finally, ITO, which is a transparent conductive layer having a thickness of about 0.1 to 0.2 μm, is deposited by using a film forming apparatus such as sputtering, and then an opening 62 is formed on the passivation insulating layer 37 by a fine processing technique. The pixel electrode 22 and the pair of openings 61
And the connection line 70 is selectively formed to complete the semiconductor device for a display device as shown in FIG. The semiconductor device for a display device and a color filter are attached to each other to form a liquid crystal panel to obtain a liquid crystal display device.

According to the above configuration, the scanning line 11 and the first connection line 70 which is a part of the signal line intersect with each other in the insulating layer formed by stacking the interlayer insulating layer 83 and the passivation insulating layer 37. It is apparent that the parasitic capacitance is reduced by the increase in the thickness of the insulating layer.

[0093]

As described above, according to the display device of the present invention, at the intersection between the electrode line of the scanning line or the signal line and another power supply line, or at the intersection between the scanning line and the signal line. ,
Any of the intersecting wirings is cut off, and a connection line connecting the separated wirings through the gate insulating layer or interlayer insulating layer and another type of insulating layer including the passivation insulating layer is formed, so that the crossing is performed. The parasitic capacitance in the section is reduced. As a result, power consumption of a circuit for driving the scanning lines and the signal lines can be reduced, which is high in terms of energy saving.

The reduction in power consumption during driving also reduces the power consumption during standby.
The power consumption reduction according to the present invention is an extremely useful technology for a battery-powered portable information terminal device such as A.

Further, since two types of insulating layers are laminated at the intersection, even if a pinhole or a defective portion occurs in any one of the insulating layers for some reason, the other insulating layer fills it. Therefore, the secondary effect of reducing the interlayer short-circuit at the intersection and improving the yield can be a notable feature from the viewpoint of production.

In the active matrix display device according to the present invention, as described above, the semiconductor material forming the insulated gate transistor as the switching element is amorphous silicon, microcrystalline silicon, (low-temperature) polycrystalline silicon, or the like. It is clear that there is no restriction on the material. In addition, there is no problem in applying the FS (field sequential) type liquid crystal display device at all. Which of the intersecting electrode lines is to be divided depends on whether or not there is an insulating layer on the connection line, or an increase in the resistance value due to the introduction of the connection line, since the divided electrode line is located in an upper layer on the substrate. It goes without saying that it is better to select the best one considering the effect.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a display device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a display device according to a second embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a display device according to a third embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a liquid crystal display device according to an eighth embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for a display device according to a tenth embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor device for a display device according to a twelfth embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing process of a semiconductor device for a display device according to a twelfth embodiment of the present invention.

FIG. 10 is a perspective view showing a mounted state of a liquid crystal panel.

FIG. 11 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 12 is a sectional view of a main part of a liquid crystal panel.

FIG. 13 is a plan view of a conventional active substrate.

FIG. 14 is a sectional view showing a manufacturing process of a conventional active substrate.

FIG. 15 is a plan view of a streamlined active substrate.

FIG. 16 is a cross-sectional view of a manufacturing process of a rationalized active substrate.

[Explanation of symbols]

Reference Signs List 1 liquid crystal image display device (liquid crystal panel) 2 active substrate (insulating substrate, glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 terminal electrode 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line ( (Gate) 12 (12 ′) signal line (source electrode) 14 counter electrode 16 storage capacity line 17 liquid crystal 21 drain electrode 22 (transparent conductive) pixel electrode 30 gate insulating layer (first SiN _x layer) 31 impurity -Free amorphous silicon layer 32 (which is an insulating layer that protects the channel)
N _x layer 33 Amorphous silicon layer containing impurities 34 Heat resistant metal layer 35 Low resistance metal layer (AL) 36 Intermediate conductive layer 37 Passivation insulating layer 42, 43 Power supply line and recovery (feedback) line for driving the display medium 61 Opening (on the disconnected signal line 12 ') 62 Opening (on the drain electrode) 70 Connection line (connecting the disconnected signal line 12') 71 Intersection between the scanning line and the signal line 72 Signal Intersection between line and power line (storage capacitor line) 73 Intersection between scan line and power line (storage capacitor line) 83 Interlayer insulating layer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 619A F-term (Reference) 2H092 HA04 HA06 HA12 JA34 JB56 JB57 KA05 KA12 KB24 KB25 MA05 MA08 NA23 NA26 NA27 NA28 NA29 PA11 PA13 QA07 5C094 AA22 BA03 BA43 CA19 DA15 EA04 EA07 5F110 AA02 AA09 DD02 DD13 DD14 EE06 EE37 FF02 FF29 FF30 GG02 GG13 GG45 HJ01 HJ13 HL03 HL04 HL12 HL23 HM19 NN03 NN04 NN23QNN PP

Claims (13)

[Claims] 1. A switching circuit comprising at least a switching insulated gate transistor, a scanning line also serving as a gate and a signal line also serving as a source, a storage capacitor connected to a drain, and a drive of the switching insulated gate transistor. A display device comprising an insulating substrate and a display medium in which unit picture elements each having an insulated gate transistor for driving and a display electrode connected to the drain of the driving insulated gate transistor are arranged in a two-dimensional matrix; Either the scan line or the signal line is divided at the intersection of the line and the signal line, and the divided scan line or the signal line is separated through a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer. A display device, wherein a first connection line for connecting any of the signal lines is formed. 2. A method according to claim 1, wherein at least one switching insulated gate transistor is provided on one main surface, a scanning line also serving as a gate of the switching insulated gate transistor, a signal line also serving as a source, a storage capacitor connected to a drain, and a drive. A display device comprising an insulating substrate and a display medium in which unit picture elements each having an insulated gate transistor for driving and a display electrode connected to the drain of the driving insulated gate transistor are arranged in a two-dimensional matrix; Either the power supply line or the signal line is cut off at the intersection of the power supply line and the signal line, which also serves as the source of the driving insulated gate transistor substantially parallel to the line, and the gate insulating layer or interlayer insulating layer of the switching insulated gate transistor A second connection line for connecting the divided power supply line or signal line via the other and the other insulating layer is formed. Display apparatus characterized by being. 3. A transistor having at least a switching insulated gate transistor on one main surface, a scanning line also serving as a gate and a signal line also serving as a source of the switching insulated gate transistor, a storage capacitor connected to a drain, A display device comprising an insulating substrate and a display medium in which unit picture elements each having an insulating gate type transistor for use and a display electrode connected to the drain of the driving insulating gate type transistor are arranged in a two-dimensional matrix, Either the power supply line or the scanning line is divided at the intersection of the power supply line and the scanning line, which also serves as the source of the driving insulated gate transistor substantially parallel to the line, and the gate insulating layer or interlayer insulating layer of the switching insulated gate transistor A third connection line for connecting the divided power supply line or the scanning line via the second power supply line and another insulating layer is formed. Display apparatus characterized by being. 4. The display device according to claim 1, further comprising a second or third connection line in addition to the first connection line. 5. The display device according to claim 1, wherein the switching insulated gate transistor and the driving insulated gate transistor are the same. 6. A unit having at least one insulated gate transistor on one principal surface, a scanning line also serving as a gate and a signal line also serving as a source of the switching insulated gate transistor, and a picture element electrode connected to a drain. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line and a signal line Either the scanning line or the signal line is cut off at the intersection, and either the scanning line or the signal line is connected via a gate insulating layer or an interlayer insulating layer of the insulated gate transistor and another insulating layer. A liquid crystal display device, wherein a first connection line is formed. 7. A unit having, on one main surface, at least an insulated gate transistor, a scanning line also serving as a gate and a signal line also serving as a source of the switching insulated gate transistor, and a picture element electrode connected to a drain. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a common liquid crystal substantially parallel to a scanning line is provided. Either the common capacitance line or the signal line is divided at the intersection of the capacitance line and the signal line, and the divided common capacitance line is separated via the gate insulating layer or interlayer insulating layer of the insulated gate transistor and another insulating layer. Alternatively, a liquid crystal display device is provided with a second connection line for connecting any of the signal lines. 8. A unit having at least an insulated gate transistor on one principal surface, a scanning line also serving as a gate and a signal line also serving as a source of the switching insulated gate transistor, and a pixel electrode connected to a drain. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter opposed to the insulating substrate, a common liquid crystal substantially parallel to a signal line is provided. Either the common capacitance line or the scanning line is divided at the intersection of the capacitance line and the scanning line, and the divided common capacitance line is separated via the gate insulating layer or interlayer insulating layer of the insulated gate transistor and another insulating layer Alternatively, a liquid crystal display device is provided with a third connection line for connecting one of the scan lines. 9. The liquid crystal display device according to claim 1, further comprising a second or third connection line in addition to the first connection line. 10. A scanning line comprising one or more metal layers and also serving as a gate of an insulated gate transistor is formed on one main surface of an insulating substrate, and impurities are formed on the gate via one or more gate insulating layers. Is formed in an island shape, and the second semiconductor layer is formed on the first semiconductor layer so as to overlap with the gate and contain impurities, and the second semiconductor layer is used as a source / drain. A drain electrode and a source (signal line) electrode separated except on the scanning line are formed of one or more metal layers, and a pair of first electrodes are provided at both ends of the separated source (signal line) electrode. A passivation insulating layer having an opening and a second opening is formed on the drain electrode. The pixel electrode and the pair of first openings including the second opening are formed on the passivation insulating layer. Including said divided Source (signal line) display device for a semiconductor device characterized by a connecting line for connecting the electrodes is formed. 11. The semiconductor device for a display device according to claim 10, wherein the picture element electrode and the connection line are simultaneously formed of the same member. 12. An island-shaped semiconductor layer is formed on one main surface of an insulating substrate, and a gate made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer via a gate insulating layer; A semiconductor layer into which impurities are implanted except under the gate is used as a source / drain, an interlayer insulating layer having an opening is formed on the source / drain, and a drain electrode is formed on the interlayer insulating layer including the opening. A source (signal line) electrode separated except on the scanning line is formed, and a pair of first openings and a second opening on the drain electrode at both ends of the source (signal line) electrode. Is formed on the passivation insulating layer, and the picture element electrode including the second opening and the divided source (signal line) electrode including the pair of first openings are connected to the passivation insulating layer. Connection line and formed A semiconductor device for a display device, comprising: 13. The semiconductor device for a display device according to claim 12, wherein the picture element electrode and the connection line are formed simultaneously by the same member.