JP2002190603A - Liquid crystal image display and method for manufacturing semiconductor device for image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that overlap capacitance between a source and a drain is large and varies within the surface, and causes flickers and crosstalks in a high resolution device having a large display, since the positional relation between a gate and the source/drain is determined not by self alignment but by mask alignment at exposure, in the conventional TFT, regardless of whether it is a channel etch type or an etch stop type. SOLUTION: A self aligned TFT is used as a basic component. In the TFT, a gate metal/gate insulating layer, a semiconductor layer, a protective insulating layer, and even a lift-off layer are formed by collective lithography, an organic insulating layer is formed on the side surface of a gate, a resist pattern is retreated, and a source/drain region is formed. Rationalization is enabled, and the number of processes is reduced by introducing a low-temperature technique where an organic insulating layer is formed on a source/drain wiring and a passivation insulating layer is made unnecessary; and a technique where an organic insulating layer is formed on an exposed scanning line by using a process for forming a source/drain electrode and a process for forming an aperture part on the insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a color image display function, and more particularly to an active liquid crystal display.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of large quantities of television images and various image display devices on a commercial basis on liquid crystal panels with a diagonal of 5 to 50 cm. ing. Further, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0003] These liquid crystal image display devices (liquid crystal panels)
Represents 200 to 1200 scanning lines and 200 to 16 signal lines
A matrix organization of about 00 lines is generally used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 15 shows a state of mounting on a liquid crystal panel.
A semiconductor integrated circuit chip 3 for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, a group of scanning line terminal electrodes 6 formed on a glass substrate 2, is connected using a conductive adhesive. COG (Chip-On-Glass) method, for example, a T based on a polyimide resin thin film and having gold or solder plated copper foil terminals (not shown)
TCP (Tape-Car) for fixing the CP film 4 to the terminal electrodes 5 of the signal lines by pressing with a suitable adhesive containing a conductive medium.
An electric signal is supplied to the image display unit by a mounting means such as a carrier-package method. Here, for the sake of convenience, two mounting methods are shown simultaneously, but in practice, either method is appropriately selected.

[0005] Reference numeral 8 denotes a wiring path for connecting the image display portion, which is located substantially at the center of the liquid crystal panel 1, to the terminal electrodes 5 and 6 of the signal lines and the scanning lines. It does not need to be made of a conductive material. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface.

FIG. 16 shows an equivalent circuit diagram of an active type liquid crystal panel in which insulated gate type transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 15).
Is a scanning line, 12 (7 in FIG. 15) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the common electrodes 14 common to all the liquid crystal cells 13 drawn by dotted lines are formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

FIG. 17 is a sectional view of a main part of an image display section of a liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a spacer material (not shown) such as resin fibers or beads. Is formed at a predetermined distance of about several μm, and the gap (gap) is sealed at the periphery of the glass substrate 9 with a sealing material made of an organic resin and a sealing material (neither is shown). It is a closed space, and the liquid crystal 17 is filled in this closed space.

In order to realize a color display, an organic thin film having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the glass substrate 9. Since a color display function is provided, in this case, the glass substrate 9 is also called a color filter (Color
The Filter abbreviation is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element.
At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials.
Usually, two polarizing plates 19 are required. Although not shown, a rear light source is arranged as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described later in detail. Colored layers 1 adjacent on color filter 9
8 and a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technology fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (referred to as an etch stop type). FIG. 18 is a plan view of a unit picture element of an active substrate (semiconductor device for an image display device) constituting a conventional liquid crystal panel. FIG. Will be briefly described below. The projection 50 formed on the scanning line 11
A region 51 where the pixel electrode 22 and the pixel electrode 22 overlap with each other with a gate insulating layer interposed therebetween (a hatched portion inclined downward to the right) forms the storage capacitor 15, but a detailed description thereof is omitted here.

First, as shown in FIG. 19A, an insulating substrate having high heat resistance, chemical resistance, and transparency has a thickness of 0.5 to 0.5 mm.
A glass substrate 2 having a thickness of about 1.1 mm, for example, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a product 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo, or the like, or an alloy or silicide thereof, a gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, AL (aluminum) is used as the material of the scanning line. At present, it is also a general technique to laminate with Cr, Ta, Mo or silicide thereof, or to add an oxide layer (AL2O3) to the surface of AL by anodic oxidation. That is, the scanning line 11 is formed of one or more metal layers.

Next, as shown in FIG. 19B, a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (Plasma Thievey) apparatus, and almost all impurities are removed. Not including first amorphous silicon (a-Si) to be the channel of the insulated gate transistor
A second SiNx layer serving as an insulating layer for protecting the layer and the channel and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32.

As a know-how technique, when forming a gate insulating layer, another type of insulating layer (for example, TaOx or SiO2) is used.
Etc. or laminated with AL2O3) mentioned above, or S
In many cases, yield improvement measures such as providing an iNx layer in two steps and providing a cleaning step in the middle thereof are performed, and the gate insulating layer is not limited to one type or a single layer.

Subsequently, the second amorphous SiNx layer on the gate 11 is selectively left narrower than the gate 11 by a fine processing technique to form 32 ', exposing the first amorphous silicon layer 31, and the PCVD apparatus is also used. A second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface with a thickness of, for example, about 0.05 μm, and then only on the vicinity of the gate 11 as shown in FIG. The gate insulating layer 30 is exposed while the first amorphous silicon layer 31 and the second amorphous silicon layer 33 are left in island shapes 31 'and 33'.

Subsequently, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as PT, and the pixel electrode 22 is formed on the gate insulating layer 30 by a fine processing technique. Formed selectively.

Further, as shown in FIG. 19 (e), a selective opening 63 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display section necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 19 (f), a thin film layer 34 of, for example, Ti, Cr, Mo, or the like is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by a microfabrication technique. A drain electrode 21 of the transistor and a source electrode 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 'between the source and drain electrodes is removed to expose the second SiNx layer 32', and the other regions are formed. Then, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the second SiNx layer 32 'which is a protective layer of the channel is present and the etching of the second amorphous silicon layer 33' is automatically completed. is there.

The source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 (several μm) so that the insulated gate transistor does not have an offset structure.
Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the mask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about. In addition, at the periphery of the image display unit, including the opening 63 on the scanning line 11, the signal line 12 and the scanning line side terminal electrode 6 simultaneously with the signal line 12, or the wiring connecting the scanning line 11 and the scanning line side terminal electrode 6. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, a SiNx layer having a thickness of about 0.3 to 0.7 μm is applied to the entire surface of the glass substrate 2 by using a PCVD apparatus in the same manner as the gate insulating layer 30 to form a passivation insulating layer. 37, an opening 38 is formed on the pixel electrode 22 as shown in FIG.
Are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines, and most of the terminal electrodes are also exposed.

When the wiring resistance of the signal line 12 does not matter, the low-resistance wiring layer 35 made of AL is not always necessary. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is, firstly, to prevent a decrease in the effective voltage applied to the liquid crystal cell, and secondly, because the film quality of the passivation insulating layer 37 is generally poor, This is for avoiding the accumulation of the electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film forming temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The manufacturing process of the active substrate described above requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for liquid crystal panel manufacturers in order to realize lower prices for liquid crystal panels and respond to further increases in demand. I've been.

FIG. 20 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 21 is a cross-sectional view taken along the line AA 'of FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. A region 52 where the storage capacitance line 16 and the drain electrode 21 overlap each other with the gate insulating layer 30 interposed therebetween (a hatched portion falling to the right) forms the storage capacitance 15, but a detailed description thereof is omitted here. .

First, similarly to the conventional example, as shown in FIG. 21A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT. And a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by a fine processing technique.

Next, as shown in FIG. 21B, a SiNx layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD apparatus, and a first layer serving as a channel of an insulated gate transistor containing almost no impurities. An amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are sequentially formed in a thickness of, for example, about 0.3-0.2-0.05 μm. 30, 31, and 33 are attached.

Then, as shown in FIG. 21C, the gate insulating layer 30 is formed on the gate 11 by leaving the semiconductor layers composed of the first and second amorphous silicon layers in the form of islands 31 'and 33'. Exposed.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as PT, for example, a Ti thin film layer 34 as a heat-resistant metal layer with a thickness of about 0.1 μm, an AL thin film layer 35 with a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm-thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer, and the drain electrode 21 of the insulated gate transistor and the source electrode 12 also serving as a signal line are selectively formed by a fine processing technique. This selective patterning is
Using the photosensitive resin pattern used for forming the drain wiring as a mask, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', and the first amorphous silicon layer 31' Are sequentially etched, and the first amorphous silicon layer 31 'is etched by leaving about 0.05 to 0.1 .mu.m, so that it is called a channel etch.

After the photosensitive resin pattern is further removed, as shown in FIG. 21E, a transparent insulating layer is formed on the entire surface of the glass substrate 2 by PCVD in the same manner as the gate insulating layer.
A passivation insulating layer 37 is formed by depositing a SiNx layer having a thickness of about 0.3 μm using an apparatus, and an opening 63 is formed on the drain electrode 21 and an opening 63 is formed on a position where the terminal electrode 6 of the scanning line 11 is formed. To form the drain electrode 21 and the scanning line 1
Expose a portion of 1. Although not shown, an opening 64 is also formed on the position where the terminal electrode 5 of the signal line is formed to expose a part of the signal line 12.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as Then, the picture element electrode 22 is selectively formed to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 63 may be used as the terminal electrode 6, and the terminal electrode 6 ′ made of ITO is selectively formed on the passivation insulating layer 37 including the opening 63 as shown in the figure. It may be formed.

As described above, the five-mask process is one time in the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the process of forming an opening (contact) to a scanning line and the process of forming an opening to a pixel electrode and the process of forming a contact, which were required twice, have been streamlined once. Can be. In addition, since the pixel electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a transparent resin thin film, for example, for 1.5 times.
If the pixel electrode 22 is formed thicker than μm, even if the pixel electrode 22 overlaps the scanning line 11 or the signal line 12, interference due to capacitance is small and deterioration of image quality can be avoided.
Can be formed large and the aperture ratio can be improved.

[0031]

As described above, the source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 so that the insulated gate transistor does not have an offset structure. Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better.
It is about μm. Rather, the thickness is preferably about 3 μm from the viewpoint of manufacturing margin during mass production.

In the case of the etch stop type, since the gate and the source / drain electrodes are aligned with an etch stop layer interposed therebetween, an overlap capacitance of two times of alignment accuracy is required. Although it cannot be obtained, these overlapping capacitances fluctuate within the glass substrate (although at most 1 μm) due to the optical distortion of the lens or mirror of the exposure apparatus, so that flickering, printing, and display occur on a large screen and high definition device. It is inevitable from image quality problems such as spots.

Prior examples in which source / drain electrodes can be formed in a self-aligned manner with the gate are disclosed in JP-A-62-205664 and JP-A-63-168052. Then, an etch stop layer slightly thinner (at most 1 μm) than the gate is formed on the gate, and the source / drain is formed by irradiating or implanting impurities with the etch stop layer as a mask. For the source / drain formed in a self-aligned manner, the former is incomplete and cannot be formed in a self-aligned manner up to the source / drain electrodes. When a metal having a melting point, for example, Cr is deposited and heated, silicide is formed on the source / drain. Therefore, if Cr on the etch stop layer is removed with an etching solution, a source / silicide having a low resistance value is formed.
The drain electrode is formed in a self-aligned manner.

However, the back exposure stage naturally requires a highly transparent quartz or glass plate, and a warp or undulation of the glass substrate requires a vacuum suction mechanism to the stage. Whether it can meet the requirements and be able to be mass-produced stably is still opaque compared to the conventional metallic stage. There is a problem that deterioration of electrical characteristics is inevitable due to heat treatment (200 ° C. or higher).

In general, a passivation insulating layer is employed for passivating the source / drain wirings.
However, even if the film formation is performed at a low temperature of several tens of degrees Celsius or lower and 250 degrees Celsius or less, it is unavoidable that a certain degree of influence is unavoidable.
A reduction of about 0% is inevitable. The reduction in the current driving capability of the insulated gate transistor becomes a major obstacle to increase the wiring resistance in order to obtain a large screen and high definition liquid crystal panel.

In addition, in the case of a channel-etch type insulated gate transistor, the first region containing no impurity in the channel region is used.
The amorphous silicon layer must be thicker (typically 0.2 μm
If not, the transistor characteristics tend to be uneven due to the in-plane uniformity of the glass substrate. This greatly affects the operation rate of PCVD and the state of particle generation, and is very important from the viewpoint of production cost.

The present invention has been made in view of the above situation, and has developed a new self-aligned source / drain formation technique without using backside exposure, and also has a low-temperature passivation to compensate for the low heat resistance of an insulated gate transistor. It is an object of the present invention to solve the above-mentioned problems by formation. As already mentioned, it is necessary to pursue a further reduction in the number of manufacturing steps in order to realize a reduction in the price of the liquid crystal panel and to respond to an increase in demand.

[0038]

According to the present invention, first, a resist pattern at the time of gate formation is receded to expose an amorphous silicon layer containing no impurities on a gate end portion. A source / drain is formed by ion-implanting or irradiating an impurity into the silicon layer, and a lift-off layer is also used so that the source / drain and the source / drain electrode are formed in a self-aligned manner. Then, the passivation that can be formed at a low temperature of 200 ° C. or less using an organic insulating layer is realized by electrodeposition. Japanese Patent Application Laid-Open No. -216129 is intended to realize a streamlined process and a low temperature in a manner similar to the anodic oxidation technique of forming an insulating layer on the surface of a source / drain wiring made of aluminum disclosed in JP-A-216129. Further, by forming an organic insulating layer on the exposed scanning line to further reduce the number of steps, it is possible to streamline the step of forming source / drain wiring and the step of forming an opening in the gate insulating layer.

The insulated gate transistor according to claim 1, wherein at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface is used as a gate, and a gate insulating layer is formed on the gate. A semiconductor layer that is narrower than the gate and contains no impurities and a pair of semiconductor layers that contain impurities in contact with the semiconductor layer are formed in a self-aligned manner, and a protective insulating layer is formed over the semiconductor layer that does not contain impurities. A metal layer formed on the pair of semiconductor layers is used as a source / drain electrode, and an organic insulating layer is provided on the source / drain electrode.

With this configuration, in the insulated gate transistor, the source / drain electrodes are formed in a self-aligned manner with respect to the gate, and the parasitic capacitance between the gate and the source / drain is reduced to a fraction of the conventional value.

According to a second aspect of the present invention, in the liquid crystal image display device, a unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor is two-dimensional. In a liquid crystal image display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, at least one layer is formed on one main surface of the insulating substrate. A scanning line which has a gate insulating layer on its surface and an organic insulating layer on its side and also serves as a gate of an insulated gate transistor is formed, and has a width greater than that of the gate via the gate insulating layer over the gate. A thin semiconductor layer containing no impurities and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner, and a protective insulating layer is formed on the semiconductor layer containing no impurities. Is formed on the pair of semiconductor layers and the insulating substrate, a drain electrode made of one or more metal layers and a source (signal line) electrode are formed except on a scanning line, and the drain electrode is formed on the insulating substrate. A connection layer that connects the pixel electrode and the divided source (signal line) electrode, and an organic insulating layer is formed on the surface of the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode; It is characterized by having. With this configuration, a self-aligned insulated gate transistor is obtained, and the parasitic capacitance between the gate and the source / drain is reduced to a fraction of that in the related art. The image display device not only reduces flicker and crosstalk but also reduces driving power. Further, passivation of the source / drain electrodes can be formed at a low temperature, and the heat resistance of the insulated gate transistor is reduced.

A liquid crystal image display device according to a third aspect of the present invention is also provided with one or more metal layers on one main surface of an insulating substrate, having a gate insulating layer on its surface and an organic insulating layer on its side surfaces. A scanning line also serving as a gate of the gate type transistor and an auxiliary signal line having openings at both ends are formed, and a semiconductor layer narrower than the gate and containing no impurities is formed on the gate via a gate insulating layer; A pair of semiconductor layers containing impurities is formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurities, and one or more layers are formed on the pair of semiconductor layers and the insulating substrate. A source / drain electrode made of a metal layer is formed, and a connection layer for connecting a pixel electrode including the drain electrode and an auxiliary signal line including the opening and the source electrode is formed on an insulating substrate. And Wherein the organic insulating layer on the surface of the drain electrode, except for the source electrode and the pixel electrode except for the serial connection layer is formed.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also lowering of the temperature of the process and lowering of the resistance of the signal line can be promoted without increasing the number of film forming steps. Production becomes possible.

A liquid crystal image display device according to a fourth aspect of the present invention comprises an insulating substrate having one or more metal layers on one main surface, a gate insulating layer on the surface thereof, and an organic insulating layer on the side surfaces thereof. A scanning line also serving as a gate of the gate transistor is formed. A semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed on the gate. A protective insulating layer is formed on the semiconductor layer which is formed in a consistent manner and does not contain the impurity, and a source / drain electrode made of a metal layer is formed on the pair of semiconductor layers and on the insulating substrate. A signal line including one or more metal layers including the source electrode is formed, a picture element electrode including the drain electrode is formed on an insulating substrate, and the source electrode and the picture element excluding the signal line and the signal line are formed. Electric Wherein the organic insulating layer is formed on the surface of the drain electrode, except for.

With this configuration, not only a self-aligned insulated gate transistor can be obtained, but also lower temperatures in the process and lower resistance of the signal lines are promoted, and fabrication of a large-screen device is facilitated.

A liquid crystal image display device according to a fifth aspect of the present invention comprises one or more metal layers on one main surface of the insulating substrate and has a surface except for between channels and below a source (signal line) / drain electrode. A scan line having an organic insulating layer and also serving as a gate of an insulated gate transistor is formed, and a pair of a semiconductor layer which is narrower than the gate and contains no impurities through the gate insulating layer over the gate and a pair of the semiconductor layers is in contact with the semiconductor layer. A semiconductor layer containing impurities is formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurities, and a drain electrode and a scan line made of a metal layer are formed on the pair of semiconductor layers and the insulating substrate. Excluding the above, a source (signal line) electrode is formed, and a connection layer connecting the picture element electrode including the drain electrode and the divided source (signal line) electrode is formed on an insulating substrate; Wherein the organic insulating layer is formed on the surface of the drain electrode, except for the source electrode and the pixel electrode excluding.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also lowering and rationalization of the process are promoted, and reduction in manufacturing cost is promoted. The liquid crystal image display device according to claim 6, further comprising one or more metal layers on one main surface of the insulating substrate and having an organic insulating layer on the surface except between the channels and below the source / drain electrodes. A scanning line also serving as the gate of the gate type transistor and an auxiliary signal line having an organic insulating layer on its surface except for both end portions are formed, and the impurity is thinner than the gate via the gate insulating layer on the gate and contains no impurities. A semiconductor layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode made of a metal layer capable of being anodized is formed on the insulating substrate. A connecting layer connection to is formed, characterized in that the organic insulating layer on the surface of the drain electrode, except for the source electrode and the pixel electrode except for the connection layer is formed.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also a lowering of the signal line resistance can be realized without increasing the film forming process in addition to lowering and rationalizing the process. Large screen devices can be manufactured.

A liquid crystal display according to a seventh aspect of the present invention is the liquid crystal image display device, wherein one or more metal layers are also formed on one main surface of the insulating substrate, and an organic insulating layer is formed on the surface except between the channels and below the source / drain electrodes. A scanning line which also serves as a gate of the insulated gate transistor is formed, and a semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer over the gate and a semiconductor which contains a pair of impurities in contact with the semiconductor layer; A layer is formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurity; source and drain electrodes made of a metal layer are formed on the pair of semiconductor layers and on the insulating substrate; A signal line composed of one or more metal layers including the source electrode is formed on the substrate, a picture element electrode including the drain electrode is formed on the insulating substrate, and a signal line excluding the signal line and the signal line is formed. Wherein the organic insulating layer is formed on the surface of the drain electrode, except for the scan electrode and the pixel electrode.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reduced in addition to the lowering and rationalization of the process, and the fabrication of a large-screen device is facilitated. .

According to a eighth aspect of the present invention, there is provided the method for manufacturing a liquid crystal image display device according to the second aspect, wherein one or more first metal layers are deposited on one principal surface of the insulating substrate; Exposing a lift-off layer after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. And a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer, a lift-off layer using the photosensitive resin pattern as a mask, a protective insulating layer, Sequentially etching the first semiconductor layer, the gate insulating layer and the first metal layer; reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer; Resin pattern and mask A step of exposing the first semiconductor layer partially sequentially etched and liftoff layer and the protective insulating layer Te,
Forming an organic insulating layer on a side surface of the scan line, implanting an impurity into a first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, Selectively removing the second metal layer on the lift-off layer together with the removal of the gate electrode; Forming a source (signal line) electrode selectively, applying a conductive thin film, and including a picture element electrode including the drain electrode and the source (signal line) electrode on an insulating substrate. Selectively forming a connection layer for connecting the separated source (signal line) electrode, and protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. While irradiating light Characterized by a step of forming an organic insulating layer to the drain electrode, except for the source electrode and the pixel electrode excluding the connection layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be reduced in temperature and the heat resistance of the insulated gate transistor can be reduced.

A ninth aspect is a liquid crystal image display according to the third aspect.
A method for manufacturing a device, wherein one layer is formed on one main surface on an insulating substrate.
The step of applying the first metal layer, and the step of
One or more layers except for a part of the first metal layer in the peripheral portion.
Insulation layer and first semiconductor layer containing no impurity and protective insulation
Depositing a lift-off layer after sequentially depositing the layers,
The gate of an insulated gate transistor on the lift-off layer
A photosensitive resin pattern corresponding to the scanning line and the auxiliary signal line
Selectively forming a turn, and the photosensitive resin pattern.
Lift-off layer, protective insulating layer, first
Etching semiconductor layer, gate insulating layer and first metal layer sequentially
And removing the photosensitive resin pattern to reduce the film thickness.
Partially exposing the soft-off layer, and reducing the film thickness.
With the lift-off layer using the photosensitive resin pattern as a mask.
And the first insulating layer is partially etched to partially expose the first semiconductor layer.
Forming an organic insulating layer on the side surface of the scanning line.
And removing impurities using the lift-off layer as a mask.
Implanting into one semiconductor layer; and
An opening is formed on the scanning line and at both ends of the auxiliary signal line, and the opening is formed.
Lift-off layer, protective insulating layer and impurity-free
Selectively removing the conductor layer and the gate insulating layer;
Depositing a metal layer, and removing the lift-off layer.
Both selectively remove the second metal layer on the lift-off layer
And an insulating group on the impurity-implanted semiconductor layer.
A source / drain electrode composed of a second metal layer on the plate
Step of selectively forming and step of depositing a conductive thin film
And a pixel electrode including the drain electrode on an insulating substrate.
Auxiliary signal divided including the opening and the source electrode
Selectively forming a connection layer for connecting the signal lines;
Photosensitive tree used for selective patterning of picture element electrodes
Use the grease pattern as a mask to protect the pixel electrodes and shine light.
While excluding the source and pixel electrodes except for the connection layer.
Forming an organic insulating layer on the rain electrode.
And features.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the resistance of the signal line can be reliably reduced without lowering the temperature of the process and increasing the number of film forming steps. Can be manufactured.

A tenth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the fourth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, and depositing a second metal layer;
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selectively forming a pair of source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Forming an opening on a scanning line in a region outside the image display unit and selectively removing a gate insulating layer on the scanning line; applying one or more third metal layers; Selectively forming a signal line composed of a third metal layer including: forming a third metal layer; applying a conductive thin film; and selectively forming a pixel electrode including the drain electrode on an insulating substrate. Excluding the signal line and the signal line while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask, excluding the source electrode and the pixel electrode Forming an organic insulating layer on the drain electrode. Characterized in that it.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, so that a large-screen device can be easily manufactured.

(11) The method for manufacturing a liquid crystal image display device according to (4), wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, and depositing a second metal layer;
With the removal of the lift-off layer, a second
Selectively removing the metal layer of step (a), and selectively forming a pair of source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Depositing one or more third metal layers;
Selectively forming a signal line made of a third metal layer including the source electrode; and forming an opening on a scanning line in a region outside the image display unit and selectively removing a gate insulating layer on the scanning line. , A step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of selectively forming a pixel electrode on the insulating substrate. Forming an organic insulating layer on the signal line, the source electrode excluding the signal line, and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the conductive resin pattern as a mask. And

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, and a large-screen device can be easily manufactured.

A twelfth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the fifth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, and depositing a second metal layer;
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selecting a drain electrode made of a second metal layer and a separated source (signal line) electrode on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Exposing the scanning lines except between the source and drain electrodes and under the source and drain electrodes, and forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit, A step of applying a conductive thin film, and a step of selectively forming a connection layer for connecting a divided source electrode including the pixel electrode and the source electrode including the drain electrode on the insulating substrate, The photosensitive resin pattern used for the selective pattern formation of the picture element electrode is used as a mask to protect the picture element electrode while irradiating light while irradiating light to the source electrode excluding the connection layer and the drain electrode excluding the picture element electrode. Layers Characterized by a step of forming.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also, in addition to lowering the temperature of the process, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. A device can be manufactured with a single photomask.

A thirteenth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the sixth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line and an auxiliary signal line also serving as a gate of an insulated gate transistor on the lift-off layer, a lift-off layer using the photosensitive resin pattern as a mask, a protective insulating layer, Sequentially etching the first semiconductor layer, the gate insulating layer and the first metal layer; reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer; Etching a lift-off layer and a protective insulating layer sequentially using the conductive resin pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on a side surface of the scan line; Implanting impurities into the first semiconductor layer using the layer as a mask, depositing a second metal layer, removing the lift-off layer and removing the second metal on the lift-off layer. And selectively forming source / drain electrodes made of a second metal layer on the semiconductor layer into which impurities are implanted on the gate and on the insulating substrate, and Exposing the scanning lines and auxiliary signal lines except under the source / drain electrodes, forming an organic insulating layer on the exposed scanning lines and gates in the image display unit, and applying a conductive thin film Selectively forming a pixel electrode including the drain electrode and a connection layer connecting the source electrode including both ends of the auxiliary signal line, including the drain electrode, on the insulating substrate; Using the photosensitive resin pattern used for pattern formation as a mask, an organic insulating layer is formed on the source electrode excluding the connection layer, the auxiliary signal line, and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrodes. Process Characterized in that it has a.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also in addition to lowering the temperature of the process, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured using a single photomask, and the resistance of the wiring can be reduced, so that the manufacture of a large-screen device is promoted.

A fourteenth aspect is the method for manufacturing a liquid crystal image display device according to the seventh aspect, wherein one principal plane on the insulating substrate is provided.
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, and selectively removing the second metal layer on the lift-off layer while removing the lift-off layer A step of selectively forming a pair of source / drain electrodes made of a second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate; Exposing the scanning lines except below, forming an organic insulating layer on the exposed scanning lines and gates in the image display unit, and applying one or more third metal layers. Selectively forming a signal line made of a third metal layer including the source electrode, applying a conductive thin film, and selecting a pixel electrode including the drain electrode on an insulating substrate. Forming step; The photosensitive resin pattern used for the selective pattern formation of the picture element electrodes is used as a mask to protect the picture element electrodes while irradiating light while irradiating light. And forming an organic insulating layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also in addition to lowering the temperature of the process, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured with a single photomask, and the resistance of the wiring is surely reduced, thereby promoting the manufacture of a large-screen device.

[0065]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Claim 1 shows the basic structure of an insulated gate transistor as a skeleton of the present invention, and its positioning as a component of a liquid crystal image display device will be described in detail in the embodiments. . 1 to 1 show an embodiment of the present invention.
4 will be described. FIG. 1 is a plan view of a semiconductor device (active substrate) for an image display device according to a first embodiment of the present invention, and FIG. 2 is a view showing a manufacturing process on lines AA ′ and BB ′ in FIG. FIG. Similarly, the second embodiment is shown in FIGS. 3 and 4, the third embodiment is shown in FIGS. 5 and 6, the fourth embodiment is shown in FIGS. 7 and 8, and the fifth embodiment is shown in FIGS. ,
The sixth embodiment is shown in FIGS. 11 and 12, and the seventh embodiment is a plan view of an active substrate and a cross-sectional view of a manufacturing process in FIGS. 13 and 14, respectively. The same parts as those in the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In the first embodiment of the present invention, that is, in the method of manufacturing an active substrate according to the tenth aspect, first,
As shown in FIG. 2A, a first metal layer 80 having a thickness of about 0.1 to 0.5 μm is formed on one main surface of the glass substrate 2 which is an insulating substrate by using a vacuum film forming apparatus such as SPT (sputtering). To adhere. The film thickness is a main determining parameter of the screen size and definition of the liquid crystal display device. Considering the low resistance, AL is overwhelmingly preferable, but considering that the heat resistance of the AL alone is poor, the configuration of the scanning line is made of AL (Zr, Ta) alloy or the like to reduce the resistance of the scanning line. Layer structure or AL / Ta, Ta / A
A laminated configuration such as L / Ta, AL / Ti, Ti / AL / Ti, and AL / AL (Zr, Ta) can be selected. Note that AL (Zr, Ta) means an AL-based alloy to which Zr, Ta, etc. of several percent or less is added in order to improve heat resistance. In FIG. 2 (a), AL having a film thickness of about 0.2 / 0.1 μm is used. / AL (Zr)
2 illustrates a two-layer configuration. Next, the glass substrate 2
A first SiNx (silicon nitride) layer serving as a gate insulating layer and a semiconductor layer serving as a channel of an insulated gate transistor containing almost no impurities are formed on the entire surface except for a part of the peripheral portion by using a PCVD apparatus. A silicon layer, a second SiNx layer serving as an insulating layer for protecting a channel, and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32. Further, a Mo (molybdenum) layer 40 having a thickness of about 0.2 μm, for example, is deposited on the protective layer 32 as a lift-off layer.

Subsequently, as shown in FIG. 2B, a photosensitive resin pattern 41 corresponding to a gate (and a common capacitance line) also serving as a scanning line is selectively formed to a thickness of, for example, about 2 μm by a fine processing technique. Form. And the photosensitive resin pattern 4
1 as a mask, the molybdenum layer 40, the protective insulating layer 32,
The first amorphous silicon layer 31, the gate insulating layer 30, and the first metal layer 80 are sequentially etched to form 40 ', 32',
31 ′, 30 ′ and the scanning line 11 (and the common capacitance line 16) are formed. At this time, as shown in FIG. 22, a wiring path 82 (and 83) for connecting the leading end of the scanning line 11 (and the common capacitance line 16) is provided in an area outside the image display unit, and the wiring path is as described above. The second portion exposed at a part of the peripheral portion of the glass substrate 2
It is necessary to include one metal layer 80 '. Unless the wiring path 82 is disconnected somewhere in the subsequent manufacturing process and the scanning lines 11 are not separated one by one, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal image display device is hindered. Needless to say. However, a wiring path 83 for connecting the common capacitance lines 16 in parallel
Does not need to disconnect. In this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using a gas, and it is preferable to control the taper of the cross section of the multilayer film.

Subsequently, the film thickness of the photosensitive resin pattern 41 is reduced by, for example, about 0.5 μm to 41 ′ by a treatment in oxygen gas plasma, and then as shown in FIG. 2C, the photosensitive resin pattern 41 ′ is formed. Molybdenum layer 4 using
The first amorphous silicon layer 31 ′ is partially exposed (about 0.5 μm on one side) by etching the 0 ′ and the protective insulating layer 32 ′.
In order to enhance the lift-off function of the molybdenum layer 40 ″ after the etching, the etching of the molybdenum layer 40 ′ is strongly anisotropic so that the cross-sectional shape thereof stands sharply by RIE (Reactive).
-Ion-Etch) dry etching is required.

After that, the photosensitive resin pattern 41 ′ is removed, and then a direct current is applied to the first metal layer 80 ′ exposed at a part of the peripheral portion of the glass substrate 2 shown in FIG. Electrodeposition is performed in an electrodeposition solution while giving a + (plus) potential, and an organic insulating layer 71 is formed on the side surface of the gate 11 as shown in FIG. The thickness of the organic insulating layer 71 is 0.5
μm or more is required.

Here, the organic insulating thin film and its manufacturing method will be described in detail. Among materials that can be electrodeposited as an organic insulating thin film that can secure the insulating properties necessary for a device, as described in the literature Electronology C-112 Vol. 0.01% salt
The solution containing the solution was used as an electrodeposition solution, and + (plus) was added to the scanning line 11.
When the electrodeposition is performed by applying a potential, the polyimide layer 71 can be selectively formed on the side surface of the gate 11 as shown in FIG. The electrodeposition voltage is about several volts and the polyimide layer 5
It is easy to make the thickness of 1 more than 0.5 μm. After the formation of the polyimide layer 71, preferably 200 to 300 ° C., several minutes to several
Insulation properties and chemical resistance of the polyimide layer 71 by performing a heat treatment for 10 minutes (for example, there is a step of removing the photosensitive resin pattern in a subsequent step, and the organic insulating thin film needs to have resistance to chemicals such as a resist stripping solution) ) May be increased, but the required insulation characteristics are governed by the heat resistance of the insulated gate transistor and the composition of the liquid crystal material. Therefore, the optimum heating conditions may be determined experimentally.

After forming the organic insulating layer 71 on the side surface of the gate 11, as shown in FIG. 2E, using the molybdenum layer 40 ″ as a mask, an amorphous silicon layer partially containing no impurities and containing no impurities is formed. 31 ′ is ion-implanted or ion-irradiated with phosphorus 81 as an impurity to transform into an impurity-containing amorphous silicon layer 33′.The difference between ion irradiation and ion implantation is that hydrogenated ions and radicals of the impurity depend on the presence or absence of the mass separation function. Is included, but detailed description is omitted.

Amorphous silicon has lower heat resistance than other silicon elements such as single crystal silicon, polycrystal silicon, and low-temperature polycrystal silicon, and a heat treatment temperature for activation performed after ion implantation or ion irradiation. If the temperature exceeds 300 ° C., the electrical characteristics are significantly deteriorated.
Generally, an ion implantation dose or ion irradiation dose that is at least one order of magnitude greater than other silicon devices is required. For this reason, if a photosensitive resin is used for the mask material, the deterioration is so severe that the removal of the resist becomes difficult, or the insulating layer and the semiconductor layer under the mask material are physically damaged (damage), and the electrical characteristics are largely changed. However, in the present invention, since the mask material (lift-off layer 40) is made of molybdenum, which is a metal layer having a large ion shielding effect, it is also noted that the above-mentioned disadvantages can be avoided. It is a feature.

After ion implantation or ion irradiation of impurities,
As shown in FIG. 2 (f), using a SPT device as a source (signal line) / drain electrode material, for example, a film thickness of 0.1 to 0.2
A heat-resistant metal thin film 34 of about μm, such as Ti, Ta, or Cr, is deposited on the entire surface. Then, the total thickness of the molybdenum layer 40 ″ and the protective insulating layer 32 is 0.3 μm and the Ti thin film 34
Since the thickness of the thin film 34 is larger, the Ti thin film 34 easily breaks at the edge of the lift-off layer 40 ″. g), the molybdenum layer 40 ″ disappears and the Ti on the molybdenum layer 40 ″ disappears.
The thin film 34 is selectively lifted off (peeled off) to expose the second SiNx 32 ″ serving as a protective layer.

Subsequently, as shown in FIG. 2H, T is formed on the amorphous silicon layer 33 ′ containing (implanted) impurities on the gate 11 and on the insulating substrate 2 by the fine processing technique.
A pair of sources (signal lines) while selectively leaving the i thin film 34 '
Forming the drain electrodes 12 ′ and 21,
Since the upper Ti thin film 34 has already disappeared, the signal line 12 ′ is divided and formed on the scanning line 11 as shown in FIG. When the Ti thin film 34 is etched, the scanning line 11 (and the common capacitance line 16) is over-etched or the etching material (gas) is changed.
The upper protective insulating layer 32 ″ and the amorphous silicon layer 31 ′ containing no impurity are removed to remove the scanning line 11 (and the common capacitance line 1).
6) Exposing the upper gate insulating layer 30 'is important to prevent formation of a parasitic transistor.

Subsequently, as shown in FIG. 2I, an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is to be formed, and the gate insulating layer 30 'is etched and removed. Expose part of 11.

Subsequently, as shown in FIG. 2 (j), the entire surface of the glass substrate 2 is coated with a film using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide), and the signal line 1 including the drain electrode 21 and the picture element electrode 22 and the signal line (source electrode) 12 ′ separated on the insulating substrate 2 by the fine processing technique.
A connection layer 91 for interconnecting 2 'is selectively formed. Then, while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrode 22 as a mask, the signal line 12 ′ (source electrode) except the connection layer 91 and the pixel electrode 22 were removed. An organic insulating layer 73 is formed on the drain electrode 21. It is sufficient that the film thickness of the organic insulating layer 73 is 0.1 μm or more. At this time, if expressed precisely, the organic insulating layer 73 is also formed on the side surfaces of the amorphous silicon layer 33 ′ containing impurities and the connection layer 91.

As described above, although three types of organic insulating layers 71 to 73 are employed in the present invention (72 will be described later), the organic insulating layer 73 used as the passivation insulating layer of the signal line 12 is compared with the other two. Since the required voltage may be low, in other words, the required withstand voltage may be low, the heat treatment temperature can be set to 200 ° C. or less, and the heat resistance of the insulated gate transistor is eased.

It should be noted that the formation of the organic insulating layer 73 on the source / drain electrodes 12 ', 21 is not shown, but all the signal lines 12' need to be formed electrically in parallel or in series. Needless to say, unless this series-parallel connection is released somewhere in the subsequent manufacturing process, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal image display device will be hindered.

Further, unless the resistance of the channel semiconductor layer of the insulated gate transistor is reduced by irradiating strong light of preferably 10,000 lux or more, the thickness of the organic insulating layer 73 on the drain electrode 21 may be reduced. You need to be careful. The organic insulating layer 73 may be formed only in the image display section. In order to prevent the organic insulating layer from being formed in the terminal electrode forming region at the end of the signal line 12 ′, a prior patent application It is recommended to use an in-substrate selective electrochemical treatment apparatus as disclosed in JP 2000-107577.

The reason that the picture element electrode 22 is covered with the photosensitive resin pattern 65 is not only that it is not necessary to form an organic insulating layer on the picture element electrode 22, but also that the drain electrode 21 is formed via an insulated gate transistor. This is because it is not necessary to secure an unnecessarily large electrodeposition current flowing through the electrode. During the electrodeposition, the terminal electrode 6 of the scanning line 11 is electrically floating (neutral), so that no organic insulating layer is formed even if the terminal electrode 6 is exposed. If the terminal electrode is made of the transparent conductive layer 6 ', it will be covered with the photosensitive resin, so that no problem occurs similarly to the pixel electrode 22.

If the above-described selective electrodeposition in the glass substrate 2 is performed, a part of the signal line 12 ′ can be used as the terminal electrode 5 in a region outside the image display portion as shown in FIG. In a conventional electrodeposition method in which the entire glass substrate 2 is immersed in an electrodeposition solution, the signal line 1 is used unless an appropriate mask material is used in combination.
2 'cannot be selectively electrodeposited, and as shown separately in FIG. 1, a terminal electrode 5' made of a transparent conductive layer is formed including a part of the signal line 12 'in a region outside the image display portion. Will be done. This configuration corresponds to the picture element electrode 22 shown in FIG.
And the drain electrode 21 are connected in the same manner.

As for the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 ′ may be formed so as to include a part of the exposed scanning line 11 in the opening 63 when the pixel electrode 22 is formed. Alternatively, the transparent conductive layer can be removed and a part of the scanning line 11 exposed in the opening 63 can be used as the terminal electrode 6. Avoiding exposure of dissimilar metals can easily avoid side effects due to the battery effect. Therefore, the terminal electrode 5 'of the signal line 12' and the terminal electrode 6 'of the scanning line 11 are formed while leaving the transparent conductive layer, and these terminal electrodes are connected with the transparent conductive layer to provide a short-circuit line for countermeasures against static electricity. It seems that there are many things. Finally, the photosensitive resin pattern 65 is removed, and FIG.
The active substrate 2 is completed as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the first embodiment of the present invention is completed.

As for the configuration of the storage capacitor 15, FIG. 1 shows an example in which the pixel electrode 22 and the preceding scanning line 11 are formed via the gate insulating layer 30 ′.
The configuration of the pixel electrode 22 is not limited to this.
And the storage capacitor line 16. Other configurations are also possible, but detailed description is omitted. However, when the storage capacitor line 16 is introduced, the signal line 12 ′ that intersects like the scanning line 11 is cut off, so that a new connection layer is required (see FIG. 23).

In the first embodiment described above, unlike the conventional etch-stop type insulated gate transistor, the amorphous silicon layer 31 'containing no impurities and the amorphous silicon layer 33' containing (implanted) impurities are contained. And the source / drain electrodes 12 and 21 are present on the impurity-containing amorphous silicon layer 33 ', so that the source / drain electrode material is a metal layer having high heat resistance, such as Ti, T
Although it is not limited to a, Cr, etc., a low-resistance AL single layer can be adopted, but these electrodes disappear due to a developing solution due to a battery action with an ITO layer which is a transparent electrode or an alkaline resist stripping solution. Or A to avoid film thinning
It is necessary to add Nd to L. It is also possible to use a laminate of a heat-resistant metal layer and a low-resistance AL layer as the source / drain electrode material, but the thickness of the lift-off layer is set to be large because the lamination increases the thickness of the source / drain electrodes. In addition, since the lift-off is likely to be difficult due to the soft AL, there is a restriction that the chemical solution must be strongly jetted in the form of a jet at the time of the lift-off.

As described above, in the first embodiment, it is not so easy to increase the thickness of the source / drain electrodes. If AL is not used for the signal line material, wiring resistance becomes a problem, and the formation of a device with a diagonal width of 50 cm or more is required. Difficulty is expected. Therefore, in the second embodiment, the multilayer wiring technology is introduced to promote the reduction of the resistance of the signal line.

In the second embodiment, that is, in the method of manufacturing an active substrate according to the ninth aspect, as shown in FIG. 2E, the molybdenum layer 40 ″ is used as a mask to exclude partially exposed impurities. The amorphous silicon layer 31 ′ is ion-implanted or ion-irradiated with phosphorus 81 as an impurity,
Until the amorphous silicon layer 33 'containing impurities is transformed, the process proceeds in the same manufacturing process as in the first embodiment. However, the difference from the third embodiment is that the auxiliary signal line 92 is formed simultaneously with the scanning line 11 as shown in FIG.

Subsequently, as shown in FIG. 4F, the opening 63 is formed on the position where the terminal electrode 6 of the scanning line 11 is formed by the fine processing technique, and the opening 61 is formed at both ends of the auxiliary signal line 92.
The lift-off layer 40 ″, the protective insulating layer 32 ″, the semiconductor layer 31 ′ containing no impurities, and the gate insulating layer 30 ′ in the opening are removed, and the scanning line 11 and the auxiliary signal line 9 are removed.
Expose part of 2

Subsequently, a Ti thin film 34 having a thickness of, for example, about 0.1 μm, which is a heat-resistant metal layer, is deposited on the entire surface using a SPT device as a source (signal line) / drain electrode material. Thereafter, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of dilute nitric acid or ammonia, the molybdenum layer 40 ″ disappears as shown in FIG. The Ti thin film 34 on 40 "is selectively lifted off (peeled off), and the second SiNx as a protective layer is formed.
32 "is exposed. At the same time, the insides of the openings 61 and 63 are covered with a Ti thin film.

Further, as shown in FIG. 4 (h), the Ti thin film layer 3
4 ′, a pair of source / drain electrodes 12 ″, 21
Are formed selectively. Due to over-etching or changing the etching material (gas) when etching the Ti thin film layer 34 ', the protective insulating layer 32 "on the scanning line 11 and the amorphous silicon layer 3 containing no impurities are formed.
By removing 1 ′, the gate insulating layer 30 ′ on the scanning line 11 is exposed. In order to leave a Ti thin film in the opening 63, a photosensitive resin may be left in the opening 63 and the periphery thereof during the above-mentioned fine processing.

Then, as shown in FIG. 4 (i), the entire surface of the glass substrate 2 is processed to a film thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and is divided on the insulating substrate 2 including the drain electrode 21, the picture element electrode 22, the opening 61 of the auxiliary signal line 92, and the source electrode 12 ″ by the fine processing technique. The connection layer 91 interconnecting the auxiliary signal lines 92 is selectively formed, and the first embodiment is performed while irradiating light using the photosensitive resin pattern 65 used for the selective pattern formation of the pixel electrodes 22 as a mask. Similarly to the embodiment, the organic insulating layer 73 is formed in the electrodeposition liquid on the signal line 12 ″ (source electrode) excluding the connection layer 91 and the drain electrode 21 excluding the pixel electrode 22. At this time, if expressed accurately, the organic insulating layer 73 is also formed on the side surfaces of the amorphous silicon layer 33 ′ containing impurities, the connection layer 91, and the auxiliary signal line 92 (the exact expression is omitted hereinafter). .

Regarding the configuration of the terminal electrodes of the signal lines, if selective electrodeposition within the glass substrate 2 is performed as described above,
As shown in FIG. 3, the signal line 12 ″ is located outside the image display unit.
Can be used as the terminal electrode 5. Glass substrate 2
In the case of a conventional electrodeposition method in which the whole is immersed in an electrodeposition solution, an organic insulating layer cannot be selectively formed on the signal line 12 "unless an appropriate mask material is used in combination. As shown separately, the terminal electrode 5 'made of a transparent conductive layer is formed to include a part of the signal line 12 "in a region outside the image display unit. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG. Further, a part of the terminal electrode 92 ′ made of the same material as the scanning line,
Alternatively, it is also possible to obtain a terminal electrode 5 'made of a transparent conductive layer formed including the same.

Regarding the configuration of the scanning line terminal electrode 6, when forming the picture element electrode 22, the transparent conductive terminal electrode 6 'including the Ti thin film in the opening 63 can be formed. And the Ti thin film in the opening 63 can be used as the terminal electrode 6.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the second embodiment of the present invention.

In the third embodiment, an easy manufacturing process of a low-resistance signal line is added to the first embodiment in order to facilitate fabrication of a large-screen device. A third embodiment,
That is, in the method of manufacturing an active substrate according to the tenth aspect, as shown in FIG. Until a pair of source / drain electrodes 12 ″ and 21 composed of the Ti thin film layer 34 ′ are selectively formed thereon, the process proceeds in the same manufacturing process as in the first embodiment.

Subsequently, as shown in FIGS. 5 and 6 (i), an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is formed, and the gate insulating layer 30 'is etched away. A part of the scanning line 11 is exposed.

Thereafter, the AL thin film layer 35 having a thickness of about 0.3 μm is formed as a low-resistance wiring layer by using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 made of Ti or the like is sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. Then, these two layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. 6 (j), the signal line 12 including the source electrode 12 ″ of the insulated gate transistor is selectively formed. The signal line 12 can be formed as a single AL layer without being laminated with the intermediate conductive layer 36 made of a heat-resistant metal thin film layer of Ti or the like. In order to avoid the loss due to the action of the developer or the alkaline resist stripper, it is necessary to add Nd to AL or to use a special developer or resist stripper.

At this time, regarding the configuration of the scanning line terminal electrode 6, the AL thin film layer 35 and the heat-resistant metal thin film layer 36 such as Ti
Of the scanning line 11 exposed in the opening 63 by removing the stack of the AL thin film layer 35 and the heat-resistant metal thin film layer 36 of Ti or the like. Can be used as the terminal electrode 6, or the transparent conductive terminal electrode 6 'can be formed in the next step including a part of the scanning line 11 exposed in the opening 63. The AL thin film layer 35 A transparent conductive terminal electrode 6 ′ may be formed including a laminated layer 6 ″ of a thin film 36 of a heat-resistant metal such as Ti.

After forming the signal lines 12, as shown in FIG. 6K, a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, ITO. (Indium-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique. The signal line 12 and the source electrode 12 ″ excluding the signal line 12 and the drain excluding the pixel electrode 22 are irradiated while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrode 22 as a mask. The organic insulating layer 73 is formed on the electrode 21.

When the selective electrodeposition in the glass substrate 2 is performed, the signal lines 1 are disposed outside the image display section as shown in FIG.
A part of 2 can be used as the terminal electrode 5. in this case,
The signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer 35 and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. However, if the scanning wire is A
In the case of the L-based alloy, a part of the exposed scanning line 11 (inside the opening 63) is also connected to the signal line 12 as shown in FIG.
It is necessary to leave the AL thin film layer (6 ″) at the time of formation. If a conventional electrodeposition method in which the entire glass substrate 2 is immersed in a chemical conversion solution, signal lines are used unless an appropriate mask material is used together. 12 cannot be selectively anodized, and the terminal electrode 5 ′ made of a transparent conductive layer is formed including a part of the signal line 12 in a region outside the image display unit as shown separately. .

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the third embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example in which the storage electrode 21 'formed simultaneously with the signal line 12 including the drain electrode 21 and the storage capacitor line 16 are formed via the gate insulating layer 30'. Although illustrated in FIG. 5, the configuration of the storage capacitor 15 is not limited to this, and the pixel electrode 2
A configuration between the scanning line 2 and the preceding scanning line 11 is also possible. Other configurations are also possible, but detailed description is omitted.

The main manufacturing steps in the third embodiment are as follows:
A semiconductor device for an image display device having a heterogeneous configuration can be obtained by changing the step of forming an opening in a gate insulating layer and the step of forming source / drain wirings, and this is described below as a fourth embodiment. . In the fourth embodiment, that is, in the method of manufacturing an active substrate according to the eleventh aspect, as shown in FIG. 8H, the amorphous silicon layer 33 in which the impurity on the gate 11 is implanted by the fine processing technique. '
Until a pair of source (signal line) / drain electrodes 12 ″ and 21 composed of a Ti thin film layer 34 ′ are selectively formed on the upper and insulating substrates 2, the process proceeds in the same manufacturing process as in the third embodiment. .

Subsequently, the AL thin film layer 35 having a thickness of about 0.3 μm was formed as a low-resistance wiring layer using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 made of Ti or the like is sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. Then, these two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique to include the source electrode 12 ″ of the insulated gate transistor as shown in FIGS. 7 and 8 (i). The signal lines 12 are selectively formed.

Thereafter, as shown in FIG. 8 (j), an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is to be formed, and the gate insulating layer 30 'is etched and removed. Expose a part of.

Further, as shown in FIG. 8 (k), the entire surface of the glass substrate 2 is processed to a film thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

As for the configuration of the scanning line terminal electrode 6, at this time, a transparent conductive terminal electrode 6 'can be formed including a part of the exposed scanning line 11 in the opening 63, or it can be transparent. A part of the scanning line 11 exposed in the opening 63 by removing the conductive layer may be used as the terminal electrode 6.

Then, while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrodes 22 as a mask, the signal lines 12 and the source electrodes 12 ″ excluding the signal lines and the pixel electrodes 22 are removed. An organic insulating layer 73 is formed on the drain electrode 21 thus formed.

When the selective electrodeposition in the glass substrate 2 is performed, the signal lines 1 are disposed outside the image display section as shown in FIG.
A part of 2 can be used as the terminal electrode 5. in this case,
The signal line 12 does not necessarily have to be a laminate of a low resistance wiring layer and an intermediate conductive layer 36, and the formation of the signal line 12 precedes the formation of the opening 63. Is a single layer of the AL thin film layer 35 as a low-resistance wiring layer and does not cause any problem. In the case of conventional electrodeposition in which the entire glass substrate 2 is immersed in a chemical conversion solution, an organic insulating layer cannot be selectively formed on the signal line 12 unless an appropriate mask material is used in combination. As described above, the terminal electrode 5 ′ made of the transparent conductive layer is formed including a part of the signal line 12 in a region outside the image display unit.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, thereby completing the fourth embodiment of the present invention.

The manufacturing process can be reduced by rationalizing the process of forming the source (signal line) / drain electrode and the process of forming the opening in the gate insulating layer, which will be described below as a fifth embodiment. I do. In the fifth embodiment, that is, in the method of manufacturing an active substrate according to the twelfth aspect, ion implantation or ion irradiation of impurities is performed using the molybdenum layer 40 ″ as a mask, and an SPT device is used as a source (signal line) / drain electrode. After a Ti thin film 34 having a thickness of, for example, about 0.1 μm is
Until the Ti thin film 34 above 0 ″ is selectively lifted off, the process proceeds in the same manufacturing process as in the fourth embodiment.

Thereafter, as shown in FIG. 9 and FIG. 10 (h), a pair of sources (signals) made of a second metal layer Lines) and drain electrodes 12 'and 21 are selectively formed. At this time, the gate insulating layer 30 'is added to the protective insulating layer 32 "on the scanning line 11 and the amorphous silicon layer 31' containing no impurities by over-etching of the Ti thin film 34 or changing the etching material (gas). To remove the source / drain electrode 1
Most of the scanning line 11 is exposed except between the 2 'and 21 and under the source / drain electrodes 12' and 21. (At the intersection of the scanning line 11 and the signal line pattern, the Ti thin film 34 on the scanning line 11 has already disappeared, but by leaving the photosensitive resin, the protective insulating layer 32 ″ and the amorphous The gate insulating layer 30 'can be left in addition to the porous silicon layer 31'.) In this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using gas. The source / drain electrodes 12 ′ and 21 are made of a heat-resistant metal layer other than Ti, Ta, Cr, etc.
L can be used, but Nd is added to AL to avoid disappearance by the developer or alkaline resist stripping solution due to battery action with the ITO layer as a transparent electrode, or lift-off because AL is soft. Attention must be paid to setting the thickness of the layer to be large.

As a result, scanning is performed except for the portion under the protective insulating layer 32 ″ (between the source and drain electrodes 12 ′ and 21) where the channel portion of the insulated gate transistor is located, and the intersection between the scanning line 11 and the signal line pattern. Most of the lines 11 are exposed, however, since a direct current bias is always applied between the scanning lines 11 and the counter electrode 14 in a liquid crystal panel state, the scanning lines 11 cannot be used as a liquid crystal device when the scanning lines 11 are exposed. It is necessary to form an organic insulating layer 72 by electrodeposition on the exposed scanning line 106 and a part of the gate 105. A thickness of 0.1 μm or more is sufficient, and a too thick film will be described later. This is disadvantageous in the configuration of the storage capacitor 15. In this electrodeposition step, the source / drain electrodes 12 ', 2
1 is electrically insulated from the scanning line 11 via the gate insulating layer 30 ', so that the source / drain electrodes 12', 2
No organic insulating layer is formed on the uppermost Ti thin film layer 34 'on the first layer. However, in performing the electrodeposition of the exposed scanning line 106 and the gate 105, it is prevented that an organic insulating layer is formed on the scanning line 11 in a region where the terminal electrode 6 of the scanning line 11 outside the image display unit is formed. For this reason, the selective electrodeposition process using the photosensitive resin pattern as a mask causes an increase in the number of manufacturing steps. Therefore, the use of a selective electrochemical treatment apparatus in the substrate is also recommended here.

Subsequently, as shown in FIG. 10 (i), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, as ITO (I).
A source electrode (signal line) 12 ′ including a drain electrode 21, a picture element electrode 22 and a source electrode 12 ′ is formed on the insulating substrate 2 by microfabrication technology. A connection layer 91 for interconnecting is selectively formed.

The source electrode 12 ′ excluding the connection layer 91 and the drain electrode 21 excluding the pixel electrode 22 are irradiated while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the pixel electrode 22 as a mask. An organic insulating layer 73 is formed on the surfaces of these electrodes by electrodeposition.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'can be formed so as to include a part of the scanning line 11 exposed at the same time. A part of the scanning line 11 that has been removed and exposed can be used as the terminal electrode 6.

When the selective electrodeposition in the glass substrate 2 is performed, the signal lines 1 are disposed outside the image display section as shown in FIG.
Part of 2 ′ can be used as the terminal electrode 5. With a conventional electrodeposition method in which the entire glass substrate 2 is immersed in an electrodeposition liquid, an organic insulating layer cannot be selectively formed on the signal line 12 'unless an appropriate mask material is used in combination. As shown separately, in a region outside the image display unit, the terminal electrode 5 'made of a transparent conductive layer is formed to include a part of the signal line 12'. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG. Finally, the photosensitive resin pattern 65 is removed, as shown in FIG.
As shown in (j), the active substrate 2 is completed. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the fifth embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, the preceding scanning line 11 (projection 106 of the scanning line) and the pixel electrode 22 are formed via the organic insulating layer 72 formed on the scanning line 11. Although an example is illustrated in FIG. 9, the configuration of the storage capacitor 15 is not limited to this, and may be configured between the pixel electrode 22 and the storage capacitor line 16. Other configurations are also possible, but detailed description is omitted.

Also in the fifth embodiment, it is not so easy to increase the thickness of the source / drain electrodes, and there remains a problem that the wiring resistance is a problem which is limited to the formation of a device with a diagonal of 50 cm or less. Therefore, in the sixth embodiment, the multilayer wiring technology is introduced to promote the reduction in the resistance of the signal line. In the sixth embodiment, that is, in the method of manufacturing an active substrate according to the thirteenth aspect, ion implantation or ion irradiation of impurities is performed using the molybdenum layer 40 ″ as a mask, and an SPT device is used as a source (signal line) / drain electrode. After the Ti thin film 34 having a thickness of, for example, about 0.1 μm is applied over the entire surface, the process proceeds in the same manufacturing process as in the fifth embodiment until the Ti thin film 34 on the molybdenum layer 40 ″ is selectively lifted off. . However, the difference from the fifth embodiment is that the auxiliary signal line 92 is formed simultaneously with the scanning line 11.

Then, as shown in FIGS. 11 and 12 (h), the source / drain electrodes 12 ″ and 21 made of the Ti thin film layer 34 ′ are selectively formed and the protective insulating layer 3 is formed.
In addition to 2 ″ and the amorphous silicon layer 31 ′ containing no impurity, the gate insulating layer 30 ′ is also removed, and the space between the source / drain electrodes 12 ″ and 21 and the source / drain electrodes 12 ″ and 21 ″ are removed.
Except for the lower part, most of the scanning lines 11 and the auxiliary signal lines 92 are exposed. As described above, it is necessary to form the organic insulating layer 72 by electrodeposition on the exposed scanning line 106 and part of the gate 105, and the thickness of 0.1 μm or more is sufficient.

Subsequently, as shown in FIG. 12 (i), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, as ITO (I).
n-tin-oxide), the auxiliary electrode divided by including the drain electrode 21, the pixel electrode 22, the source electrode 12 ″, and both ends of the auxiliary signal line 92 on the insulating substrate 2 by the fine processing technique. A connection layer 91 for interconnecting the signal lines 92 is selectively formed.

Using the photosensitive resin pattern 65 used for the selective pattern formation of the connection layer 91 and the picture element electrode 22 as a mask, the light is irradiated and the source electrode 12 ″ on the auxiliary signal line 92 and the connection layer 91 is removed. An organic insulating layer 73 is formed on the drain electrode 21 excluding the pixel electrode 22.

As for the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the scanning line 11 exposed at the same time, or the transparent conductive layer may be removed. The exposed part of the scanning line 11 is connected to the terminal electrode 6.
It can also be.

By performing selective electrodeposition in the glass substrate 2, a part of the source electrode 12 ″ (signal line) can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. Further, it is also possible to obtain a terminal electrode 92 'made of the same material as the scanning lines 11 or a terminal electrode 5' made of a transparent conductive layer formed including the same.
With a conventional electrodeposition method in which the whole is immersed in an electrodeposition solution, an organic insulating layer cannot be selectively formed on the source electrode 12 ″ unless an appropriate mask material is used in combination. As described above, the terminal electrode 5 'made of a transparent conductive layer in a region outside the image display portion is formed to include a part of the signal line 12 ". This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG. Finally, the photosensitive resin pattern 65 is removed, as shown in FIG.
As shown in (j), the active substrate 2 is completed. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the sixth embodiment of the present invention.

Also in the sixth embodiment, the thickness of the source / drain electrodes cannot be increased excessively to cope with lift-off, and in the seventh embodiment, the third electrode is formed to reduce the wiring resistance.
Also, similarly to the fourth embodiment, a low-resistance signal line is separately formed. Seventh embodiment, that is, Claim 14
In the method of manufacturing an active substrate described in (1), as shown in FIGS.
Until the 2 ″ and 21 are selectively formed and the organic insulating layer 72 is formed on the surface of the exposed scanning line 106 and the portion 105 of the gate, the process proceeds in the same manufacturing process as in the sixth embodiment.

Then, using a vacuum film forming apparatus such as SPT or the like, an AL thin film layer 35 having a thickness of about 0.2 to 0.6 μm as a low resistance wiring layer, and a Ti film as an intermediate conductive layer having a thickness of about 0.1 μm.
The heat-resistant metal thin film layer 36 is sequentially applied. Then, these two metal layers are sequentially etched by a fine processing technique using a photosensitive resin pattern to form a signal line 12 including a source electrode 12 ″ of an insulated gate transistor as shown in FIG. At this time, since the scanning line 11 is exposed in a region outside the image display unit, the scanning line material is AL.
In the case of a system alloy, it is necessary to leave the AL thin film layer on the exposed part of the scanning line 11 (region where the terminal electrode 6 is formed) as shown in FIG. There is.
In FIG. 14 (i), when the scanning line 11 is formed of, for example, a stack of AL / Ti, the Ti thin film serves as a mask when the AL thin film layer 35 is etched to protect the underlying AL, so that the scanning line 11 does not disappear. The case is illustrated.

Subsequently, as shown in FIG. 14 (j), a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, as ITO (I).
Then, a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

The photosensitive resin pattern 65 used for the selective pattern formation of the picture element electrode 22 is used as a mask to irradiate light while irradiating light on the signal line 12, the source electrode 12 ″ excluding the signal line, and the picture element electrode 22. The organic insulating layer 73 is formed on the drain electrode 21 excluding the above.

By performing selective electrodeposition in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. With a conventional electrodeposition method in which the entire glass substrate 2 is immersed in an electrodeposition solution, an organic insulating layer cannot be selectively formed on the signal line 12 unless an appropriate mask material is used in combination. As shown separately, the terminal electrode 5 ′ made of a transparent conductive layer is formed including a part of the signal line 12 in a region outside the image display unit. Finally, the photosensitive resin pattern 65 is removed, and FIG.
The active substrate 2 is completed as shown in FIG.

The configuration of the scanning line terminal electrode 6 includes a part of the scanning line 11 exposed at the time of forming the signal line 12 and a terminal electrode composed of a laminate of the AL thin film layer 35 and the heat-resistant metal thin film layer 36 of Ti. 6 "can be formed, AL
A part of the scanning line 11 exposed by removing the lamination of the thin film layer 35 and the heat-resistant metal thin film layer 36 of Ti can be used as the terminal electrode 6, or a transparent conductive material including the exposed part of the scanning line 11 can be used. Terminal electrode 6 'can be formed. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the seventh embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example is shown in which the storage electrode 21 'formed simultaneously with the signal line 12 including the drain electrode 21 and the storage capacitor line 16 are formed via the organic insulating layer 52. 13, the storage capacity 1
The configuration of the pixel electrode 22 is not limited to this.
And the scanning line 11 in the preceding stage. Other configurations are also possible, but detailed description is omitted.

The polyimide thin film which is an organic insulating layer employed in the present invention has a certain resistance to an organic resist stripping solution, but is not sensitive to stripping means such as an oxygen plasma treatment or a high-concentration ozone aqueous solution. Therefore, it is necessary to restrict and pay attention to resist stripping.

[0132]

As described above, according to the liquid crystal image display device of the present invention, the source / drain made of an amorphous silicon layer containing (implanted) impurities in a self-aligned manner on the gate pattern edge. And a source / drain electrode made of a heat-resistant metal can be formed, so that the parasitic capacitance of the insulated gate transistor can be reduced to a value one-several of the conventional value. As a result, even in a large-screen, high-definition liquid crystal image display device, a special effect is obtained in which flicker, printing, or display unevenness is less likely to occur.

Next, the passivation according to the present invention is a wiring passivation in which an organic insulating layer is formed only on source / drain wirings without changing the basic structure of an insulated gate transistor. The technology can be used as is. In other words, there is no possibility that the characteristics of the insulated gate transistor change, and a new design using the currently held design and reliability data can be used as it is, and it is easy to introduce it into a mass production factory.

Further, since the passivation formation according to the present invention does not involve a special heating step, an insulated gate transistor using an amorphous silicon layer as a semiconductor layer does not require excessive heat resistance. In other words, the effect of preventing the electrical performance from being deteriorated by the passivation is obtained. Also, in some cases, the AL can be used without interposing a heat-resistant barrier metal layer.
It is also possible to employ a single-layer source / drain electrode.

In addition, by making the auxiliary signal line formed of the same member as the scanning line function as a signal line, the resistance of the signal line can be reduced without increasing the number of manufacturing steps, and a large screen can be realized. became. Then, by introducing an organic insulating layer by electrodeposition, it is possible to simultaneously perform the source / drain electrode forming step and the opening forming step on the gate insulating layer, thereby further reducing the number of photo-etching steps from the conventional five times. Excellent effects such as reduction of manufacturing cost were promoted.

As is clear from the above description, the requirements of the present invention are not limited to forming a scanning line by etching a gate metal layer, a gate insulating layer, a semiconductor layer, a protective insulating layer, and a lift-off layer all at once. The point that an organic insulating layer is formed by electrodeposition on the side surface of the exposed scanning line, the recession (thickness reduction) of the photosensitive resin pattern used for forming the scanning line, the impurity-containing semiconductor layer and the source / drain electrode Image formation with different material and film thickness of picture element electrode, gate metal layer, gate insulating layer etc. in the formation by lift-off and wiring passivation on source / drain electrode using organic insulating layer. It is obvious that the semiconductor device for the device, or the difference in the manufacturing method thereof also belongs to the category of the present invention,
IPS (In-Plain-Switching) type liquid crystal that controls by applying a horizontal electric field to the liquid crystal between a pixel electrode and a counter electrode formed at a predetermined distance on the same substrate The present invention can be easily applied to a panel. For example, in the semiconductor device for an image display device according to the first embodiment shown in FIG. 23, a counter electrode (common capacitance line) formed at the same time as the scanning line 11 on the insulating substrate is used. ) 16 is formed at a predetermined distance from the drain (picture element) electrode 21, and the drain electrode 21
A region (double shaded portion) where the and the counter electrode 16 overlap with the gate insulating layer 30 ′ therebetween forms the storage capacitor 15.
In addition, the usefulness of the present invention is not changed even in a reflection type liquid crystal image display device using a picture element electrode as a metal electrode (in the claims, both a transparent conductive layer and a metal reflection layer are expressed by a conductive thin film). It is obvious that, since a transparent conductive layer is not required, a signal line forming step for lowering resistance and a reflective electrode forming step can be performed simultaneously. The same applies to a transflective liquid crystal image display device that requires both a transparent conductive (transmissive) picture element electrode and a reflective electrode. Also, the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon, and it is apparent that microcrystalline silicon, polycrystalline silicon, or a mixed crystal thereof does not cause any problem.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for an image display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the first embodiment of the present invention;

FIG. 3 is a plan view of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor device for an image display device according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the third embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor device for an image display device according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor device for an image display device according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the seventh embodiment of the present invention.

FIG. 15 is a diagram showing a mounting state of a liquid crystal panel.

FIG. 16 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 17 is a sectional view of a main part of a liquid crystal panel.

FIG. 18 is a plan view of a conventional active substrate.

FIG. 19 is a sectional view showing a manufacturing process of a conventional active substrate.

FIG. 20 is a plan view of a rationalized active substrate.

FIG. 21 is a cross-sectional view of a manufacturing process of a streamlined active substrate.

FIG. 22 is a diagram showing a pattern layout at the time of electrodeposition of the scanning line side surface according to the present invention.

FIG. 23 is a plan view of a semiconductor device for an IPS type image display device according to the present invention.

[Explanation of symbols]

Reference Signs List 1 liquid crystal image display device (liquid crystal panel) 2 active substrate (insulating substrate, glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 terminal electrode 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line ( (Gate) 12 (12 ′, 12 ″) signal line (source electrode) 16 common capacitance line 17 liquid crystal 21 drain electrode 22 (transparent conductive) picture element electrode 30 gate insulating layer (first SiNx layer) 31 impurity Amorphous silicon layer 32 which is not included (which is a first semiconductor layer) 32 (which is an insulating layer for protecting a channel)
Nx layer 33 Amorphous silicon layer containing impurities (a second semiconductor layer) 34 Heat-resistant metal layer 35 Low-resistance metal layer (AL) 36 Intermediate conductive layer 37 Passivation insulating layer 40 Lift-off layer 61 (on auxiliary signal line) Opening 62 (on the drain electrode) 63 Opening (on the scanning line) 64 Opening (on the signal line) 65 Photosensitive resin pattern (for pixel electrode formation) 71 Formed on the side of the gate (scanning line) Organic insulating layer 72 Organic insulating layer formed on the surface of gate (scanning line) 73 Organic insulating layer formed on source / drain electrode 80 First metal layer 81 Ion (and radical) of impurity (phosphorus) 91 Connection layer (connecting the separated source electrode) 92 Auxiliary signal line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 617J F term (Reference) 2H092 JA26 JA29 JA38 JA40 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB52 JB57 JB63 JB69 KA05 KA07 KA16 KA18 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA25 NA27 5C094 AA05 AA09 AA14 BA03 BA43 CA19 DA14 DA15 EA04 EA07 FB14 FB15 5F110 AA02 AA16 BB01 CC08 DD02 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE04 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE03 EE04 HJ01 HJ12 HJ13 HK03 HK04 HK07 HK21 HK22 HK33 HK42 NN12 NN14 NN24 NN35 NN72 QQ11 QQ14

Claims (14)

[Claims] 1. A gate comprising at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface, wherein the gate is thinner than the gate via a gate insulating layer and contains no impurities. A semiconductor layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner, a protective insulating layer is formed over the semiconductor layer containing no impurities, and formed over the pair of semiconductor layers. An insulated gate transistor including a metal layer as a source / drain electrode and an organic insulating layer on the source / drain electrode. 2. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate, and a gate insulating layer is formed on the surface. A scanning line having a layer and an organic insulating layer on a side surface thereof, the scanning line also serving as a gate of the insulated gate transistor, and a semiconductor layer thinner than the gate and containing no impurities on the gate via the gate insulating layer; A semiconductor layer containing a pair of impurities is formed in self-alignment with the layer; a protective insulating layer is formed on the semiconductor layer containing no impurities; A drain electrode made of one or more metal layers and a source (signal line) electrode are formed on an insulating substrate except on a scanning line, and a pixel electrode including the drain electrode and the separated source are formed on the insulating substrate. (Signal line) A liquid crystal image display device comprising: a connection layer for connecting electrodes; and an organic insulating layer formed on the surface of the source electrode except for the connection layer and the drain electrode except for the pixel electrode. . 3. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate, and a gate insulating layer is formed on the surface. A scanning line having a layer and an organic insulating layer on a side surface thereof, and also serving as a gate of an insulated gate transistor, and an auxiliary signal line having openings at both ends are formed. A thin semiconductor layer containing no impurities and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner, and protective insulation is provided on the semiconductor layer containing no impurities. A source / drain electrode made of one or more metal layers is formed on the pair of semiconductor layers and the insulating substrate, and a pixel electrode including the drain electrode on the insulating substrate and the opening are formed. A connection layer for connecting the divided auxiliary signal lines including the source electrode is formed, and an organic insulating layer is formed on the surface of the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode. Characteristic liquid crystal image display device. 4. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate, and a gate insulating layer is formed on the surface. A scanning line having a layer and an organic insulating layer on a side surface thereof, the scanning line also serving as a gate of the insulated gate transistor, and a semiconductor layer thinner than the gate and containing no impurities on the gate via the gate insulating layer; A semiconductor layer containing a pair of impurities is formed in self-alignment with the layer; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode formed of a metal layer is formed on the insulating substrate; a signal line including one or more metal layers including the source electrode is formed on the insulating substrate; and the drain electrode is formed on the insulating substrate. A liquid crystal image display device, wherein a picture element electrode is formed, and an organic insulating layer is formed on a surface of the signal line, a source electrode excluding the signal line, and a drain electrode excluding the picture element electrode. 5. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate. A scanning line which has an organic insulating layer on its surface except for below the signal line / drain electrode and also serves as a gate of an insulated gate transistor is formed, and an impurity narrower than the gate is formed on the gate via the gate insulating layer. A semiconductor layer containing no impurity and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner; and a protective insulating layer is formed on the semiconductor layer containing no impurities. A drain electrode made of a metal layer and a source (signal line) electrode are formed on the pair of semiconductor layers and the insulating substrate except on a scanning line, and a pixel electrode including the drain electrode is formed on the insulating substrate. A connection layer for connecting the divided source (signal line) electrode is formed, and an organic insulating layer is formed on the surface of the source electrode except for the connection layer and the drain electrode except for the pixel electrode. Liquid crystal image display device. 6. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate. A scanning line having an organic insulating layer on its surface except under the drain electrode and also serving as a gate of an insulated gate transistor, and an auxiliary signal line having an organic insulating layer on its surface except for both ends are formed on the gate. A semiconductor layer narrower than the gate and containing no impurities via the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner; A protective insulating layer is formed on a semiconductor layer containing no impurities, source / drain electrodes made of a metal layer are formed on the pair of semiconductor layers and on an insulating substrate, and a picture including the drain electrode is placed on an insulating substrate. A connection layer for connecting the auxiliary signal line divided including the element electrode and the both ends and the source electrode is formed, and an organic insulating layer is formed on the surface of the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode. A liquid crystal image display device comprising: 7. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more metal layers are formed on one main surface of the insulating substrate. A scanning line which has an organic insulating layer on its surface except for below the drain electrode and also serves as a gate of an insulated gate transistor is formed, and a semiconductor layer which is narrower than the gate and contains no impurities on the gate via the gate insulating layer Forming a pair of semiconductor layers containing impurities in contact with the semiconductor layer in a self-aligned manner; forming a protective insulating layer on the semiconductor layer containing no impurities; A source / drain electrode made of a metal layer is formed on the pair of semiconductor layers and an insulating substrate. A signal line made of one or more metal layers including the source electrode is formed on the insulating substrate. A pixel electrode including the drain electrode, and an organic insulating layer formed on the surface of the signal line, the source electrode excluding the signal line, and the drain electrode excluding the pixel electrode. Display device. 8. A step of applying one or more first metal layers on one main surface on an insulating substrate, and a step of forming a first metal layer on a peripheral portion of the insulating substrate.
Depositing a lift-off layer after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except on a part of the metal layer, and Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, a first semiconductor layer, and a gate insulating layer. Etching the layer and the first metal layer sequentially, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and using the reduced thickness photosensitive resin pattern as a mask to form a lift-off layer. And a protective insulating layer are sequentially etched to partially expose the first semiconductor layer; a step of forming an organic insulating layer on the side surface of the scan line; Implanting an object into the first semiconductor layer, depositing a second metal layer, removing the lift-off layer and selectively removing the second metal layer on the lift-off layer, Selectively forming a drain electrode made of a second metal layer and a separated source (signal line) electrode on the semiconductor layer into which the impurities are implanted and on the insulating substrate; And a step of selectively forming, on an insulating substrate, a connection layer that connects the picture element electrode including the drain electrode and the divided source (signal line) electrode including the source (signal line) electrode. And the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. Step of forming an organic insulating layer Method of manufacturing an image display apparatus for a semiconductor device having a. 9. A step of applying one or more first metal layers on one main surface on an insulating substrate, and a step of forming a first metal layer on a peripheral portion of the insulating substrate.
Depositing a lift-off layer after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except on a part of the metal layer, and Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, Sequentially etching the semiconductor layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, forming openings on the scanning lines outside the image display section and at both ends of the auxiliary signal lines, and forming a protective insulating layer between the lift-off layer and the lift-off layer in the openings; Selectively removing the layer, the semiconductor layer containing no impurities, and the gate insulating layer; applying a second metal layer; and selectively removing the second metal layer on the lift-off layer while removing the lift-off layer. And a second step on the insulating layer and on the semiconductor layer into which the impurity has been implanted.
Selectively forming source / drain electrodes made of a metal layer, applying a conductive thin film, and forming a pixel electrode, the opening, and the source electrode including the drain electrode on an insulating substrate. Selectively forming a connection layer for connecting the separated auxiliary signal lines, and protecting the pixel electrodes using the photosensitive resin pattern used for the selective pattern formation of the pixel electrodes as a mask. Forming an organic insulating layer on a source electrode excluding a connection layer and a drain electrode excluding a picture element electrode while irradiating light, the method comprising the steps of: 10. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming an impurity, implanting an impurity into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, removing the lift-off layer, and forming a second metal layer on the lift-off layer. Selectively removing the metal layer of (a), and selectively forming a pair of source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Forming an opening on a scanning line in a region outside the image display unit and selectively removing a gate insulating layer on the scanning line; applying one or more third metal layers; Selectively forming a signal line made of a third metal layer including: a step of applying a conductive thin film; and selectively forming a pixel electrode including the drain electrode on an insulating substrate. Process and selective pattern formation of the picture element electrode Forming the organic insulating layer on the signal line and the source electrode excluding the signal line and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask. Of manufacturing a semiconductor device for an image display device having the same. 11. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming an impurity, implanting an impurity into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, removing the lift-off layer, and forming a second metal layer on the lift-off layer. Selectively removing the metal layer of (a), and selectively forming a pair of source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Depositing one or more third metal layers, selectively forming signal lines of the third metal layer including the source electrode, and scanning lines in a region outside the image display unit. Forming an opening and selectively removing a gate insulating layer on a scanning line; applying a conductive thin film; and selectively forming a pixel electrode including the drain electrode on an insulating substrate. Process and selective pattern formation of the picture element electrode Forming the organic insulating layer on the signal line and the source electrode excluding the signal line and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask. Of manufacturing a semiconductor device for an image display device having the same. 12. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming an impurity, implanting an impurity into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, removing the lift-off layer, and forming a second metal layer on the lift-off layer. Selectively removing the metal layer of (a), and selecting a source electrode (signal line) electrode separated from the drain electrode made of the second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Exposing the scanning lines except between the source and drain electrodes and under the source and drain electrodes, and forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit, A step of applying a conductive thin film, and a step of selectively forming, on an insulating substrate, a connection layer that connects the separated source electrode including the pixel electrode and the source electrode including the drain electrode, The picture element An organic insulating layer is formed on the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pole as a mask. And a method for manufacturing a semiconductor device for an image display device. 13. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. And a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line on the lift-off layer, and Using the photosensitive resin pattern as a mask, sequentially etching a lift-off layer, a protective insulating layer, a first semiconductor layer, a gate insulating layer, and a first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, and selecting the second metal layer on the lift-off layer while removing the lift-off layer Removing step, selectively forming source / drain electrodes made of a second metal layer on the semiconductor layer into which impurities are implanted on the gate and on the insulating substrate, and forming the source / drain electrodes between the source / drain electrodes and the source / drain electrodes. Exposing the scanning lines and auxiliary signal lines except under the drain electrode, forming an organic insulating layer on the exposed scanning lines and gates in the image display unit, and applying a conductive thin film. Selectively forming, on an insulating substrate, a pixel electrode including the drain electrode and a connection layer connecting the source electrode including both ends of the auxiliary signal line; and selectively forming the pixel electrode. Used for Forming an organic insulating layer on the source electrode excluding the connection layer, the auxiliary signal line, and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrodes using the photo-resin pattern as a mask. A method for manufacturing a semiconductor device for a display device. 14. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the semiconductor layer, the gate insulating layer and the first metal layer using the pattern as a mask, and a step of partially exposing the lift-off layer by reducing the thickness of the photosensitive resin pattern. A step of etching the lift-off layer and the protective insulating layer sequentially using the photosensitive resin pattern with the reduced film as a mask to partially expose the first semiconductor layer; and forming an organic insulating layer on a side surface of the scan line. The shape A step of, implanting an impurity into the first semiconductor layer by the lift-off layer as a mask,
A step of depositing a second metal layer, a step of selectively removing the second metal layer on the lift-off layer together with the removal of the lift-off layer; Selectively forming a pair of source / drain electrodes made of a second metal layer on the top and exposing the scanning lines except between the source / drain electrodes and below the source / drain electrodes; Forming an organic insulating layer on the scanning line and the gate, applying one or more third metal layers, and forming a signal line comprising the third metal layer including the source electrode. A step of selectively forming, a step of applying a conductive thin film, a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate, and a step of selectively forming a pattern of the pixel electrode. Used photosensitive resin pattern Forming an organic insulating layer on a signal line and a source electrode excluding the signal line and a drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode as a mask. Production method.