JP2002185002A - Liquid crystal image display device and method for manufacturing semiconductor device for image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where overlap capacity between a source and a drain is large and dispersed in a surface, and it causes flickers and crosstalks in a high precision device having a large display, since positional relation between a gate and the source/drain is determined by not a self-aligned type manner but mask alignment at the time of exposure, in the conventional TFT whether it is a channel etch type or an etch stop type. SOLUTION: A self alignment TFT is used basically. In the TFT, a gate metal/gate insulating layer, a semiconductor layer, a protective insulation layer, and even a lift-off layer are formed by collective lithography, an organic insulation layer is formed on a side surface of a gate, a resist pattern is withdrawn, and a source/drain region is formed. Rationalization is enabled and the number of processes is reduced by introducing a low-temperature technique wherein a source/drain wiring is anodized and a passivation insulation layer is made unnecessary, and a technique wherein an organic insulating layer is formed on an exposed scanning line by using a process for forming a source/drain electrode and a process for forming an aperture part on the insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a color image display function, and more particularly to an active liquid crystal display.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of large quantities of television images and various image display devices on a commercial basis on liquid crystal panels with a diagonal of 5 to 50 cm. ing. Further, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response, and high contrast ratio is guaranteed.

[0003] These liquid crystal image display devices (liquid crystal panels)
Represents 200 to 1200 scanning lines and 200 to 16 signal lines
A matrix organization of about 00 lines is generally used, but recently, a large screen and a high definition have been simultaneously developed to cope with an increase in display capacity.

FIG. 19 shows a mounting state on a liquid crystal panel.
A semiconductor integrated circuit chip 3 for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, a group of scanning line terminal electrodes 6 formed on a glass substrate 2, is connected using a conductive adhesive. COG (Chip-On-Glass) method, for example, a T based on a polyimide resin thin film and having gold or solder plated copper foil terminals (not shown)
TCP (Tape-Car) for fixing the CP film 4 to the terminal electrodes 5 of the signal lines by pressing with a suitable adhesive containing a conductive medium.
An electric signal is supplied to the image display unit by a mounting means such as a carrier-package method. Here, for the sake of convenience, two mounting methods are shown simultaneously, but in practice, either method is appropriately selected.

[0005] Reference numerals 7 and 8 denote an image display portion located substantially at the center of the liquid crystal panel 1 and terminal electrodes 5 and 6 for signal lines and scanning lines.
Between the terminal electrode groups 5, 6
It is not necessary to be made of the same conductive material as that described above. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface.

FIG. 20 shows an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 19).
Is a scanning line, 12 (7 in FIG. 19) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the common electrodes 14 common to all the liquid crystal cells 13 drawn by dotted lines are formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

FIG. 21 is a sectional view of a main part of an image display portion of a liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a spacer material (not shown) such as resin fibers or beads. Is formed at a predetermined distance of about several μm, and the gap is sealed at the periphery of the glass substrate 9 with a sealing material made of an organic resin and a sealing material (neither is shown). The closed space is filled with liquid crystal 17.

In order to realize a color display, an organic thin film having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the glass substrate 9. Since a color display function is provided, in this case, the glass substrate 9 is also called a color filter (Color
The Filter abbreviation is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element.
At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials.
Usually, two polarizing plates 19 are required. Although not shown, a rear light source is arranged as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described later in detail. Colored layers 1 adjacent on color filter 9
8 and a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technique fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (referred to as an etch stop type). FIG. 22 is a plan view of a unit picture element of an active substrate (semiconductor device for an image display device) constituting a conventional liquid crystal panel. FIG. Is briefly described below. The projection 50 formed on the scanning line 11
A region 51 where the pixel electrode 22 and the pixel electrode 22 overlap with each other with a gate insulating layer interposed therebetween (a hatched portion inclined downward to the right) forms the storage capacitor 15, but a detailed description thereof is omitted here.

First, as shown in FIG. 23A, an insulating substrate having a high heat resistance, a high chemical resistance and a high transparency has a thickness of 0.5 to 0.5 mm.
A glass substrate 2 having a thickness of about 1.1 mm, for example, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a product 1737 manufactured by Corning using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo, or the like, or an alloy or silicide thereof, a gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, it is reasonable to use AL (aluminum) as the material of the scanning line. However, AL alone has low heat resistance. Therefore, Cr, T
Lamination with a, Mo or their silicides, or adding an oxide layer (AL2O3) to the surface of AL by anodic oxidation is also currently a common technique. That is, the scanning line 11 is formed of one or more metal layers.

Next, as shown in FIG. 23 (b), a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (Plasma Thievey) apparatus. Not including first amorphous silicon (a-Si) to be the channel of the insulated gate transistor
A second SiNx layer serving as an insulating layer for protecting the layer and the channel and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32.

As a know-how technique, when forming a gate insulating layer, another type of insulating layer (for example, TaOx or SiO2) is used.
In many cases, yield improvement measures such as laminating with the above-described AL2O3), or forming the first SiNx layer in two steps and applying a cleaning step in the middle are often performed. Is not limited to one type or a single layer.

Subsequently, the second amorphous SiNx layer on the gate 11 is selectively left narrower than the gate 11 by a fine processing technique to form 32 ', exposing the first amorphous silicon layer 31, and the PCVD apparatus is also used. A second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface with a thickness of, for example, about 0.05 μm, and then only on the vicinity of the gate 11 as shown in FIG. The gate insulating layer 30 is exposed while leaving the first amorphous silicon layer 31 and the second amorphous silicon layer 33 in island shapes 31 'and 33'.

Subsequently, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as PT, and the pixel electrode 22 is formed on the gate insulating layer 30 by a fine processing technique. Formed selectively.

Further, as shown in FIG. 23 (e), a selective opening 63 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display section necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 23 (f), a thin film layer 34 of, for example, Ti, Cr, Mo or the like is formed as a heat-resistant metal layer having a thickness of about 0.1 μm by using a vacuum film forming apparatus such as SPT. An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by a fine processing technique. A drain electrode 21 of the transistor and a source electrode 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 'between the source and drain electrodes is removed to expose the second SiNx layer 32', and the other regions are formed. Then, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the etching of the second amorphous silicon layer 33 'is automatically terminated due to the presence of the second SiNx layer 32' which is a protective layer of the channel. It is.

The source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 (several μm) so that the insulated gate transistor does not have an offset structure.
Since this overlap acts electrically as a parasitic capacitance, the smaller the better, the better. It is about 2 μm. In addition, at the periphery of the image display unit, including the opening 63 on the scanning line 11, the signal line 12 and the scanning line side terminal electrode 6 simultaneously with the signal line 12, or the wiring connecting the scanning line 11 and the scanning line side terminal electrode 6. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, a SiNx layer having a thickness of about 0.3 to 0.7 μm is deposited on the entire surface of the glass substrate 2 using a PCVD apparatus in the same manner as the gate insulating layer 30 to form a passivation insulating layer. 37, and an opening 38 is formed on the pixel electrode 22 as shown in FIG.
Most of the terminals 5 are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines, and most of the terminal electrodes are also exposed.

When the wiring resistance of the signal line 12 does not matter, the low-resistance wiring layer 35 made of AL is not always necessary. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is, firstly, to prevent a decrease in the effective voltage applied to the liquid crystal cell, and secondly, because the film quality of the passivation insulating layer 37 is generally poor, This is for avoiding the accumulation of the electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film forming temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The manufacturing process of the active substrate described above requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for liquid crystal panel manufacturers in order to realize lower prices for liquid crystal panels and respond to further increases in demand. I've been.

FIG. 24 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 25 is a cross-sectional view taken along the line AA 'in FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. A region 52 where the storage capacitance line 16 and the drain electrode 21 overlap each other with the gate insulating layer 30 interposed therebetween (a hatched portion falling to the right) forms the storage capacitance 15, but a detailed description thereof is omitted here. .

First, similarly to the conventional example, as shown in FIG. 25A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a glass substrate 2 by using a vacuum film forming apparatus such as SPT. And a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by a fine processing technique.

Next, as shown in FIG. 25B, a SiNx layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD apparatus, and a first channel serving as a channel of an insulated gate transistor containing almost no impurities. An amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are sequentially formed in a thickness of, for example, about 0.3-0.2-0.05 μm. 30, 31, and 33 are attached.

Then, as shown in FIG. 25C, the gate insulating layer 30 is formed on the gate 11 by leaving the semiconductor layers made of the first and second amorphous silicon layers in the form of islands 31 'and 33'. Exposed.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as PT, for example, a Ti thin film layer 34 as a heat-resistant metal layer with a thickness of about 0.1 μm, an AL thin film layer 35 with a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm-thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer, and the drain electrode 21 of the insulated gate transistor and the source electrode 12 also serving as a signal line are selectively formed by a fine processing technique. This selective patterning is
Using the photosensitive resin pattern used for forming the drain wiring as a mask, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', and the first amorphous silicon layer 31' Are sequentially etched, and the first amorphous silicon layer 31 'is etched by leaving about 0.05 to 0.1 .mu.m, so that it is called a channel etch.

After removing the photosensitive resin pattern, a transparent insulating layer is formed on the entire surface of the glass substrate 2 as shown in FIG.
A passivation insulating layer 37 is formed by depositing a SiNx layer having a thickness of about 0.3 μm using an apparatus, and an opening 63 is formed on the drain electrode 21 and an opening 63 is formed on a position where the terminal electrode 6 of the scanning line 11 is formed. To form the drain electrode 21 and the scanning line 1
Expose a portion of 1. Although not shown, an opening 64 is also formed on the position where the terminal electrode 5 of the signal line is formed to expose a part of the signal line 12.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as Then, the picture element electrode 22 is selectively formed to complete the active substrate 2. A part of the scanning line 11 exposed in the opening 63 may be used as the terminal electrode 6, and the terminal electrode 6 ′ made of ITO is selectively formed on the passivation insulating layer 37 including the opening 63 as shown in the figure. It may be formed.

As described above, the five-mask process is one time in the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the step of forming an opening (contact) to a scanning line and the step of forming an opening to a pixel electrode and the step of forming a contact, which were required twice, have been streamlined once, thereby eliminating a total of two photo etching steps. Can be. Further, since the pixel electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a transparent resin thin film, for example, for 1.5 times.
If the pixel electrode 22 is formed thicker than μm, even if the pixel electrode 22 overlaps the scanning line 11 or the signal line 12, interference due to capacitance is small, and deterioration of image quality can be avoided, so that the pixel electrode 22 can be formed large. There are many advantages such as an improvement in the aperture ratio.

[0031]

As described above, the source / drain electrodes 12 and 21 are formed so as to partially overlap the gate 11 so that the insulated gate transistor does not have an offset structure. Since this overlap acts electrically as a parasitic capacitance, the smaller the better, the better. It is about 2 μm. Rather, the thickness is preferably about 3 μm from the viewpoint of manufacturing margin during mass production.

In the case of the etch stop type, since the gate and the source / drain electrodes are aligned with an etch stop layer interposed therebetween, an overlap capacitance of two times of alignment accuracy is required. Although it cannot be obtained, these overlapping capacitances fluctuate within the glass substrate (although at most 1 μm) due to the optical distortion of the lens or mirror of the exposure apparatus, so that flickering, printing, and display occur on a large screen and high definition device. It is inevitable from image quality problems such as spots.

Japanese Patent Application Laid-Open Nos. 62-205664 and 63-168052 disclose prior art examples in which a source / drain electrode can be formed in a self-aligned manner with a gate. Then, an etch stop layer slightly thinner (at most 1 μm) than the gate is formed on the gate, and the source / drain is formed by irradiating or implanting impurities with the etch stop layer as a mask. For the source / drain formed in a self-aligned manner, the former is incomplete and cannot be formed in a self-aligned manner up to the source / drain electrodes. When a metal having a melting point, for example, Cr is deposited and heated, silicide is formed on the source / drain. Therefore, if Cr on the etch stop layer is removed with an etching solution, a source / silicide having a low resistance value is formed.
The drain electrode is formed in a self-aligned manner.

However, the back exposure stage naturally requires a highly transparent quartz or glass plate, and a warp or undulation of the glass substrate requires a vacuum suction mechanism to the stage. Whether it can meet the requirements and be able to be mass-produced stably is still opaque compared to the conventional metallic stage. There is a problem that deterioration of electrical characteristics is inevitable due to heat treatment (200 ° C. or higher).

In general, a passivation insulating layer is employed for passivating the source / drain wirings.
Even if it is carried out in a low-temperature film formation of several tens of degrees Celsius or lower and 250 degrees Celsius or less in comparison with
Particularly, it is inevitable that the ON current of the insulated gate transistor is reduced by about 10 to 30%. The reduction in the current driving capability of the insulated gate transistor becomes a major obstacle to increase the wiring resistance in order to obtain a large screen and high definition liquid crystal panel.

In addition, in the case of a channel-etch type insulated gate transistor, the first region containing no impurity in the channel region is used.
If the amorphous silicon layer is not deposited thicker (typically 0.2 μm or more for the channel etch type), the transistor characteristics tend to be uneven due to the in-plane uniformity of the glass substrate. . This greatly affects the operation rate of PCVD and the state of particle generation, and is very important from the viewpoint of production cost.

The present invention has been made in view of the above situation, and has developed a new self-aligned source / drain formation technique without using backside exposure, and also has a low-temperature passivation to compensate for the low heat resistance of an insulated gate transistor. It is an object of the present invention to solve the above-mentioned problems by formation. As already mentioned, it is necessary to pursue a further reduction in the number of manufacturing steps in order to realize a reduction in the price of the liquid crystal panel and to respond to an increase in demand.

[0038]

According to the present invention, first, a resist pattern at the time of gate formation is receded to expose an amorphous silicon layer containing no impurities on a gate end portion. A source / drain is formed by ion-implanting or irradiating an impurity into the silicon layer, and a lift-off layer is also used so that the source / drain and the source / drain electrode are formed in a self-aligned manner. Further, in order to effectively passivate only the source / drain wiring, the anodic oxidation technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in Japanese Patent Application Laid-Open No. 2-216129, which is a prior art, is fused. In this way, it is intended to realize a streamlining process and a low temperature. Further, by forming an organic insulating layer on the exposed scanning line to further reduce the number of steps, it is possible to streamline the step of forming source / drain wiring and the step of forming an opening in the gate insulating layer.

The insulated gate transistor according to claim 1, wherein at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface is used as a gate, and a gate insulating layer is provided on the gate. A semiconductor layer that is narrower than the gate and contains no impurities and a pair of semiconductor layers that contain impurities in contact with the semiconductor layer are formed in a self-aligned manner, and a protective insulating layer is formed over the semiconductor layer that does not contain impurities. A metal layer formed on the pair of semiconductor layers is used as a source / drain electrode.

With this configuration, in the insulated gate transistor, the source / drain electrodes are formed in a self-aligned manner with respect to the gate, and the parasitic capacitance between the gate and the source / drain is reduced to a fraction of the conventional value.

According to a second aspect of the present invention, in the liquid crystal image display device, a unit pixel having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor is two-dimensional. In a liquid crystal image display device in which liquid crystal is filled between an insulating substrate arranged in a matrix and a transparent insulating substrate or a color filter facing the insulating substrate, the surface of the insulating substrate is formed on one main surface. 1 having a gate insulating layer and an organic insulating layer on its side
A scan line formed of at least one metal layer and also serving as a gate of the insulated gate transistor, and a pair of a semiconductor layer thinner than the gate and containing no impurities through the gate insulating layer on the gate, and A semiconductor layer containing impurities is formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurities, and a semiconductor layer containing impurities and a metal layer are formed on the pair of semiconductor layers and the insulating substrate. A source (signal line) electrode is formed except on a scanning line and a drain electrode composed of a stack of
A passivation insulating layer having a pair of second openings is formed on the entire surface of the pixel electrode and the source (signal line) electrode, and the pixel electrode and the second opening including the first opening are formed. A connection layer for connecting a source (signal line) electrode including and separated from the connection layer is formed on the passivation insulating layer.

With this structure, the parasitic capacitance between the gate and the source / drain is reduced to a fraction of that of the conventional device. Reduce.

A liquid crystal image display device according to claim 3, wherein the insulated gate comprises at least one metal layer having a gate insulating layer on one main surface of the insulating substrate and an organic insulating layer on the side surface. A scanning line also serving as the gate of the type transistor is formed, and a semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer is formed on the gate by self-alignment. A protective insulating layer is formed on the semiconductor layer containing no impurity, a source / drain electrode formed of a metal layer is formed on the pair of semiconductor layers and on the insulating substrate, and the insulating layer is formed on the insulating substrate. A signal line including one or more metal layers including a source electrode is formed, a passivation insulating layer having an opening on the drain electrode is formed on the entire surface, and a passivation insulating layer including the opening is formed. Characterized in that the pixel electrodes are formed on the Deployment insulating layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reduced, and a large-screen device can be manufactured.

A liquid crystal image display device according to claim 4, wherein the insulated gate comprises at least one metal layer having a gate insulating layer on one main surface of the insulating substrate and an organic insulating layer on the side surface thereof. A scanning line also serving as the gate of the type transistor is formed, and a semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer is formed on the gate by self-alignment. A protective insulating layer is formed on the semiconductor layer containing no impurity, and a drain electrode comprising one or more metal layers that can be anodized on the pair of semiconductor layers and the insulating substrate; Except that a source (signal line) electrode is formed, and a pixel electrode including the drain electrode and a connection layer for connecting the divided source (signal line) electrode are formed on an insulating substrate; And an anodized layer is formed on the surface of the drain electrode, except for the source electrode and the pixel electrode excluding.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be performed at a lower temperature, and it is not necessary to apply a passivation insulating layer over the entire surface of the glass substrate. Is reduced in heat resistance.

A liquid crystal image display device according to a fifth aspect of the present invention also comprises one or more anodically oxidizable metal layers on one main surface of the insulating substrate, a gate insulating layer on the surface thereof, and an organic insulating layer on the side surface. A scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line having an opening at both ends having a gate insulating layer and an anodized layer on the side surface thereof are formed on the surface thereof, and on the gate, A semiconductor layer narrower than the gate and containing no impurities through the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner, and a protective insulating layer is formed on the semiconductor layer containing no impurities. A source / drain electrode made of one or more anodizable metal layers is formed on the pair of semiconductor layers and on the insulating substrate; and a pixel electrode including the drain electrode is provided on the insulating substrate. And before A connection layer for connecting the divided auxiliary signal lines including the opening and the source electrode is formed, and an anodic oxide layer is formed on the surface of the source electrode except for the connection layer and the drain electrode except for the pixel electrode. It is characterized by being.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also lower temperature of the process and lowering of the resistance of the signal line can be promoted without increasing the number of film forming steps. Production becomes possible.

The liquid crystal image display device according to claim 6, further comprising at least one metal layer having a gate insulating layer on one surface and an organic insulating layer on the side surface on one main surface of the insulating substrate. A scanning line also serving as the gate of the type transistor is formed, and a semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer is formed on the gate by self-alignment. A protective insulating layer is formed on the semiconductor layer containing no impurity, a source / drain electrode made of an anodizable metal layer is formed on the pair of semiconductor layers and on the insulating substrate, A signal line including one or more metal layers that can be anodized including the source electrode is formed on a substrate, and a picture element electrode including the drain electrode is formed on an insulating substrate. And an anodized layer on the surface of the drain electrode, except for the source electrode and the pixel electrode except for the Route is formed.

With this configuration, not only a self-aligned insulated gate transistor can be obtained, but also a lower temperature process and a lower resistance of the signal line are promoted, so that a large screen device can be easily manufactured.

According to a seventh aspect of the present invention, in the liquid crystal image display device, at least one layer having an organic insulating layer on one main surface of the insulating substrate except for between channels and below a source (signal line) / drain electrode. A scanning line which is also made of a metal layer and which also serves as a gate of an insulated gate transistor is formed. Is formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurity, and a drain electrode made of an anodizable metal layer on the pair of semiconductor layers and on the insulating substrate And source (signal line) except on scanning line
An electrode is formed, a pixel electrode including the drain electrode and a connection layer for connecting the divided source (signal line) electrode are formed on the insulating substrate, and the source electrode and the pixel electrode excluding the connection layer are formed. Characterized in that an anodic oxide layer is formed on the surface of the drain electrode excluding the above.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be reduced in temperature and rationalized, and the manufacturing cost can be reduced.

In the liquid crystal image display device according to the present invention, at least one anodic oxidizable layer having an organic insulating layer on one main surface of the insulating substrate except for between channels and below source / drain electrodes. A scanning line which is also made of a metal layer and also serves as a gate of an insulated gate transistor, and an auxiliary signal line having an anodized layer on its surface except for both end portions are formed. A thin semiconductor layer containing no impurity and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode made of an anodizable metal layer is formed on the layer and on the insulating substrate. Nde connection layer for connecting the separated auxiliary signal line is formed, and an anodized layer on the surface of the drain electrode, except for the source electrode and the pixel electrode except for the connection layer is formed.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also a reduction in the resistance of the signal line can be realized without increasing the film forming process in addition to lowering and rationalizing the process. Large screen devices can be manufactured.

A liquid crystal image display device according to a ninth aspect of the present invention comprises one or more metal layers having an organic insulating layer on the surface thereof except for between channels and below source / drain electrodes on one main surface of the insulating substrate. A scanning line serving also as a gate of the insulated gate transistor is formed, and a semiconductor layer narrower and containing no impurities than the gate via the gate insulating layer over the gate and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer Are formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurity, and a source and a source layer made of an anodizable metal layer are formed on the pair of semiconductor layers and on the insulating substrate.
A drain electrode is formed, a signal line including one or more anodizable metal layers including the source electrode is formed on the insulating substrate, and a picture element electrode including the drain electrode is formed on the insulating substrate. An anodic oxide layer is formed on the surface of the signal line, the source electrode excluding the signal line, and the drain electrode excluding the pixel electrode.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reduced in addition to the lowering and rationalization of the process, which facilitates the manufacture of a large-screen device. .

According to a tenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal image display device according to the second aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, and depositing a second metal layer;
With the removal of the lift-off layer, a second
And selectively removing the drain electrode and the separated source (signal line) electrode made of the second metal layer on the semiconductor layer on the gate where impurities are implanted and on the insulating substrate. Forming a passivation layer, applying a passivation insulating layer, and forming a source (signal line) on the drain electrode.
Forming an opening on the electrode and selectively removing the passivation insulating layer in the opening, applying a conductive thin film, and including an opening on the drain electrode on the passivation insulating layer. A step of selectively forming a picture element electrode and a connection layer for connecting a divided source (signal line) electrode including an opening on the source (signal line) electrode.

According to this structure, a semiconductor layer containing impurities can be formed at both ends of a semiconductor layer containing no impurities formed on the gate via the gate insulating layer, and the semiconductor layer containing impurities (source / drain) can be formed. ) And the source / drain electrodes are formed in a self-aligned manner to obtain a self-aligned insulated gate transistor.

An eleventh aspect is the method for manufacturing a liquid crystal image display device according to the third aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, and depositing a second metal layer;
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selectively forming source / drain electrodes made of the second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Depositing at least a third metal layer, selectively forming a signal line made of a third metal layer including the source electrode, and depositing a passivation insulating layer; Forming an opening on the drain electrode to selectively remove the passivation insulating layer in the opening, applying a conductive thin film, and including the opening on the drain electrode on the passivation insulating layer. Selectively forming picture element electrodes.

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the resistance of the signal line can be reliably reduced, and a large-screen device can be easily manufactured.

A twelfth aspect of the present invention is the method of manufacturing a liquid crystal image display device according to the fourth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying a second metal layer capable of being anodized, removing the lift-off layer, and removing the second metal on the lift-off layer. A step of selectively removing the layer, and a step of selectively forming a source (signal line) electrode separated from a drain electrode made of a second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Forming, applying a conductive thin film, and connecting the separated source (signal line) electrode including the drain electrode including the drain electrode and the source (signal line) electrode on the insulating substrate. A source layer excluding the connection layer while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. Electrodes and pixel electrodes Characterized in that the drain electrode, except a step of forming an anodic oxide layer.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be reduced in temperature and the heat resistance of the insulated gate transistor can be reduced.

According to a thirteenth aspect, in the method for manufacturing a liquid crystal image display device according to the fifth aspect, at least one anodizable first metal layer is applied on one main surface of the insulating substrate. Lift-off after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. A step of applying a layer, and a step of selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line on the lift-off layer,
Lift-off layer using the photosensitive resin pattern as a mask,
A protective insulating layer, a first semiconductor layer, a gate insulating layer, and a first insulating layer.
Sequentially etching the metal layer, reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer, and using the reduced thickness photosensitive resin pattern as a mask, a lift-off layer and a protective insulating layer. Sequentially exposing the first semiconductor layer to partially expose the first semiconductor layer, forming an organic insulating layer on the side surface of the scanning line, and using the lift-off layer as a mask to remove impurities from the first semiconductor layer. And forming openings on the scanning lines outside the image display area and at both ends of the auxiliary signal lines to selectively remove the lift-off layer, the protective insulating layer, the semiconductor layer containing no impurities, and the gate insulating layer. Process and
Applying a second metal layer capable of being anodized, selectively removing the second metal layer on the lift-off layer together with the removal of the lift-off layer, insulating the semiconductor layer into which the impurity has been implanted; Selectively forming source / drain electrodes made of a second metal layer on a substrate, applying a conductive thin film, and forming a pixel electrode including the drain electrode and the opening on an insulating substrate. Selectively forming a connection layer for connecting a divided auxiliary signal line including a portion and a source electrode; and forming a pixel using the photosensitive resin pattern used for selective pattern formation of the pixel electrode as a mask. Forming an anodic oxide layer on the source electrode excluding the connection layer and the drain electrode excluding the picture element electrode while irradiating light while protecting the electrodes.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the resistance of the signal line can be reliably reduced without lowering the temperature of the process and increasing the number of film forming steps. Can be manufactured.

A fourteenth aspect is the method for manufacturing a liquid crystal image display device according to the sixth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying a second metal layer capable of being anodized, removing the lift-off layer, and removing the second metal on the lift-off layer. Selectively removing a layer, selectively forming a pair of source / drain electrodes made of a second metal layer on an insulating substrate on a semiconductor layer on which impurities on the gate are implanted, and displaying an image. Forming an opening on a scan line in an outer region and selectively removing a gate insulating layer on the scan line; applying one or more third metal layers capable of being anodized; A step of selectively forming a signal line made of a third metal layer including an electrode; a step of depositing a conductive thin film; and a step of selectively forming a pixel electrode including the drain electrode on an insulating substrate And selectively patterning the picture element electrode A step of forming an anodized layer on a signal line, a source electrode excluding the signal line, and a drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrodes using the photosensitive resin pattern used as a mask as a mask And characterized in that:

According to this configuration, not only a self-aligned insulated gate transistor can be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, so that a large-screen device can be easily manufactured.

A fifteenth aspect of the present invention is also the method for manufacturing a liquid crystal image display device according to the sixth aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying a second metal layer capable of being anodized, removing the lift-off layer, and removing the second metal on the lift-off layer. Selectively removing the layer, selectively forming a pair of source / drain electrodes made of a second metal layer on the semiconductor layer on the gate where impurities are implanted, and on the insulating substrate; Depositing at least one oxidizable third metal layer, selectively forming a signal line comprising the third metal layer including the source electrode, and forming a region outside the image display unit. A step of forming an opening on a scanning line and selectively removing a gate insulating layer on the scanning line; a step of applying a conductive thin film; and selectively forming a pixel electrode including the drain electrode on an insulating substrate. Forming and selectively patterning the pixel electrodes Forming an anodized layer on the signal line, the source electrode excluding the signal line, and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for forming the mask as a mask. And a process.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also the process can be performed at a low temperature and the resistance of the signal line can be reduced, and a large-screen device can be easily manufactured.

A sixteenth aspect of the present invention is the method for manufacturing a liquid crystal image display device according to the seventh aspect, wherein one principal surface on the insulating substrate is
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying a second metal layer capable of being anodized, removing the lift-off layer, and removing the second metal on the lift-off layer. A step of selectively removing the layer, and a step of selectively forming a source (signal line) electrode separated from a drain electrode made of a second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Form and sauce
Exposing the scanning lines except between the drain electrodes and below the source / drain electrodes, forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit, and applying a conductive thin film Selectively forming a pixel electrode including the drain electrode and a connection layer connecting the divided source electrode including the source electrode on the insulating substrate; Forming the anodic oxide layer on the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask as a mask. It is characterized by having.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also in addition to lowering the process temperature, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. A device can be manufactured with a single photomask.

A seventeenth aspect is the method for manufacturing a liquid crystal image display device according to the eighth aspect, wherein one or more anodically oxidizable first metal layers are deposited on one main surface of the insulating substrate. Lift-off after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Applying a layer, selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor and an auxiliary signal line on the lift-off layer, and masking the photosensitive resin pattern. Sequentially etching a lift-off layer, a protective insulating layer, a first semiconductor layer, a gate insulating layer, and a first metal layer; and partially exposing the lift-off layer by reducing the thickness of the photosensitive resin pattern. And said film was reduced A step of sequentially exposing the lift-off layer and the protective insulating layer using the optical resin pattern as a mask to partially expose the first semiconductor layer, and a step of forming an organic insulating layer on a side surface of the scan line; Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying an anodically oxidizable second metal layer, removing the lift-off layer, and removing the second metal on the lift-off layer. Selectively removing the layer, selectively forming a source / drain electrode made of a second metal layer on the semiconductor layer into which impurities on the gate are implanted, and on the insulating substrate; Exposing the scanning lines and auxiliary signal lines except under the source and drain electrodes, forming an organic insulating layer on the exposed scanning lines and gates in the image display area, and depositing a conductive thin film. Process and Selectively forming a pixel electrode including the drain electrode and a connection layer connecting the source electrode including both ends of the auxiliary signal line on the insulating substrate, and selectively forming the pixel electrode on the insulating substrate. Forming an anodized layer on the source electrode excluding the connection layer and the auxiliary signal line and the drain electrode excluding the pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used as a mask; and It is characterized by having.

With this configuration, not only can a self-aligned insulated gate transistor be obtained, but also, in addition to lowering the temperature of the process, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured with a single photomask, and the resistance of the wiring can be reduced, thereby promoting the manufacture of a large-screen device.

In a eighteenth aspect of the present invention, there is provided a method of manufacturing a liquid crystal image display device according to the ninth aspect, wherein one principal surface on the insulating substrate is provided.
Depositing at least one first metal layer and at least one gate insulating layer and an impurity-free first semiconductor except on a part of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing a layer and a protective insulating layer,
Selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and using the photosensitive resin pattern as a mask, a lift-off layer, a protective insulating layer, and a first semiconductor. Sequentially etching the layer, the gate insulating layer and the first metal layer;
A step of partially exposing the lift-off layer by reducing the film thickness of the photosensitive resin pattern, and sequentially etching the lift-off layer and the protective insulating layer using the reduced photosensitive resin pattern as a mask. Partially exposing the layer, and forming an organic insulating layer on the side of the scanning line,
Implanting impurities into the first semiconductor layer using the lift-off layer as a mask, applying a second metal layer capable of being anodized, removing the lift-off layer, and removing the second metal on the lift-off layer. Selectively removing the layer, selectively forming a pair of source / drain electrodes made of a second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate; Exposing the scanning lines except between the electrodes and below the source / drain electrodes; forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit; A step of depositing a third metal layer, a step of selectively forming a signal line made of the third metal layer including the source electrode, a step of depositing a conductive thin film, Including the drain electrode Removing the signal lines and signal lines while irradiating light while protecting the pixel electrodes using the photosensitive resin pattern used as a mask for the selective pattern formation of the pixel electrodes, Forming an anodic oxide layer on the source electrode and the drain electrode excluding the picture element electrode.

According to this configuration, not only can a self-aligned insulated gate transistor be obtained, but also, in addition to lowering the process temperature, the rationalization of devices and processes is promoted, and the number of photolithography steps is reduced. The device can be manufactured with a single photomask, and the resistance of the wiring is surely reduced, thereby promoting the manufacture of a large-screen device.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Claim 1 shows the basic structure of an insulated gate transistor as a skeleton of the present invention, and its positioning as a component of a liquid crystal image display device will be described in detail in the embodiments. . 1 to 1 show an embodiment of the present invention.
8 will be described. FIG. 1 is a plan view of a semiconductor device (active substrate) for an image display device according to a first embodiment of the present invention, and FIG. 2 is a view showing a manufacturing process on lines AA ′ and BB ′ in FIG. FIG. Similarly, the second embodiment is shown in FIGS. 3 and 4, the third embodiment is shown in FIGS. 5 and 6, the fourth embodiment is shown in FIGS. 7 and 8, and the fifth embodiment is shown in FIGS. ,
The sixth embodiment is shown in FIGS. 11 and 12, the seventh embodiment is shown in FIGS. 13 and 14, the eighth embodiment is shown in FIGS.
17A and 17B are a plan view of an active substrate and a cross-sectional view of a manufacturing process, respectively, in FIGS. The same parts as those in the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In the first embodiment of the present invention, that is, in the method of manufacturing an active substrate according to claim 10, first,
As shown in FIG. 2A, a first metal layer 80 having a thickness of about 0.1 to 0.5 μm is formed on one main surface of the glass substrate 2 which is an insulating substrate by using a vacuum film forming apparatus such as SPT (sputtering). To adhere. The film thickness is a main parameter for determining the screen size and definition of the liquid crystal display device. Considering the low resistance, AL is overwhelmingly preferable, but considering that the heat resistance of the AL alone is poor, the configuration of the scanning line is made of AL (Zr, Ta) alloy or the like to reduce the resistance of the scanning line. Layer structure or AL / Ta, Ta / A
A laminated configuration such as L / Ta, AL / Ti, Ti / AL / Ti, and AL / AL (Zr, Ta) can be selected. AL (Zr, Ta) means an AL alloy to which several percent or less of Zr, Ta, etc. is added to improve heat resistance. In FIG. 2A, AL (Zr, Ta) having a film thickness of about 0.2 / 0.1 μm is used. / AL (Zr)
2 illustrates a two-layer configuration. Next, using a PCVD apparatus, a first SiNx (silicon nitride) layer serving as a gate insulating layer and a semiconductor layer serving as a channel of an insulated gate transistor are almost entirely doped with impurities using a PCVD apparatus except for a part of the peripheral portion of the glass substrate 2. An amorphous silicon layer that does not contain the same, a second SiNx layer serving as an insulating layer for protecting the channel, and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm. , 32. Further, a Mo (molybdenum) layer 40 having a thickness of about 0.2 μm, for example, is deposited on the protective layer 32 as a lift-off layer.

Subsequently, as shown in FIG. 2B, a photosensitive resin pattern 41 corresponding to a gate (and a common capacitance line) also serving as a scanning line is selectively formed with a film thickness of, for example, about 2 μm by a fine processing technique. Form. And the photosensitive resin pattern 4
1 as a mask, a molybdenum layer 40, a protective insulating layer 32,
The first amorphous silicon layer 31, the gate insulating layer 30, and the first metal layer 80 are sequentially etched to form 40 ', 32',
31 ′, 30 ′ and the scanning line 11 (and the common capacitance line 16) are formed. At this time, as shown in FIG. 26, a wiring path 82 (and 83) for connecting the leading end of the scanning line 11 (and the common capacitance line 16) is provided in an area outside the image display unit, and the wiring path is as described above. The second portion exposed at a part of the peripheral portion of the glass substrate 2
It is necessary to include one metal layer 80 '. Note that this wiring path 82 must be disconnected somewhere in the subsequent manufacturing process to separate the scanning lines 11 one by one, not only in the electrical inspection of the active substrate 2 but also in the actual operation as a liquid crystal image display device. Needless to say. However, a wiring path 83 for connecting the common capacitance line 16 in parallel
Does not need to disconnect. In this step, since a plurality of types of thin films are etched, it is reasonable to employ dry etching using gas, and it is preferable to control the taper of the cross section of the multilayer film.

Subsequently, the thickness of the photosensitive resin pattern 41 is reduced by, for example, about 0.5 μm to 41 ′ by a treatment in an oxygen gas plasma, and then as shown in FIG. 2C, the photosensitive resin pattern 41 ′ is formed. Molybdenum layer 4 using as a mask
The first amorphous silicon layer 31 ′ is partially exposed (about 0.5 μm on one side) by etching the 0 ′ and the protective insulating layer 32 ′.
In order to enhance the lift-off function of the molybdenum layer 40 ″ after the etching, the etching of the molybdenum layer 40 ′ is strongly anisotropic so that the cross-sectional shape thereof stands sharply by RIE (Reactive).
-Ion-Etch) dry etching is required.

Thereafter, the photosensitive resin pattern 41 ′ is removed, and then a direct current is applied to the first metal layer 80 ′ exposed at a part of the peripheral portion of the glass substrate 2 shown in FIG. Electrodeposition is performed in an electrodeposition solution while giving a + (plus) potential, and an organic insulating layer 71 is formed on the side surface of the gate 11 as shown in FIG. The thickness of the organic insulating layer 71 is 0.5
μm or more is required.

Here, the organic insulating thin film and its manufacturing method will be described in detail. From materials that can be electrodeposited as an organic insulating thin film that can secure the insulating properties required for the device, as described in the literature Electronology C-112 Vol. 0.01% salt
The solution containing the solution was used as an electrodeposition solution, and + (plus) was added to the scanning line 11.
When the electrodeposition is performed by applying a potential, the polyimide layer 71 can be selectively formed on the side surface of the gate 11 as shown in FIG. The electrodeposition voltage is about several volts and the polyimide layer 7
It is easy to make the thickness of 1 more than 0.5 μm. After the formation of the polyimide layer 71, preferably 200 to 300 ° C., several minutes to several
Insulation properties and chemical resistance of the polyimide layer 71 by performing a heat treatment for 10 minutes (for example, there is a step of removing the photosensitive resin pattern in a subsequent step, and the organic insulating thin film needs to have resistance to chemicals such as a resist stripping solution) ) May be increased, but the required insulation characteristics are governed by the heat resistance of the insulated gate transistor and the composition of the liquid crystal material. Therefore, the optimum heating conditions may be determined experimentally.

After the organic insulating layer 71 is formed on the side surface of the gate 11, an amorphous silicon layer containing no impurity which is partially exposed using the molybdenum layer 40 ″ as a mask is further formed as shown in FIG. 31 ′ is ion-implanted or ion-irradiated with phosphorus 81 as an impurity to transform the amorphous silicon layer 33 ′ containing the impurity into hydrogen. Is included, but detailed description is omitted.

Amorphous silicon has lower heat resistance than other silicon devices such as single crystal silicon, polycrystal silicon, and low-temperature polycrystal silicon, and a heat treatment temperature for activation performed after ion implantation or ion irradiation. If the temperature exceeds 300 ° C., the electrical characteristics are significantly deteriorated.
Generally, an ion implantation dose or ion irradiation dose that is at least one order of magnitude greater than other silicon devices is required. For this reason, if a photosensitive resin is used for the mask material, the deterioration is so severe that the removal of the resist becomes difficult, or the insulating layer and the semiconductor layer under the mask material are physically damaged (damage), and the electrical characteristics are largely changed. However, in the present invention, since the mask material (lift-off layer 40) is made of molybdenum, which is a metal layer having a large ion shielding effect, it is also noted that the above-mentioned disadvantages can be avoided. It is a feature.

After ion implantation or ion irradiation of impurities,
As shown in FIG. 2F, a Ti thin film 34 having a thickness of, for example, about 0.1 μm is deposited on the entire surface as a source (signal line) / drain metal layer using an SPT apparatus. Then, the total film thickness of the molybdenum layer 40 ″ and the protective insulating layer 32 is 0.3 μm.
Since it is thicker than the Ti thin film 34, the Ti thin film 34 easily breaks at the edge of the lift-off layer 40 ". Thereafter, the insulating substrate 2 is placed in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia. When left as it is, the molybdenum layer 40 "disappears and the Ti thin film 34 on the molybdenum layer 40" is selectively lifted off (peeled off) as shown in FIG. I do.

Subsequently, as shown in FIG. 2H, T is formed on the amorphous silicon layer 33 'containing impurities (implanted) on the gate 11 and on the insulating substrate 2 by the fine processing technique.
A pair of sources (signal lines) while selectively leaving the i thin film 34 '
Although the drain electrodes 12 'and 21 are formed, the amorphous silicon layer 33 and the Ti thin film 34 on the scanning line 11 have already disappeared, so that the signal line 12' is connected to the scanning line 1 as shown in FIG.
1 is formed by being divided. The scanning line 11 is formed by over-etching or changing the etching material (gas) when etching the Ti thin film 34.
Then, the protective insulating layer 32 ″ and the amorphous silicon layer 31 ′ containing no impurity on the (and the common capacitance line 16) are removed, and the scanning line 1 is removed.
It is important to expose the gate insulating layer 30 'on 1 (and the common capacitance line 16) in order to prevent formation of a parasitic transistor.

Further, as shown in FIG. 2 (i), a transparent insulating layer was formed on the entire surface of the glass
An x layer is applied to form a passivation insulating layer 37. An opening 61 is formed on both ends of the signal line 12 ′ separated by the fine processing technology, an opening 62 is formed on the drain electrode 21, and an opening 63 is formed on a position where the terminal electrode 6 of the scanning line 11 is formed.
The opening 64 is also formed on the position of the signal line 12 where the terminal electrode 5 is formed. The passivation insulating layer 37 in the opening 61 and the opening 62 is removed to remove The electrode 21 is partially exposed, the passivation insulating layer 37 and the gate insulating layer 30 ′ in the opening 63 are removed to partially expose the scanning line 11, and the passivation insulating layer 37 in the opening 64 is removed. After removal, the signal line 12 'is also partially exposed. Since the second SiNx for protecting the channel portion of the insulated gate transistor has already been formed, an acrylic photosensitive resin having high heat resistance and high transparency can be used as the passivation insulating layer 37.

Finally, as shown in FIG. 2 (j), the entire surface of the glass substrate 2 is processed to a film thickness of 0.5 using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and the drain electrode 21 in the opening 62 is formed on the passivation insulating layer 37 by a fine processing technique.
And the connection layer 91 interconnecting the divided signal lines 12 ′ including the signal lines (source electrodes) 12 ′ in the openings 61, and selectively forming the active substrate 2 ( (A semiconductor device for an image display device).

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the scanning line 11 exposed in the opening 63 when the picture element electrode 22 is formed. Alternatively, part of the scanning line 11 exposed in the opening 63 by removing the transparent conductive layer may be used as the terminal electrode 6. Regarding the configuration of the terminal electrode 5 of the signal line, the exposed signal line 1 in the opening 64 when the pixel electrode 22 is formed.
The transparent conductive terminal electrode 5 ′ may be formed to include a part of the signal line 12 ′. You can also. Generally, the signal line 12 'is left while leaving the transparent conductive layer.
And the terminal electrode 6 ′ of the scanning line 11 are formed.
In addition, it is likely that these terminal electrodes are connected by a transparent conductive layer to provide a short-circuit line for countermeasures against static electricity. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the first embodiment of the present invention is completed.

As for the configuration of the storage capacitor 15, FIG. 1 shows an example in which the pixel electrode 22 and the preceding scanning line 11 are formed via the gate insulating layer 30 '.
The configuration of the pixel electrode 22 is not limited to this.
And the storage capacitor line 16. However, when the storage capacitor line 16 is introduced, the signal line 12 ′ that intersects like the scanning line 11 is divided, so that a new connection layer is required (see FIG. 27). Other configurations are also possible, but detailed description is omitted.

In the first embodiment described above, unlike the conventional etch-stop type insulated gate transistor, the amorphous silicon layer 31 ′ containing no impurities and the amorphous silicon layer 33 ′ containing (implanted) impurities are contained. And the source / drain electrodes 12 and 21 are present on the impurity-containing amorphous silicon layer 33 ', so that the source / drain electrode material is a metal layer having high heat resistance, such as Ti, T
Although it is not limited to a, Cr, etc., a low-resistance AL single layer can be adopted, but these electrodes disappear due to a developing solution due to a battery action with an ITO layer which is a transparent electrode or an alkaline resist stripping solution. Or A to avoid film thinning
It is necessary to add Nd to L. It is also possible to use a laminate of a heat-resistant metal layer and a low-resistance AL layer as the source / drain electrode material, but the thickness of the lift-off layer is set to be large because the lamination increases the thickness of the source / drain electrodes. In addition, since the lift-off is likely to be difficult due to the soft AL, there is a restriction that the chemical solution must be strongly jetted in the form of a jet at the time of the lift-off. Generally, since lift-off of AL is not easy, the thickness of the source / drain electrodes cannot be increased in order to cope with the lift-off, and the wiring resistance is a problem that is limited to the formation of a device with a diagonal width of 50 cm or less. Remains. Therefore, in the second embodiment, the resistance of the signal line is reduced by newly providing a signal line.

In the second embodiment, that is, in the method of manufacturing an active substrate according to the eleventh aspect, as shown in FIG. Thereafter, using a vacuum film forming apparatus such as SPT, an AL thin film layer 35 having a thickness of about 0.3 μm as a low-resistance wiring layer,
A heat-resistant metal thin film layer 36 of Ti, Ta, Cr or the like is sequentially deposited as an intermediate conductive layer of about μm. Then, these two metal layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. 4 (i), the signal line 12 including the source electrode 12 ″ of the insulated gate transistor is formed. Is selectively formed.

Subsequently, as shown in FIG. 4 (j), an SiNx layer having a thickness of about 0.3 μm is applied as a transparent insulating layer on the entire surface of the glass substrate 2 by using a PCVD apparatus, thereby forming a passivation insulating layer. An opening 63 is formed on the drain electrode 21 on the position where the terminal electrode 6 of the scanning line 11 is formed on the drain electrode 21, and an opening 64 is formed on the position where the terminal electrode 5 of the signal line 12 is formed on the drain electrode 21. The drain electrode 21, the scanning line 11, and a part of the signal line 12 are exposed by removing the insulating layer in the opening.

Finally, as shown in FIG. 4K, the entire surface of the glass substrate 2 is processed to a film thickness of 0.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide) and the opening 6
The picture element electrode 22 is selectively formed on the passivation insulating layer 37 including the drain electrode 21 in 2 to complete the active substrate 2. The configuration of the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines can be selected in the same manner as in the first embodiment. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the second embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example in which the storage electrode 21 ′ including the drain electrode 21 and formed simultaneously with the signal line 12 and the storage capacitor line 16 are configured via the gate insulating layer 30 ′. Although illustrated in FIG. 3, the configuration of the storage capacitor 15 is not limited to this, and the pixel electrode 2
A configuration between the scanning line 2 and the preceding scanning line 11 is also possible. Other configurations are also possible, but detailed description is omitted.

In the first and second embodiments, the passivation insulating layer is made of SiNx or 200 by conventional PCVD.
Acrylic or polyimide resin that requires heat treatment at a temperature of at least 100 ° C. is employed, but passivation that can be formed at a low temperature of at most 200 ° C. is also possible. In the third embodiment, that is, in the method of manufacturing an active substrate according to the twelfth aspect, as shown in FIG. A pair of source (signal line) / drain electrodes 1 is selectively left on the silicon layer 33 ′ and on the insulating substrate 2 while leaving the Ta thin film 34 ′.
Until 2 ′ and 21 are formed, the process proceeds in the same manufacturing process as in the first embodiment. However, unlike the first and second embodiments, the source / drain electrodes 12 ′ and 21 need to be anodically oxidizable metals, and Ta or Ta, W, Mo
Etc. are selected. Since the film thickness is reduced by anodic oxidation, the film is formed to be slightly thicker, for example, about 0.15 μm.

Subsequently, as shown in FIG. 6I, an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is to be formed, and the gate insulating layer 30 'is etched and removed. Expose part of 11.

Subsequently, as shown in FIG. 6 (j), the entire surface of the glass substrate 2 is formed using a vacuum film forming apparatus such as SPT.
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide), and the signal line 1 including the drain electrode 21 and the picture element electrode 22 and the signal line (source electrode) 12 ′ separated on the insulating substrate 2 by the fine processing technique.
A connection layer 91 for interconnecting 2 'is selectively formed. Then, while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the signal line 12 ′ (source electrode) except the connection layer 91 and the pixel electrode 22 are connected. The removed drain electrode 21 is anodized to form these oxide layers. It is sufficient that the thickness of the anodized layer is 0.1 μm or more. At this time, a silicon oxide layer (SiO2) 67 as an insulating layer is formed on the side surface of the amorphous silicon layer 33 'containing impurities.

When Ta is used as the source / drain electrode material, the insulating layer 5 is formed by anodic oxidation on the surface of the signal line 12 'and the drain electrode 21 except for the picture element electrode 22.
Tantalum oxide (Ta2O5) 68 is formed. A point to be noted in anodic oxidation of the source / drain electrodes 12 ′ and 21 is that although not shown, all the signal lines 12 ′ need to be formed electrically in parallel or in series. If this series-parallel connection is not released, it goes without saying that not only the electrical inspection of the active substrate 2 but also the actual operation of the liquid crystal image display device is hindered.

Further, unless the resistance of the channel semiconductor layer of the insulated gate transistor is reduced by irradiating a strong light of 10,000 lux or more, the thickness of the anodic oxide layer on the drain electrode 21 may be reduced. Caution must be taken. The signal line 12 'need only be anodized only in the image display area. In order to prevent the anodized layer from being formed in the terminal electrode formation region at the end of the signal line 12', a prior patent is disclosed. It is recommended to use an in-substrate selective electrochemical treatment apparatus as disclosed in JP 2000-107577.

The reason that the pixel electrode 22 is covered with the photosensitive resin pattern 65 is not only that the pixel electrode 22 does not need to be anodized, but also that the formation current that flows to the drain electrode 21 via the insulated gate transistor is used. This is because it is not necessary to secure the value larger than necessary. During the anodic oxidation, the terminal electrodes 6 of the scanning lines 11 are electrically floating (neutral), so that even if the terminal electrodes 6 are exposed, no anodic oxidation layer is formed. If the terminal electrode is formed of the transparent conductive layer 6 ', no problem arises as in the case of the pixel electrode 22, since it is covered with the photosensitive resin. As described above, if the selective anodic oxidation in the glass substrate 2 is performed, as shown in FIG.
Part of 2 ′ can be used as the terminal electrode 5. In a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 1 is used unless an appropriate mask material is used in combination.
2 'cannot be selectively anodized, and as shown separately in FIG. 5, a terminal electrode 5' made of a transparent conductive layer is formed including a part of the signal line 12 'in a region outside the image display portion. Will be done. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG.

Regarding the configuration of the scanning line terminal electrode 6, the transparent conductive terminal electrode 6 'may be formed so as to include a part of the exposed scanning line 11 in the opening 63 when the pixel electrode 22 is formed. Alternatively, the transparent conductive layer may be removed and a part of the exposed scanning line 11 in the opening 63 may be used as the terminal electrode 6. Avoiding exposure of dissimilar metals can easily avoid side effects due to the battery effect. As described above, the terminal electrode 5 ′ of the signal line is also formed of a transparent conductive layer, and it is safe to connect the terminal electrode 5 ′ and the terminal electrode 6 ′ with the transparent conductive layer to form a short-circuit line for preventing static electricity. It is a choice.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the third embodiment of the present invention.

In the third embodiment, since the passivation is performed at a low temperature, a low-resistance AL single layer other than Ta can be used as the source / drain electrode material as the anodizable metal layer. However, it is necessary to add Nd to AL in order to avoid disappearance or film loss of these electrodes due to a developing solution or an alkaline resist stripping solution due to a battery action with the ITO layer as a transparent electrode. It is also possible to use a stack of a Ta layer and a low-resistance AL layer as a source / drain electrode material. In addition, since the AL is soft, the lift-off is likely to be difficult. Therefore, there is a restriction that the chemical liquid must be strongly jetted at the time of the lift-off.

As described above, in the third embodiment, it is not so easy to increase the thickness of the source / drain electrodes, and there remains a problem that the wiring resistance is a problem which is limited to the formation of a device with a diagonal of 50 cm or less. Therefore, in the fourth embodiment, the multilayer wiring technology is introduced to promote the reduction in the resistance of the signal line.

In the fourth embodiment, that is, in the method of manufacturing an active substrate according to the thirteenth aspect, as shown in FIG. 2E, the molybdenum layer 40 ″ is used as a mask to exclude partially exposed impurities. 31 ′ amorphous silicon layer
Until the impurity 81 is ion-implanted or ion-irradiated with phosphorus 81 to be transformed into the amorphous silicon layer 33 ′ containing the impurity, the process proceeds in the same manufacturing process as in the first embodiment. However, as shown in FIG.
The point formed at the same time is a difference from the third embodiment.

Subsequently, as shown in FIG. 8F, the opening 63 is formed on the position where the terminal electrode 6 of the scanning line 11 is formed by the fine processing technique, and the opening 61 is formed at both ends of the auxiliary signal line 92.
The lift-off layer 40 ″, the protective insulating layer 32 ″, the semiconductor layer 31 ′ containing no impurities, and the gate insulating layer 30 ′ in the opening are removed, and the scanning line 11 and the auxiliary signal line 9 are removed.
Expose part of 2

Subsequently, an anodically oxidized Ta thin film 34 having a thickness of, for example, about 0.15 μm is deposited on the entire surface as a source (signal line) / drain electrode material using an SPT apparatus. Thereafter, when the insulating substrate 2 is left in a hydrogen peroxide solution containing a small amount of diluted nitric acid or ammonia, the molybdenum layer 40 ″ disappears as shown in FIG. The Ta thin film 34 on 40 "is selectively lifted off (peeled off), and the second SiNx as a protective layer is formed.
32 "is exposed. At the same time, the insides of the openings 61 and 63 are covered with a Ta thin film.

Further, as shown in FIG. 8 (h), the Ta thin film layer 3 is formed on the amorphous silicon layer 33 'into which impurities on the gate 11 are implanted by the fine processing technique and on the insulating substrate 2.
4 ′ pair of source (signal line) and drain electrode 1
2 "and 21 are selectively formed. The amorphous silicon layer 31 'containing no impurities on the scanning line 11 is removed by over-etching or changing the etching material (gas) at the time of etching the Ta thin film layer 34'. Then, the gate insulating layer 30 'on the scanning line 11 is exposed.
In order to leave the Ta thin film in the opening 63, a photosensitive resin may be left around the opening 63 and the periphery thereof during the above-mentioned fine processing.

Then, as shown in FIG. 8 (i), the entire surface of the glass substrate 2 is processed to a thickness of 0.
As a transparent conductive layer of about 1 to 0.2 μm, for example, ITO (Indiu
m-Tin-Oxide), and the auxiliary signal line 9 divided including the pixel electrode 22 including the drain electrode 21 and the opening 61 of the auxiliary signal line 92 on the insulating substrate 2 by the fine processing technique.
A connection layer 91 interconnecting the two is selectively formed. Then, while irradiating light using the photosensitive resin pattern 65 used for the selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the side of the auxiliary signal line 92 and the signal line 12 ″ (source electrode) excluding the connection layer 91 are irradiated. ) And the drain electrode 21 excluding the picture element electrode 22 are anodized to form oxide layers of these electrodes in the same manner as in the third embodiment. Since it is exposed, it is preferable to select an anodic oxidizable material for the first metal layer so that the first metal layer is preferably insulated by the anodic oxide layer as described above.

Regarding the configuration of the terminal electrodes of the signal lines, if the selective anodic oxidation in the glass substrate 2 is performed as described above, the signal lines 1 in the area outside the image display section as shown in FIG.
A part of 2 "can be used as the terminal electrode 5. In a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 1 is used unless an appropriate mask material is used in combination.
2 "cannot be selectively anodized, and as shown separately in FIG. 7, a terminal electrode 5 'made of a transparent conductive layer is formed including a part of the signal line 12" in a region outside the image display portion. Will be done. This configuration is the same as the connection between the picture element electrode 22 and the drain electrode 21 shown in FIG. Further, a part 92 ′ of the terminal electrode made of the same material as the scanning line,
Alternatively, it is also possible to obtain a terminal electrode 5 'made of a transparent conductive layer formed including the same.

Regarding the configuration of the scanning line terminal electrode 6, when forming the picture element electrode 22, the transparent conductive terminal electrode 6 'including the Ta thin film in the opening 63 can be formed, or the transparent conductive layer can be formed. And the Ta thin film in the opening 63 can be used as the terminal electrode 6.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, thereby completing the fourth embodiment of the present invention.

The fifth embodiment is similar to the second embodiment except that a process for easily manufacturing a low-resistance signal line is added to the third embodiment in order to facilitate the manufacture of a large-screen device. . In the fifth embodiment, that is, in the method of manufacturing an active substrate according to the fourteenth aspect, as shown in FIG. 10H, the amorphous silicon layer 33 in which the impurity on the gate 11 is implanted by the fine processing technique. Until a pair of source (signal line) / drain electrodes 12 ″ and 21 made of a Ta thin film layer 34 ′ are selectively formed on the upper surface and the insulating substrate 2, the third step is performed.
The process proceeds in the same manufacturing process as the embodiment.

Subsequently, as shown in FIG. 10I, an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is formed.
Is formed, the gate insulating layer 30 'is etched away, and the scanning line 1 is formed.
Expose part of 1.

Thereafter, the AL thin film layer 35 having a thickness of about 0.3 μm is formed as a low-resistance wiring layer using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 of Ta or the like is further sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. These two layers are sequentially etched using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. 10 (j), the signal line 12 including the source electrode 12 ″ of the insulated gate transistor is selectively formed. The signal line 12 can be formed as a single AL layer without being laminated with the intermediate conductive layer 36 made of a heat-resistant metal thin film layer of Ta or the like.
In order to avoid disappearance by a developing solution or an alkaline resist stripping solution due to a battery action with the layer, it is necessary to add Nd to AL or to use a special developing solution or resist stripping solution.

At this time, regarding the configuration of the scanning line terminal electrode 6, the AL thin film layer 35 and the heat-resistant metal thin film layer 36 such as Ta
Of the scanning line 11 exposed in the opening 63 by removing the stack of the AL thin film layer 35 and the heat-resistant metal thin film layer 36 of Ta or the like. Can be used as the terminal electrode 6, or the transparent conductive terminal electrode 6 'can be formed in the next step including a part of the scanning line 11 exposed in the opening 63. The AL thin film layer 35 A transparent conductive terminal electrode 6 ′ may be formed by including a laminate 6 ″ of a heat-resistant metal thin film layer 36 of Ta or the like.

After forming the signal lines 12, as shown in FIG. 10 (k), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, ITO. (Indium-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique. Then, while irradiating light with the photosensitive resin pattern 65 used for selective pattern formation of the picture element electrodes 22 as a mask, the signal lines 12 and 12 are
When the source electrode 12 "excluding the pixel electrode 22 and the drain electrode 21 excluding the picture element electrode 22 are anodized to form these oxide layers, the source electrode 12" and the signal wiring 12 have an insulating layer of tantalum pentoxide on the surface. (Ta2O5) 68 is formed. Alumina (Al2O3) 6 which is an insulating layer on the side surface of the signal wiring 12
The point that 9 is formed is a difference between the third and fourth embodiments. Needless to say, when an AL single layer containing Nd or the like is used for the signal line 12, alumina (Al2O3) 69, which is an insulating layer, is entirely formed on the signal line 12.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. However, if the scanning wire is A
In the case of the L-based alloy, the AL thin film layer (6 ″) is also formed on a part of the exposed scanning line 11 (the area where the terminal electrode 6 is formed) as shown in FIG. However, when the scanning line material is a laminated layer such as Ta / AL / Ta, it is not necessary because Ta exerts a mask function against the etching of AL. If a conventional anodic oxidation method such as immersion in a chemical conversion solution is used, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a transparent conductive layer in the region is formed to include a part of the signal line 12 (the intermediate conductive layer 36 ′ is formed on the surface).

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. Active substrate 2 thus obtained
And a color filter are bonded to form a liquid crystal panel, thereby completing the fifth embodiment of the present invention.

The main manufacturing steps in the fifth embodiment are as follows:
A semiconductor device for an image display device having a heterogeneous configuration can be obtained by changing the step of forming an opening in a gate insulating layer and the step of forming a source / drain wiring, and this will be described below as a sixth embodiment. . In the sixth embodiment, that is, in the method of manufacturing an active substrate according to the fifteenth aspect, as shown in FIG.
Until a pair of source (signal line) / drain electrodes 12 ″ and 21 made of a Ta thin film layer 34 ′ are selectively formed on 3 ′ and on the insulating substrate 2, the manufacturing steps are the same as those in the fifth embodiment. proceed.

Subsequently, the AL thin film layer 35 having a thickness of about 0.3 μm was formed as a low resistance wiring layer using a vacuum film forming apparatus such as SPT.
Then, a heat-resistant metal thin film layer 36 of Ta or the like is further sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. Then, these two metal layers are sequentially etched by using a photosensitive resin pattern by a fine processing technique, and as shown in FIG. Is selectively formed.

Thereafter, as shown in FIG. 12 (j), an opening 63 is formed on the scanning line 11 at a position where the terminal electrode 6 is to be formed, and the gate insulating layer 30 'is etched and removed.
Expose a part of.

Further, as shown in FIG. 12 (k), the entire surface of the glass
As a transparent conductive layer of about 0.1 to 0.2 μm, for example, ITO (Ind
ium-Tin-Oxide), and a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

As for the configuration of the scanning line terminal electrode 6,
At this time, a part of the exposed scanning line 11 in the opening 63 at the same time.
To form a transparent conductive terminal electrode 6 ′.
The transparent conductive layer was removed to expose the inside of the opening 63.
A part of the scanning line 11 can be used as the terminal electrode 6.

Then, while irradiating light using the photosensitive resin pattern 65 used for the selective pattern formation of the pixel electrodes 22 as a mask, the signal lines 12 and the source electrodes 12 ″ excluding the signal lines and the pixel electrodes 22 are removed. The drain electrode 21 is anodized to form an oxide layer on the surface of these electrodes.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and the formation of the signal line 12 is not limited to the opening 63.
Therefore, the signal line 12 is a single layer of the AL thin film layer 35 as a low-resistance wiring layer without any problem even if the scanning line material is an AL-based alloy. With a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a transparent conductive layer in a region outside the image display unit is formed including a part of the signal line 12.

Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. Active substrate 2 thus obtained
And a color filter are bonded to form a liquid crystal panel, thereby completing the sixth embodiment of the present invention.

By rationalizing the process of forming source (signal line) / drain electrodes and the process of forming openings in the gate insulating layer, the number of manufacturing steps can be reduced. This is described below as the seventh embodiment. I do. In the seventh embodiment, that is, in the method of manufacturing an active substrate according to claim 16, ion implantation or ion irradiation of impurities is performed using the molybdenum layer 40 ″ as a mask, and an SPT device is used as a source (signal line) / drain electrode. For example, using a film thickness of 0.15 μm
After the Ta thin film 34 is applied to the entire surface, the process proceeds in the same manufacturing process as in the sixth embodiment until the Ta thin film 34 on the molybdenum layer 40 ″ is selectively lifted off. As shown in FIG. 14H, a pair of source (signal line) / drain electrodes 12 ′ and 21 made of a second metal layer are formed on the semiconductor layer 33 ′ into which impurities on the gate are implanted and on the insulating substrate 2. Are selectively formed at this time.
The gate insulating layer 30 'as well as the protective insulating layer 32 "and the impurity-free amorphous silicon layer 31' on the scanning line 11 are removed by over-etching or changing the etching material (gas) of the thin film 34. Most of the scanning line 11 is exposed except for between the source / drain electrodes 12 ′ and 21 and below the source / drain electrodes 12 ′ and 21 (at the intersection of the scanning line 11 and the signal line pattern, the scanning line 11 is exposed. Although the Ta thin film 34 has already disappeared, the protective insulating layer 3 is formed by leaving the photosensitive resin.
The gate insulating layer 30 'can be left in addition to the amorphous silicon layer 31' containing no 2 "impurities.) In this step, since a plurality of types of thin films are etched, dry etching using a gas is performed. The source / drain electrodes 12 ′ and 21 may be made of a low-resistance AL other than Ta as the anodizable metal layer.
Nd is added to AL to avoid disappearance by a developer or an alkaline resist stripping solution due to battery action with the ITO layer as a transparent electrode, or the thickness of the lift-off layer is set to be thick because AL is soft. Attention is necessary.

As a result, scanning is performed except for the portion under the protective insulating layer 32 ″ (between the source / drain electrodes 12 ′ and 21) where the channel portion of the insulated gate transistor is located and the intersection between the scanning line 11 and the signal line pattern. Most of the lines 11 are exposed, however, since a direct current bias is applied between the scanning lines 11 and the counter electrode 14 in the liquid crystal panel state, the scanning lines 11 cannot be used as a liquid crystal device when the scanning lines 11 are exposed. It is necessary to form an organic insulating layer 72 by electrodeposition on the exposed scanning line 106 and a part of the gate 105. A thickness of 0.1 μm or more is sufficient, and if the thickness is excessively large, it will be described later. This is disadvantageous in the configuration of the storage capacitor 15. In this electrodeposition step, the source / drain electrodes 12 ', 2
1 is electrically insulated from the scanning line 11 via the gate insulating layer 30 ', so that the source / drain electrodes 12', 2
The organic insulating layer is not formed on the uppermost Ta thin film layer 34 'on the first layer. However, in performing the electrodeposition of the exposed scanning line 106 and the gate 105, it is prevented that an organic insulating layer is formed on the scanning line 11 in a region where the terminal electrode 6 of the scanning line 11 outside the image display unit is formed. For this reason, the selective electrodeposition process using the photosensitive resin pattern as a mask causes an increase in the number of manufacturing steps. Therefore, the use of a selective electrochemical treatment apparatus in the substrate is also recommended here.

Subsequently, as shown in FIG. 14 (i), a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, as ITO (I).
A source electrode (signal line) 12 ′ including a drain electrode 21, a picture element electrode 22 and a source electrode 12 ′ is formed on the insulating substrate 2 by microfabrication technology. A connection layer 91 for interconnecting is selectively formed.

Then, while irradiating light using the photosensitive resin pattern 65 used for selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the source electrode 12 ′ except the connection layer 91 and the pixel electrode 22 are removed. The drain electrode 21 is anodized to form an oxide layer on the surface of these electrodes.

Regarding the configuration of the scanning line terminal electrode 6, a transparent conductive terminal electrode 6 'can be formed including a part of the scanning line 11 which is simultaneously exposed at this time. A part of the scanning line 11 that has been removed and exposed can be used as the terminal electrode 6.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 'can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. A conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical solution cannot selectively anodize the signal line 12 ′ unless a suitable mask material is used in combination, as shown in FIG. In a region outside the image display section, the terminal electrode 5 'made of a transparent conductive layer is formed including a part of the signal line 12'. This configuration corresponds to the picture element electrode 2 shown in FIG.
2 and the drain electrode 21 are connected in the same manner. Finally, the photosensitive resin pattern 65 is removed, and FIG.
The active substrate 2 is completed as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the seventh embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, the preceding scanning line 11 (projection portion 106 of the scanning line) and the pixel electrode 22 are configured via the organic insulating layer 72 formed on the scanning line 11. Although an example is illustrated in FIG. 13, the configuration of the storage capacitor 15 is not limited to this, and may be configured between the pixel electrode 22 and the storage capacitor line 16. Other configurations are also possible, but detailed description is omitted.

Also in the seventh embodiment, it is not so easy to increase the thickness of the source / drain electrodes, and there remains a problem that the wiring resistance is a problem which is limited to the formation of a device with a diagonal of 50 cm or less. Therefore, in the eighth embodiment, the multilayer wiring technology is introduced to promote the reduction in the resistance of the signal line. In the eighth embodiment, that is, in the method of manufacturing an active substrate according to claim 17, the molybdenum layer 40 ″ is formed.
Is used as a mask to perform ion implantation or ion irradiation of impurities, and using a SPT device as a source (signal line) / drain electrode, for example, a Ta thin film 34 having a thickness of about 0.15 μm is deposited on the entire surface, and then the molybdenum layer 40 ″ is formed. Ta thin film 34
The process proceeds in the same manufacturing process as in the seventh embodiment until is selectively lifted off. However, the point that the auxiliary signal line 92 is formed simultaneously with the scanning line 11 is a difference from the seventh embodiment. Further, since the auxiliary signal line 92 is anodized in a later step, it is necessary to form an insulating layer by anodization, which is a great difference from the other embodiments. Therefore, Ta or AL is selected for the scanning line 11 (auxiliary signal line 92) by itself. Alternatively, silicide which is an alloy of Ta, W, Mo, Cr and the like with Si may be used. Considering the low resistance, AL is overwhelmingly preferable, but considering that the heat resistance of the AL alone is poor, the configuration of the scanning line is made of AL (Zr, Ta) alloy or the like to reduce the resistance of the scanning line. Layer structure or AL / Ta, Ta / A
A laminated configuration such as L / Ta, AL / AL (Zr, Ta) can be selected.

Thereafter, as shown in FIGS. 15 and 16 (h), the source / drain electrodes 12 ″ and 21 composed of the Ta thin film layer 34 ′ are selectively formed, and the protective insulating layer 3 is formed.
In addition to 2 ″ and the amorphous silicon layer 31 ′ containing no impurity, the gate insulating layer 30 ′ is also removed, and the space between the source / drain electrodes 12 ″ and 21 and the source / drain electrodes 12 ″ and 21 ″ are removed.
Except for the lower part, most of the scanning lines 11 and the auxiliary signal lines 92 are exposed. As described above, it is necessary to form the organic insulating layer 72 by electrodeposition on the exposed scanning line 106 and part of the gate 105, and the thickness of 0.1 μm or more is sufficient.

Subsequently, as shown in FIG. 16 (i), a transparent conductive layer having a thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, using ITO (I
n-tin-oxide), the auxiliary electrode divided by including the drain electrode 21, the pixel electrode 22, the source electrode 12 ″, and both ends of the auxiliary signal line 92 on the insulating substrate 2 by the fine processing technique. A connection layer 91 for interconnecting the signal lines 92 is selectively formed.

Using the photosensitive resin pattern 65 used for selective pattern formation of the connection layer 91 and the pixel electrode 22 as a mask, the source electrode 12 ″ excluding the connection layer 91 and the auxiliary signal line 92 are irradiated with light while irradiating light. The drain electrode 21 excluding the picture element electrode 22 is anodized to form an oxide layer on the surface of these electrodes.

Regarding the configuration of the scanning line terminal electrode 6, a transparent conductive terminal electrode 6 'may be formed including a part of the scanning line 11 exposed at the same time, or the transparent conductive layer may be removed. The exposed part of the scanning line 11 is connected to the terminal electrode 6.
It can also be.

By performing selective anodic oxidation in the glass substrate 2, a part of the source electrode 12 ″ (signal line) can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. Further, it is also possible to obtain a terminal electrode 92 'made of the same material as the scanning line 11 or a terminal electrode 5' made of a transparent conductive layer formed including the same. In the case of a conventional anodic oxidation method such as immersion, the signal line 12 ″ is used unless an appropriate mask material is used in combination.
Cannot be selectively anodized, and the terminal electrode 5 ′ made of a transparent conductive layer is formed including a part of the source electrode 12 ″ in a region outside the image display unit as shown separately. This configuration corresponds to the picture element electrode 22 shown in FIG.
And the drain electrode 21 are connected in the same manner. Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the eighth embodiment of the present invention.

Also in the eighth embodiment, the thickness of the source / drain electrodes cannot be increased so much to cope with the lift-off. In the ninth embodiment, the second, fifth and fifth layers are formed to reduce the resistance of the wiring. As in the sixth embodiment, a low-resistance signal line is separately formed. In a ninth embodiment, that is, a method for manufacturing an active substrate according to claim 18,
As shown in FIG.
Until the 2 ″ and 21 are selectively formed and the organic insulating layer 72 is formed on the surface of the exposed scanning line 106 and part of the gate 105, the process proceeds in the same manufacturing process as in the eighth embodiment.

Then, using a vacuum film forming apparatus such as SPT or the like, an AL thin film layer 35 having a thickness of about 0.2 to 0.6 μm as a low resistance wiring layer, and a Ta film as an intermediate conductive layer having a thickness of about 0.1 μm.
The heat-resistant metal thin film layer 36 is sequentially applied. Then, these two metal layers are sequentially etched by a fine processing technique using a photosensitive resin pattern to form the signal line 12 including the source electrode 12 ″ of the insulated gate transistor as shown in FIG. At this time, since the scanning line 11 is exposed in a region outside the image display unit, the scanning line material is AL.
In the case of a system alloy, it is necessary to leave the AL thin film layer on the exposed part of the scanning line 11 (the area where the terminal electrode 6 is formed) as shown in FIG. There is. In FIG. 18 (i), when the scanning line 11 is formed of, for example, a layer of AL / Ta, the Ta thin film serves as a mask at the time of etching the AL thin film layer 35 to protect the underlying AL.
1 exemplifies a case in which it does not disappear.

Subsequently, as shown in FIG. 18 (j), a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm is formed on the entire surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, using ITO (I
Then, a pixel electrode 22 including a drain electrode 21 is selectively formed on the insulating substrate 2 by a fine processing technique.

Using the photosensitive resin pattern 65 used for the selective pattern formation of the pixel electrodes 22 as a mask, the signal lines 12 and the source electrodes 12 ″ excluding the signal lines and the pixel electrodes 22 are removed while irradiating light. The drain electrode 21 is anodized to form an oxide layer on the surface of these electrodes.

By performing selective anodic oxidation in the glass substrate 2, a part of the signal line 12 can be used as the terminal electrode 5 in a region outside the image display section as shown in FIG. In this case, the signal line 12 does not necessarily have to be a laminate of the low resistance wiring layer and the intermediate conductive layer 36, and there is no problem with a single layer of the AL thin film layer 35 as the low resistance wiring layer. With a conventional anodic oxidation method in which the entire glass substrate 2 is immersed in a chemical conversion solution, the signal line 12 cannot be selectively anodized unless an appropriate mask material is used in combination. The terminal electrode 5 ′ made of a transparent conductive layer in a region outside the image display unit is formed including a part of the signal line 12. Finally, the photosensitive resin pattern 65 is removed to complete the active substrate 2 as shown in FIG.

The terminal electrode 6 of the scanning line includes a part of the scanning line 11 exposed at the time of forming the signal line 12 and is formed by laminating the AL thin film layer 35 and the refractory metal thin film layer 36 of Ta. 6 "can be formed, AL
A portion of the scanning line 11 exposed by removing the lamination of the thin film layer 35 and the heat-resistant metal thin film layer 36 of Ta may be used as the terminal electrode 6, or a transparent conductive material including the exposed portion of the scanning line 11 may be used. A terminal electrode 6 ′ having a characteristic property can also be formed. The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, thereby completing the ninth embodiment of the present invention.

Regarding the configuration of the storage capacitor 15, an example is shown in which the storage electrode 21 'formed simultaneously with the signal line 12 including the drain electrode 21 and the storage capacitor line 16 are formed via the organic insulating layer 72. 17, the storage capacity 1
The configuration of the pixel electrode 22 is not limited to this.
And the scanning line 11 in the preceding stage. Other configurations are also possible, but detailed description is omitted.

The polyimide thin film which is an organic insulating layer employed in the present invention has a certain resistance to an organic resist stripping solution, but is not sensitive to a stripping means such as an oxygen plasma treatment or a high-concentration ozone aqueous solution. Therefore, it is necessary to restrict and pay attention to resist stripping.

[0148]

As described above, according to the liquid crystal image display device of the present invention, the source / drain made of an amorphous silicon layer containing (implanted) impurities in a self-aligned manner on the gate pattern edge. And a source / drain electrode made of a heat-resistant metal can be formed, so that the parasitic capacitance of the insulated gate transistor can be reduced to a value one-several of the conventional value. As a result, even in a large-screen, high-definition liquid crystal image display device, a special effect is obtained in which flicker, printing, or display unevenness is less likely to occur.

Next, since the passivation formation according to the present invention does not involve a special heating step, an insulated gate transistor using an amorphous silicon layer as a semiconductor layer does not require excessive heat resistance. In other words, the effect of preventing the electrical performance from being deteriorated by the passivation is obtained. In some cases, it is also possible to adopt a single-layer AL source / drain electrode without interposing a heat-resistant barrier metal layer.

Further, by making the auxiliary signal lines formed of the same members as the scanning lines function as the signal lines, the resistance of the signal lines can be reduced without increasing the number of manufacturing steps, and the screen can be enlarged. Was. In addition, by introducing an organic insulating layer by electrodeposition, it is possible to simultaneously perform the source / drain electrode forming step and the opening forming step on the gate insulating layer. Excellent effects such as further reduction and promotion of reduction of manufacturing cost were obtained.

As is clear from the above description, the requirement of the present invention is not limited to forming a scanning line by etching a gate metal layer, a gate insulating layer, a semiconductor layer, a protective insulating layer, and a lift-off layer all at once. The point is that the organic insulating layer is formed by electrodeposition on the side surface of the exposed scanning line, and the source / drain electrodes are formed by retreating (reducing the film thickness) and lift-off of the photosensitive resin pattern used for forming the scanning line. It is self-evident that semiconductor devices for image display devices having different materials and film thicknesses of picture element electrodes, gate metal layers, gate insulating layers, etc., and differences in manufacturing methods thereof also belong to the scope of the present invention. IPS (In-Plain-Switchi) which controls by applying a horizontal electric field to the liquid crystal between a pixel electrode and a counter electrode formed at a predetermined distance on the same substrate.
The present invention can be easily applied to a liquid crystal panel of the ng) type. For example, in the semiconductor device for an image display device according to the third embodiment shown in FIG. An electrode (common capacitance line) 16 is formed at a predetermined distance from the drain (picture element) electrode 21, and a region (double hatched portion) where the drain electrode 21 and the counter electrode 16 overlap with a gate insulating layer interposed therebetween is formed. An example in which a storage capacitor is formed is illustrated. In addition, the usefulness of the present invention is not changed even in a reflection type liquid crystal image display device using a picture element electrode as a metal electrode (in the claims, both a transparent conductive layer and a metal reflection layer are expressed by a conductive thin film). It is obvious that, since a transparent conductive layer is not required, a signal line forming step for lowering resistance and a reflective electrode forming step can be performed simultaneously. The same applies to a transflective liquid crystal image display device that requires both a transparent conductive (transmissive) picture element electrode and a reflective electrode. Also, the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon, and it is apparent that microcrystalline silicon, polycrystalline silicon, or a mixed crystal thereof does not cause any problem.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for an image display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the first embodiment of the present invention;

FIG. 3 is a plan view of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a second embodiment of the present invention.

FIG. 5 is a plan view of a semiconductor device for an image display device according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the third embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fourth embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device for an image display device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor device for an image display device according to a sixth embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor device for an image display device according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the seventh embodiment of the present invention.

FIG. 15 is a plan view of a semiconductor device for an image display device according to an eighth embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device for an image display device according to the eighth embodiment of the present invention.

FIG. 17 is a plan view of a semiconductor device for an image display device according to a ninth embodiment of the present invention;

FIG. 18 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the ninth embodiment of the present invention.

FIG. 19 is a diagram showing a mounting state of a liquid crystal panel.

FIG. 20 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 21 is a sectional view of a main part of a liquid crystal panel.

FIG. 22 is a plan view of a conventional active substrate.

FIG. 23 is a sectional view showing a manufacturing process of a conventional active substrate.

FIG. 24 is a plan view of a streamlined active substrate.

FIG. 25 is a sectional view of a manufacturing process of a streamlined active substrate.

FIG. 26 is a view showing a pattern arrangement when forming an organic insulating layer on the side of a scanning line according to the present invention.

FIG. 27 is a plan view of a semiconductor device for an IPS image display device according to the present invention.

[Explanation of symbols]

Reference Signs List 1 liquid crystal image display device (liquid crystal panel) 2 active substrate (insulating substrate, glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 terminal electrode 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line ( (Gate) 12 (12 ′, 12 ″) signal line (source electrode) 16 common capacitance line 17 liquid crystal 21 drain electrode 22 (transparent conductive) picture element electrode 30 gate insulating layer (first SiNx layer) 31 impurity Amorphous silicon layer 32 which is not included (which is a first semiconductor layer) 32 (which is an insulating layer for protecting a channel)
Nx layer 33 Amorphous silicon layer containing impurities (second semiconductor layer) 34 Heat resistant metal layer (anodizable) 35 Low resistance metal layer (AL) (anodizable) 36 (anodizable) ) Intermediate conductive layer 37 Passivation insulating layer 40 Lift-off layer 61 Opening (on auxiliary signal line) 62 Opening (on drain electrode) 63 Opening (on scanning line) 64 Opening (on signal line) 65 (pixel electrode) Photosensitive resin pattern (formed) 66 Impurity-free silicon oxide layer 67 Impurity-containing silicon oxide layer 68 5 Tantalum oxide (Ta2O5) 69 Alumina (Al2O3) 71 Organic insulating layer 72 formed on the side surface of gate (scanning line) 72 Organic insulating layer formed on the surface of a gate (scanning line) 80 First metal layer 81 Ions (and radicals) of impurity (phosphorus) 91 (divided source electrode) Connected to) the connecting layer 92 the auxiliary signal line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 616V 617J F term (Reference) 2H092 JA26 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA05 KA07 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA27 NA29 5C094 AA02 AA03 AA43 AA44 BA23 BA43 CA19 CA24 DA14 DA15 EA04 EA05 EA06 EA07 EB02 FB12 FB14 FB15 GB10 5F110 AA02 A03A04 A03A04 EE44 FF03 FF30 GG02 GG15 GG22 GG25 GG35 GG45 HJ01 HJ12 HJ13 HK03 HK04 HK06 HK21 HK22 HK33 HL07 NN02 NN12 NN24 NN27 NN35 NN72 QQ02 QQ04 QQ11 QQ14

Claims (18)

[Claims] 1. A gate comprising at least one metal layer having a gate insulating layer on its surface and an organic insulating layer on its side surface, wherein the gate is thinner than the gate via a gate insulating layer and contains no impurities. A semiconductor layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer are formed in a self-aligned manner, a protective insulating layer is formed over the semiconductor layer containing no impurities, and formed over the pair of semiconductor layers. An insulated gate transistor comprising a metal layer serving as a source / drain electrode. 2. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scan line formed of at least one metal layer having the following characteristics, and also serving as a gate of an insulated gate transistor; and a semiconductor layer thinner than the gate and containing no impurities on the gate via a gate insulating layer; A pair of semiconductor layers containing impurities is formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source electrode (signal line) is formed on a drain electrode and a scan line except a scan electrode and a source electrode on the insulating substrate, and a first opening and a source are formed on the drain electrode. (Signal line)
A passivation insulating layer having a pair of second openings is formed on the entire surface of the electrode, and the source electrode (signal line including the first opening and the pixel electrode separated from the second opening) is separated. A) a liquid crystal image display device, wherein a connection layer for connecting electrodes is formed on a passivation insulating layer. 3. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scan line formed of at least one metal layer having the following characteristics, and also serving as a gate of an insulated gate transistor; and a semiconductor layer thinner than the gate and containing no impurities on the gate via a gate insulating layer; A pair of semiconductor layers containing impurities is formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode made of a metal layer is formed on the insulating substrate, and a signal line made of one or more metal layers including the source electrode is formed on the insulating substrate, and an opening is formed on the drain electrode. A liquid crystal image display device, wherein a passivation insulating layer having: is formed on the entire surface, and a picture element electrode is formed on the passivation insulating layer including the opening. 4. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scan line formed of at least one metal layer having the following characteristics, and also serving as a gate of an insulated gate transistor; and a semiconductor layer thinner than the gate and containing no impurities on the gate via a gate insulating layer; A semiconductor layer containing a pair of impurities is formed in a self-aligned manner in contact with the semiconductor layer; a protective insulating layer is formed on the semiconductor layer containing no impurities; A drain electrode made of one or more metal layers that can be anodized and a source (signal line) electrode except on a scanning line, and a pixel electrode including the drain electrode on the insulating substrate And a connection layer for connecting the separated source (signal line) electrode, and an anodic oxide layer is formed on the surface of the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode. Liquid crystal image display device. 5. An insulating substrate in which unit pixels having at least an insulated gate transistor on one main surface and a pixel electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, one or more anodically oxidizable metal layers are formed on one main surface of the insulating substrate. A scanning line which has a gate insulating layer on the surface and an organic insulating layer on the side surface and also serves as a gate of an insulated gate transistor, has a gate insulating layer on the surface and an anodic oxide layer on the side surface, and has openings at both ends. An auxiliary signal line is formed, and a semiconductor layer thinner than the gate and containing no impurity over the gate via a gate insulating layer and a semiconductor containing a pair of impurities in contact with the semiconductor layer Are formed in a self-aligned manner, a protective insulating layer is formed on the semiconductor layer containing no impurity, and a source and / or a source layer comprising at least one anodizable metal layer on the pair of semiconductor layers and on the insulating substrate. A drain electrode is formed, and a connection layer for connecting a pixel electrode including the drain electrode and the auxiliary signal line separated including the opening and the source electrode is formed on the insulating substrate. A liquid crystal image display device, wherein an anodized layer is formed on the surface of the source electrode except for the source electrode and the drain electrode except for the pixel electrode. 6. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, a gate insulating layer is formed on one main surface of the insulating substrate and an organic insulating layer is formed on a side surface thereof. A scan line formed of at least one metal layer having the following characteristics, and also serving as a gate of an insulated gate transistor; and a semiconductor layer thinner than the gate and containing no impurities on the gate via a gate insulating layer; A semiconductor layer containing a pair of impurities is formed in a self-aligned manner in contact with the semiconductor layer; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode made of an anodizable metal layer is formed on the insulating substrate and on the insulating substrate.
A signal line composed of at least one metal layer; a pixel electrode including the drain electrode on an insulating substrate; and a surface of the drain electrode excluding the source electrode and the pixel electrode excluding the signal line and the signal line. A liquid crystal image display device, wherein an anodized layer is formed on the liquid crystal image display device. 7. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter facing the insulating substrate, a channel and a source (signal line).
A scanning line which is formed of at least one metal layer having an organic insulating layer on its surface except for the area under the drain electrode and also serves as a gate of the insulated gate transistor is formed, and the width of the scanning line is larger than the gate over the gate via the gate insulating layer A thin semiconductor layer containing no impurities and a pair of semiconductor layers containing impurities in contact with the semiconductor layer are formed in a self-aligned manner; a protective insulating layer is formed on the semiconductor layer containing no impurities; A drain electrode made of an anodizable metal layer and a source (signal line) electrode are formed on the insulating substrate except on the scanning line, and the pixel electrode including the drain electrode is separated from the picture element electrode on the insulating substrate. A connection layer for connecting the source (signal line) electrode is formed, and an anodic oxide layer is formed on the surface of the source electrode excluding the connection layer and the drain electrode excluding the pixel electrode. Liquid crystal image display device comprising. 8. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, the surface of the insulating substrate is formed on one main surface of the insulating substrate except for between channels and below source and drain electrodes. A scanning line which is formed of one or more metal layers capable of anodization and has an organic insulating layer and also serves as a gate of the insulated gate transistor, and an auxiliary signal line having an anodized layer on its surface except for both end portions are formed, A semiconductor layer, which is narrower than the gate and contains no impurities, is formed on the gate via a gate insulating layer and a semiconductor layer containing a pair of impurities in contact with the semiconductor layer is self-aligned. A protective insulating layer is formed on the semiconductor layer containing no impurities; source / drain electrodes made of an anodizable metal layer are formed on the pair of semiconductor layers and on the insulating substrate; A connection layer for connecting the divided auxiliary signal lines including the drain electrode and the both ends and the source electrode including the drain electrode is formed thereon, and the source electrode and the pixel electrode excluding the connection layer are formed. A liquid crystal image display device, wherein an anodized layer is formed on the surface of the drain electrode except for the surface. 9. An insulating substrate in which unit picture elements having at least an insulated gate transistor on one main surface and a picture element electrode connected to a drain of the insulated gate transistor are arranged in a two-dimensional matrix; In a liquid crystal image display device in which liquid crystal is filled between the insulating substrate and a transparent insulating substrate or a color filter opposed to the insulating substrate, the surface of the insulating substrate is formed on one main surface of the insulating substrate except for between channels and below source and drain electrodes. A scan line formed of at least one metal layer having an organic insulating layer and also serving as a gate of the insulated gate transistor; and a semiconductor layer which is narrower than the gate and contains no impurities via the gate insulating layer on the gate. A semiconductor layer containing a pair of impurities is formed in self-alignment with the semiconductor layer; a protective insulating layer is formed on the semiconductor layer containing no impurities; A source / drain electrode made of an anodizable metal layer is formed on the pair of semiconductor layers and the insulating substrate, and the source / drain electrode including the source electrode is formed on the insulating substrate.
A signal line composed of at least one metal layer; a pixel electrode including the drain electrode on an insulating substrate; and a surface of the drain electrode excluding the source electrode and the pixel electrode excluding the signal line and the signal line. A liquid crystal image display device, wherein an anodized layer is formed on the liquid crystal image display device. 10. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming an impurity, implanting an impurity into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, removing the lift-off layer, and forming a second metal layer on the lift-off layer. And selectively removing the drain electrode and the separated source (signal line) electrode made of the second metal layer on the semiconductor layer into which impurities are implanted on the gate and on the insulating substrate. Forming a passivation layer, and applying a passivation insulating layer,
Forming an opening on the drain electrode and on the source (signal line) electrode, selectively removing a passivation insulating layer in the opening, and applying a conductive thin film;
A connection layer for connecting a pixel electrode including an opening on the drain electrode and a source (signal line) electrode including an opening on the source (signal line) electrode on the passivation insulating layer is selected. Forming a semiconductor device for an image display device. 11. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming an impurity, implanting an impurity into the first semiconductor layer using the lift-off layer as a mask, depositing a second metal layer, removing the lift-off layer, and forming a second metal layer on the lift-off layer. Selectively removing the metal layer of (a), and selectively forming source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Depositing at least a third metal layer, selectively forming a signal line made of a third metal layer including the source electrode, and depositing a passivation insulating layer; Forming an opening on the drain electrode to selectively remove the passivation insulating layer in the opening, applying a conductive thin film, and including the opening on the drain electrode on the passivation insulating layer. Select a pixel electrode Method of manufacturing an image display apparatus for a semiconductor device having a step of formed. 12. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming a, a step of implanting an impurity by the lift-off layer as a mask to the first semiconductor layer, a step of depositing the anode second metal layer oxidizable,
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selecting a source electrode (signal line) electrode separated from the drain electrode made of the second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Forming a conductive thin film, applying a conductive thin film, and separating a source (signal line) electrode including the picture element electrode including the drain electrode and the source (signal line) electrode on the insulating substrate. Selectively forming a connection layer for connecting the pixel electrode, and forming the connection layer while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. Forming a anodic oxide layer on the source electrode except for the source electrode and the drain electrode except for the picture element electrode. 13. A step of depositing one or more anodically oxidizable first metal layers on one main surface of an insulating substrate, and a step of forming a portion of the first metal layer at a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except for the step of: forming a gate of an insulated gate transistor on the lift-off layer; Selectively forming a photosensitive resin pattern corresponding to the scanning line and the auxiliary signal line also serving as a lift-off layer using the photosensitive resin pattern as a mask, a protective insulating layer,
Sequentially etching the first semiconductor layer, the gate insulating layer and the first metal layer; reducing the thickness of the photosensitive resin pattern to partially expose the lift-off layer; Etching a lift-off layer and a protective insulating layer sequentially using a conductive resin pattern as a mask to partially expose the first semiconductor layer; forming an organic insulating layer on a side surface of the scan line; Implanting impurities into the semiconductor layer using the layer as a mask, and forming openings on the scanning lines outside the image display area and at both ends of the auxiliary signal lines to form a first layer which does not include the lift-off layer, the protective insulating layer, and the impurities. Selectively removing the semiconductor layer and the gate insulating layer; applying an anodically oxidizable second metal layer; and selectively removing the second metal layer on the lift-off layer together with the removal of the lift-off layer. Before and after A step of selectively forming source / drain electrodes made of a second metal layer on a semiconductor layer into which impurities are implanted and on an insulating substrate; a step of depositing a conductive thin film; A step of selectively forming a pixel electrode including an electrode and a connection layer for connecting the divided auxiliary signal line including the opening and the source electrode, and a step of selectively forming a pattern of the pixel electrode. Forming an anodized layer on a source electrode excluding a connection layer and a drain electrode excluding a pixel electrode while irradiating light while protecting the pixel electrode using the photosensitive resin pattern as a mask. A method for manufacturing a semiconductor device. 14. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming a, a step of implanting an impurity by the lift-off layer as a mask to the first semiconductor layer, a step of depositing the anode second metal layer oxidizable,
With the removal of the lift-off layer, a second
Selectively removing the metal layer, and selectively forming a pair of source / drain electrodes made of the second metal layer on the insulating substrate on the semiconductor layer into which impurities on the gate have been implanted. Forming an opening on a scanning line in a region outside the image display unit and selectively removing a gate insulating layer on the scanning line;
Depositing one or more third metal layers that can be anodized, selectively forming a signal line comprising the third metal layer including the source electrode, and depositing a conductive thin film. And selectively forming a pixel electrode including the drain electrode on an insulating substrate, and forming a pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. Forming a anodic oxide layer on a signal line, a source electrode excluding the signal line, and a drain electrode excluding the picture element electrode while irradiating light while protecting the semiconductor device for an image display device. 15. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming a, a step of implanting an impurity by the lift-off layer as a mask to the first semiconductor layer, a step of depositing the anode second metal layer oxidizable,
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selectively forming a pair of source / drain electrodes made of the second metal layer on the semiconductor layer and the insulating substrate on which impurities are implanted on the gate. Applying one or more third metal layers that can be anodized, selectively forming a signal line made of the third metal layer including the source electrode, Forming an opening on a scanning line in a region and selectively removing a gate insulating layer on the scanning line; applying a conductive thin film; and selecting a pixel electrode including the drain electrode on an insulating substrate. Forming a signal line and excluding the signal line and the signal line while irradiating light while protecting the picture element electrode using the photosensitive resin pattern used for the selective pattern formation of the picture element electrode as a mask. An anodic oxide layer is formed on the drain electrode except the element electrode. Method of manufacturing an image display apparatus for a semiconductor device having a step of. 16. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming a, a step of implanting an impurity by the lift-off layer as a mask to the first semiconductor layer, a step of depositing the anode second metal layer oxidizable,
With the removal of the lift-off layer, a second
Selectively removing the metal layer of (a), and selecting a source electrode (signal line) electrode separated from the drain electrode made of the second metal layer on the semiconductor layer into which impurities on the gate are implanted and on the insulating substrate. Exposing the scanning lines except between the source and drain electrodes and under the source and drain electrodes, and forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit, A step of applying a conductive thin film, and a step of selectively forming, on an insulating substrate, a connection layer that connects the separated source electrode including the pixel electrode and the source electrode including the drain electrode, The photosensitive resin pattern used for the selective pattern formation of the picture element electrode is used as a mask to protect the picture element electrode while irradiating light while anodic oxidizing the source electrode except the connection layer and the drain electrode excluding the picture element electrode. Layers Method of manufacturing an image display apparatus for a semiconductor device having a step of forming. 17. A step of depositing one or more anodically oxidizable first metal layers on one main surface on an insulating substrate, and forming a portion of the first metal layer on a peripheral portion of the insulating substrate. Depositing a lift-off layer after sequentially depositing at least one gate insulating layer, a first semiconductor layer containing no impurities, and a protective insulating layer except for the step of: forming a gate of an insulated gate transistor on the lift-off layer; Selectively forming a photosensitive resin pattern corresponding to a scanning line and an auxiliary signal line also serving as a lift-off layer, a protective insulating layer, a first semiconductor layer, a gate insulating layer, and a second insulating layer using the photosensitive resin pattern as a mask. (A) sequentially etching the metal layer, (b) reducing the film thickness of the photosensitive resin pattern to partially expose the lift-off layer, and using the reduced photosensitive resin pattern as a mask to protect the lift-off layer and the protective insulation. Layers and order Etching to partially expose the first semiconductor layer, forming an organic insulating layer on the side surface of the scan line, and injecting impurities into the first semiconductor layer using the lift-off layer as a mask. Depositing a second metal layer capable of being anodized, selectively removing the second metal layer on the lift-off layer while removing the lift-off layer, and implanting impurities on the gate. The source / drain electrodes made of the second metal layer are selectively formed on the semiconductor layer and the insulating substrate, and the scanning lines and the auxiliary signal lines are formed except between the source / drain electrodes and under the source / drain electrodes. Exposing, forming an organic insulating layer on exposed scanning lines and gates in the image display unit, applying a conductive thin film, and forming a picture element including the drain electrode on an insulating substrate. Both electrodes and auxiliary signal lines Selectively forming a connection layer for connecting the source electrode comprise parts,
A source electrode, an auxiliary signal line, and a drain electrode excluding a pixel electrode except for a connection layer while irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. And a step of forming an anodic oxide layer. 18. One or more first layers on one main surface of an insulating substrate.
Depositing at least one gate insulating layer, an impurity-free first semiconductor layer, and a protective insulating layer except for a part of the first metal layer at a peripheral portion of the insulating substrate. Sequentially applying a lift-off layer after sequentially applying, and selectively forming a photosensitive resin pattern corresponding to a scanning line also serving as a gate of an insulated gate transistor on the lift-off layer; and A step of sequentially etching the lift-off layer, the protective insulating layer, the first semiconductor layer, the gate insulating layer, and the first metal layer using the pattern as a mask; An exposing step, a step of sequentially etching the lift-off layer and the protective insulating layer by using the photosensitive resin pattern whose film thickness has been reduced as a mask to partially expose the first semiconductor layer, Organic insulation Forming a, a step of implanting an impurity by the lift-off layer as a mask to the first semiconductor layer, a step of depositing the anode second metal layer oxidizable,
With the removal of the lift-off layer, a second
And selectively forming a pair of source / drain electrodes made of a second metal layer on the semiconductor layer into which impurities on the gate have been implanted and on the insulating substrate. A step of exposing the scanning lines except between the drain electrodes and below the source / drain electrodes; a step of forming an organic insulating layer on the exposed scanning lines and the gate in the image display unit; A step of depositing the third metal layer, a step of selectively forming a signal line made of the third metal layer including the source electrode, a step of depositing a conductive thin film, Selectively forming a pixel electrode including the drain electrode thereon, and irradiating light while protecting the pixel electrode using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode as a mask. While removing signal lines and signal lines. Method of manufacturing an image display apparatus for a semiconductor device having a step of forming an anodic oxide layer to the drain electrode, except for the source electrode and the pixel electrode.