JP4871507B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device.

With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, and the like, television images and various image display devices are provided in large quantities on a commercial basis in a 5-75 cm diagonal liquid crystal display device. In addition, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, a so-called active liquid crystal panel in which a switching element is incorporated for each picture element guarantees an image having a low contrast and a fast response speed and a high contrast ratio.

These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 300 to 1600 signal lines, but recently, a large screen is required to cope with an increase in display capacity. And high definition are progressing simultaneously.

FIG. 7 shows a state of mounting on a liquid crystal panel, and a semiconductor integrated circuit that supplies a drive signal to an electrode terminal group 5 of a scanning line formed on one transparent insulating substrate, for example, a glass substrate 2, constituting the liquid crystal panel 1. A COG (Chip-On-Glass) system in which the chip 3 is connected using a conductive adhesive, or a TCP film 4 having terminals of gold or solder-plated copper foil based on, for example, a polyimide resin thin film as a signal An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) method in which the electrode terminal group 6 of the wire is fixed by being pressed with an appropriate adhesive containing a conductive medium. Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.

Wiring paths 7 and 8 connect the pixels in the image display unit located almost at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 of the scanning lines and signal lines, and are not necessarily the same as the electrode terminal groups 5 and 6. It is not necessary to be made of a conductive material. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

FIG. 8 shows an equivalent circuit diagram of an active liquid crystal display device in which insulated gate transistors 10 are arranged for each picture element as a switching element, 11 (7 in FIG. 7) is a scanning line, and 12 (8 in FIG. 7) is a signal. A line 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. Elements drawn with solid lines are formed on one glass substrate 2 constituting a liquid crystal panel, and the counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is the main electrode facing the other glass substrate 9. It is formed on the surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a storage capacitor serving as a common bus for the storage capacitor 15.

FIG. 9 is a cross-sectional view of the main part of the image display portion of the liquid crystal display device, and the two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of resin fibers, beads, or the same resin formed on the color filter 9. Formed by a spacer material (not shown) such as a porous columnar spacer at a predetermined distance of about several μm, and the gap (gap) is a sealing material and a sealing material made of an organic resin at the peripheral edge of the glass substrate 9. It is a closed space sealed with (not shown), and this closed space is filled with liquid crystal 17.

In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is also called a color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use a TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.

The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. It is a technology that is fixed as a so-called black matrix (Black Matrix abbreviation is BM).

Here, a structure and a manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently widely used, and one of them called etch stop type is introduced as a conventional example. FIG. 10 is a plan view of unit picture elements of an active substrate (semiconductor device for display device) that constitutes a conventional liquid crystal panel, on the lines AA ′, BB ′, and CC ′ of FIG. FIG. 11 shows a cross-sectional view of this, and the manufacturing process will be briefly described below.

First, as shown in FIG. 10 (a) and FIG. 11 (a), a glass substrate 2 having a thickness of about 0.5 to 1.1 mm as an insulating substrate having high heat resistance, chemical resistance and transparency, for example, Corning A first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of a product name 1737 manufactured by using a vacuum film forming apparatus such as SPT (sputtering), and gates are formed by a fine processing technique. The scanning lines 11 and the storage capacitor lines 16 that also serve as the electrodes 11A are selectively formed. The scanning line material is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and conductivity. Generally, a metal or alloy having high heat resistance such as Cr, Ta, or MoW alloy is used. The

It is reasonable to use AL (aluminum) as the scanning line material to reduce the resistance value of the scanning line in response to the increase in the screen size and resolution of the liquid crystal panel. Since it is low, it is a common technique to stack with Cr, Ta, Mo or their silicides as mentioned above, or to add an oxide layer (Al 2 O 3) by anodic oxidation on the surface of AL. That is, the scanning line 11 is composed of one or more metal layers.

Next, a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma sieve fluid) apparatus, and a first serving as a channel of an insulated gate transistor containing almost no impurities. An amorphous silicon (a-Si) layer 31, a second SiNx layer 32 serving as an insulating layer for protecting the channel, and three kinds of thin film layers, for example, a film of about 0.3-0.05-0.1 μm After sequentially depositing with a thickness, as shown in FIGS. 10B and 11B, the second SiNx layer on the gate electrode 11A is selectively left narrower than the gate electrode 11A by a microfabrication technique. As a protective insulating layer 32D, the first amorphous silicon layer 31 is exposed.

Subsequently, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface using a PCVD apparatus in a thickness of about 0.05 μm, for example, and then FIG. 10C and FIG. ) Using a vacuum film-forming apparatus such as SPT, as a heat-resistant metal layer having a film thickness of about 0.1 μm, for example, a thin film layer 34 of Ti, Cr, Mo or the like, and a film having a thickness of 0.3 μm as a low-resistance metal layer. For example, a Ti thin film layer 36 is sequentially deposited as an intermediate thin film layer having a thickness of about 0.1 μm, and these three kinds of thin film layers 34A, which are source / drain wiring materials, are formed by a fine processing technique. A source electrode 12 that also serves as a signal line and a drain electrode 21 of an insulated gate transistor including a stack of 35A and 36A are selectively formed. In this selective pattern formation, the Ti thin film layer 36, the AL thin film layer 35, and the Ti thin film layer 34 are sequentially etched using the photosensitive resin pattern used for forming the source / drain wiring as a mask, and then the source / drain electrodes 12, The second amorphous silicon layer 33 between the two regions 21 is removed to expose the second SiNx layer 32D, and the first amorphous silicon layer 31 is also removed in other regions to form the gate insulating layer 30. Made by exposing. Since the second SiNx layer 32D serving as the channel protective layer exists in this manner and the etching of the second amorphous silicon layer 33 is automatically terminated, this manufacturing method is called an etch stop.

Further, after removing the photosensitive resin pattern, a SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus in the same manner as the gate insulating layer. As the insulating layer 37, as shown in FIGS. 10D and 11D, the passivation insulating layer 37 is selectively removed by a microfabrication technique, and an opening 62 is formed on the drain electrode 21 and outside the image display portion. In this region, an opening 63 is formed on the scanning line 11 and an opening 64 is formed on the signal line 12 to expose the drain electrode 21, the scanning line 11, and a part of the signal line 12. Similarly, an opening 65 is formed on the electrode pattern in which the storage capacitor lines 16 are bundled in parallel to expose a part of the storage capacitor line 16.

Finally, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIG. 10E and FIG. 11E, the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening 62 by a microfabrication technique to complete the active substrate 2. A part of the exposed scanning line 11 in the opening 63 may be used as the electrode terminal 5 and a part of the exposed signal line 12 in the opening 64 may be used as the electrode terminal 6. As shown in FIG. The electrode terminals 5A and 6A made of ITO may be selectively formed on the passivation insulating layer 37 including 63 and 64. Usually, however, the transparent conductive short-circuit line 40 connecting the electrode terminals 5A and 6A is also provided. Formed simultaneously. The reason is that although not shown, the resistance between the electrode terminals 5A and 6A and the short-circuit line 40 can be increased in resistance by increasing the resistance by forming an elongated stripe. Similarly, although no number is given, an electrode terminal to the storage capacitor line 16 is formed including the opening 65.

When the wiring resistance of the signal line 12 does not become a problem, the low resistance wiring layer 35 made of AL is not necessarily required. In this case, the source / drain wiring 12 can be selected by selecting a heat-resistant metal material such as Cr, Ta, and Mo. , 21 can be simplified by forming a single layer. As described above, it is important to ensure electrical connection between the source / drain wiring and the second amorphous silicon layer by using a refractory metal layer, and the heat resistance of the insulated gate transistor is a precedent example. Details are described in Japanese Utility Model Publication No. 7-74368. In FIG. 10C, the storage capacitor 15 is formed by a region 50 (shaded portion to the right) where the storage capacitor line 16 and the drain electrode 21 overlap in plan view with the gate insulating layer 30 interposed therebetween. Then, the detailed description is abbreviate | omitted.

Although the detailed process of the five-mask process described above is omitted, it was obtained as a result of streamlining the semiconductor layer islanding process and reducing the contact formation process once. The number of photomasks that required about 7 to 8 sheets has been reduced to 5 at the present time, greatly contributing to the reduction of process costs. In order to reduce the production cost of the liquid crystal display device, it is a well-known development target that it is effective to reduce the process cost in the manufacturing process of the active substrate and the member cost in the panel assembly process and the module mounting process. In order to lower the process cost, there are a process reduction that shortens the process and a cheap process development or replacement with a process. Here, the process is reduced to a four-mask process where an active substrate can be obtained with four photomasks. An example will be described. The four-mask process reduces the number of photo-etching steps by introducing halftone exposure technology. FIG. 12 is a plan view of unit picture elements of an active substrate corresponding to the four-mask process. FIG. 13 is a cross-sectional view taken along the lines AA ′, BB ′, and CC ′. As already described, two types of insulated gate transistors are currently widely used. Here, a channel-etched insulated gate transistor is used.

First, as in the five-mask process, a first metal layer having a thickness of about 0.1 to 0.3 μm is deposited on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. As shown in FIGS. 12A and 13A, the scanning lines 11 and the storage capacitor lines 16 that also serve as the gate electrodes 11A are selectively formed by a fine processing technique.

Next, a SiNx layer 30 that becomes a gate insulating layer, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and an insulating material that contains impurities by using a PCVD apparatus over the entire surface of the glass substrate 2. The second amorphous silicon layer 33 and the three types of thin film layers that are the source and drain of the gate type transistor are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm. Subsequently, using a vacuum film forming apparatus such as SPT, for example, a Ti thin film layer 34 as a heat resistant metal layer having a film thickness of about 0.1 μm, an AL thin film layer 35 as a low resistance metal layer having a film thickness of about 0.3 μm, and a film For example, a Ti thin film layer 36, that is, a source / drain wiring material is sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm, and the signal line 12 also serving as the drain electrode 21 and the source electrode of the insulated gate transistor is formed by a fine processing technique. In this selective pattern formation, the source / drain channel formation region 80B (shaded portion) is formed by a halftone exposure technique as shown in FIGS. 12 (b) and 13 (b). The photosensitive resin patterns 80A, 8 having a film thickness of, for example, 1.5 μm and thinner than the film thickness of 3 μm of the source / drain wiring formation regions 80A (12), 80A (21). A major feature is that 0B is formed.

Since the photosensitive resin patterns 80A and 80B usually use a positive photosensitive resin for the production of a substrate for a liquid crystal display device, the source / drain wiring formation region 80A is black, that is, a Cr thin film is formed. The channel region 80B is gray (halftone), for example, a line and space Cr pattern having a width of about 0.5 to 1 μm is formed, and the other regions are white, that is, a photomask from which the Cr thin film has been removed. Should be used. In the gray area, since the resolution of the exposure machine is insufficient, fine line and space is not resolved, and it is possible to transmit about half of the photomask irradiation light from the lamp light source. The photosensitive resin patterns 80A and 80B having a cross-sectional shape as shown in FIG. 13B can be obtained according to the remaining film characteristics of the photosensitive resin. It is also possible to obtain a photomask having an equivalent function by forming, for example, a MoSi2 thin film having a thickness different from that of the Cr thin film instead of the Cr thin film slit in the gray region.

Using the photosensitive resin patterns 80A and 80B as a mask, as shown in FIG. 12B, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first non-crystalline layer 33 are used. After sequentially etching the crystalline silicon layer 31 to expose the gate insulating layer 30, as shown in FIGS. 12C and 13C, the photosensitive resin pattern 80A, When the film thickness of 80B is reduced by 1.5 μm or more, the photosensitive resin pattern 80B disappears, the channel region is exposed, and the photosensitive resin patterns 80C (12) and 80C (21) whose film thickness is reduced only in the source / drain wiring formation region. Can be left as is. Therefore, the Ti thin film layer, the AL thin film layer, the Ti thin film layer, and the second amorphous film between the source and drain wirings (channel formation region) are again formed using the photosensitive resin patterns 80C (12) and 80C (21) whose thickness has been reduced as a mask. The porous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. Since the source / drain wiring is formed by etching the source / drain wiring material and then leaving the first amorphous silicon layer 31A by about 0.05 to 0.1 μm, it can be obtained by such a manufacturing method. The insulated gate transistor is called a channel etch type. In the oxygen plasma treatment, the resist pattern 80A is reduced to 80C and is preferably converted to 80C. Therefore, it is desirable to increase the anisotropy in order to suppress the change in the pattern dimension. Specifically, the RIE (Reactive Ion Etching) method, An ICP (Inductive Coupled Plasma) method or a TCP (Transfer Coupled Plasma) method oxygen plasma treatment having a high-density plasma source is more desirable.

Further, after removing the photosensitive resin patterns 80C (12) and 80C (21), as shown in FIGS. 12D and 13D, the entire surface of the glass substrate 2 is formed as in the five-mask process. A second SiNx layer having a thickness of about 0.3 μm is deposited as a transparent insulating layer to form a passivation insulating layer 37, on the scanning electrode 11 and the signal line 12 on the drain electrode 21 and in a region outside the image display portion. Openings 62, 63, 64 are respectively formed thereon, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed, and a part of the scanning line is exposed in the opening 63, and the opening 62 is formed. , 64 is removed to expose part of the drain electrode 21 in the opening 62 and part of the signal line in the opening 64.

Finally, for example, ITO or IZO was deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, as shown in FIGS. 12 (e) and 13 (e). As described above, the transparent conductive picture element electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by the fine processing technique to complete the active substrate 2. The electrode terminals are formed on the passivation insulating layer 37 at the same time as the pixel electrodes 22 with transparent conductive electrode terminals 5A and 6A made of ITO.

As already mentioned, the spacer is the member that regulates the gap of the liquid crystal cell. Historically, it started with an alumina ball with a simple TN liquid crystal panel diameter of about 10 μm, but the alumina ball has high rigidity and gap accuracy. However, there were many problems that the glass substrate was scratched or cracked. In addition, since the active element is formed in the later active type liquid crystal panel, the level difference is large and the gap accuracy is lowered, and above all, the insulated gate transistor is destroyed, so the resin material is used to give the spacer material flexibility. A fiber with a diameter of about 10 μm and a length of about 50 μm has been introduced, and after several years, it has shifted to resin beads from the viewpoint of improving the gap accuracy, and recently in order to further improve the contrast ratio, that is, from the viewpoint of improving the display image quality, A columnar spacer made of resin having high heat resistance is formed. The columnar spacer has a diameter of 10 μm and a height of usually 3 to 5 μm, and its cross-sectional shape is tapered so as not to damage the rubbing cloth.

Since such columnar spacers form resin-made columnar spacers made of a photosensitive resin on a conventional CF using a photo-etching technique, naturally, the number of manufacturing steps and necessary members increase as compared with the conventional CF. Therefore, it is inevitable that the purchase price or production price of CF will rise.

However, liquid crystal TVs, which are expected to develop greatly as large liquid crystal display devices in the future, are fiercely priced. As explained in the previous technology, the four-mask mask that has become possible through the use of halftone exposure technology. Technological development to reduce production costs as in processes is as important as cost reduction of components.

The present invention has been made in view of the present situation, and is intended to reduce the production cost of a liquid crystal display device by forming columnar spacers on an active substrate by concentrating on the manufacturing process of the active substrate.

The liquid crystal display device according to claim 1, comprising at least an insulated gate transistor on one principal surface, and a signal line serves also as the scanning lines and the source electrode serves also as a gate electrode of said insulated gate transistor, connected to the drain electrode a first transparent insulating substrate unit pixel having a pixel electrode are arranged in a two-dimensional matrix, and the first transparent insulating substrate facing the second transparent insulating substrate or a color filter In the liquid crystal display device in which liquid crystal is filled in between, the liquid crystal display device further includes a passivation insulating layer made of an inorganic material formed on the first transparent insulating substrate, and the passivation insulating layer includes a plurality of passivation insulating layers. The passivation insulating layer has a columnar spacer made of a photosensitive organic insulating layer on the surface of the passivation insulating layer, and the columnar spacer has the passivation layer. Characterized in that it at least one aperture and self-alignment of the plurality of different apertures formed in the down insulating layer.

3. The liquid crystal display device according to claim 2, wherein the at least one opening is an opening formed in a passivation insulating layer on the scanning line or an opening formed in a passivation insulating layer on the signal line.

The liquid crystal display device according to claim 3, wherein the columnar spacer has a thickness of 6 μm.
5. The liquid crystal display device according to claim 4, wherein the thickness of the columnar spacer is 3 μm.
6. The liquid crystal display device according to claim 5, wherein the columnar spacer is formed on the signal line.

With these configurations it is possible to function the photosensitive organic insulating layer pattern formed on the active substrate and a columnar space Sa, columnar spacers on CF is not needed.

As described above, according to the present invention, when forming the columnar spacers made of the photosensitive organic insulating layer pattern, the number of manufacturing steps is not increased by utilizing the photolithography process used for forming the portion constituting the active substrate. in which elaborate creativity and ingenuity to.

6. The method of manufacturing a liquid crystal display device according to claim 1, at least, the first transparent insulating substrate, forming a at least a scanning line signal Line interruption edge gate transistor Depositing a passivation insulating layer made of an inorganic material on the first transparent insulating substrate after forming at least the scanning line, the signal line, and the insulated gate transistor in the step; and the passivation insulating layer. Forming a photosensitive organic insulating layer pattern on the surface of the substrate, removing a part of the passivation insulating layer using the photosensitive organic insulating layer pattern as a mask, and forming a plurality of different openings in the passivation insulating layer It is characterized by including .

The method of manufacturing a liquid crystal display device according to claim 7 further includes a step of exposing the passivation insulating layer by reducing a film thickness of the photosensitive organic insulating layer pattern.
According to the method for manufacturing a liquid crystal display device according to an eighth aspect, the photosensitive organic insulating layer patterns have different film thicknesses, and a thick portion of them forms columnar spacers.

The method for producing a liquid crystal display device according to claim 9 is characterized in that the photosensitive organic insulating layer pattern is formed using a halftone exposure method.

The method for manufacturing a liquid crystal display device according to claim 10 is characterized in that the columnar spacers are formed on the signal lines.

The method for manufacturing a liquid crystal display device according to claim 11 further includes a step of forming the pixel electrode on a surface of the passivation insulating layer having a plurality of different openings.

With this configuration, the photosensitive organic insulating layer pattern used for forming the opening in the passivation insulating layer made of an inorganic material can be reduced in thickness so that the photosensitive organic insulating layer pattern remaining on the active substrate can function as a columnar spacer. It becomes possible. On the other hand, since the conventional liquid crystal display device also requires a photolithography process for forming an opening in the passivation insulating layer, the manufacturing cost of the liquid crystal display device is reduced because the manufacturing process is combined with the columnar spacer formation process. To do. In the present invention, since the opening and the columnar spacer are formed using the same photomask as described above, the columnar spacer is self-aligned with the opening, and the relative positions of the columnar spacer and the opening are multifaceted. Further, it is constant and unchanged everywhere in each image display section in the glass substrate 2. That is, when the formation process of the opening and the columnar spacer is compared with a liquid crystal display device manufactured using two photomasks, a phenomenon corresponding to the misalignment of the photomask does not occur.

As described above, in the present invention, the halftone exposure technique is employed in the photolithography process for forming the passivation insulating layer for protecting the active substrate or the photosensitive organic insulating layer on the source / drain wiring that exhibits an equivalent function. Thus, the portion having the passivation function is locally thickened, and the locally thick portion functions as a columnar spacer.

As a result, columnar spacers can be formed on the active substrate without increasing the number of manufacturing steps of the active substrate, and the effect of greatly contributing to the reduction in manufacturing cost of the liquid crystal display device can be obtained.

As is apparent from the above description, the requirement of the present invention is to form a passivation insulating layer that protects the active substrate or a photosensitive organic insulating layer on the source / drain wiring that exhibits an equivalent function when manufacturing the active substrate. By adopting a halftone exposure technique in the photo-etching process, a columnar spacer is formed by locally forming a portion having these passivation functions, and for other configurations, a scanning line, It is obvious that a semiconductor device for a display device having a different material or film thickness, such as a signal line or a gate insulating layer, or a manufacturing method thereof belongs to the category of the present invention, and a liquid crystal display using vertically aligned liquid crystal The usefulness of the present invention does not change even in an apparatus. Further, unlike a TN liquid crystal, an IPS (In-Plane-Switching) that applies a horizontal electric field to a liquid crystal between a pair of pixel electrodes formed on an active substrate and spaced apart from each other by a predetermined distance. The liquid crystal display device according to claim 1 is applicable. However, in this case, it is not necessary to form an opening on the drain electrode (pixel electrode), and the counter electrode is generally formed on the glass substrate simultaneously with the scanning line. The liquid crystal display device according to claim 2 corresponds to an IPS liquid crystal display device with a high aperture ratio in which a pixel electrode and a counter electrode are formed on a thick passivation insulating layer. It is also clear that the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon, and there is no difference depending on the configuration of the insulated gate transistor except for claims 3 and 6.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor device (active substrate) for a display device according to Embodiment 1 of the present invention, and FIG. 2 is on the AA ′ line, the BB ′ line, and the CC ′ line in FIG. Sectional drawing of a manufacturing process is shown. Similarly, FIG. 3 and FIG. 4 show Example 2 and FIGS. 5 and 6 show Example 3 and FIG. 5 and FIG. In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

In Example 1, as in the conventional example, a device was manufactured based on a five-mask process using a channel-etched insulated gate transistor as a switching element, as shown in FIGS. 1 (c) and 2 (c). Thus, the same manufacturing process proceeds until the source / drain wirings 12 and 21 are formed.

After the source / drain wirings 12 and 21 are formed, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer made of an inorganic material using a conventional PCVD apparatus. As shown in FIGS. 1D and 2D, an opening 62 is formed on the drain electrode 21 , and an opening is formed on a part 5 of the scanning line in a region outside the image display section. 63, a photosensitive organic insulating layer having an opening 64 on a part 6 of the signal line, a thickness of the region 85A corresponding to the columnar spacer being 4 μm, and a thickness of the other region 85B being 1 μm. Patterns 85A and 85B are formed by a halftone exposure technique.

In order to control the amount of light transmitted through the photomask in the pattern formation with such a large difference in film thickness, the gray tone mask formed with two types of metal thin film patterns having different transmittances is more suitable than the conventional thin slit pattern. Favorable results are obtained.

Using the photosensitive organic insulating layer patterns 85A and 85B as a mask, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed as in the conventional example, and a part 5 of the scanning line is formed in the opening 63. In addition to being exposed, the passivation insulating layer 37 in the openings 62 and 64 is removed to expose a part of the drain electrode 21 in the opening 62 and a part 6 of the signal line in the opening 64.

Then, when the photosensitive organic insulating layer patterns 85A and 85B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive organic insulating layer pattern 85B is formed as shown in FIGS. 1 (e) and 2 (e). It disappears and the passivation insulating layer 37 is exposed, and the photosensitive organic insulating layer pattern 85 </ b> C whose thickness is reduced only in a predetermined region on the source / drain wirings 12 and 21 can be left as it is.

Finally, for example, ITO, IZO, or a mixed crystal thereof is deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm by using a vacuum film forming apparatus such as SPT, and FIGS. As shown in f), the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening 62 by the microfabrication technique to complete the active substrate 2. The electrode terminals are formed on the passivation insulating layer 37 at the same time as the pixel electrodes 22 with transparent conductive electrode terminals 5A and 6A made of ITO.

The active substrate 2 and the color filter 9 thus obtained are bonded to form a liquid crystal panel, and Example 1 of the present invention is completed. It goes without saying that the photosensitive organic insulating layer pattern 85C having a film thickness of 3 μm functions as the columnar spacer 77 and keeps the gap between the active substrate 2 and the color filter 9 constant.

Unless the liquid crystal is a vertically aligned liquid crystal, an alignment process with a rubbing cloth is usually performed for the alignment process on the alignment film. Therefore, in order to prevent disturbance of the alignment process due to a high step of the columnar spacer 77 in the display image, the columnar spacer 77 is used. Is preferably arranged at a location away from the pixel electrode 22, although not shown, on the drain electrode 21 close to the channel of the insulated gate transistor or on the signal line 12 on the intersection region of the scanning line 11 and the signal line 12. It is best to arrange the columnar spacers 77.

The columnar spacer 77 is a photosensitive organic insulating layer excellent in heat resistance and chemical resistance in order to avoid problems such as damage in the pixel electrode formation process and reduction in film thickness or collapse of the shape. It is necessary to select a photosensitive organic insulating layer whose main component is an acrylic resin or a polyimide resin. Further, since the columnar spacer 77 is in contact with the liquid crystal 17 in the liquid crystal cell, high purity is required in order to prevent impurities from eluting and to deteriorate various characteristics of the liquid crystal.

Although not described in detail, the active substrate on which the transparent conductive pixel electrode is formed prior to the deposition of the passivation insulating layer 37 or the metal layer and the transparent conductive layer after the formation of the passivation insulating layer 37 is described. An active substrate in which an opening is formed on a laminate pattern composed of a laminate and an exposed transparent conductive pixel electrode is obtained by removing the metal layer of the laminate pattern in addition to the passivation insulating layer in the opening However, it is supplemented that the effectiveness of claim 1 (Example 1) does not change. This is because after the passivation insulating layer is formed, it is necessary to expose a part of the scanning line, the signal line, and the drain electrode to provide an electrical connection place, or to form a poor film quality passivation insulating layer on the pixel electrode. This is because a step of forming an opening in the penetration insulating layer is always accompanied with the removal in order to prevent the display image from being burned out.

The present inventor has already filed and filed a wide variety of liquid crystal display devices and active substrates from the viewpoint of process reduction, and the transparent conductive pixel electrode 22 is formed before the formation of the passivation insulating layer. Examples of such active substrates include Japanese Patent Application Nos. 2003-109729, 2003-182006, 2003-282303, and 2003-396557, and a laminated pattern of a metal layer and a transparent conductive layer in addition to the passivation insulating layer in the opening. As an active substrate in which the transparent conductive layer pattern exposed by removing the metal layer is used as the pixel electrode 22, Japanese Patent Application Nos. 2003-182006, 2003-182303, 2003-396558, 2003-396558, 2004-21288, 2004 are available. Detailed examples are described in publications Nos. 21290 and 2004-93945. It has been mounting.
Japanese Patent Application No. 2003-109729 Japanese Patent Application No. 2003-182106 Japanese Patent Application No. 2003-282303 Japanese Patent Application No. 2003-396557 Japanese Patent Application No. 2003-396558 Japanese Patent Application No. 2004-21288 Japanese Patent Application No. 2004-21290 Japanese Patent Application No. 2004-93945

In Example 1, the film thickness of the columnar spacer 77 varies naturally if the uniformity when the photosensitive organic insulating layer is applied and when the film thickness is reduced by oxygen plasma, the variation is naturally caused. Since a variation in film thickness of about ± 0.2 μm may be a problem, a liquid crystal display device in which the thickness variation of the columnar spacer 77 is small will be described in the following examples.

In the second embodiment, as in the first embodiment, the same manufacturing process is performed until the source / drain wirings 12 and 21 are formed as shown in FIGS. 3 (c) and 4 (c).

After the source / drain wirings 12 and 21 are formed, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer made of an inorganic material using a PCVD apparatus. As shown in FIGS. 3D and 4D, the insulating layer 37 is formed, and the opening 62 is formed on the drain electrode 22, and the opening 63 is formed on a part 5 of the scanning line in a region outside the image display unit. The photosensitive organic insulation has an opening 64 on a part 6 of the signal line, the thickness of the region 86A (77) corresponding to the columnar spacer is 6 μm, and the thickness of the other region 86B is 3 μm. Layer patterns 86A and 86B are formed by a halftone exposure technique.

Then, using the photosensitive organic insulating layer patterns 86A and 86B as a mask, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed as in the conventional example, and a part of the scanning line 5 is formed in the opening 63. In addition, the passivation insulating layer 37 in the openings 62 and 64 is removed to expose part of the drain electrode 21 in the opening 62 and part 6 of the signal line in the opening 64. However, when an etch stop type insulated gate transistor having a protective insulating layer on the channel is employed, there is no problem even if the passivation insulating layer 37 is not present. Therefore, formation of the photosensitive organic insulating layer patterns 86A and 86B is not required. Immediately after that, a part of the drain electrode 21 and a part 6 of the signal line are exposed in the openings 62 and 64, and the gate insulating layer 30 in the opening 63 is removed and the scanning line is formed in the opening 63. It is only necessary to expose part 5.

Finally, for example, ITO or IZO was deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, as shown in FIGS. 3 (e) and 4 (e). As described above, the pixel electrode 22 is selectively formed on the photosensitive organic insulating layer pattern 86B including the opening 62 by the fine processing technique, and the active substrate 2 is completed. The electrode terminals are formed on the passivation insulating layer 37 at the same time as the pixel electrodes 22 with transparent conductive electrode terminals 5A and 6A made of ITO.

The active substrate 2 and the color filter 9 thus obtained are bonded to form a liquid crystal panel, and Example 2 of the present invention is completed. The photosensitive organic insulating layer pattern 86 </ b> A having a thickness of 6 μm functions as the columnar spacer 77. The reason why the photosensitive organic insulating layer pattern 86B is formed as thick as 3 μm is that the surface of the active substrate 2 is flattened to facilitate the alignment process, and the pixel electrode 22 overlaps the scanning line 11 and the signal line 12. This is a device for obtaining a liquid crystal display device having a large aperture ratio and a high aperture ratio, which is a well-known technique as a so-called flattening technique. Since 3 μm of the difference in film thickness between the photosensitive organic insulating layer patterns 86A and 86B is the thickness (gap thickness) of the liquid crystal cell, the photosensitive organic insulating layer pattern is controlled by controlling the halftone transmitted light amount of halftone exposure. The film thickness of 86B can be set to 2 μm, and the thickness of the liquid crystal cell can be set to 4 μm. The thickness of the liquid crystal cell determined from the optical design of the liquid crystal display device can also be accommodated.

In Example 2, since the columnar spacer 77 made of the photosensitive organic insulating layer pattern 86A is not subjected to the ashing process by the oxygen plasma process, the film thickness variation as the columnar spacer is small as compared with the columnar spacer described in Example 1. When the film thickness of the photosensitive organic insulating layer pattern 86B changes, the gap of the liquid crystal cell changes, so that it is necessary to pay close attention to the process management of halftone exposure.

In the third embodiment, the source / drain wirings 12 and 21 are formed using the photosensitive organic insulating layer pattern, and a passivation insulating layer may be further formed on the active substrate 2 without removing the photosensitive organic insulating layer pattern. However, this is a technique applicable to a liquid crystal display device on the premise that a liquid crystal display device is obtained by bonding the color filter 9 as a completed active substrate 2 as it is, and Japanese Patent Application No. 2003 previously filed by the present inventor. The details are described in the publications Nos. 109730, 2003-182107, 2003-282703, 2003-336706, 2003-336707, 2004-21289, 2003-339659, and 2004-93944. A device and process described as Example 1 described in Japanese Patent Application No. 2004-93944 among these prior documents will be applied to the present invention to explain Example 3 of the present invention.
Japanese Patent Application No. 2003-109730 Japanese Patent Application No. 2003-182107 Japanese Patent Application No. 2003-336706 Japanese Patent Application No. 2003-336707 Japanese Patent Application No. 2003-339659 Japanese Patent Application No. 2004-21289 Japanese Patent Application No. 2004-93944

In Example 3, first, as a transparent conductive layer 91 having a film thickness of about 0.1 to 0.2 μm on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, ITO and a film thickness of 0.1 to A first metal layer 92 having a thickness of about 0.3 μm is deposited, and the transparent conductive layer 91A and the first metal layer 91A are formed using a photosensitive resin pattern by a microfabrication technique as shown in FIGS. 5 (a) and 6 (a). A scanning line 11 and a pseudo electrode terminal 94 of the scanning line that also serve as the gate electrode 11A, and a pseudo pixel electrode 93 that includes the transparent conductive layer 91B and the first metal layer 92B. A pseudo electrode terminal 95 of a signal line made of a laminate of the transparent conductive layer 91C and the first metal layer 92C is selectively formed. As the first metal layer, for example, a refractory metal such as Cr, Ta, or Mo, or an alloy or silicide thereof is selected. In order to improve the withstand voltage with respect to the signal line through the gate insulating layer and increase the yield, it is desirable to control the taper of the cross-sectional shape of these electrodes by dry etching. Although the etching technology was developed using hydrogen iodide or hydrogen bromide as the etching gas, the deposition amount due to the reaction products in the gas exhaust system was large and was not put to practical use. Sputtering and etching using Alternatively, if the film formation temperature is low and the combination of a transparent conductive layer such as IZO that has almost no crystallinity and an AL (Ta, Nd) alloy having high heat resistance, the cross-sectional shape is adjusted with a phosphoric acid-based etching solution. It is also possible to obtain these multilayer film patterns 93 to 95 at the same time while controlling the taper. AL (Ta, Nd) means an AL alloy to which Ta or Nd of several percent or less is added as a component ratio.

Next, a transparent insulating layer serving as a plasma protective layer, for example, TaOx or SiO 2 is deposited on the entire surface of the glass substrate 2 to a thickness of about 0.1 μm to 71. The plasma protective layer 71 is formed by reducing the transparent conductive layers 91A and 91B exposed at the edge of the scanning line 11 and the pseudo picture element electrode 93 during the formation of SiNx which is a gate insulating layer by a subsequent PCVD apparatus. It is necessary to prevent the fluctuation of the angle, and for details, refer to the prior example Japanese Patent Laid-Open No. 59-9962. However, when the film thickness of the transparent conductive layer 91 is as thin as 500 mm or less, the deterioration of the transparency of the SiNx layer is small, and the formation of the plasma protective layer 71 can be omitted.

After the deposition of the plasma protective layer 71, the first SiNx layer 30 serving as a gate insulating layer is formed using a PCVD apparatus in the same manner as in the conventional example. A silicon layer 31, a second SiNx layer 32 serving as an insulating layer for protecting the channel, and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.2-0.05-0.1 μm. As shown in FIG. 5B and FIG. 6B, the second SiNx layer 32 is selectively etched using a photosensitive resin pattern by a fine processing technique, and the pattern width is narrower than that of the gate electrode 11A. 2 SiNx layer 32D (protective insulating layer) and the first amorphous silicon layer 31 are exposed. Here, since the gate insulating layer is a laminate of the plasma protective layer 71 and the first SiNx layer 30, there is a secondary merit that the first SiNx layer may be formed thinner than the conventional one.

Subsequently, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface of the glass substrate 2 by using a PCVD apparatus with a film thickness of, for example, about 0.05 μm, and then FIG. As shown in FIG. 6 (c), an opening 74A is formed on the pseudo picture element electrode 93 and the pseudo electrode terminals 94 and 95 on the pseudo electrode terminals 94 and 95 in a region outside the image display section by using a photosensitive resin pattern by a fine processing technique. In addition to the second amorphous silicon layer 33, the first amorphous silicon layer 31, the gate insulating layer 30, and the plasma protective layer 71 in the opening, the first metal layers 92A to 92C are formed. The transparent conductive layer 91A of a part of the scanning line 11 (pseudo electrode terminal 94) is exposed to form the electrode terminal 5A of the scanning line, and the transparent conductive layer 91C of the pseudo electrode terminal 95 is similarly exposed to expose the signal. The line electrode terminal 6A is used as the pseudo-pixel electrode 93. The pixel electrode 22 to expose the transparent conductive layer 91B. In addition, if the multilayer film pattern 96 which consists of lamination | stacking of the transparent conductive layer 91 and the 1st metal layer 92 is formed also in the area | region outside an image surface part, since the short circuit line 40 which consists of a transparent conductive layer is obtained by this process, It is possible to take measures against static electricity.

Subsequently, using a vacuum film forming apparatus such as SPT, a thin film layer 34 of Ti, Ta or the like as a heat resistant metal layer having a thickness of about 0.1 μm and an AL thin film layer 35 as a low resistance metal layer of a thickness of about 0.3 μm are sequentially formed. Adhere. Then, as shown in FIGS. 5D and 6D, the region 87A (corresponding to the columnar spacer on the source / drain wirings 12, 21 corresponding to the source / drain wirings 12, 21 by the halftone exposure technique. 77) The photosensitive organic insulating layer patterns 87A and 87B having a thickness of 3 μm and a thickness of 87B in other regions of 1 to 2 μm are formed by a halftone exposure technique. Then, using the photosensitive organic insulating layer patterns 87A and 87B as a mask, the source / drain wiring material composed of these two thin film layers, the second amorphous silicon layer 33, and the first amorphous silicon layer 31B are sequentially etched. Then, the protective insulating layer 32D and the gate insulating layer 30A are exposed, the drain electrode 21 of the insulated gate transistor including a part of the pixel electrode 22 and a stack of 34A and 35A, and the electrode terminal 6A of the signal line A signal line 12 including a part and also serving as a source electrode is selectively formed. The electrode terminal 5A of the scanning line is exposed on the active substrate 2 after the etching of the source / drain wirings 12 and 21 is completed. Then, the manufacturing process of the active substrate 2 is completed without removing the photosensitive organic insulating layer patterns 87A and 87B.

The active substrate 2 and the color filter 9 thus obtained are bonded to form a liquid crystal panel, and Example 3 of the present invention is completed. The photosensitive organic insulating layer pattern 87 A having a thickness of 3 μm functions as the columnar spacer 77. Since the pixel electrode 22 is formed on the glass substrate 2, unlike the other embodiments, the gap of the liquid crystal cell tends to be large. Therefore, the thickness of the photosensitive organic insulating layer pattern 87A is set from the viewpoint of liquid crystal design. It is easy to make it a little thinner, for example, 2 μm. With respect to the configuration of the storage capacitor 15, as shown in FIG. 5D, the storage capacitor 72 is formed on the storage electrode 72 formed including a part of the pixel electrode 22 simultaneously with the source / drain wirings 12 and 21 and the scanning line 11 in the previous stage. The protrusions thus formed are planarly overlapped via the plasma protective layer 71A, the gate insulating layer 30A, the first amorphous silicon layer 31E, and the second amorphous silicon layer 33E (both not shown). The example (the downward slanting shaded part 52) is illustrated.

As described above, in the active substrate 2 obtained by the third embodiment, the protective insulating layer 32D is formed on the channel, and the photosensitive organic insulating layer patterns 87A and 87B are formed on the source / drain wirings 12 and 21. Therefore, sufficient reliability as a liquid crystal display device can be obtained without forming a transparent insulating passivation insulating layer on the active substrate 2. Further, regarding the columnar spacer 77 which is the subject of the present invention, the height from the glass substrate 2 corresponds to the thickness of the liquid crystal cell, so that the variation in gap accuracy is determined only by the variation in the coating thickness of the photosensitive organic insulating layer pattern 87A. In the embodiment of the present invention, the variation in gap accuracy is the smallest.

Note that it is not always necessary to use a specific region of the photosensitive organic insulating layer pattern on the source / wiring (signal line) as a columnar spacer to make the film thickness thicker than other regions. As disclosed in Japanese Patent Application Publication No. 2003-336707, a source / wiring (signal line) made of a laminate of a metal layer and a transparent conductive layer and a drain wiring (picture element electrode) made of a transparent conductive layer are formed. In a liquid crystal display device in which a photosensitive organic insulating layer pattern is formed on a source / wiring (signal line) in a display unit, the photosensitive organic insulating layer pattern is thickened to form a bank-like spacer instead of a columnar shape. It is also possible to do. This is because many parts such as insulated gate transistors are formed on the active substrate, and the intersection region of the scanning line and the signal line is usually the highest from the glass substrate, and this region is the spacer. As an effective function, a gap of about 0.5 μm is formed between the photosensitive organic insulating layer pattern on the source / wiring (signal line) of the other region and the color filter facing the other, and when liquid crystal is injected or liquid crystal This is because the diffusion of the liquid crystal in the cell is rarely restricted by the levee-like spacers at the time of dropping.

Plan view of a semiconductor device for a display device according to Example 1 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 1 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 2 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 2 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 3 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 3 of this invention. The perspective view which shows the mounting state of a liquid crystal panel Equivalent circuit diagram of LCD panel Cross section of liquid crystal panel Plan view of conventional active substrate Cross-sectional view of conventional active substrate manufacturing process Plan view of streamlined active substrate Streamlined manufacturing process of active substrate

Explanation of symbols

1: Liquid crystal panel 2: Active substrate (glass substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: scanning line electrode terminal made of metal layer, part of scanning line 5A: scanning line electrode terminal made of transparent conductive layer, part of scanning line 6: metal layer Signal line electrode terminal, signal line part 6A: signal line electrode terminal made of transparent conductive layer, signal line part 9: color filter (opposing glass substrate)
10: Insulated gate transistor 11: Scanning line 11A: (Gate wiring, gate electrode)
12: Signal line (source wiring, source electrode)
16: Storage capacitor line 21: Drain electrode 22: (Transparent conductive) picture element electrode 30, 30A, 30B, 30C: Gate insulating layer (first SiNx layer)
31, 31 </ b> A, 31 </ b> B, 31 </ b> C: first amorphous silicon layer (without impurities) 32: second SiNx layer 32D: channel protective layer (etch stop layer, protective insulating layer)
33: Second amorphous silicon layer (including impurities) 34, 34A: refractory metal layer (including silicide)
35, 35A: Low resistance metal layer (AL)
36, 36A: Intermediate conductive layer 37: Passivation insulating layer (made of SiNx) 38: Opening (on the pixel electrode) 50, 51: Storage capacitor forming region 62: Opening (on the drain electrode) 63, 63A: Opening (on the scanning line) 64, 64A: Opening (on the signal line) 65, 65A: Opening (on the storage capacitor line) 77: Columnar spacer (85C, 86A, 87A)
85A, 85B, 86A, 86B, 87A, 87B
: Photosensitive organic insulating layer pattern formed by halftone exposure technology 91, 91A, 91B, 91C: Transparent conductive layer 92, 91A, 91B, 91C: First metal layer

Claims (11)

At least an insulated gate transistor on one principal surface, and a scanning line doubling as a gate electrode of said insulated gate transistor, a signal line also serves as a source electrode, a unit pixel having a pixel electrode connected to the drain electrode A liquid crystal display in which a liquid crystal is filled between a first transparent insulating substrate arranged in a two-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. in the device,
The liquid crystal display device further includes a passivation insulating layer made of an inorganic material formed on the first transparent insulating substrate, and the passivation insulating layer has a plurality of different openings, and
The surface of the passivation insulating layer has a columnar spacer made of a photosensitive organic insulating layer,
The liquid crystal display device, wherein the columnar spacer is self-aligned with at least one of the plurality of different openings formed in the passivation insulating layer. 2. The liquid crystal display device according to claim 1, wherein the at least one opening is an opening formed in a passivation insulating layer on the scanning line or an opening formed in a passivation insulating layer on the signal line. The liquid crystal display device according to claim 1, wherein the columnar spacer has a thickness of 6 μm. The liquid crystal display device according to claim 1, wherein the columnar spacer has a thickness of 3 μm. The liquid crystal display device according to claim 1, wherein the columnar spacer is formed on the signal line. At least an insulated gate transistor on one principal surface, and a scanning line doubling as a gate electrode of said insulated gate transistor, a signal line also serves as a source electrode, a unit pixel having a pixel electrode connected to the drain electrode A liquid crystal display in which a liquid crystal is filled between a first transparent insulating substrate arranged in a two-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In the device manufacturing method , at least,
Forming at least a scanning line, a signal line, and an insulated gate transistor on a first transparent insulating substrate;
Depositing a passivation insulating layer made of an inorganic material on the first transparent insulating substrate after forming at least the scanning line, the signal line, and the insulated gate transistor in the step;
Forming a photosensitive organic insulating layer pattern on the surface of the passivation insulating layer;
Removing a part of the passivation insulating layer using the photosensitive organic insulating layer pattern as a mask, and forming a plurality of different openings in the passivation insulating layer;
A method of manufacturing a liquid crystal display device comprising: 7. The method of manufacturing a liquid crystal display device according to claim 6, further comprising a step of exposing the passivation insulating layer by reducing a film thickness of the photosensitive organic insulating layer pattern. 8. The method of manufacturing a liquid crystal display device according to claim 6, wherein the photosensitive organic insulating layer pattern has different film thicknesses, and a thick part of the pattern forms columnar spacers. The method of manufacturing a liquid crystal display device according to claim 6, wherein the photosensitive organic insulating layer pattern is formed using a halftone exposure method. The method for manufacturing a liquid crystal display device according to claim 8, wherein the columnar spacer is formed on the signal line. 10. The method of manufacturing a liquid crystal display device according to claim 7, further comprising a step of forming the pixel electrode on a surface of the passivation insulating layer having a plurality of different openings.

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