CN112736104B - Preparation method of flat panel detector - Google Patents

Preparation method of flat panel detector Download PDF

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CN112736104B
CN112736104B CN202011577154.9A CN202011577154A CN112736104B CN 112736104 B CN112736104 B CN 112736104B CN 202011577154 A CN202011577154 A CN 202011577154A CN 112736104 B CN112736104 B CN 112736104B
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layer
flat panel
electrode
panel detector
thickness
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CN112736104A (en
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解海艇
金利波
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Iray Technology Co Ltd
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Iray Technology Co Ltd
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Abstract

The application provides a preparation method of a flat panel detector, which adopts a layer or a laminated metal isolation layer to isolate an AOS TFT, so that the damage to an amorphous oxide channel layer in the AOS TFT in the subsequent process of preparing a photodiode film can be avoided, and the performance degradation of the amorphous oxide channel layer can be avoided, thereby improving the quality and performance of the flat panel detector; impurity ions in the substrate can be reduced from entering the device through the buffer layer, and the influence of the stress of the film or the substrate on the device can be reduced; after the metal isolation layer is patterned once, two gate electrodes of the double-AOS TFT and the bottom electrode of the PD can be formed simultaneously, the reserved metal isolation layer is directly used as the bottom electrode of the PD, so that the Lag value of the flat panel detector is reduced, the formed double-AOSTFT with a vertical structure is insensitive to film stress in the flat panel detector, and the dynamic reading frame rate of the flat panel detector is improved.

Description

Preparation method of flat panel detector
Technical Field
The application belongs to the field of flat panel detectors, and relates to a preparation method of a flat panel detector.
Background
Digital radiography (Digital Radio Graphy, abbreviated as DR) is a new technology of radiography developed in the 90 th century, and has been the dominant direction of digital radiography technology and accepted by clinical institutions and imaging specialists in all countries of the world due to the remarkable advantages of faster imaging speed, more convenient operation, higher imaging resolution and the like. The method is widely applied in the fields of medical image diagnosis imaging, industrial flaw detection, security inspection and the like, in the application of X-ray radiation imaging, the area of a flat panel detector is generally required to be 43cm multiplied by 43cm, and the design of a TFT panel of the X-ray detector plays a great role in realizing the functions of the TFT panel.
Flat panel detectors are generally described as detectors that use semiconductor technology to convert X-ray energy into electrical signals to produce X-ray images. Flat panel detectors consist of millions or even tens of millions of pixel cell circuits, typically made up of Thin Film Transistors (TFTs) and Photodiodes (PDs). The traditional flat panel detector is mainly an amorphous silicon flat panel detector, and a pixel unit circuit of the flat panel detector consists of an a-Si TFT and an a-Si PD.
With the development of society, the requirement on TFT reading rate is higher and higher, compared with the traditional a-Si TFT, the Amorphous Oxide (AOS) TFT has the advantages of higher field effect mobility (about more than 10 times of the mobility of the a-Si TFT), lower off-state current (fA level) and the like, so that the Amorphous Oxide (AOS) TFT can be applied to the preparation of a dynamic flat panel detector with the advantages of high frame rate, low noise and the like.
However, in the case of fabricating a flat panel detector composed of an AOS TFT and an a-Si PD array, the a-Si PD array film forming process may adversely affect the AOS TFT, which may cause performance degradation of the AOS TFT, and reduce product yield.
Therefore, it is necessary to provide a method for manufacturing a flat panel detector.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a method for manufacturing a flat panel detector, which is used for solving the problem that the a-Si PD array film forming process adversely affects the AOS TFT and degrades the performance of the AOS TFT in the prior art when the flat panel detector is manufactured.
To achieve the above and other related objects, the present application provides a method for manufacturing a flat panel detector, comprising the steps of:
providing a substrate;
forming a buffer layer on the substrate;
forming a source electrode on the buffer layer;
forming a patterned insulating isolation layer and a patterned drain electrode on the source electrode to expose part of the source electrode;
forming an amorphous oxide film, and patterning the amorphous oxide film to form a first amorphous oxide channel layer and a second amorphous oxide channel layer which are in contact with the source electrode and the drain electrode;
forming a gate insulating layer which covers the first amorphous oxide channel layer and the second amorphous oxide channel layer and exposes a part of the source electrode;
forming a metal isolation layer, wherein the metal isolation layer covers the gate insulation layer and the exposed source electrode;
forming a photodiode and a transparent top electrode on the metal isolation layer;
patterning the photodiode and the transparent top electrode to expose a portion of the metal isolation layer;
patterning the metal isolation layer to form a first gate electrode and a second gate electrode, and obtaining a first TFT and a second TFT and a bottom electrode of the photodiode;
forming a first protection layer, wherein the first protection layer covers the first TFT, the second TFT, the photodiode and the transparent top electrode;
patterning the first protective layer to form a common electrode through hole exposing the transparent top electrode;
forming a metal layer, patterning the metal layer, and forming a common electrode and a shading layer, wherein the shading layer is positioned above the first TFT and the second TFT, and the common electrode fills the common electrode through hole;
forming a second protection layer, wherein the second protection layer covers the public electrode and the shading layer;
a scintillator layer is formed, the scintillator layer covering the second protective layer.
Optionally, the buffer layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the buffer layer is in the range of
Optionally, the insulating isolation layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the insulating isolation layer ranges from
Optionally, the source electrode includes one or a combination of Mo layer, al layer, ainb layer, cr layer, cu layer, ti layer, and Nb layer; the thickness of the source electrode ranges fromThe drain electrode comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and an Nb layer;the thickness of the drain electrode is in the range of +.>
Optionally, the amorphous oxide film comprises an a-IGZO layer, an a-IZO layer, an a-IGO layer, in 2 O 3 Layer, znO layer, a-IZTO layer and AlZnO x One or a combination of layers; the thickness of the amorphous oxide film is in the range of
Optionally, the gate insulating layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the gate insulating layer is in the range of
Optionally, the metal isolation layer comprises one or a combination of a Mo layer, an Al layer, an ainb layer, a Cr layer and a Cu layer; the thickness of the metal isolating layer isThe metal layer comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is +.>
Optionally, the first protective layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the first protective layer ranges fromThe second protective layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the second protective layer is in the range +.>
Optionally, the transparent top electrode comprises an ITO layer; the thickness range of the transparent top electrode is
Optionally, the scintillator layer comprises one or a combination of a CsI layer, a GOS layer, and a perovskite layer.
As described above, the preparation method of the flat panel detector has the following beneficial effects:
the application adopts a layer or laminated metal isolation layer to isolate the AOS TFT, thereby avoiding damage to an amorphous oxide channel layer in the AOS TFT in the subsequent process of preparing the photodiode film, avoiding performance degradation of the amorphous oxide channel layer and further improving the quality and performance of the flat panel detector; impurity ions in the substrate can be reduced from entering the device through the buffer layer, and the influence of the stress of the film or the substrate on the device can be reduced; after the metal isolation layer is patterned once, two gate electrodes of the double-AOS TFT and the bottom electrode of the PD can be formed simultaneously, and the reserved metal isolation layer is directly used as the bottom electrode of the PD, so that the Lag value of the flat panel detector is reduced, the formed double-AOS TFT with a vertical structure is insensitive to film stress in the flat panel detector, and the dynamic reading frame rate of the flat panel detector is improved.
Drawings
FIG. 1 is a schematic diagram of a process flow for fabricating a flat panel detector according to an embodiment of the application.
Fig. 2 to 14 are schematic structural views showing steps of preparing a flat panel detector according to the embodiment.
Description of element reference numerals
110. Substrate and method for manufacturing the same
120. Buffer layer
130. Source electrode
140. Insulation isolation layer
150. Drain electrode
161. First amorphous oxide channel layer
162. Second amorphous oxide channel layer
170. Gate insulating layer
180. Metal isolation layer
181. First gate electrode
182. Second gate electrode
183. Bottom electrode of photodiode
190. Photodiode having a high-k-value transistor
111. Transparent top electrode
1111. Common electrode via
112. First protective layer
1131. Common electrode
1132. Light shielding layer
114. A second protective layer
115. Scintillator layer
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Referring to fig. 1 to 14, the present embodiment provides a method for manufacturing a flat panel detector, in which a metal isolation layer or a stacked metal isolation layer is used to isolate an AOS TFT, so that damage to an amorphous oxide channel layer in the AOS TFT during a subsequent process of manufacturing a photodiode film is avoided, and performance degradation of the amorphous oxide channel layer is avoided, thereby improving quality and performance of the flat panel detector; impurity ions in the substrate can be reduced from entering the device through the buffer layer, and the influence of the stress of the film or the substrate on the device can be reduced; after the metal isolation layer is patterned once, two gate electrodes of the double-AOS TFT and the bottom electrode of the PD can be formed simultaneously, and the reserved metal isolation layer is directly used as the bottom electrode of the PD, so that the Lag value of the flat panel detector is reduced, the formed double-AOS TFT with a vertical structure is insensitive to film stress in the flat panel detector, and the dynamic reading frame rate of the flat panel detector is improved.
The preparation method of the embodiment is further described below with reference to the accompanying drawings, and specifically includes:
referring to fig. 2, a substrate 110 is provided first, and a buffer layer 120 is formed on the substrate 110.
In particular, the substrate 110 may include a glass substrate or a flexible PI, PET substrate, etc., but is not limited thereto. One or more layers of insulating layer may be prepared by CVD, PVD or solution method as the buffer layer 120, and the buffer layer 120 may include SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the buffer layer 120 may range fromFor example->Is->Etc. Wherein the buffer layer 120 does not need to be patterned, which can reduce the impurity ions in the substrate 110 from entering the device, and can reduce the influence of the stress of the film or the substrate on the device. The specific material, structure, thickness, forming method, etc. of the buffer layer 120 may be selected according to the need, and are not limited thereto.
Next, referring to fig. 3, a source electrode 130 is formed on the buffer layer 120.
Specifically, one or more metal films may be deposited by PVD, and then the metal films may be patterned by dry or wet etching to form the source electrode 130, which may be formed byThe source electrode 130 may include one or a combination of Mo layer, al layer, ainb layer, cr layer, cu layer, ti layer, and Nb layer; the source electrode 130 may have a thickness in the range ofSuch asIs->Etc. The specific material, structure, thickness, forming method, etc. of the source electrode 130 may be selected according to need, and are not limited thereto.
Next, referring to fig. 4 and 5, a patterned insulating isolation layer 140 is formed on the source electrode 130, and a patterned drain electrode 150 is formed on the insulating isolation layer 140 to expose a portion of the source electrode 130.
Specifically, referring to FIG. 4, the insulating spacer 140 may be prepared by CVD, PVD, or solution processes, and the insulating spacer 140 may comprise SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the insulating spacer 140 may range fromFor example->AndEtc. The specific material, structure, thickness, forming method, etc. of the insulating spacer 140 may be selected according to the need, and are not limited thereto. Then, one or more metal films may be deposited as the drain electrode 150 of the subsequent TFT by PVD, wherein the drain electrode 150 may include one of Mo layer, al layer, alNb layer, cr layer, cu layer, ti layer and Nb layerOr a combination; the thickness of the drain electrode 150 may be in the range +.>For example->Is->Etc. The specific material, structure, thickness, formation method, etc. of the drain electrode 150 may be selected according to need, and are not particularly limited.
Next, referring to fig. 5, a dry etching or a wet etching is adopted to obtain the patterned drain electrode 150, and then obtain the patterned insulating isolation layer 140, so as to expose a portion of the source electrode 130, so as to facilitate subsequent electrical connection.
Next, referring to fig. 6, an amorphous oxide film is formed, and patterned to form a first amorphous oxide channel layer 161 and a second amorphous oxide channel layer 162 in contact with the source electrode 130 and the drain electrode 150.
Specifically, one or more layers of the amorphous oxide film may be prepared by PVD or solution method, and patterned by wet or dry etching to form the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162, wherein the amorphous oxide film may include an a-IGZO layer, an a-IZO layer, an a-IGO layer, an In 2 O 3 Layer, znO layer, a-IZTO layer and AlZnO x One or a combination of layers; the thickness of the amorphous oxide film may be in the range ofFor example->Is->Etc.; thereby can seeThe first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 having the same material and the same thickness are formed. The specific material, structure, thickness, formation method, etc. of the amorphous oxide film may be selected as desired, and are not particularly limited.
Next, referring to fig. 7, a gate insulating layer 170 is formed, the gate insulating layer 170 covers the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162, and a portion of the source electrode 130 is exposed.
Specifically, one or more gate insulating film layers may be prepared by CVD, PVD or solution method, and then patterned by dry or wet etching to form the gate insulating layer 170 exposing a portion of the TFT of the source electrode 130, wherein the gate insulating layer 170 may include SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the gate insulating layer 170 has a thickness in the range ofFor example->AndAnd the specific material, structure, thickness, formation method, etc. of the gate insulating layer 170 may be selected according to need, and are not excessively limited herein.
Next, referring to fig. 8, a metal isolation layer 180 is formed, the metal isolation layer 180 covers the gate insulating layer 170 and the exposed source electrode 130, and a photodiode 190 and a transparent top electrode 111 are formed on the metal isolation layer 180.
Specifically, one or more layers of metal films may be deposited by PVD, then thereon, an amorphous silicon PIN photodiode layer is formed by CVD, and finally an ITO electrode layer is formed by PVD to form a stack of the metal spacersLayer 180, photodiode 190, and transparent top electrode 111. Wherein, the metal isolation layer 180 may include one or a combination of Mo layer, al layer, ainb layer, cr layer and Cu layer; the thickness of the metal spacer 180 may beFor example->Is->And the specific materials, structures, thicknesses, forming methods, etc. of the metal isolation layer 180 may be selected according to need, and are not limited thereto. The transparent top electrode 111 may employ an ITO layer, but is not limited thereto, and the thickness of the transparent top electrode 111 may be in the range +.>For example->Is->And the specific materials, structures, thicknesses, forming methods, and the like of the transparent top electrode 111 may be selected as desired, and are not excessively limited herein.
Next, referring to fig. 9, the photodiode 190 and the transparent top electrode 111 are patterned to expose a portion of the metal isolation layer 180.
Specifically, dry etching or wet etching may be adopted, where the ITO electrode layer is patterned to form the patterned transparent top electrode 111, and then the amorphous silicon PIN photodiode layer is patterned to form the patterned photodiode 190. In the process of preparing the photodiode 190 and the transparent top electrode 111, the metal isolation layer 180 may serve to protect the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 of the TFT, so as to prevent the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 from being affected by the deposition process of the photodiode 190, and prevent the performance of the TFT from being degraded.
Next, referring to fig. 10, the metal isolation layer 180 is patterned to form a first gate electrode 181 and a second gate electrode 182, thereby obtaining a first TFT and a second TFT, and a bottom electrode 183 of the photodiode 190.
Specifically, the metal isolation layer 180 may be patterned by dry etching or wet etching, so that the first gate electrode 181, the second gate electrode 182 and the bottom electrode 183 of the photodiode 190 may be formed simultaneously by one patterning, thereby reducing the complexity of the process; and the reserved metal isolation layer 180 is directly used as the bottom electrode of the photodiode 190, so that the Lag value of the flat panel detector is reduced; thus, the first TFT, the second TFT and the PD can be conveniently obtained.
Next, referring to fig. 11, a first protection layer 112 is formed, the first protection layer 112 covers the first TFT, the second TFT, the photodiode 190 and the transparent top electrode 111; and patterning the first protective layer 112 to form a common electrode via 1111 exposing the transparent top electrode 111.
Specifically, one or more insulating layer films may be prepared by CVD, PVD or solution method to form the first protective layer 112, and the first protective layer 112 may include SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; to cover the photodiode 190 as a protective layer of the photodiode 190. And then patterned by wet or dry etching to form the common electrode through-hole 1111 exposing a portion of the transparent top electrode 111. The thickness of the first protective layer 112 may be in the range ofFor example-> Is->And the specific materials, structures, thicknesses, methods of forming the first protective layer 112 may be selected according to the need, and are not limited thereto.
Next, referring to fig. 12, a metal layer is formed, and patterned to form a common electrode 1131 and a light shielding layer 1132, wherein the light shielding layer 1132 is located above the first TFT and the second TFT, and the common electrode 1131 fills the common electrode via 1111.
Specifically, a metal film with one or more layers of laminated structures can be prepared by adopting a PVD method to form the metal layer, wherein the metal layer can comprise one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is in the range ofFor example->And then patterning the metal layer to form the common electrode 1131 and the light shielding layer 1132, wherein the common electrode 1131 and the light shielding layer 1132 have the same plane and the same material and thickness. The material, thickness and forming method of the metal layer are not limited thereto, and may be selected as needed.
Next, referring to fig. 13, a second protection layer 114 is formed, and the second protection layer 114 covers the common electrode 1131 and the light shielding layer 1132.
Specifically, an insulating layer with a layer or a stacked structure may be prepared by CVD, PVD or solution method to form the second protective layer 114, wherein the second protective layer 114 may include SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer. The thickness of the second passivation layer 114 may be in the range ofSuch asFor example, the material, thickness and forming method of the second protective layer 114 are not limited thereto, and may be selected as needed.
Next, referring to fig. 14, a scintillator layer 115 is formed, and the scintillator layer 115 covers the second protection layer 114.
In particular, the scintillator layer 115 may include one or a combination of a CsI layer, a GOS layer, and a perovskite layer to convert X-rays into visible light through the scintillator layer 115. The material, thickness, and formation method of the scintillator layer 115 are not limited thereto, and may be selected as needed.
In summary, the preparation method of the flat panel detector adopts one or a plurality of metal isolation layers to isolate the AOS TFT, thereby avoiding damage to an amorphous oxide channel layer in the AOS TFT in the subsequent process of preparing the photodiode film and avoiding performance degradation of the amorphous oxide channel layer, and further improving the quality and performance of the flat panel detector; impurity ions in the substrate can be reduced from entering the device through the buffer layer, and the influence of the stress of the film or the substrate on the device can be reduced; after the metal isolation layer is patterned once, two gate electrodes of the double-AOS TFT and the bottom electrode of the PD can be formed simultaneously, and the reserved metal isolation layer is directly used as the bottom electrode of the PD, so that the Lag value of the flat panel detector is reduced, the formed double-AOS TFT with a vertical structure is insensitive to film stress in the flat panel detector, and the dynamic reading frame rate of the flat panel detector is improved.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the flat panel detector is characterized by comprising the following steps of:
providing a substrate;
forming a buffer layer on the substrate;
forming a source electrode on the buffer layer;
forming a patterned insulating isolation layer and a patterned drain electrode on the source electrode to expose part of the source electrode;
forming an amorphous oxide film, and patterning the amorphous oxide film to form a first amorphous oxide channel layer and a second amorphous oxide channel layer which are in contact with the source electrode and the drain electrode;
forming a gate insulating layer which covers the first amorphous oxide channel layer and the second amorphous oxide channel layer and exposes a part of the source electrode;
forming a metal isolation layer, wherein the metal isolation layer covers the gate insulation layer and the exposed source electrode;
forming a photodiode and a transparent top electrode on the metal isolation layer;
patterning the photodiode and the transparent top electrode to expose a portion of the metal isolation layer;
patterning the metal isolation layer to form a first gate electrode and a second gate electrode, and obtaining a first TFT and a second TFT and a bottom electrode of the photodiode;
forming a first protection layer, wherein the first protection layer covers the first TFT, the second TFT, the photodiode and the transparent top electrode;
patterning the first protective layer to form a common electrode through hole exposing the transparent top electrode;
forming a metal layer, patterning the metal layer, and forming a common electrode and a shading layer, wherein the shading layer is positioned above the first TFT and the second TFT, and the common electrode fills the common electrode through hole;
forming a second protection layer, wherein the second protection layer covers the public electrode and the shading layer;
a scintillator layer is formed, the scintillator layer covering the second protective layer.
2. The method for manufacturing a flat panel detector according to claim 1, wherein: the buffer layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the buffer layer is in the range of
3. The method for manufacturing a flat panel detector according to claim 1, wherein: the insulating isolation layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the insulating isolation layer ranges from
4. The method for manufacturing a flat panel detector according to claim 1, wherein: the source electrode comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and an Nb layer; the thickness of the source electrode ranges fromThe drain electrode comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and an Nb layer; the thickness of the drain electrode is in the range of +.>
5. The method for manufacturing a flat panel detector according to claim 1, wherein: the amorphous oxide film comprises an a-IGZO layer, an a-IZO layer, an a-IGO layer, and In 2 O 3 Layer, znO layer, a-IZTO layer and AlZnO x One or a combination of layers; the thickness of the amorphous oxide film is in the range of
6. The method for manufacturing a flat panel detector according to claim 1, wherein: the gate insulating layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the gate insulating layer is in the range of
7. The method for manufacturing a flat panel detector according to claim 1, wherein: the metal isolation layer comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal isolating layer isThe metal layer comprises one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is
8. The method for manufacturing a flat panel detector according to claim 1, wherein: the first protective layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the first protective layer ranges fromThe second protective layer comprises SiO x Layer, siN x Layer, siO x N y Layer, alO x Layer, zrO x Layer, tiO x One or a combination of a layer and an organic insulating layer; the thickness of the second protective layer is in the range +.>
9. The method for manufacturing a flat panel detector according to claim 1, wherein: the transparent top electrode comprises an ITO layer; the thickness range of the transparent top electrode is
10. The method for manufacturing a flat panel detector according to claim 1, wherein: the scintillator layer comprises one or a combination of a CsI layer, a GOS layer and a perovskite layer.
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