CN114038868A - Flat panel detector and manufacturing method thereof - Google Patents
Flat panel detector and manufacturing method thereof Download PDFInfo
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- CN114038868A CN114038868A CN202111497169.9A CN202111497169A CN114038868A CN 114038868 A CN114038868 A CN 114038868A CN 202111497169 A CN202111497169 A CN 202111497169A CN 114038868 A CN114038868 A CN 114038868A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 21
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 239000007769 metal material Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
- H01L27/14663—Indirect radiation imagers, e.g. using luminescent members
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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Abstract
The invention provides a flat panel detector and a manufacturing method thereof, wherein the flat panel detector comprises a first TFT, a second TFT, a lower electrode, a photoelectric conversion layer and an upper electrode; the first TFT comprises first polycrystalline silicon, second polycrystalline silicon, third polycrystalline silicon, a first drain electrode connected with the first polycrystalline silicon, a first source electrode connected with the second polycrystalline silicon and a first grid electrode above the third polycrystalline silicon; the second TFT comprises a second grid electrode, a metal oxide semiconductor layer, a second source electrode and a second drain electrode which are connected with the metal oxide semiconductor layer; the second source electrode of the second TFT is directly connected with the first source electrode of the first TFT; the third grid is arranged above the first grid and is connected with the first grid through a through hole, and the lower electrode is connected with the first grid through the through hole. The first TFT is a polysilicon TFT which can be of an NMOS structure or a PMOS structure, adopts a top gate structure and is used for amplifying an electric signal of a photoelectric detector, so that the detection sensitivity of a light source can be improved; the second TFT adopts a bottom gate structure and is used for transmitting a photoelectric signal of the PIN and reducing the leakage current of the photoelectric conversion layer.
Description
Technical Field
The invention relates to the technical field of flat panel detectors, in particular to a flat panel detector and a manufacturing method thereof.
Background
The X-ray of the flat panel detector is firstly converted into visible light through a fluorescent medium material, then the visible light signal is converted into an electric signal through a photosensitive element, and finally the analog electric signal is converted into a digital signal through A/D.
The metal oxide has the advantage of low leakage current, is suitable for being used as a switching TFT, and effectively reduces the X-ray dosage; the Low Temperature Polysilicon (LTPS) has high electron mobility and is suitable for current amplification and compensation.
X-rays are harmful to human bodies, so that a lower X-ray radiation dose is required as much as possible, but the generated photocurrent is small, and lower leakage current and current compensation amplification are required to form a clearer image and a smaller exposure dose.
The existing flat panel detector adopts metal oxide as an amplifying circuit and a TFT, and is limited by the electron mobility of the metal oxide, and the amplification factor is insufficient; the LTPS is used as an amplifying circuit and a TFT, and although the amplification factor is large, the leakage current of the TFT is large, which is not an effective solution.
Therefore, a new flat panel detector is needed.
Disclosure of Invention
The invention aims to provide a flat panel detector which improves the detection sensitivity of a light source and reduces the leakage current of a photoelectric conversion layer and a manufacturing method thereof.
The invention provides a flat panel detector, which comprises a first TFT, a second TFT, a lower electrode, a photoelectric conversion layer and an upper electrode, wherein the first TFT is arranged on the lower electrode; the first TFT comprises first polycrystalline silicon, second polycrystalline silicon, third polycrystalline silicon, a first drain electrode connected with the first polycrystalline silicon, a first source electrode connected with the second polycrystalline silicon and a first grid electrode above the third polycrystalline silicon; the second TFT comprises a second grid electrode, a metal oxide semiconductor layer, a second source electrode and a second drain electrode which are connected with the metal oxide semiconductor layer; the second source electrode of the second TFT is directly connected with the first source electrode of the first TFT; the third grid is arranged above the first grid and is connected with the first grid through a through hole, and the lower electrode is connected with the first grid through the through hole.
Preferably, the first TFT is of an NMOS structure or a PMOS structure; the second TFT is a metal oxide semiconductor structure.
Preferably, the first TFT is a top gate structure; the second TFT is a bottom gate structure.
Preferably, the first gate is located above the third polysilicon.
The invention also provides a manufacturing method of the flat panel detector, which comprises the following steps:
s1: forming a first polysilicon, a second polysilicon and a third polysilicon which are arranged in parallel and are patterned;
s2: forming a gate insulating layer covering the first, second and third polysilicon;
s3: forming a first grid and a second grid which are patterned on the grid insulation layer by adopting a first metal material;
s4: forming a first insulating layer covering the first metal material;
s5: forming a metal oxide semiconductor layer over the second gate electrode on the first insulating layer;
s6: etching to form a first hole on the first polysilicon, a second hole on the second polysilicon and a third hole above the first gate;
s7: and forming a first drain electrode which is patterned and connected with the first polycrystalline silicon through the first hole, a first source electrode connected with the second polycrystalline silicon through the second hole, a third grid electrode connected with the first grid electrode through the third hole, and a second source electrode and a second drain electrode which are positioned on the first insulating layer by adopting a second metal material, wherein the second source electrode is directly connected with the first source electrode, and the second source electrode and the second drain electrode are respectively contacted with the metal oxide semiconductor layer.
Preferably, the method further comprises the following steps:
s8: forming a second insulating layer covering the second metal material;
s9: forming a third insulating layer covering the second insulating layer;
s10: etching to form a fourth hole which is positioned on the third grid electrode and penetrates through the second insulating layer and the third insulating layer;
s11: forming a lower electrode on the third insulating layer and contacting the third gate electrode through the fourth hole;
s12: forming a photoelectric conversion layer on the lower electrode;
s13: an upper electrode on the photoelectric conversion layer is formed.
Preferably, the lower electrode is made of a cathode metal material having a low work function.
Preferably, the gate insulating layer, the first insulating layer and the second insulating layer are all inorganic insulating layers, and the third insulating layer is an organic insulating layer.
The first TFT is used as a polysilicon TFT and can be of an NMOS structure or a PMOS structure, the first TFT adopts a top gate structure and is used for amplifying an electric signal of a photoelectric detector, and the detection sensitivity of a light source can be improved; the second TFT adopts a bottom gate structure and is used for transmitting a photoelectric signal of the PIN and reducing the leakage current of the photoelectric conversion layer.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of the structure of the flat panel detector of the present invention.
Fig. 2 is a schematic diagram of a flat panel detector pixel circuit according to the present invention.
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
Fig. 1 is a schematic structural diagram of a flat panel detector of the present invention, which includes a first TFT, a second TFT connected to the first TFT, a lower electrode 90 connected to a gate of the first TFT, a photoelectric conversion layer 100 covering the lower electrode 90, and an upper electrode 110 on the photoelectric conversion layer 100.
The lower electrode 90 is made of a metal material having a low work function, such as silver, titanium, aluminum, molybdenum, or niobium. The photoelectric conversion layer 100 includes an N-type amorphous silicon semiconductor layer 101 on the lower electrode 90, an amorphous silicon intrinsic layer 102 on the N-type amorphous silicon semiconductor layer 101, and a P-type amorphous silicon semiconductor layer 103 on the amorphous silicon intrinsic layer 102.
The first TFT includes a first polysilicon 11, a second polysilicon 12, a third polysilicon 13, a first drain 61 connected to the first polysilicon 11, a first source 62 connected to the second polysilicon 12, and a first gate 31 located above the third polysilicon 13.
The second TFT includes a second gate electrode 32 disposed at the same layer as the first gate electrode 31, a metal oxide semiconductor layer 50 located above the second gate electrode 32, and a second source electrode 62 and a second drain electrode 64 both connected to the metal oxide semiconductor layer 50; the second source 62 is directly connected to the first source 62.
And arranging a third grid 63 on the second metal layer, and connecting the third grid with the first grid 31 through a through hole.
The lower electrode 90 is connected to the third gate electrode 63.
The first TFT is used as a polysilicon TFT which can be in an NMOS structure or a PMOS structure, the first TFT is in a top gate structure, and the first TFT is connected with a circuit and used for amplifying an electric signal of a photoelectric detector, so that the detection sensitivity of a light source can be improved; the second TFT is of a bottom gate structure and is connected with the first TFT through a source electrode, so that photoelectric signals of the PIN are transmitted, and meanwhile, the leakage current of the photoelectric conversion layer is reduced.
The invention also discloses a manufacturing method of the flat panel detector, which comprises the following steps:
s1: forming a first polysilicon 11, a second polysilicon 12 and a third polysilicon 13 which are arranged in parallel and are patterned;
s2: forming a gate insulating layer 20 covering the first polysilicon 11, the second polysilicon 12 and the third polysilicon 13, the gate insulating layer being silicon dioxide;
s3: forming a first gate electrode 31 and a second gate electrode 32 patterned on the gate insulating layer 20 by using a first metal material, wherein the first gate electrode 31 is located above the third polysilicon 13 and serves as a gate electrode of the polysilicon TFT, and the second gate electrode 32 serves as a gate electrode of the metal oxide TFT;
s4: forming a first insulating layer 40 covering the first metal material, wherein the first insulating layer is of a multilayer structure, the lower layer is silicon nitride, and the upper layer is silicon dioxide;
s5: forming a metal oxide semiconductor layer 50 over the second gate electrode 32 on the first insulating layer 40;
s6: etching to form a first hole 41 on the first polysilicon 11, a second hole 42 on the second polysilicon 12, and a third hole 43 on the first gate 31;
s7: forming a first drain electrode 61 patterned and connected to the first polysilicon 11 through the first hole 41, a first source electrode 62 connected to the second polysilicon 12 through the second hole 42, a third gate electrode 63 connected to the first gate electrode 31 through the third hole 43, and a second drain electrode 64 and a second source electrode 62 on the first insulating layer 40, the second source electrode 62 and the second drain electrode 64 being respectively located at both sides of the metal oxide semiconductor layer 50 and both contacting the metal oxide semiconductor layer 50, using a second metal material;
s8: forming a second insulating layer 70 covering the second metal material;
s9: forming a third insulating layer 80 covering the second insulating layer 70;
s10: etching to form a fourth hole 81 on the third gate electrode 63 and through the second insulating layer 70 and the third insulating layer 80;
s11: forming a lower electrode 90 on the third insulating layer 80 and contacting the third gate electrode 63 through the fourth hole 81;
s12: forming a photoelectric conversion layer 100 on the lower electrode 90;
s13: an upper electrode 110 on the photoelectric conversion layer 100 is formed.
The gate insulating layer 20, the first insulating layer 40, and the second insulating layer 70 are all inorganic insulating layers, and the third insulating layer 80 is an organic insulating layer.
The first TFT is used as a polysilicon TFT and can be of an NMOS structure or a PMOS structure, the first TFT adopts a top gate structure and is used for amplifying an electric signal of a photoelectric detector, and the detection sensitivity of a light source can be improved; the second TFT adopts a bottom gate structure and is used for transmitting a photoelectric signal of the PIN and reducing the leakage current of the photoelectric conversion layer.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and these equivalent changes are all within the protection scope of the present invention.
Claims (8)
1. A flat panel detector is characterized by comprising a first TFT, a second TFT, a lower electrode, a photoelectric conversion layer and an upper electrode; the first TFT comprises first polycrystalline silicon, second polycrystalline silicon, third polycrystalline silicon, a first drain electrode connected with the first polycrystalline silicon, a first source electrode connected with the second polycrystalline silicon and a first grid electrode above the third polycrystalline silicon; the second TFT comprises a second grid electrode, a metal oxide semiconductor layer, a second source electrode and a second drain electrode which are connected with the metal oxide semiconductor layer; the second source electrode of the second TFT is directly connected with the first source electrode of the first TFT; the third grid is arranged above the first grid and is connected with the first grid through a through hole, and the lower electrode is connected with the first grid through the through hole.
2. The flat panel detector according to claim 1, wherein: the first TFT is of an NMOS structure or a PMOS structure; the second TFT is a metal oxide semiconductor structure including, but not limited to, IGZO, IGTO, IGZTO, IZO, etc.
3. The flat panel detector according to claim 1, wherein: the first TFT is of a top gate structure; the second TFT is a bottom gate structure.
4. The flat panel detector according to claim 1, wherein: the first grid is positioned above the third polysilicon.
5. A method of fabricating a flat panel detector, comprising the steps of:
s1: forming a first polysilicon, a second polysilicon and a third polysilicon which are arranged in parallel and are patterned;
s2: forming a gate insulating layer covering the first, second and third polysilicon;
s3: forming a first grid and a second grid which are patterned on the grid insulation layer by adopting a first metal material;
s4: forming a first insulating layer covering the first metal material;
s5: forming a metal oxide semiconductor layer over the second gate electrode on the first insulating layer;
s6: etching to form a first hole on the first polysilicon, a second hole on the second polysilicon and a third hole above the first gate;
s7: and forming a first drain electrode which is patterned and connected with the first polycrystalline silicon through the first hole, a first source electrode connected with the second polycrystalline silicon through the second hole, a third grid electrode connected with the first grid electrode through the third hole, and a second source electrode and a second drain electrode which are positioned on the first insulating layer by adopting a second metal material, wherein the second source electrode is directly connected with the first source electrode, and the second source electrode and the second drain electrode are respectively contacted with the metal oxide semiconductor layer.
6. The method of manufacturing a flat panel detector according to claim 5, wherein: also comprises the following steps:
s8: forming a second insulating layer covering the second metal material;
s9: forming a third insulating layer covering the second insulating layer;
s10: etching to form a fourth hole which is positioned on the third grid electrode and penetrates through the second insulating layer and the third insulating layer;
s11: forming a lower electrode on the third insulating layer and contacting the third gate electrode through the fourth hole;
s12: forming a photoelectric conversion layer on the lower electrode;
s13: an upper electrode on the photoelectric conversion layer is formed.
7. The method of manufacturing a flat panel detector according to claim 5, wherein: the lower electrode is made of a metal material with a low work function.
8. The method of manufacturing a flat panel detector according to claim 5, wherein: the gate insulating layer, the first insulating layer and the second insulating layer are all inorganic insulating layers, and the third insulating layer is an organic insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111497169.9A CN114038868A (en) | 2021-12-09 | 2021-12-09 | Flat panel detector and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111497169.9A CN114038868A (en) | 2021-12-09 | 2021-12-09 | Flat panel detector and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN114038868A true CN114038868A (en) | 2022-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111497169.9A Pending CN114038868A (en) | 2021-12-09 | 2021-12-09 | Flat panel detector and manufacturing method thereof |
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| CN (1) | CN114038868A (en) |
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- 2021-12-09 CN CN202111497169.9A patent/CN114038868A/en active Pending
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