JP2002111008A - Thin film transistor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of transfer speed delay caused by considerable gate wiring resistance in association with an increase in an area. SOLUTION: In the thin film transistor array, an insulating film of an intersection of a gate wiring and a signal wiring and a gate insulating film of a thin film transistor are formed of different film thicknesses. Further, a semiconductor layer of the intersection of the gate wiring and the signal wiring and a nonsingle crystal semiconductor layer of the thin film transistor are formed of different film thicknesses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device represented by a liquid crystal display device, an image reading device used for a scanner, etc., and a thin film transistor used for a radiation light detecting device for X-rays or .gamma.-rays. It is about the array.

[0002]

2. Description of the Related Art Conventionally, non-single-crystal silicon semiconductors, that is,
2. Description of the Related Art A display device typified by a liquid crystal display device or the like has been developed using a thin film transistor (hereinafter, referred to as a TFT) using an amorphous silicon film (hereinafter, an a-Si film). In particular, the a-Si film TFT is used as a switch element of various large-area devices because it can be easily formed in a large area by a low-temperature process. Further, the a-Si film is made of TF
It can be used not only as a semiconductor material of T but also as a photoelectric conversion material, and is used as a semiconductor layer of a photoelectric conversion element and a semiconductor layer of a switch TFT, and is widely applied to a photodetector.

First, an outline of a TFT array used in a conventional liquid crystal display device using an a-Si film will be described. FIG. 21 shows an equivalent circuit of a liquid crystal display device composed of 3 × 3 pixels as an example, and FIG. 22 shows a schematic plan view of one pixel. In the figure, 101 is a TFT, 102 is a gate wiring connected to a gate electrode, 103 is a data wiring connected to source / drain electrodes of the TFT, 104 is an auxiliary capacitor, 105 is a liquid crystal capacitor, and is a pixel region. is there.
Reference numeral 121 denotes a data drive circuit, and reference numeral 122 denotes a TFT driver. The TFTs are sequentially operated by the TFT driver 122, and the liquid crystal is driven by a signal transferred from the data drive circuit 121.

In general, a channel etching type and a channel stopper type are used for a TFT structure. FIG.
3 and FIG. 24 show schematic cross-sectional views of each. In the figure,
106 is a TFT gate electrode, 107 is a gate insulating film, 1
08 is an a-Si film, 109 is an ohmic contact layer,
110 is a pair of source / drain electrodes, and 111 is a protective film. The channel etching type is manufactured by a simple manufacturing method, but has a structure in which formation of a channel portion and formation of a protective film greatly affect characteristics. The gap stopper type is manufactured by a complicated manufacturing method, but has a structure capable of obtaining stable characteristics. As described above, both have advantages and disadvantages, and which type is selected is determined by comprehensive judgment including the manufacturing cost and the like.

Next, as a representative example, a method of manufacturing a channel etching type TFT array will be described with reference to FIG. First, as shown in FIG. 25A, a TFT gate electrode and a gate wiring are formed on a glass substrate. Second, a gate insulating film, a semiconductor layer, and an ohmic contact layer are formed on a glass substrate as shown in FIG.
The semiconductor layer other than the TFT part and the ohmic contact layer are removed. Third, as shown in FIG. 25C, a transparent electrode ITO is formed in the pixel portion.

Next, as shown in FIG. 25D, source / drain electrodes of the TFT portion are formed. Fifth, as shown in FIG. 25E, the semiconductor layer and the ohmic contact layer in the TFT channel portion are removed. Sixth, FIG.
As shown in (f), a protective film is formed on the TFT portion. The outline of the manufacturing method has been described above. What is important here is that the gate insulating film, the semiconductor layer, and the ohmic contact layer described in the second step are generally formed continuously. It is necessary. This is because if the interface between the gate insulating film and the semiconductor layer is contaminated, the TFT characteristics deteriorate.

Next, an example of an X-ray detection device using a PIN type photosensor and a TFT array as a photoelectric conversion device will be described. FIG. 26 shows an equivalent circuit diagram of 3 × 3 pixels of the present device, and FIG. 27 shows a schematic cross-sectional view of one pixel.

In FIG. 26, 201 is a switch TF
T and 202 are PIN type photodiodes, 203 is TF
A gate line 204 is connected to the gate electrode of T, and a signal line 204 is connected to the source electrode of the TFT. The gate wiring is sequentially biased from a gate driver 205, and each signal is amplified by an amplifier IC 206 connected to a signal line, converted into a digital signal by an A / D converter 207, and output.

In FIG. 27, 211 is a glass substrate, 212 is a TFT gate electrode, 213 is a gate insulating film, 214 is an a-Si layer, 215 is a protective film, 216 is an ohmic contact layer, 217 is an interlayer insulating film, 218 is a source / drain wiring, 219 is a lower electrode of a PIN photodiode, 220 is a PIN photodiode, 22
Reference numeral 1 denotes a PIN photodiode upper electrode, and reference numeral 222 denotes a final protective film. A phosphor is stacked on the upper part of the conventional example, and incident X-rays are converted into visible light by the phosphor and photoelectrically converted by a photodiode. Thereafter, the generated charges are accumulated inside the photodiode and are sequentially read out by the switch TFT.

[0010]

However, the TFT array widely used as described above has a characteristic that the area of the gate wiring is not negligible due to the large area, which is a characteristic of the TFT array. And the realization of a wiring with lower resistance is required. From such a request, the following measures are considered.

(1) Enlargement of gate wiring width (2) Increase in thickness of gate wiring (3) Development of low-resistance wiring However, in the liquid crystal display device, the following problems corresponding to each of the above are encountered. Has occurred and cannot be easily realized.

(1) The aperture ratio is reduced, and the display quality and the like are reduced.

(2) The coverage of the gate insulating film at the intersection of the TFT and the wiring is reduced, causing a reduction in the withstand voltage, which causes problems such as a reduction in quality and a reduction in yield. Also,
If the thickness of the gate insulating film is increased, T
The driving capability of the FT is reduced, the driving voltage is increased, and conversely, the breakdown voltage is reduced, the TFT size needs to be increased, and as a result, the aperture ratio decreases.

(3) Materials such as Al have been studied.
In order to obtain a sufficient resistance due to problems such as heat resistance, the film thickness is still necessary, and the same result as the above problem is obtained.

As described above, as the area becomes larger at present,
Reduction of the resistance of the gate wiring is a major issue at present.

On the other hand, the TFT array used in the above-described conventional PIN type photodetector has the following problems unique to the optical sensor in addition to the above-mentioned problems.

(1) The capacitance formed at the intersection of the gate wiring and the signal wiring becomes signal noise and lowers the S / N ratio.

(2) The resistance of the gate wiring similarly causes signal wiring noise, which lowers the S / N ratio. This has been studied in the same manner as the TFT array for a liquid crystal display device, but a fundamental solution has not yet been made.

Therefore, similarly to the above, lowering the resistance of the gate wiring is a major subject to be studied in the future. In general, when a TFT array is formed, at least a gate insulating film is formed at the same time at a TFT intersection and a wiring intersection, so that the film thickness and the like are set so as to satisfy each function.
Simply put, in the TFT section, as the gate insulating film becomes thinner, the driving capability of the TFT is improved, and the size of the TFT is reduced.
In other words, the aperture ratio can be improved, but conversely, the parasitic capacitance formed there increases at the wiring intersection, and as a result,
As described above, the result is an increase in noise. That is, T
Parasitic capacitance was inevitable in fabricating an FT array.

Accordingly, it is an object of the present invention to provide a thin film transistor array having a high aperture ratio by solving the above-mentioned conventional problems, achieving a reduction in resistance of a gate wiring and a reduction in parasitic capacitance.

[0021]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, a non-single-crystal semiconductor film, and a pair of semiconductor devices via an ohmic contact layer. And a signal line connected to one of the pair of electrodes, and at least an intersection of the gate line and the signal line. The thin film transistor array is characterized in that the insulating film of the portion and the gate insulating film of the thin film transistor are formed with different thicknesses.

Another object of the present invention is to provide a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, a non-single-crystal semiconductor film, and a pair of electrodes via an ohmic contact layer. And a signal line connected to one of the pair of electrodes, and at least a semiconductor layer at an intersection of the gate line and the signal line. And a non-single-crystal semiconductor layer of the thin film transistor are formed with different film thicknesses.

With the above configuration, a TFT array having a high aperture ratio and a high function can be realized, and the photodetector can achieve low noise, high S / N ratio, and high reliability.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) In the first embodiment,
A TFT array used in a liquid crystal display will be described. FIG. 1 is a schematic plan view showing the structure of a thin film transistor array according to a first embodiment of the present invention, and FIG. 2 is a schematic sectional view thereof. In FIG. 1, 1 is a gate wiring, 2 is a gate electrode, 3 is a data line, 4 is a source / drain electrode, 5
Denotes a pixel electrode, 6 denotes an intersection of a gate line and a data line, and 7 denotes a TFT portion. In FIG. 2, 8 is a gate insulating film, 9 is an a-Si film, 10 is an ohmic contact layer,
Reference numeral 12 denotes an intersection insulating film.

Next, an outline of a method for manufacturing the TFT array of the present embodiment will be described. First, a Cr thin film is formed on a glass substrate as a gate electrode 2 and a gate wiring 1 by a sputtering method at a thickness of 2000 .ANG., And the gate electrode 2 and the gate wiring 1 are simultaneously formed by wet or dry etching. Second, an SiN film is formed to a thickness of 3000 ° by a plasma CVD method, and the wiring intersections 6 are formed in an island shape by dry etching.

Third, a SiN film as the gate insulating film 8,
An a-Si film as a semiconductor layer and a SiN film as a protective film are formed by plasma CVD at 3000, 500, and 1000 Å.
ÅContinuous film formation. Thereafter, the protective film in the TFT source / drain region is removed by dry etching, and an ohmic contact layer 10 is formed to a thickness of 300 ° by a plasma CVD method.

Fourth, as the source / drain 4 electrodes,
An Al film is formed to a thickness of 1 μm by a sputtering method to form source / drain electrodes 4 and data wirings 3. Then, TF
The ohmic contact layer in the T channel portion is removed by dry etching. Fifth, a SiN film as a final protective film is formed.

In the TFT array manufactured as described above, the insulating film thickness at the intersection of the data wiring and the gate wiring is twice as large as that of the gate insulating film of the TFT. The film can be 2000 mm. As a result, it is possible to solve problems such as a delay in driving time due to an increase in area, and to improve an aperture ratio of a TFT array by optimizing a gate wiring width. At this time, since the insulating film between the gate electrode and the source / drain electrode of the TFT portion is not thickened, the withstand voltage is reduced. Various configurations can be realized. The standard is that the breakdown voltage satisfies approximately 80V.

(Second Embodiment) In the second embodiment,
A TFT array used in a liquid crystal display will be described. FIG. 3 is a schematic plan view showing the configuration of the second embodiment,
FIG. 4 is a schematic sectional view thereof. In FIG. 3, 1 is a gate wiring, 2 is a gate electrode, 3 is a data line, 4 is a source / drain electrode, 5 is a pixel electrode, 6 is an intersection of a gate wiring and a data line, and 7 is a TFT portion. In FIG. 4, reference numeral 8 denotes a gate insulating film, 9 denotes an a-Si film, 10 denotes an ohmic contact layer, and 12 denotes an intersection insulating film.

Next, an outline of a method of manufacturing the TFT array according to the second embodiment will be described. First, a Cr thin film is formed as a first gate wiring on a glass substrate by sputtering at a thickness of 1500 ° and a wiring is formed by wet or dry etching. Second, a Cr thin film is formed as a gate electrode and a second gate wiring by sputtering.
Then, a gate electrode 2 and a gate wiring 1 are formed by wet or dry etching. as a result,
The gate wiring is 2,000 degrees, and the gate electrode is 500 degrees. At this time, the wiring (first Cr) formed in the first step as shown in FIG. 5 is formed in the second step so that the first gate wiring is not etched at the time of forming the second gate wiring. In this structure, the wiring and the electrode (second Cr) are completely covered.

Next, third, a SiN film is formed by plasma CVD.
Then, the wiring intersection 6 is formed in an island shape by dry etching. Fourth, a SiN film as a gate insulating film 8, an a-Si film 9 as a semiconductor layer, and a SiN film as a protective film are formed by plasma CVD at 2000.
A film is continuously formed at 00 ° and 1000 °. Thereafter, the protective film in the TFT source / drain region is removed by dry etching, and an ohmic contact layer is formed to a thickness of 300 ° by a plasma CVD method.

Fifth, as the source / drain electrodes 4,
1 μm is formed by sputtering to form source / drain electrodes 4 and data wirings 3. After that, TFT
The ohmic contact layer in the channel portion is removed by dry etching. Sixth, a SiN film as a final protective film is formed.

In the TFT array manufactured as described above, the gate wiring has a thick film of 2000 な く without lowering the dielectric strength at the intersection 6 between the data wiring 3 and the gate wiring 1 as in the first embodiment. Further, since the gate electrode is 500 に お い て in the TFT portion, the thickness of the gate insulating film can be reduced to 2000 Å. In terms of withstand voltage, the thickness of the insulating film is required to be twice, preferably about three times the thickness of the gate electrode. As a result, it is possible to solve a problem such as a delay in driving time due to an increase in area,
The T capability is improved, and the TFT can be reduced in size. Further, the aperture ratio of the TFT array can be improved by optimizing the gate wiring width.

(Third Embodiment) In the third embodiment,
A photoelectric conversion element and a TFT array used in an X-ray detector will be described. FIG. 6 shows an equivalent circuit of the present embodiment.
In the figure, 31 is a TFT, 32 is a MIS type photoelectric conversion element, 3
3 is a gate wiring, 34 is a signal line, 35 is a sensor bias line, 36 is a gate driver, 37 is an amplifier IC, 38
Is an A / D converter.

FIG. 7 is a schematic sectional view of one pixel. In the figure, an incident X-ray 40 is converted into visible light by a phosphor 41, and the converted light is photoelectrically converted by a MIS type photoelectric conversion element 42. The photoelectrically converted charge is stored in the MIS type photoelectric conversion element 42 and read out as an electric signal by the switch TFT 43. Specifically, as shown in FIG. 8, the MIS-type photoelectric conversion element is composed of a combined capacitance of the semiconductor layer capacitance Ci and the insulating film capacitance Csin, the potential of the portion A in the figure rises by light incidence, and the potential is read. It has a configuration.

FIG. 9 is a schematic plan view of the present embodiment.
10 and 11 are enlarged sectional views of the portion A and the portion B in the drawings, respectively. Thus, the gate wiring has a two-layer structure,
Low resistance has been achieved, while the thickness of the TFT gate electrode has been reduced to improve TFT performance. The insulating film at the intersection of the wirings has a two-layer structure to prevent a decrease in withstand voltage due to a thicker gate wiring. In FIG. 9, the signal line is a straight wiring, but in the case of FIG. 12, the configuration is preferably such that the insulating film at the wiring intersection crosses the maximum width.

As a result, the TFT capability is improved and the TFT
It is possible to reduce the size, to reduce the parasitic capacitance at the wiring intersection, and to reduce the gate wiring resistance. Accordingly, the signal noise can be reduced, the aperture ratio can be further increased, and the performance of the photoelectric conversion element is also improved. As a result, as shown in FIG.
A ratio can be achieved.

Next, the manufacturing method of this embodiment will be described. FIGS. 14A to 14D and FIGS. 15A to 15C show mask patterns used in each step. In the first step, Cr was deposited on a glass substrate (OA-10 manufactured by NEC Corporation).
A thin film 1500 is formed by a sputtering method, and thereafter, the gate wiring 1 of the switch TFT is formed by a photolithography method using a first mask shown in FIG.
To form In the second step, the Cr thin film is continuously
Is formed by a sputtering method, and then the gate wiring 1 and the gate electrode 2 of the switch TFT and the lower electrode 13 of the MIS type photoelectric conversion element are formed by a photolithography method using a second mask shown in FIG. Form.

Next, in a third step, a 4000 nm SiN film 12 is formed as an intersection insulating film by a plasma CVD method, and at least a gate wiring and a signal are formed using a third mask shown in FIG. Form an intersection with a line.
In the fourth step, S is used as the gate insulating film of the switch TFT.
The iN film 8 is 2000 °, the a-Si film 9 is 6000 ° as a semiconductor layer, and the n ⁺ film 10 is an ohmic contact layer.
Is continuously formed at 500 °. In the fifth step, a contact hole 14 between the TFT drain electrode and the lower electrode of the MIS type photoelectric conversion element is formed. In this method, a predetermined pattern is formed by a photolithography method using a fourth mask shown in FIG. 14D, and is processed by an RIE method.

Subsequently, in a sixth step, an Al thin film of 1 μm is formed by a sputtering method. Thereafter, the bias wiring 15 of the MIS type photoelectric conversion element is formed by a photolithography method using the fifth mask shown in FIG. In the seventh step, the source / drain electrodes 1 of the TFT are similarly formed by using the sixth mask shown in FIG.
6 is formed. Thereafter, n is successively obtained by the RIE method.
^{The +} film 500 ° and the a-Si film are etched by about 200 °. In the eighth step, FIG.
A predetermined pattern is formed using a seventh mask shown in FIG. 5C, and an n ⁺ film, an a-Si film, and a SiN film are formed by RIE.
The film is simultaneously etched to separate elements.

In a ninth step, a SiN film (not shown) is formed as a passivation film by a plasma CVD method, and then formed in a predetermined pattern using an eighth mask.
Unnecessary portions such as a wiring lead portion (not shown) are etched by RIE. After that, probing the wiring lead-out part and performing characteristic inspection, connecting the open part of the wiring by laser CVD and cutting the short part by laser,
Isolate the defective part. Then, the repaired portion is protected by polyimide. FIG. 16 shows a schematic plan view of the photodetector thus manufactured. In the figure, 21 is MI
An S-type sensor section, 22 is a switch TFT section, 23 is a signal wiring, 24 is a gate wiring, and 25 is a sensor upper electrode wiring.

(Fourth Embodiment) In the fourth embodiment,
A photoelectric conversion element and a TFT array used in an X-ray detector will be described. In the fourth embodiment, only the semiconductor layer in the TFT section is thinned in the third embodiment, and
The aperture ratio is improved by improving the FT capability and reducing the size of the TFT. Hereinafter, the manufacturing method of the fourth embodiment will be described.

In the first step, a 1500 nm Cr thin film is formed on a glass substrate (OA-10 manufactured by NEC Corporation) by a sputtering method, and then the first mask shown in FIG. The gate wiring 1 of the switch TFT is formed by using this. In the second step, a Cr thin film 500 引 き 続 き is continuously formed by the sputtering method, and thereafter, FIG.
The gate wiring 1 and gate electrode 2 of the switch TFT and the lower electrode 13 of the MIS type photoelectric conversion element are formed using the second mask shown in FIG.

Next, in a third step, a 4000 nm SiN film 12 is formed as an intersection insulating film by a plasma CVD method, and at least a gate wiring and a signal line are formed using a third mask shown in FIG. To form an intersection. In the fourth step, SiN is used as the gate insulating film of the switch TFT.
The film 8 is 2000Å, and the a-Si film 9 is 60
00 ° is continuously formed. In the fifth step, only the TFT portion has a predetermined film thickness, in this case, a mask (not shown).
It is thinned by RIE method to a thickness of up to 000 °.

Further, in the sixth step, an n ⁺ film 10 is formed as an ohmic contact electrode by a plasma CVD method.
0 ° continuous film formation. In the seventh step, a contact hole 14 between the TFT drain electrode and the lower electrode of the MIS type photoelectric conversion element is formed. In this method, a predetermined pattern is formed by a photolithography method using a fourth mask shown in FIG. 14D, and is processed by an RIE method. In an eighth step, an Al thin film of 1 μm is formed by a sputtering method.
After that, the bias wiring 15 of the MIS type photoelectric conversion element is formed by a photolithography method using the fifth mask shown in FIG.

In the ninth step, similarly, the source / drain electrodes 16 of the TFT are formed using the sixth mask shown in FIG. Thereafter, n is continuously obtained by the RIE method.
^{The +} film 500 ° and the a-Si film are etched by about 200 °. In a tenth step, a predetermined pattern is formed by photolithography using a seventh mask shown in FIG. 15C, and an n ⁺ film, a-Si film, and Si film are formed by RIE.
The N film is simultaneously etched to perform element isolation. Eleventh
In the process, an SiN film (not shown) is formed as a passivation film by a plasma CVD method, and then a predetermined pattern is formed using an eighth mask, and unnecessary portions such as a wiring lead portion (not shown) are formed. Is etched by the RIE method.

(Fifth Embodiment) In the fifth embodiment,
An X-ray direct conversion element and a TFT array used in an X-ray detection device will be described. FIG. 17 is a diagram illustrating the principle of the present embodiment. GdTe fixed at a constant bias, a-
When an X-ray is incident on a direct conversion detector such as Se or PbI ₂ , an electron-hole pair is generated, and electrons and holes travel according to electrolysis, and are stored in a connected storage capacitor. Thereafter, the data is sequentially transferred to the readout circuit by the TFT.

FIG. 18 shows a material 5 such as a-Se or PbI _2.
2 is formed so as to be sandwiched between electrodes on a base 51 and connected to a TFT array 53 by an anisotropic adhesive or the like. In the case where a crystal such as CdTe is used, it is possible to directly connect electrodes without using a base. FIG. 19 shows a structure in which a direct conversion material is directly formed on a TFT array.

FIG. 20 is a schematic sectional view when the TFT array of the present invention is used in a direct X-ray detector in the same manner as in the second embodiment. In FIG. 20, 300 is TF
T portion, 301 is a wiring intersection, 302 is a storage capacitor portion, 303 is a pixel electrode, 304 is an X-ray direct conversion material,
05 is a bias electrode. By using such a TFT array, it is possible to reduce signal noise and achieve an improvement in the aperture ratio that can increase the size of the storage capacitor.

[0051]

As described above, according to the present invention, at least the insulating film at the intersection of the gate wiring and the signal wiring and the gate insulating film of the thin film transistor are formed to have different thicknesses, so that the TFT structure can be improved. Optimization and optimization of wiring intersections can be achieved simultaneously. Further, by separately forming the gate wiring and the gate electrode, a reduction in wiring resistance can be achieved.

Similarly, at least the semiconductor layer at the intersection of the gate wiring and the signal wiring and the semiconductor layer of the thin film transistor are formed with different thicknesses, thereby optimizing the TFT structure and the wiring intersection. Can be achieved simultaneously. Similarly, by separately forming the TFT source / drain electrode and the wiring for each function in the signal line or the data line, noise depending on the wiring resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of FIG.

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a schematic sectional view of FIG.

FIG. 5 is an enlarged view showing a part of FIG. 4;

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

7 is a schematic cross-sectional view of one pixel of FIG.

FIG. 8 is a circuit diagram of FIG. 7;

FIG. 9 is a schematic plan view of a third embodiment of the present invention.

FIG. 10 is an enlarged sectional view of a portion A in FIG. 9;

FIG. 11 is an enlarged sectional view of a portion B in FIG. 9;

FIG. 12 is a diagram showing another example of the wiring intersection.

FIG. 13 is a diagram showing an S / N ratio of the third embodiment in comparison with a conventional example.

FIG. 14 is a plan view showing a mask pattern used in the manufacturing method according to the third embodiment of the present invention.

FIG. 15 is a plan view showing a mask pattern used in the manufacturing method according to the third embodiment of the present invention.

FIG. 16 is a schematic plan view showing a photodetector completed by the manufacturing method according to the third embodiment of the present invention.

FIG. 17 is a diagram showing the principle of the fifth embodiment of the present invention.

FIG. 18 is a schematic sectional view of a fifth embodiment of the present invention.

FIG. 19 is a diagram showing an embodiment in which a direct conversion material is formed on a direct TFT array.

FIG. 20 is a schematic cross-sectional view when a TFT array according to the present invention is used in a direct X-ray detector.

FIG. 21 is a circuit diagram showing a liquid crystal display device using a conventional TFT array.

FIG. 22 is a schematic sectional view of one pixel of FIG. 21;

FIG. 23 is a schematic sectional view of a channel etching type.

FIG. 24 is a schematic sectional view of a channel stopper type.

FIG. 25 is a diagram illustrating a method of manufacturing a channel etching type TFT array.

FIG. 26 shows X using a PIN photosensor and a TFT array.
It is a circuit diagram showing an example of a line detection device.

FIG. 27 is a schematic sectional view of one pixel of FIG. 26;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate wiring 2 Gate electrode 3 Data line 4 Source / drain electrode 5 Pixel electrode 6 Wiring intersection 7 TFT part 8 Gate insulating film 9 a-Si film 10 Ohmic contact layer 12 Intersection insulating film 13 Lower electrode 14 Contact hole 15 Bias Line 16 Source / drain electrode 21 MIS type optical sensor 22 Switch TFT section 23 Signal wiring 24 Gate wiring

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA05 AB01 BA05 CA05 CB06 CB11 FB03 FB13 5F110 AA02 AA03 AA30 BB01 BB10 CC07 DD02 EE04 EE37 EE44 FF03 FF30 GG02 GG15 GG25 GG45 HK03 NN21 NN19 NN33

Claims (10)

[Claims] A thin film transistor including a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, a non-single-crystal semiconductor film, and a pair of electrodes via an ohmic contact layer; In a thin film transistor array including a gate wiring connected to an electrode and a signal wiring connected to one of the pair of electrodes, at least an insulating film at an intersection of the gate wiring and the signal wiring and a gate insulating film of the thin film transistor A thin film transistor array characterized by having different film thicknesses. 2. The thin film transistor array according to claim 1, wherein the gate electrode and the gate wiring have different thicknesses. 3. The thin film transistor array according to claim 1, wherein the gate electrode and the gate wiring are made of different materials. 4. The thin film transistor array according to claim 1, wherein the pair of electrodes and the signal wiring have different thicknesses. 5. The thin film transistor array according to claim 1, wherein the pair of electrodes and the signal wiring are made of different materials. 6. A thin film transistor comprising a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, a non-single-crystal semiconductor film, and a pair of electrodes via an ohmic contact layer; In a thin film transistor array including a gate wiring connected to an electrode and a signal wiring connected to one of the pair of electrodes, at least a semiconductor layer at an intersection of the gate wiring and the signal wiring and a non-single-crystal thin film transistor A thin film transistor array, wherein the semiconductor layer is formed with a different film thickness. 7. The thin film transistor array according to claim 6, wherein the gate electrode and the gate wiring have different thicknesses. 8. The thin film transistor array according to claim 6, wherein the gate electrode and the gate wiring are made of different materials. 9. The thin film transistor array according to claim 6, wherein the pair of electrodes and the signal wiring have different thicknesses. 10. The thin film transistor array according to claim 6, wherein the pair of electrodes and the signal wiring are made of different materials.