TWI281999B - LCD device and manufacturing method thereof - Google Patents

Abstract

Conventional manufacturing method for cutting the quantity in production engineering has the technical issue in small production tolerance and low production quantity. The resolution combines the introduction of half-tone exposure technique, islandization of semiconductor layers and formation of the opening of gate insulation layer as a rational new technique, and introduces the half-tone exposure technique to the source pertinent to know technique, drain wiring and anode oxidation to form rational new technique for passivation of electrode terminal, and the known technique also pertinent to rational technique in formation of image electrode and scan line, so as to built up the 4 mask fabrication solution and 3 mask fabrication solution of the TN LCD device and IPS LCD device.

Description

1281999 (1) Field of the Invention The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active type liquid crystal display device. [Prior Art] Based on recent advances in microfabrication technology, liquid crystal material technology, and high-density mounting technology, a large number of liquid crystal display devices with diagonal sizes of 5 to 5 cm are provided for commercial use as television image or various image display devices. . Further, it is also easy to perform color display by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, the active liquid crystal panel in which the switching elements are incorporated in each pixel ensures a low-contrast image with relatively low cross-talk and fast response speed. Although the liquid crystal display devices (liquid crystal panels) are generally prepared by a matrix of 200 to 1 200 scanning lines and 300 to 1 600 signal lines, they have recently been performed correspondingly to an increase in display capacity. The big picture and high definition. Fig. 1 is a view showing the actual mounting state of the liquid crystal panel, and the driving signal is supplied to the electrode formed on the transparent insulating substrate constituting one of the liquid crystal panels 1, for example, the scanning line on the glass substrate 2, using a conductive adhesive connection. The COG (Chip-On-G1 ass) method of the semiconductor integrated circuit chip 3 of the terminal group 5, or a polyimide resin film, for example, as a substrate, and a suitable adhesive containing a conductive medium, will have gold plating or A TCP (Tape_Carrier-Package 1281999 (2)) film 4 on which a copper terminal (not shown) of a solder is plated, an actual mounting means such as a TCP method of pressing and fixing the electrode terminal group 6 of the signal line, and an electric signal is supplied. To the image display section. Here, in order to facilitate the simultaneous display of the two mounting methods, one of the two may be appropriately selected in practice. 7 and 8 are connecting lines between the pixels in the image display portion located at the approximate central portion of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the scanning lines and the signal lines, and are not necessarily required to be combined with the electrode terminal groups 5 and 6. Consisting of the same conductive material. 9 is an opposite glass substrate or a color filter having another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposite surface. Fig. 14 is an equivalent circuit diagram of an active type liquid crystal display device in which an insulating gate type transistor is disposed as a switching element per pixel, and Fig. 1 1 (7 in Fig. 13) is a scanning line, 12 (first) In the figure, 8) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically used as a capacitive element. The elements drawn by the solid line are formed on the glass substrate 2 constituting one of the liquid crystal panels, and all the counter electrodes 14 common to the liquid crystal cells 13 drawn by the broken lines are formed on the opposite main surfaces of the other glass substrate 9. on. When the OFF resistance of the insulating gate type transistor 10 or the resistance of the liquid crystal cell 13 is low or when the gray scale of the image is emphasized, it is necessary to seek some time for increasing the liquid crystal cell as a load. The number of storage capacitors 15 is applied in parallel to the circuit improving means such as the liquid crystal cell 13 or the like. And '16' is a common bus of the storage capacitor 15. Fig. 15 is a cross-sectional view showing an important part of an image display unit of a liquid crystal display device. The two glass substrates 2 and 9 constituting the liquid crystal panel 1 are formed of color by -5 - (3) 1281999 resin fibers, beads or a spacer material (not shown) such as a columnar spacer on the filter 9, and a sealing material and/or a sealing material composed of an organic resin between the specific distances of #m, and no sealing material (all of which are not shown) The sealing portion is formed on the peripheral portion of the glass substrate 9 to form a closed space between the two glass plates 2'9, and the crystal material 17 is accommodated in the closed space. In the case of color display, it is given a color display function by any one of dyes or pigments called the colored layer 18 on the side of the closed space of the glass substrate or an organic film containing both degrees 1 to 1 The glass substrate 9 is also called a color filter (abbreviated as Color Filter). Then, a polarizing plate 1 is attached to either or both of the surfaces of the liquid crystal panel 1 in accordance with the properties of the liquid crystal material 17. The liquid crystal panel 1 functions as a photovoltaic element. Nowadays, the liquid crystal material of most liquid crystal surfaces on the market is a liquid crystal material using a TN (Twist Nematic) series. The polarizing plate 19 usually requires two sheets. Although not shown, the back surface light source is disposed as a light source through the crystal panel, and white light is irradiated from below. Connected to the liquid crystal 17 is formed on the two glass substrates 2, 9 as the thickness is 0. The polyimine resin film 20 of about 1/zm is an alignment film for aligning liquid crystal molecules in a determined direction. 2 1 is a pixel electrode connected to the edge of the gate type transistor 10 and a transparent conductive pixel 22 electrode (wiring), which is formed at the same time as the signal line (source line) at the signal line 1 2 and 汲Between the electrode electrodes 2 1 is a semiconductor 23, which will be described in detail later. The Cr film layer 24 having a thickness formed on the side of the adjacent colored layer 18 on the color filter 9 is used to prevent the external gap from being attached to the CF side as a sheet liquid.于界光-6- 1281999 (4) A light-shielding member that is incident on the semiconductor layer 23 and the scanning line 1 1 and the signal line 1 2 is defined as a so-called black matrix (abbreviated as BM). . Here, a configuration and a manufacturing method of an insulating gate type transistor which is a switching element will be described. There are two types of common insulated gate type transistors, and one of them is referred to as a channel etching type. With the introduction of dry etching technology, it used to require about 8 masks, which is now reduced to 5 channels, which greatly contributes to the reduction of manufacturing costs. Fig. 16 is a plan view showing a unit pixel of an active substrate (a semiconductor device for a display device) corresponding to a five-mask process, and Fig. 17 is a view showing A-A' and B-B' of Fig. 16(e). And the cross-section on the C-C' line, the following is a brief description of the manufacturing process. In Fig. 16(c), a storage capacitor 15 is formed in a region 5 〇 (upper diagonal line from the upper left to the lower right) in which the storage capacitor 16 and the drain electrode 2 1 are interposed by the gate insulating layer, but This explanation is omitted here. First, as shown in Fig. 16 (a) and Fig. 17 (a), the thickness of the insulating substrate which is high in heat resistance and chemical resistance and transparency is 0. 5~ l. 】mm glass substrate 2, for example, using SPT (sputtering) on the main surface of one of the trade names 1737 produced by C. Niiig Co., Ltd., the film thickness is 〇·1~0. The first metal layer of 3/m is selectively formed to serve as the scan line 1 1 of the gate electrode 1 1 A and the storage capacitor line 16 by microfabrication techniques. The material of the scanning line is selected in consideration of chemical resistance, fluorine acid resistance, and electrical conductivity. However, generally, a metal or alloy having high heat resistance such as chromium Cr, giant Ta, or tungsten molybdenum (MoW) alloy is used. -7- (5) 1281999 In order to reduce the resistance of the scanning line in response to the large screen or high definition of the liquid crystal panel, although A1 (aluminum) is used as the scanning line material, the heat resistance of the A1 monomer is low, so Nowadays, it is a general technique to laminate Ci*, Ta, Mo or a telluride which is a heat resistant metal or to apply an anodization to an oxide layer (ai2o3) on the surface of A1. That is, the scanning line 11 is composed of one or more metal layers. Next, a plasma chemical oxygen phase deposition (PC VD) device is used on the entire surface of the glass substrate 2, for example, 0. 3-0. 2-0· 05 /im film thickness, sequentially depositing a tantalum nitride (SiNx) layer 30 as a gate insulating layer, a first amorphous germanium layer 3 of a channel of an insulating gate type transistor containing almost no impurities 1 and 3 kinds of thin film layers such as the source of the insulating gate type transistor containing impurities and the second amorphous germanium layer 3 3 of the drain. Then, as shown in FIGS. 16(b) and 17(b), the first sum which is wider than the width of the electrode A1 of the gate 1 1 remains in the island shape (31A, 32A) on the gate electrode 11A. The semiconductor layer formed of the second amorphous germanium layer exposes the gate insulating layer 30. Next, using a vacuum film forming apparatus such as SPT, a Ti (titanium) thin film layer 34 is sequentially deposited to have a film thickness of 0. A heat resistant metal layer of about 1 / im, A1 film layer 35 is a film thickness of 0. A low-resistance wiring layer of about 3 // m, for example, a Ti film layer 36 is a film thickness of 0. An intermediate conductive layer of about 1/m is selectively laminated by the thin film layers 34A, 35A, and 36A by microfabrication techniques as shown in Figs. 16(c) and 7(c). The gate electrode 2 1 of the insulated gate type transistor and the signal line 1 2 which also serves as the source electrode. The selective pattern formation is to form the photosensitive resin pattern used for the drain wiring as a mask, and sequentially etch the Ti thin film layer 36, the A1 thin film layer-8-(6) 1281999 3 5, the T i thin film layer. 3 4. The second amorphous germanium layer 3 3 A and the first amorphous layer 3 1 A, and the first amorphous sand layer 3 1 A is engraved by uranium.  〇 5~0 .  //m or so, so it is called channel etching. In order to prevent the insulating gate type transistor from becoming a compensation structure, the source electrode electrodes 12, 21 are partially formed (number #πι) and planarly overlap with the gate electrode. Since the overlap is performed as a parasitic capacitance, the smaller the better, the better the accuracy of the exposure machine and the expansion coefficient of the glass substrate and the temperature of the glass substrate during exposure. 2//m or so. When the wiring resistance of the signal line 1 2 is not a problem, the low-resistance wiring layer 35 composed of A1 is not required. At this time, if a heat-resistant metal material such as Ti, Ta, or Mo is selected, the source can be used. Pole and bungee 1 2, 2 1 are single-layered to simplify the process. In addition, the heat resistance of the insulating body is described in detail in JP-A-H07-74368, and after removing the photosensitive resin pattern, PC VD is used on the entire surface of the glass substrate 2 to be transparent. The gate layer of the insulating layer is identically covered. The SiNx layer of film thickness of about 3 // m is used as a passivation insulating layer 37. As shown in Fig. 16 (d) and Fig. 17, the protective insulating layer is selectively removed and applied to the drain electrode according to microfabrication techniques. An opening 62 is formed in the upper surface of the image display portion, and an opening 63 is formed at a position where the electrode terminal 5 of the scanning line 1 is formed, and a portion 64 is formed at a position where the electrode terminal 6 of the signal line 1 is formed to be exposed. The drain electrode 2 1 and the scan line 1 1 and the signal line 1 2 are divided. On the storage capacitor line 16 (electrode pattern of the parallel bundle), the shape is 矽•汲1 1 A, the accuracy is determined, and the Cr and the wiring crystal device are absolutely protected ((d) 37, the opening of the mouth part is The part is opened -9 - (7) 1281999 Port 6 5 and one part of the storage capacitor line 1 6 is exposed. Finally, the vacuum film forming apparatus such as SPT is used to cover the film thickness 〇1~〇·2 in or so ΪΤΟ (Indium- Tin-Oxide, Indium-Zinc-〇xide, as a transparent conductive layer, as shown in Figures 16(e) and 17(e), The pixel electrode 22 is selectively formed by the microfabrication technique including the opening portion 62 on the protective insulating layer 37, and the active substrate 2 is completed. Even if a portion of the exposed scanning line 11 in the opening portion 63 is regarded as the electrode terminal 5 A portion of the exposed signal line 1 2 in the opening portion 64 may be used as the electrode terminal 6. Alternatively, as shown in the figure, the protective insulating layer 37 may be formed of ITO by including openings 63 and 64. The electrode terminals 5A, 6A may also be, but generally also form a transparent conductive connection between the electrode terminals 5A, 6A. The short-circuit line 40. The reason for this is that the electrode terminals 5A and 6A and the short-circuit line 40 are formed in a long strip shape to increase the resistance, and the high-resistance can be used as a countermeasure against static electricity. The electrode terminal of the portion 65 leads to the storage capacitor line 16. The problem to be solved by the invention is that in the five-mask project, since the contact formation between the gate electrode 21 and the scanning line 11 is simultaneously performed, it is necessary to The thickness and type of the insulating layer in the openings 6 2, 6 3 are different. The protective insulating layer 37 has a lower film forming temperature than the gate insulating layer 30', and the film quality is poor, and is performed by an etching solution of a gas acid series. The wet etching is performed because the etching speed is several 〇〇〇A/min, the number is 100 A/min, and the difference is one order of magnitude. The opening on the drain electrode 21 (8) 1281999 The cross-sectional shape of the mouth portion 62 is due to the upper portion. In the case of excessive pore size, even if dry etching is used, the gas on the drain electrode 2 1 is the protective insulating layer 3 7, so that over-etching is avoided as compared with the opening on the scan line 1 1 . There are times when the material is different The film thickness is reduced by the etching gas. Further, in order to remove the photosensitive resin pattern, first, in order to remove the fluorine-containing compound, oxygen plasma is ashed, and the photosensitive resin is patterned. 1~0. 3 / m or so, after that, the liquid medicine such as the stripping liquid 106 produced by using the organic peeling treatment is treated as the oxygen electrode ash when the intermediate conductive layer 3 6 A is cut to expose the aluminum f of the base. The Al2〇3 in the surface insulator of the aluminum layer 35A is treated to be in contact with the pixel electrode 22. Here, in order to reduce the film of the intermediate conductive layer 3 6 A, the film thickness is set to 0. 2 // m to solve the problem. At the time of the mouth portions 62 to 65, the aluminum layer 35A is removed to expose the film layer 34A of the base layer, and then the pixel electrode 22 is formed. In this case, the intermediate gas guide point is not required from the beginning. However, in the former countermeasures, if the film properties of the films are not good, the blending does not necessarily play an effective role. The in-plane uniformity of the speed is not the same. Therefore, although the intermediate conductive layer 36A is not required, the addition process is increased, and the cross-section control of the opening portion 6 2 is not sufficiently etched to control the dry etching. The mouth portion 62 is a surface-reducing liquid for agglomerating the surface of the surface after the etching of the conductive layer 3 6 A is not performed, for example, the Tokyo-like method, but the state surface of the i 3 5 A is formed. It is not necessary to obtain an ohmic thickness. For example, the heat-resistant metal avoiding countermeasure for forming the opening may be uniform in the in-plane of the I layer 36A, and further, when the aluminum layer is removed from the aluminum layer 3 5 A in the countermeasure of etching the latter, Then there is a possibility that -11 - (9) 1281999 pixel electrode 2 2 is broken. In addition, the first amorphous sand layer 31 containing no impurities in the channel region of the channel-etched insulating gate type transistor is not thickened (the channel etching type is usually 0. When 2 # m or more, the influence on the in-plane uniformity of the glass substrate is greatly affected, and the characteristics of the transistor are inconsistent, especially the OFF current is inconsistent. This situation greatly affects the operating rate of the PVCD device and the particle generation state, which is also a very important issue from the viewpoint of production cost. Next, a four-mask process for improving one of the above five mask processes will be described. The four-mask process is based on the introduction of halftone exposure technology to reduce the lithography process. Figure 18 is a plan view of the unit pixel corresponding to the active substrate of the four mask processes, and Figure 19 is the 18th figure (e). Sections of the eight-A', B-B' and C-C' lines. First, on the main surface of one of the glass substrates 2, using a vacuum film forming apparatus such as SPT, the film thickness is 0. 1~0. a first metal layer of about 3/m, and as shown in Figs. 18(a) and 19(a), a scanning line 1 which also serves as a gate electrode 1 1 A is selectively formed by a microfabrication technique. 1 and storage capacitor line 16. Then, using the PCVD apparatus, the entire surface of the glass substrate 2 is, for example, 〇·3~0. 2~0. 0 5 m around the film thickness, sequentially depositing a tantalum nitride (SiNx) layer 30 as a gate insulating layer, a first amorphous germanium layer 3 1 of an insulating gate transistor having almost no impurity And three kinds of thin film layers such as the source of the insulating gate type transistor containing impurities and the second amorphous germanium layer 3 3 of the drain. Next, a vacuum film forming apparatus such as SPT is used to sequentially coat a film thickness of, for example, a Ti film layer 34' as a heat resistant metal layer of about -12 - (10) 1281999 film thickness. 3 " AI film layer 36' which is a low-resistance wiring layer, that is, a source/drain wiring material, although selectively formed by the microfabrication technology, the film layers 3 4 A, 3 5 A, The drain electrode 2 1 of the insulating gate type transistor formed by the stack of 3 6 A and the signal line 1 2 ' which also serves as the source electrode are formed by the halftone exposure technique such as the first 8 As shown in Fig. (b) and Fig. 19 (b), for example, a film thickness is formed. The channel formation region 80C (hatched portion) between the sources of the source and the drains of the source/drainage lines is formed to have a film thickness of 3 // m which is thinner than the source/drain wiring formation regions 80A and 80B. The point of A~8 0 C is a major feature. In the photosensitive resin patterns 80A to 80C, the substrate for liquid crystal display device is made of a photosensitive resin of a normal positive type, so that the source/drain wiring formation regions 80A and 80B are black, that is, a Cr film is formed, and the channel region is formed. 80C is gray, for example, forming a width of 0. 5~1 // m is added to the line and space of the Cr pattern, and the other areas are white, that is, if the mask of the Cr film is removed. Since the resolution of the exposure machine is insufficient in the gray area, it is impossible to analyze the line and the blank line, and since the light from the light source of the light source can be transmitted by about one-half of the light, the residual film characteristics of the positive photosensitive resin can be obtained. The photosensitive resin patterns 80 A to 80C having a cross-sectional shape as shown in Fig. 19 (b). The photosensitive resin patterns 80A to 80C are used as masks, and the Ti thin film layer 36, the A1 thin film layer 35, the Ti thin film layer 34, and the second amorphous germanium layer are sequentially etched as shown in Fig. 19(b). 3 3 and the first amorphous germanium layer 3 1 and after the gate insulating layer 30 is exposed, as shown in FIGS. 18(c) and 19(c-13-(11)1281999), The ashing means of oxygen plasma or the like reduces the film thickness of the photosensitive trees 80A to 80C, for example, from 3/m. When 5/zm or more and 81 A and 81B, the photosensitive resin pattern 80C disappears and the exposed area is obtained. Here, the photosensitive resin patterns 8 1 A and 8 1 after the film reduction are used as a mask, and the Ti film layer 36A, the A1 film layer 35A, and the Ti film are again etched by the source/drain wiring (channel formation). Layer 34A 2 amorphous germanium layer 33A and first amorphous germanium layer 31 A, the first amorphous layer 31A is etching residual 0. 05~0. 1/im or so. Further, in the upper gas plasma treatment, since the change in the pattern size is suppressed, it is preferable to enhance the orientation, and the reason will be described later. Further, after the photosensitive resin patterns 8 1 A and 8 1 B are removed, the mask process is the same, and as shown in FIGS. 18(d) and 19(d), the glass substrate 2 is entirely covered with 0. A layer having a thickness of about 3/m is used as a transparent insulating layer, and is used as a protective insulating layer 37, and the electrode 2 and the electrode 5 and 6 on which the scanning line 1 1 and the signal line 1 2 are formed are formed on the electrode 2 1 . Openings 6 2, 6 3, and 6 4 are formed in the regions. Finally, a vacuum film forming apparatus such as SPT is used to cover, for example, or IZO to form a film thickness of 0. 1 ~ 〇. A transparent conductive layer of about 2/m, as shown in FIGS. 8(e) and 19(e), the transparent insulating layer is selectively formed on the protective insulating layer 37 having the opening 62 by microfabrication. The active substrate 2 is completed by the pixel electrode 22'. The electrode terminals include electrode terminals 5A and 6A formed of ITOs selectively formed on the protective insulating layer 37. The lipid case becomes the channel B. When the region is the same as the region, the SiNx is shown in the 氧 terminal ITO, and the ITO terminal is electrically conductive (12)! 281999 [invention] [the problem to be solved by the invention] By using the halftone exposure technology, it is possible to reduce the five mask processes to four masks, and obtain almost the same product as the five mask processes. However, in the four-mask process, the channel forming process is applied to selectively remove the source/drain wiring material and the semiconductor layer between the source and drain wirings 1, 2 and 2, and it is determined that the gate type can be left and right. The channel length of the ON characteristic of the transistor (currently the product is 4~6 #m) works. The length variation of the length of the channel causes a large change in the ON current of the insulated gate type transistor, so strict manufacturing management is usually required. As described above, the pattern length of the channel length, that is, the halftone exposure area is the exposure amount (light source intensity and mask precision, especially line and blank line size), the coating thickness of the photosensitive resin, the development processing of the photosensitive resin, and the In addition to the plurality of parameters such as the amount of film reduction of the photosensitive resin in the etching process, the in-plane uniformity of these amounts is also the same, and it is not always possible to achieve stable production with high throughput. More stringent manufacturing management than ever before, in the current situation, can not be said to have reached the level of high completion. In particular, when the channel length is 6/zm or less, the tendency is more remarkable. The present invention has been created in view of the current situation, and not only avoids the inconvenience in the formation contact of the past five mask processes or the four mask processes, but also realizes the deletion manufacturing process by using the halftone exposure technology with large error tolerance. By. Furthermore, in order to realize the low price of the liquid crystal panel and corresponding to the increase in demand, it is obvious that it is necessary to pursue the deletion of more manufacturing engineering numbers, which contributes to simplifying the main manufacturing engineering or the low-cost technology. Further increase -15- (13) 1281999 The price of the present invention. [Means for Solving the Problem] In the present invention, the halftone exposure technique is first applied to the islanding process of the semiconductor layer and the contact formation process of the gate insulating layer, which are easy to perform pattern precision management, and the manufacturing process is reduced. Next, in order to impart a channel protective layer to the insulating gate type transistor, the semiconductor layer containing impurities is converted into a hafnium oxide layer by anodization, which is disclosed in Japanese Patent Laid-Open No. Hei 4-3 0243 8 of the prior art. The technique, and the source-drain wiring which is effective to protect the source, is disclosed in Japanese Laid-Open Patent Publication No. Hei 2-2 16129, which is formed on the surface of the source/drain wiring composed of aluminum. The anodizing technology of the insulating layer realizes the rationalization and low temperature of the process. Further, a technique for rationalizing the formation of a pixel electrode disclosed in Japanese Laid-Open Patent Publication No. Hei. In addition, in order to eliminate the engineering, the formation of the anodized layer of the source/drain wiring is also applied to the halftone exposure technique to rationalize the formation of the protective layer of the electrode terminal. The insulated gate transistor according to the first aspect of the invention is a bottom gate type insulated gate type transistor, characterized in that a first metal layer of one or more layers is formed on the insulating substrate. In the gate electrode, one or more gate insulating layers are interposed in the gate electrode, and a first semiconductor layer containing no impurities is formed in an island shape, and a part of the first semiconductor layer is formed to overlap with the gate electrode. The first semiconductor layer containing impurities, which is a source/drain of the insulating gate type transistor, is formed on the second semiconductive-16-(14) 1281999 bulk layer and the gate insulating layer. a source/drain wiring composed of a metal layer and an anodized metal layer of one or more layers, and formed on the source/drain wiring and the channel in addition to the electrical connection region of the source wiring The anodized layer and the anodized layer do not need to be provided with a protective insulating layer such as SiNx because of the function of the protective layer. The liquid crystal display device is in the third, fourth, sixth, and second, third, and third 5. In the sixth embodiment Clearly documented. The liquid crystal display device according to the second aspect of the patent application is characterized in that the liquid crystal is charged on a main surface having at least an insulating gate type transistor and a gate electrode of the insulating gate type transistor. And a first transparent insulating substrate in which a unit line which is also used as a source wiring and a pixel element connected to a pixel electrode connected to the drain wiring is arranged in a matrix of two elements, and is insulated from the first transparent A liquid crystal display device comprising a second transparent insulating substrate or a color filter that faces between the substrates, wherein at least one of the main surfaces of the first transparent insulating substrate is formed of a transparent conductive layer and a metal layer a scan line formed by lamination and a transparent conductive pixel electrode; a plasma protective layer and a gate insulating layer are interposed on the gate electrode, and a first semiconductor layer containing no impurities is formed in an island shape; a first semiconductor layer is formed on the first semiconductor layer to form a second semiconductor layer containing impurities, which is a source/drain of the insulating gate-type transistor, and a plasma on the pixel electrode. An opening layer of -17-(15) 1281999 is formed on the protective layer and the gate insulating layer; and a heat-resistant layer is formed on the second semiconductor layer and the gate insulating layer and is anodized by one or more layers a source line (signal line) formed of a metal layer, and a drain line formed on the second semiconductor layer and the gate insulating layer and one of the pixel electrodes in the opening; A protective insulating layer having an opening on the electrode is formed on the transparent insulating substrate. According to this configuration, the lithography process number of the scanning line and the pixel electricity is reduced by using one mask, and the islanding process and the gate insulating layer for processing the semiconductor layer using one mask are also added. The number of photographic etching processes for forming the opening portion is reduced, and a TN liquid crystal display device can be manufactured using four masks. Further, since the thicknesses of the protective insulating layers of the electrode terminals of the scanning lines and the signal lines are the same, there is no problem associated with the formation of contact. The liquid crystal display device of the third aspect of the patent application is a scanning line which is filled with a gate electrode having at least an insulating gate type transistor and a gate electrode of the above-described insulating gate type transistor on a main surface. a first transparent insulating substrate in which a bit line of a source line and a pixel element connected to a pixel electrode connected to the drain line are arranged in a matrix of two elements, and the first transparent insulating substrate is opposed to the first transparent insulating substrate. A liquid crystal display device comprising a second transparent insulating substrate or a color filter is characterized in that at least one of the first transparent insulating substrates is formed on the first surface of the first transparent insulating substrate. The crystal monopole and the plate are scanning lines formed of a metal layer on -18-(16) 1281999; the gate insulating layer of the first layer or more of the spacer on the gate electrode is formed in an island shape without impurities a first semiconductor layer; a first semiconductor layer having a source and a drain which is a source gate and a drain of the insulating gate-type transistor is formed on the first semiconductor layer; 2 semiconductor A source (signal line) and a drain line including a heat-resistant metal layer and an anodized metal layer of one or more layers are formed on the upper and gate insulating layers; and the gate insulating layer is formed on the above-mentioned drain wiring Further, a transparent conductive electrode terminal is formed on the signal line in a region other than the transparent conductive pixel electrode and the image display portion; and a region overlapping the pixel electrode on the drain wiring and an electrode of the signal line An anodized layer is formed on the surface of the source/drain wiring in addition to the terminal region, and a tantalum oxide layer is formed on the first semiconductor layer between the source and drain wirings. According to this configuration, the number of lithography etchings of the scanning line and the pixel electrode is reduced by using one mask, and in addition, the lithography etching process is performed by using a mask to process the formation and protection of the pixel electrode. The number is cut off' A TN type liquid crystal display device can be manufactured using four masks. Forming a ruthenium oxide layer containing impurities on the channel between the source and the drain to protect the channel' while forming a oxidized giant (Ta205) which is an insulating anodized layer on the surface of the signal line and the drain wiring or Alumina (AI2〇3) gives protection to -19-(17) 1281999. Therefore, it is not necessary to cover the entire surface of the glass substrate with the protective insulating layer, and the heat resistance of the insulating gate type transistor does not cause a problem. In addition, since the insulating layer of the protective channel is obtained by anodizing an amorphous germanium layer containing impurities and converting it into a hafnium oxide layer, it is not necessary to form an amorphous layer which is a channel layer and which does not contain impurities. Thick film to realize TN type liquid crystal display device. The liquid crystal display device of the fourth aspect of the invention is characterized in that: scan lines composed of a laminate of a transparent conductive layer and a metal layer are formed on at least one main surface of the first transparent insulating substrate. a transparent conductive pixel electrode; a plasma protective layer and a gate insulating layer are interposed on the gate electrode; and a third semiconductor layer containing no impurities is formed in an island shape; and a part of the first semiconductor layer is formed on the first semiconductor layer The second semiconductor layer containing impurities is formed as a source/drain of the insulating gate-type transistor, and is formed on the plasma protective layer and the gate insulating layer on the pixel electrode. An opening portion; a source wiring (signal line) including one or more layers of an anodizable metal layer including a heat resistant metal layer on the second semiconductor layer and the gate insulating layer, and the second A drain wiring is formed on the semiconductor layer and on the gate insulating layer and on one of the pixel electrodes in the opening; in addition to the electrode terminal region of the signal line, the source/drain wiring is -20 - (1 8) 1281999 An anodized layer is formed on the surface; a layer is formed on the first semiconductor layer between the source and drain wirings. According to this configuration, the scanning line and the photo-etching engineering number are cut using one mask, and the photo-etching reduction of the opening forming process of the semiconductor wiring and the gate insulating layer is performed using one mask, and the use 1 The formation of the photoreceptor electrode and the photo-etching engineering number of the photomask are cut, and the TN display device can be manufactured by three masks. The liquid crystal image display described in item 5 of the patent application scope is a signal line which also serves as a source wiring for charging a liquid crystal on a main surface having at least an insulating crystal and a gate electrode which also serves as the insulating gate type transistor. And a first transparent substrate in which a unit pixel connected to the drain wiring electrode is arranged in a matrix of two elements, and a first insulating substrate or a color filter that faces the first transparent insulating substrate. The liquid crystal is characterized in that: at least one of the main transparent surfaces of the first transparent insulating substrate is formed with a scanning line formed of a metal layer thereon; and one or more gate insulating islands are interposed on the gate electrode. a first semiconductor layer containing no impurities; and a first semiconductor layer having a source and a drain which is a gate electrode of the insulating gate type transistor is formed on the first semiconductor layer; The number of islands of the bulk layer of the halogen electrode is a liquid crystal device of a film forming type, which is a gate type electric scanning line and a pixel-shaped insulating layer 2, and the transparent display device is formed by one layer and the ground is extremely overlapped. -21 - (19) 1281999 having impurities formed on the second semiconductor layer and the gate insulating layer, and having a eutectic layer composed of one or more layers of anodizable metal layers (signal lines) and drain electrodes a wiring (pixel electrode), and an electrode terminal including a portion of the scan line in the opening portion, the electrode terminal and the signal line formed on the gate, except for the electrode terminal of the scan line and the signal line A protective insulating layer is formed on the entire insulating substrate. According to this configuration, the number of uranium engraving processes for forming the opening portion of the semiconductor layer and the gate insulating layer by using one mask can be obtained by using four masks to obtain an IPS type liquid crystal display device. The film thickness of the protective insulating layer on the electrode terminals of the line and the signal line is not traced, so that the contact with the contact is not caused. The liquid crystal image display device of the sixth aspect of the invention is the scan line composed of at least one metal layer on one main surface of the first transparent insulating substrate, and one or more layers are interposed on the gate electrode. a first semiconductor layer containing no impurities in a gate insulating layer island; a first pair of source and drain electrodes which are formed as a gate electrode of the insulating gate type transistor in the first semiconductor layer; The semiconductor layer removes a gate insulating layer in an opening formed on a region other than the image display portion; and a source-polar insulating layer containing heat-resistant gold is formed on the second semiconductor layer and the gate insulating layer The wire electrode terminal 1 is transparently islanded, and the sweep is the same. It is characterized by the formation of a layer formed by the ground and having impurities formed in the layer of the heat-resistant gold-22-(20) 1281999 layer. And a source wiring (signal line) and a drain wiring (pixel electrode) composed of one or more layers of anodizable metal layers, and one of scanning lines including the opening portion formed on the gate insulating layer unit An electrode terminal of the signal line formed by the electrode terminal of the scan line and one of the signal lines is formed with an anodized layer on the surface of the source/drain wiring except for the electrode terminal region of the signal line; A ruthenium oxide layer is formed on the first semiconductor layer of the drain wiring. According to this configuration, the number of photolithography processes in which the source/drain wiring is formed and the protective layer is formed by using one mask is cut, and a ruthenium oxide layer containing impurities is formed on the channel between the source and the drain to protect the channel. At the same time, a oxidized giant (Ta205) or an aluminum oxide (A12 03 ) which is an insulating anodized layer is formed on the surface of the signal line and the drain wiring to impart a protective layer function. Therefore, it is not necessary to coat the entire surface of the glass substrate with the protective insulating layer, and the heat resistance of the insulated gate type transistor does not become a problem. In addition, since the insulating layer of the protective channel is obtained by anodizing an amorphous germanium layer containing impurities and converting it into a hafnium oxide layer, it is not necessary to form an amorphous layer which is a channel layer and which does not contain impurities. A thick film, which realizes an IP S type liquid crystal display device. The seventh aspect of the patent application is a method for manufacturing a liquid crystal display device according to claim 2, which is characterized in that the liquid crystal is filled on a main surface and has at least: An insulated gate type transistor, a scanning line which also serves as a gate electrode of the above-described insulated gate type transistor, and a signal line which also serves as a source wiring, -23-(21) 1281999, and a pixel connected to the drain wiring A unit transparent element such as an electrode is arranged between a first transparent insulating substrate of a matrix of two elements and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate. A manufacturing method of a liquid crystal display device, characterized in that a scanning line and a pseudo-pixel element composed of a transparent conductive layer and a first metal layer are formed on at least one main surface of the first transparent insulating substrate The project is sequentially covered with a circuit of the electric prize protection layer, the gate insulating layer, the first amorphous germanium layer containing no impurities, and the second amorphous germanium layer containing impurities; the electrode terminal forming region and the pseudo-picture in the scanning line On the element electrode, a photosensitive resin pattern having an opening portion and a film thickness on the gate electrode thicker than that of the other regions is formed, and the second amorphous germanium layer and the first amorphous material in the opening portion are removed. a layer of a gate layer, a gate insulating layer, a plasma protective layer, and a first metal layer to expose a portion of a transparent conductive scan line and a pixel electrode; reducing the film thickness of the photosensitive resin pattern to expose the second amorphous material The layered layer is formed by forming a second amorphous tantalum layer and a first amorphous tantalum layer wider than the width of the gate electrode on the gate electrode; after coating the second metal layer of one or more layers, On the gate insulating layer and the second amorphous germanium layer, electrode terminals including the source (signal line) and the drain wiring and the opening portion and the scanning electrode are formed on the gate electrode portion and the gate electrode portion. The electrode of the signal line formed by one part of the line -24- (22) 1281999 The process of removing the second amorphous germanium layer between the source and drain wirings; and forming a protective insulating layer on the entire first transparent insulating substrate; A process of selectively removing the protective insulating layer by forming an opening on the electrode terminal and the protective insulating layer on the pixel electrode. According to this configuration, the number of uranium engraving projects for processing the pixel electrode and the scanning line using one mask is reduced, and the light of the opening of the island portion of the semiconductor layer and the gate insulating layer is processed by using one mask. The number of etching projects is reduced, and a TN type liquid crystal display device can be fabricated by four masks. Then, since the film thickness of the protective insulating layer on the electrode terminals of the scanning line and the signal line is the same, there is no problem associated with the formation of contact. The method of manufacturing a liquid crystal display device according to claim 3, characterized in that the metal layer of one or more layers is formed on at least one main surface of the first transparent insulating substrate. The construction of the scanning line; the step of sequentially coating one or more gate insulating layers and the first amorphous germanium layer containing no impurities and the second amorphous germanium layer containing impurities; the electrode at the scanning line In the terminal formation region, a photosensitive resin pattern having an opening portion and a film thickness on the gate electrode is thicker than that of the other regions is formed. The second amorphous germanium layer and the first amorphous layer in the opening portion are removed. Engineering of the enamel layer and the gate insulating layer; the process of reducing the film thickness of the photosensitive resin pattern to expose the second amorphous ruthenium layer; -25- (23) 1281999 forming a gate electrode on the gate electrode in an island shape The second amorphous ruthenium layer and the first amorphous ruthenium layer having a wide electrode width are formed on the gate insulating layer and the second amorphous ruthenium layer by partially overlapping the gate electrode. An anodized metal layer above the layer Source (signal line) and drain wiring work; transparent conductive is formed on the gate insulating layer and a portion of the above-described drain wiring in a region other than the transparent conductive pixel electrode and the image display portion The electrode terminal is on the signal line; and the photosensitive resin pattern to be used in the selective pattern of the pixel electrode and the electrode terminal is used as a mask to protect the electrode terminals of the pixel electrode and the signal line, and the anodizing source • Engineering of amorphous germanium layers in the drain wiring and source/drain wiring. According to this configuration, the number of photolithographic processes for forming the semiconductor layer and the opening of the gate insulating layer using the one mask can be reduced. Furthermore, for the formation of the source/drain wiring and the anodization of the channel and source/drain wiring, the electrode terminal of the protection signal line can be processed by using one mask, since the number of photo-etching engineering can be prevented from increasing, A TN type liquid crystal display device can be fabricated by four masks. The method of manufacturing a liquid crystal display device according to claim 4, which is characterized in that the transparent conductive layer and the first layer are formed on at least one main surface of the first transparent insulating substrate. The scanning line composed of the metal layer and the pseudo-pixel-like electrode are sequentially coated with the plasma protective layer, the gate insulating layer, and the first amorphous -26-(24) 1281999 layer and the impurity-containing layer containing no impurities. 2The operation of the amorphous germanium layer; on the electrode terminal forming region of the scanning line and the pseudo-pixel electrode, a photosensitive resin pattern having an opening portion and a film thickness on the gate electrode thicker than that of the other regions is formed. The second amorphous germanium layer, the first amorphous germanium layer, the gate insulating layer, the plasma protective layer, and the metal layer in the opening are removed to expose a portion of the transparent conductive scan line and the pixel electrode Engineering for reducing the film thickness of the photosensitive resin pattern to expose the second amorphous germanium layer; forming a second amorphous germanium layer wider than the gate electrode width and the first non-island on the gate electrode Crystalline layer engineering After coating one or more layers of the anodizable metal layer, a part of the source (signal line) which is overlapped with the gate electrode and has a thicker film thickness than the other areas corresponding to the scan line and the signal line is formed. a process of a photosensitive resin pattern of a terminal wiring and an electrode terminal of a signal line including a portion of the scanning electrode and a signal line; and the photosensitive resin pattern is used as a mask a cover for selectively removing an anodizable metal layer to form a source/drain wiring and an electrode terminal of a scan line and an electrode terminal of a signal line; reducing a film thickness of the photosensitive resin pattern to expose a source/drain The wiring works; and the protection of the above-mentioned electrode terminals, and the anodization of the source and the drain wiring and the source/drain wiring between the amorphous germanium layers. -27- (25) 1281999 According to this configuration, the process of processing the scanning line and the pixel electrode using one mask, and the photo-etching of the opening formation process of the islanding process and the gate insulating layer using a single mask are realized. The number of projects is reduced. In addition, for the formation of source/drain wiring and the anodization of the channel and source/drain wiring, a photomask can be used to process the electrode terminals of the protection signal line. Since the number of photo-etching processes is increased, a TN-type liquid crystal display device can be fabricated by three photomasks. The method of manufacturing a liquid crystal display device according to the fifth aspect of the invention, characterized in that the metal substrate of one or more layers is formed on at least one main surface of the first transparent insulating substrate. Engineering of a scanning line and a counter electrode formed by a layer; a step of sequentially coating one or more gate insulating layers and a first amorphous germanium layer containing no impurities and a second amorphous germanium layer containing impurities; In the electrode terminal forming region of the scanning line, a photosensitive resin pattern having an opening portion and a film thickness on the gate electrode thicker than that of the other regions is formed; and the second amorphous germanium layer in the opening portion is removed The first amorphous germanium layer and the gate insulating layer; the process of reducing the film thickness of the photosensitive resin pattern to expose the second amorphous germanium layer; and forming the gate electrode width on the gate electrode in an island shape The second amorphous ruthenium layer and the first amorphous ruthenium layer are widened. On the gate insulating layer, a portion of the gate insulating layer is formed so as to overlap the gate electrode to form a second amorphous ruthenium layer. The source of the second metal layer above -28- (26) 1281999 (signal line) · drain wiring (pixel electrode) and a signal electrode terminal including the electrode terminal and the signal line of the scanning line; the source 汲In the second amorphous enamel layer of the pole wiring, in addition to the electrode terminals of the scanning line and the signal line, a protective insulating layer is formed on the entire first transparent edge substrate. According to this configuration, it is possible to process the semiconductor layer and the opening portion forming process of the gate insulating layer by using one mask, and to realize the reduction of the number of photo-etching processes, and to manufacture an IPS-type liquid crystal display device by using four masks. In addition, it has fewer change points in the four masks that have been rationalized in the past, and is included in the mass production plant. The method of manufacturing a liquid crystal display device according to claim 6 is characterized in that the metal layer on the main surface of at least one of the first transparent insulating substrates is formed on the main surface of the first transparent insulating substrate. The scanning line and the counter electrode are formed; the gate insulating layer of one or more layers and the first non-antimony layer containing no impurities and the second amorphous germanium layer containing impurities are sequentially coated; at the gate electrode a second enamel layer and a first amorphous ruthenium layer which are wider than the width of the gate electrode are formed in an island shape to expose the gate insulating layer; and an opening portion is formed in the electrode terminal forming region of the scanning line. The operation of the gate insulating layer in the opening portion; after coating one or more layers of the anodizable metal layer, a part of the electrode electrodes are overlapped, and the electrode terminals corresponding to the scanning lines and the signal lines are thicker than other regions. (signal line) • Bungee wiring (the part of the painting department and the line, and the singularity of the engraver, the easy-to-describe layer is replaced by a crystalline amorphous thyristine -29-(27) 1281999 pole) and Containing the above opening Engineering of a photosensitive resin pattern of an electrode terminal of a signal line composed of an electrode terminal of a scanning line and a signal line; using the photosensitive resin pattern as a mask to selectively remove an anodizable metal layer to form a source Electrode terminal of the electrode and the electrode terminal of the scanning line and the electrode terminal of the signal line; the film thickness of the photosensitive resin pattern is reduced to expose the source/drain wiring; and the electrode terminal is protected while anodizing Project of source/deuterium wiring and amorphous germanium layer in source/drain wiring. According to this configuration, a ruthenium oxide layer containing impurities is formed on the channel between the source and the drain to protect the channel, and an insulating anodized layer is formed on the surface of the signal line and the drain wiring to provide a protection function. Therefore, it is not necessary to coat the entire surface of the glass substrate with the protective insulating layer, and the heat resistance of the insulating gate type transistor does not become a problem. Furthermore, it is possible to use a mask to process the source/drain wiring, and to protect the electrode terminals of the signal line while anodizing the source and the drain wiring, thereby realizing the number of photolithography projects, and four masks can be used. An IPS type liquid crystal display device is produced. The method of manufacturing a liquid crystal display device according to claim 6, wherein the method further comprises forming a metal layer of one or more layers on at least one main surface of the first transparent insulating substrate. The scanning line and the counter electrode are processed; the gate insulating layer of one or more layers and the first amorphous germanium layer containing no impurities and the second amorphous germanium layer containing impurities are sequentially coated; -30- 1281999 (28) A process of forming a photosensitive resin pattern having an opening and having a film thickness on the gate electrode larger than that of other regions in the electrode terminal forming region of the scanning line; removing the second non-inside of the opening Engineering of a crystalline germanium layer, a first amorphous germanium layer, and a gate insulating layer; a process of reducing the film thickness of the photosensitive resin pattern to expose the second amorphous germanium layer; and forming an island shape on the gate electrode Engineering of the second amorphous germanium layer and the first amorphous germanium layer having a wide gate electrode width; after coating one or more layers of the anodizable metal layer, a part of the gate electrode overlaps and corresponds to the scan Electrode end of line and signal line a source (signal line) thicker than other regions, a drain electrode (pixel electrode), and a signal line including a signal line formed by one of the electrode terminal and the signal line of the scan line Engineering of a photosensitive resin pattern of a terminal; using the photosensitive resin pattern as a mask, selectively removing an anodizable metal layer to form an electrode terminal of a source/drain wiring and a scan line, and an electrode terminal of a signal line Engineering for reducing the film thickness of the photosensitive resin pattern to expose the source/drain wiring; and protecting the electrode terminal while anodizing the amorphous between the source and drain wirings and the source/drain wiring The construction of the 矽 layer. According to this configuration, the number of photolithographic processes for forming the semiconductor layer and the opening of the gate insulating layer using a single mask is cut, -31 - (29) 1281999 plus a mask can be used to form The source and the drain wiring and the electrode terminal of the protection signal line are simultaneously anodized and sourced. The number of photolithography projects of the bungee engineering is also reduced, and the liquid crystal display device can be made by three masks. [Embodiment] FIG. 1 is a plan view showing a display device body device (active substrate) according to a first embodiment of the present invention, and FIG. 2 is a view showing a first embodiment of the present invention. Manufacturing drawings of the A-A' line and B-B' line and C-C' line. Similarly, the second embodiment is a third diagram and a fourth diagram. The first embodiment is a fifth diagram and a sixth diagram, the fourth embodiment is a seventh diagram, and the fifth embodiment is a ninth diagram and a fifth embodiment. In Fig. 10, the sixth state is a plan view showing the plane of the active substrate in Fig. 1 and Fig. 2, respectively. Further, the same portions as those of the prior art are given, and detailed descriptions are omitted. (First Embodiment) In the first embodiment, first, a vacuum such as S P T is applied to one main surface of the glass substrate 2 to cover, for example, ITO as a month | 2 / / m of the transparent conductive layer 91, and for example, Cr, Ta, MoW as a film thickness of 0. 1 to the first metal layer 92, as shown in the first: and the second figure (a), the microstructure of the transparent conductive layer 91A and the metal layer 92A is selected by a microfabrication technique, and the wiring is IPS type. The first half of the semi-conductor 1 map (f section 3 implementation map and the first embodiment of the figure and the same symbol film packaging [thickness.  1 alloy, etc. 1 (a is formed into a double-32-(30) 1281999 as a scan line 1 1 of the gate electrode 1 1 A; a laminate of a transparent conductive layer 9 1 B and a first metal layer 92B The pseudo-pixel electrode 93; and the pseudo-short line 94 formed by laminating the transparent conductive layer 91C and the first metal layer 92C. The gate insulating layer is interposed to increase the insulation withstand voltage of the signal line, in order to increase the throughput. Although some electrodes are preferably controlled by tilting of the cross-sectional shape by dry etching, those using the hydrogen iodide or hydrogen bromide in the etching gas developed in the dry etching technique of ITO have a large amount of reaction product formation due to the gas exhaust system. Therefore, the surface has not been put into practical use, so the surface may be etched by sputtering such as Ar (argon, arg ο η ). Next, on the entire surface of the glass substrate 2, 0. A film thickness of about 1//m is applied to form a transparent insulating layer 71 such as TaOx or SiO 2 as a plasma protective layer. The plasma protective layer 71 is formed by the SiNx of the gate insulating layer of the subsequent PCVD device, in order to reduce the transparent conductive layers 91A, 91B exposed at the edge of the scanning line 1 1 or the pseudo pixel electrode 93. In order to prevent the film quality of SiNx from being changed, the above-mentioned Japanese Patent Publication No. 59-9962 is referred to in detail. The plasma protective layer 71 is coated in the same manner as in the first embodiment, and a PCVD apparatus is used, for example, 0. 2-0. 1-0. The film thickness of about 05//m is sequentially coated to form the first SiNx layer 30 of the gate insulating layer, and the first amorphous germanium layer 3 1 which is a channel of the insulating gate type transistor which contains almost no impurities. And three types of thin film layers of the second amorphous germanium layer 3 3 which are source and drain electrodes of the insulating gate type transistor including impurities. Here, since the gate insulating layer is composed of a laminate of the plasma protective layer and the first SiNx layer, the first SiNx layer is preferably formed to be thinner than the prior art. • 33-(31) 1281999 Then, 'on the pseudo-short line 94 of the region formed outside the image display portion, 'there is an opening portion 63 A ' on the electrode terminal forming region of the scanning line and has a pseudo-pixel electrode 93 The opening portion 74, at the same time, the formation region of the insulating gate type transistor, that is, the film thickness of the region 84A on the gate electrode 1 1 A is formed by a halftone exposure technique, for example, 2 # m and a film thickness other than the other regions 84B. 1 # m is also thick photosensitive resin patterns 84A, 84B. Then, as shown in FIGS. 1(b) and 2(b), the second amorphous germanium layer 3 3 and the first amorphous portion which are exposed by masking the photosensitive resin patterns 84A and 84B are included. The buffer layer 31 and the gate insulating layer 30 and the plasma protective layer 7 1 sequentially etch the first metal layer 92, and expose a portion of the scanning line 11 as the electrode terminal forming region 5 A of the scanning line. The transparent conductive layer exposing the short-circuit line 94 is used as the short-circuit line 91 C ( 40 ), and the transparent conductive layer 91B exposing the pseudo-pixel electrode 93 is used as the pixel electrode 22. The electrode terminal of the scanning line 1 1 is at most about one-half of the electrode pitch of the driving LSI, and since it is usually 20/zm or more, it is easy to fabricate the photomask for forming the opening 63A (white area), and it is easy. Manage the accuracy of this completed size. Next, when the photosensitive resin patterns 84A and 84B are cut by a ashing means such as oxygen plasma or the like to a film thickness of #m or more, as shown in FIGS. 1(c) and 2(c). In general, the photosensitive resin pattern 84B disappears, and the second amorphous germanium layer 3 3 is exposed, and the photosensitive resin pattern 84C can be selectively formed only on the gate electrode 1 1 A. The photosensitive resin pattern 84C, that is, the pattern width of the island-shaped semiconductor layer is such that the mask matching precision is added to the size of the source/drain wiring, so the source/drain wiring is set to 4 - 34 - (32) 1281999 to 6//m, when the matching accuracy is ±3"m, it is 1〇~i2//m, which is not strict in terms of dimensional accuracy. However, when the photoresist pattern 84A is changed to 8 4 C, if the photoresist pattern is isotropically reduced by a film thickness of 1 am, the size is not reduced by 2 // m, and the subsequent source/drain wiring is formed. The hood fit accuracy is also reduced by 1 V m to ± 2 // m, which is more serious for the latter in the process than the former. Therefore, in the above oxygen plasma treatment, it is preferable to suppress the change in the pattern size to enhance the anisotropy. Specifically, the RIE (Reactive Ion Etching) method, and the ICP (Inductive Coupled Plasama) method or the TCP (Transfer Coupled Plasama) method with high-density plasma source are optimal. Then, as shown in FIGS. 1(d) and 2(d), the second amorphous germanium layer 33B and the first amorphous germanium layer 3 are selectively selected by using the photosensitive resin pattern 84C as a mask. 1 B remains wider than the width of the gate electrode 1 1 and serves as the island shape 31A, 33A to expose the gate insulating layer 30A. The island-shaped semiconductor layers 31 A and 33A, that is, the photosensitive resin pattern 84C (black region) have a size of at least 10 // m, which is not only easy to produce a region other than the white region and the black region as a halftone exposure region. In the reticle, even if the dimensional accuracy of the island-shaped semiconductor layers 31A and 33A fluctuates, since the electrical characteristics of the insulating gateless transistor are hardly changed, it is understood that the process management should be easily performed. At this time, the electrode terminal forming region 5A and the short wiring 91 which are formed of the transparent conductive layer exposed on the glass substrate 2 (the pixel electrode 22 is exposed to the etching gas, but belongs to the amorphous germanium layer 33B, The fluorine-based gas of the etching gas of 1B is not suitable for, for example, reducing the film thickness of the transparent conductive layer -35-1281999 (33), or changing the resistance 値, or changing the transparency. After the photosensitive resin pattern 84C is removed, a heat-resistant metal thin film layer 34 such as Ti or Ta is sequentially applied as a film thickness by using a vacuum film forming apparatus such as SPT. a tempered metal layer around lym, and then coated with A1 film layer 3 5 as a film thickness of 0. 3 / m low resistance wiring layer. Then, as shown in FIGS. 1(e) and 2(e), although the thin film layers are sequentially etched by the microfabrication technique using the photosensitive resin pattern, one portion including the pixel electrode 22 is selectively formed. The drain electrode 2 1 of the insulating gate type transistor composed of the two laminated layers 34A and 35A and the signal line 1 2 which also serves as the source wiring, but in this case, the second amorphous germanium is sequentially etched as in the previous example. Layer 3 3 A and the first amorphous germanium layer 3 1 A, and the first amorphous germanium layer 3 1 A is residual 0. 0 5~0. Etching around 1 // m. Further, when the source/drain wirings 1 2 and 2 1 are formed, the electrode terminals 5 of the scanning lines including a portion of the scanning lines 11 of the openings 63 A are formed in the region outside the image display portion, and the signal is formed by the signal. An electrode terminal 6 formed by a portion of the line 12. Further, here, as the configuration of the source/drain wirings 1, 2, and 2, if the limitation of the resistance 并不 is not critical, it can be simplified to a single layer of Ta, Cr, Mo or the like. After the source/drain wirings 1, 2 and 2 are formed, they are coated on the entire surface of the glass substrate 2 in the same manner as the conventional five mask processes. The second SiNx layer having a film thickness of about 3 // m is used as a transparent insulating layer and is provided as a protective insulating layer 3 7 as shown in Fig. 1 (f) and Fig. 2 (f), at the pixel electrode 22 and the electrode terminals 5, 6 of the scanning line 1 1 and the signal line 1 2 are selectively formed with openings 3 8 , 6 3 , 6 4 respectively to expose the pixel electrode 2 2 and the electrode terminals 5 - 36 - (34) Most of 1281999 and 6. The active substrate 2 and the color killer obtained in this manner are bonded to each other to form a liquid helium panel, and the first embodiment of the present invention is completed. The configuration of the storage capacitor 1 5 is exemplified by the storage of the plasma protective layer 71 and the gate insulating layer 3 Ο A planar stack including the pixel electrode 2 2 and being formed simultaneously with the drain wiring 2 1 The electrode 73 and the scanning line 1 1 of the front stage (the upper left to the lower right oblique portion 5 2 ), but the storage capacitor 15 is not limited thereto, and may be a storage capacitor formed at the same time as the scanning line. A structure in which an insulating layer including a gate insulating layer is interposed between the line and the pixel electrode. Further, although other configurations are also possible, detailed descriptions are omitted. (Second Embodiment) In the second embodiment, the thickness of the film is first coated with a vacuum device such as SPT as in the prior art. The first metal layer of 1 to about is selectively formed by the microfabrication technique as the scanning line 1 1 of the gate electrode 1 1 A and common to each other as shown in FIGS. 3( a ) and 4 ( a ). Capacitor line 16. When the heat resistance of the A1 monomer is considered, in order to reduce the resistance of the scanning line, a single layer structure of Al (Ta, Ta) alloy or the like may be selected as the structure of the scanning line or Al/Ta, Ta/Al/Ta, Al/ A laminate of Ti, Ti/Al/Ti, Al/Al (Ta, Zr) alloy or the like is formed, but in the present invention, the scanning line material is almost unlimited. Here, A1 (Ta, Z〇 represents an A1 alloy having a high heat resistance such as Ta or Zr added in a few % or less. Next, for example, 0·3 - 0 is used on the entire surface of the glass substrate 2 using a PC VD apparatus.  1 - 〇 .  The film thickness of 〇5 #m is sequentially coated to become the first non-gate insulating-37-(35) 1281999 layer of the first SiNx layer 30, which will become the channel of the insulating gate type transistor which contains almost no impurity. The crystalline germanium layer 3 1 and the three types of thin film layers of the second amorphous germanium layer 3 3 which will be the source and drain of the insulated gate-type transistor containing impurities. Thus, the first amorphous layer 3 1 can be coated relatively thin compared with the prior art, and this point is also one of the features of the present invention, and the reason will be described later. Then, as shown in FIGS. 3(b) and 4(b), the electrode terminal forming region of the scanning line 11 has an opening portion 63 A (and an electrode terminal forming region at the common capacitance line 16). The upper portion has an opening portion 65A), and the formation region of the insulating gate type transistor is formed according to the halftone exposure technique, that is, the film thickness of the region 8 2 A on the gate electrode 1 1 A is, for example, 2//m, and the ratio The photosensitive resin patterns 82A and 82B having a film thickness l//m thick in the other region 82B are selectively removed by the photosensitive resin patterns 82A and 82B as a mask (and the opening portion 65 A). The second amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1 and the gate insulating layer 30 are exposed to expose a portion 72 of the scanning line 11 (and the common capacitance line 16). Next, when the photosensitive resin patterns 82 A and 82B are cut by a film thickness of 1 # m or more by an ashing means such as oxygen plasma, as shown in FIGS. 3(c) and 4(c) As a general rule, the photosensitive resin pattern 8 2 B disappears, and the second amorphous germanium layer 3 3 is exposed, and the photosensitive resin pattern 82C can be selectively formed only on the gate electrode 1 1 A. Here, as shown in FIGS. 1(d) and 2(d), the second amorphous germanium layer 3 3 and the first amorphous germanium are selectively used as the mask with the photosensitive resin pattern 82C as a mask. The layer 3 1 remains wider than the width of the gate electrode 1 and serves as an island shape 3 1 A, 3 3 A to expose the gate insulating layer 30. At this time, it is necessary to pay attention to the fact that one portion 72 of the scanning line 11 exposed in the opening portion -38-(36) 1281999 63A is generated by the material of the scanning line 1 1 because it is exposed to the gas of the age I or the etching agent. The film of the scanning line π is deleted, but even if the A1 alloy is exposed, it is easy to avoid the influence of oxidation if Ti is selected as the lowermost layer of the drain wiring material. In addition, as described in the previous examples, it is also possible to use the scan line 1 1 as a laminate of, for example, Al/Ti/Al, and even if the Ti of the upper layer disappears, A1 can be removed to expose the underlying Ti. System of law. After the photosensitive resin 82C is removed, a heat-resistant metal thin film layer 34 such as Ti or Ta is sequentially coated as a film thickness by using a vacuum film forming apparatus such as SPT. An anodized heat-resistant metal layer of about 1/im, A1 film layer 35 as a film thickness of 0. 3 / m or so of the same anodizable low-resistance wiring layer, and Ta and other heat-resistant metal film layer 36 as a film thickness Ο. An intermediate conductive layer that can be anodized as well as Ι/zm. Then, the source/drain wiring material composed of the three types of thin films is sequentially engraved by a microfabrication technique using a photosensitive resin pattern, as shown in FIGS. 3(e) and 4(e). Selectively forming a drain electrode (wiring) 2 1 of an insulating gate type transistor composed of a stack of 3 4 A, 3 5 A, and 3 6 A, and a signal line also serving as a source electrode (wiring) 1 2. In the selective pattern formation of the source/drain wirings 2 and 2, as in the prior art, it is not necessary to etch the second amorphous germanium layer 33A containing impurities and the second amorphous germanium layer 31A containing no impurities. Further, generally, when the source/drain wirings 1 2 and 2 1 are formed, the electrode terminal 5 including the scanning line of the scanning line n of the portion 7 2 in the opening portion 63A and the electrode terminal 5 are formed at the same time. Electrode terminal 6. As a source/drain wiring, if the resistance is not critical, it can be simplified. -39- (37) 1281999 is an anodizable Ta single layer. Furthermore, N1 alloy with Nd is chemically added. The potential potential is lowered, and the chemical uranium reaction with ITO in the alkali solution such as the developing solution or the photoresist stripping solution is suppressed, so that the intermediate conductive layer 3 6 A is not required at this time, and the source/drain wiring 1 can be used. The laminated structure of 2 and 2 is a two-layer structure (3 4 A, 3 5 A ), and the composition of the source/drain wirings 1 2 and 2 1 can be simplified. After the source/drain wirings 12 and 21 are formed, a vacuum film forming apparatus such as SPT is used on the entire surface of the glass substrate 2, for example, ITO is coated as a film thickness of 0. 1 ~ 〇. A transparent conductive layer of about 2/m is formed on the gate insulating layer 30 by using a microfabrication technique of the photosensitive resin pattern 83 as shown in Figs. 3(f) and 4(f). The pixel electrode 22 including a portion of the intermediate conductive layer 36A of the gate electrode 21 is selectively formed. At this time, a transparent conductive layer is formed on the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line to form transparent electrode terminals 5A and 6A. Here, in the same manner as in the prior art, the short-circuit line 40' which is provided with transparent conductivity is formed into a slender strip shape between the electrode terminals 5A, 6A and the short-circuit line 40, so that it is easy to increase the resistance and become high against static electricity. resistance. Next, the photosensitive resin pattern 83 is used as a mask, and the source/drain wirings 1 2 and 2 1 are anodized while the light is being irradiated, and an oxide layer is formed on the surface while the anodization is exposed to the source. A portion of the second amorphous germanium layer 33A containing impurities between the drain wirings 12 and 21 and a portion of the first amorphous germanium layer 3 1A containing no impurities, as shown in FIG. 3(g) and FIG. 4( As shown in g), a cerium oxide layer (SiO 2 ) 66 containing impurities and a cerium oxide layer (not shown) containing no impurities are formed. -40- (38) 1281999 Ta is exposed on the top of the source/drain wirings 1, 2 and 2, and a stack of Ta, Al, and Ti is exposed on the side surface, and is anodized by semiconductors. Titanium oxide (Ti〇2) 68 'A1 is an aluminum (Al2〇3) 69 which is metamorphosed into an insulating layer, and then Ta is metamorphosed into a pentoxide (Ta20 5 ) 70 which belongs to the insulating layer. Although the titanium oxide layer 68 is not an insulating layer, the film thickness is extremely thin and the exposed area is small, so that there is no problem in terms of protection, and the heat-resistant metal thin film layer 34A is also preferably selected Ta. However, unlike Ta, it is necessary to pay attention to the surface oxide layer of the absorbing substrate and the lack of capacity to function as an ohmic contact. The second crystalline germanium layer 33A containing impurities between the channels causes an increase in leakage current of the insulating drain type transistor when it is completely uninsulated in the thickness direction. Here, the implementation of anodization while irradiating light is a very important point for the anodizing process, and is also disclosed in the prior art. Specifically, if a relatively strong light of about 10,000 m of light is irradiated, and if the leakage current of the insulated gate type transistor exceeds /A, the channel portion between the source and drain electrodes 1 and 2 1 The area of the anode electrode 21 is calculated to be an anodization of about 10 m A/cm 2 to obtain a current density for obtaining a good film quality. Further, the second amorphous ruthenium layer 3 3 A containing impurities is anodized, and the voltage is set to be higher than the formation voltage ιοον of the oxidized sand layer 66 which is sufficiently deformed to belong to the insulating layer, to the contact containing setting. The reaction voltage is a part of the first amorphous ruthenium layer 31 A (about 100 A) containing no impurities in the yttrium oxide layer 6 6 of the impurity formed by the high voltage, and is transformed into a ruthenium oxide layer containing no impurities (no picture) In this way, the electrical purity of the channel is increased, and the electrical connection between the source and drain electrodes 1 2 and 2 1 can be completely separated from -41 - (39) 1281999. That is, the OFF current of the insulated gate type transistor is sufficiently reduced, and a high ΟΝ/OFF ratio can be obtained. The film thickness of each oxide layer of pentoxide 70, aluminum 69, and titanium oxide 68 formed by anodization is 〇.  1~〇.  It is sufficient to use a protective layer of about 2 m as a wiring, and a treatment liquid such as ethylene glycol is used, and the applied voltage is also more than 100V. For the anodization of the source and drain wirings 12, 21, note that although not shown, all signal lines 12 must be electrically connected in parallel or in series. After that, of course, they must be removed and connected in series at the manufacturing engineering. Otherwise, otherwise Not only the electrical inspection of the active substrate 2, but also the actual operation of the liquid crystal display device can cause obstacles. As a means for releasing, it can be explained in detail by simple means such as illuminating the laser beam by illuminating or mechanically cutting the blade. The pixel electrode 22 is covered with the photosensitive resin pattern 83 because not only the anodized pixel electrode 22 is not required, but also the reaction current of the required amount or more flowing through the insulating gate polarity transistor to the gate electrode 2 1 is not required. Just fine. Finally, the active substrate 2 (semiconductor device for display device) is completed as shown in Figs. 3(h) and 4(h) except the photosensitive resin pattern 8 3 described above. The active substrate 2 and the color filter thus obtained are bonded to each other to form a liquid crystal panel, and the first embodiment of the present invention is completed. The configuration of the storage capacitor 15 is exemplified as a configuration example in which the storage capacitor line 16 and the pixel electrode 22 are planarly overlapped by the gate insulating layer 30 as shown in Fig. 3(h) (the upper left to the lower right oblique line) The portion 5 1 ), but the configuration of the storage capacitor 15 is not limited thereto, and the insulating layer including the gate insulating layer 30 is present between the pixel electrode 22 and the scanning line 1 1 of the upper stage through -42 - (40) 1281999 The composition of the layers is also possible. Furthermore, his composition is also possible, but the detailed description is omitted. In the second embodiment, the uranium engraving is performed for the halftone exposure of the layer of the island layer chemical layer such as the semiconductor layer and the layer for removing the electrode layer forming region on the electrode line forming region for the contact of the scanning line. In the case of the subtraction of the project, the active substrate is formed by using four masks as in the first embodiment, and by the technique of forming the same photoreceptor electrode and the scanning line, the engineering can be further promoted. The third embodiment is described in the third embodiment (the third embodiment). The third embodiment is as shown in FIGS. 5(d) and 6(d), until the semiconductor islanding project and the contact engineering. It is carried out in the same process as the first one. Then, the photosensitive resin pattern 84C having a reduced film thickness is removed by a halftone exposure technique, and then a heat-resistant metal layer 34 such as Ti or Ta is sequentially coated as an anodizable film having a film thickness by using a vacuum film forming apparatus. The heat resistant metal A1 film layer 35 has a film thickness of 0. The same anodically low resistance wiring layer of about 3/m. Then, as shown in FIGS. 5(e) and 6(e), the source/drain wiring material composed of the thin films is etched by the microfabrication technique using the photosensitive resin patterns 8 5 A to 8 5 D. The gate electrode including the insulating gate type transistor formed of the laminate of 35A and the portion of the pixel electrode 22 in the opening portion 74 is formed, and the signal line 12 which also serves as the source electrode. Although at the source, its process, the gate technology, but the cover is cut and reduced, the SPT film layer is formed according to the order of 34A I 2 1 •汲-43- (41) 1281999 pole wiring 1 2. When the 2, 2 1 is formed, the electrode terminal 5 including the scanning line of the electrode terminal forming region 5 A composed of the transparent conductive material is formed by one portion of the signal line, but the color tone exposure technique is in advance The area corresponding to the electrode terminals 5, 6 is formed, the film thickness (black area) of 8 5 B is 3 // m, and the area corresponding to the gates 2 2, 2 1 is 8 5 C, 8 5 D (middle tone) Film thickness of the area)  The thick photosensitive resin pattern 8 5 A to 8 5 D is important for the present invention. Although the area corresponding to the regions 85 A, 85B of the electrode terminals 5, 6 is tens of #πι, it is extremely easy to manage the finish for the mask production, but corresponds to the source/drain wiring 1 2, 2 1 The minimum size of the area 8 5 C is 4 to 8 / / m. The dimensional accuracy is relatively high, so a fine stitch pattern is required in terms of the adjustment area. However, the source/drain wirings 12 and 2 1 of the present invention are formed by one exposure treatment and one etching, so that the first halftone and the second etching treatment are used in comparison with the conventional halftone exposure technique. In the case of formation, the size management of the channel length is better than the previous halftone exposure technology, regardless of the size management of the source/twist line 1 2, 2 1 or the source/dole wiring 1 2, 2 1 . Pattern accuracy. When the source/drain wirings 1 and 2 are formed, when the photosensitive resin patterns 8 5 A to 8 5 D are reduced by a thickness of / m or more by the oxygen ashing means, the photosensitive resin is used. The patterns 8 5 c and 8 5 D expose the source/drain wirings 1 2 and 2 1, and the photosensitive resin patterns 8 5 E and 8 5 F can be selectively formed only on the electrode terminals 6. It is also easy to understand from the size of the electrodes 5, 6 'here by the oxygen plasma treatment layer|, and the half 85 A wiring is 5 μm characteristic small size, 85D half color, engraved at the light, Easy tube pulp, etc.; 5 Loss ‘5. Terminals and a few -44-(42) 1281999 The case where the pattern size is not affected is also a feature of the present invention. Here, as shown in Fig. 5 (f) and Fig. 6 (f), the photosensitive resin patterns 8 5 E and 8 5 F are used as masks, and the light is irradiated while the anode is the same as in the second embodiment. The oxidation source and the drain wiring 1 2 and 2 1 form an oxide layer 6 8 and 6 9 , and the anode is oxidized and exposed to the second amorphous germanium layer 3 3 A between the source and drain wirings 1 and 2 1 And a part of the adjacent first amorphous germanium layer 3 1 A forms a cerium oxide layer 66 containing impurities and a cerium oxide layer (not shown) which does not contain impurities. After the anodization is completed, the photosensitive resin patterns 8 5 E, 8 5 F are removed, and as shown in FIGS. 5(g) and 6(g), an anodized layer is formed on the side surface to expose the low-resistance metal. Electrode terminals 5, 6 formed by layers. However, in order to resist static electricity, the electrode terminal forming region 5A is connected to, for example, the short-circuit line 9 1 C, and as shown in the figure, if the electrode terminal 6 is formed without including the short-circuit line 9 1 C, it is on the side of the electrode terminal 5 No anodized layer is formed on the upper surface. Further, in the case of the configuration of the source/drain wirings 1, 2 and 2, if the limitation of the resistance 不 is not critical, the single layer of Ta which can be anodized can be simplified. The active substrate 2 and the color filter thus obtained are bonded to each other to form a liquid crystal panel, and the second embodiment of the present invention is completed. The configuration of the storage capacitor 15 is exemplified as shown in Fig. 5(g), in which a laminate of the plasma protective layer 71A and the gate insulating layer 30A is interposed, and a portion of the pixel electrode 22 is planarly overlapped and simultaneously The storage electrode 7 3 formed by the source/drain wirings 1 2 and 2 1 and the configuration example of the protrusion region formed on the front scanning line 1 1 (the upper left to the lower right oblique line portion 5 2 ) 'but the storage capacitor 〖5 The configuration is not limited thereto, and is the same as that of the second embodiment. -45-1281999 (43) Between the pixel electrode 22 and the common capacitance line 16 formed simultaneously with the scanning line 11, a gate insulating layer 3 Ο A is interposed. The composition of the insulating layer may also be. Further, other configurations are also possible, but detailed descriptions are omitted. In the third embodiment, when the source/drain electrodes 1 2, 2 1 and the second amorphous germanium layer 3 3 A are anodized, the pixel electrode 22 electrically connected to the gate electrode 2 1 is also exposed. Therefore, the pixel electrode 22 is also anodized at the same time. This point is greatly different from that of the first embodiment. Therefore, there is also a case where the resistance of the transparent conductive layer constituting the pixel electrode 22 is different, and the resistance 値 is increased by anodization. At this time, the film formation conditions of the transparent conductive layer must be appropriately changed, and prepared in advance. Oxygen is insufficient in film quality, but the case where the transparency of the transparent conductive layer is not reduced occurs in anodization. Further, although the current for anodizing the gate electrode 21 and the pixel electrode 22 is also supplied through the channel of the insulating gate type transistor, since the area of the pixel electrode 22 is large, a large oxidation is required. The current or the oxidation for a long time does not cause an obstacle to the resistance of the channel portion even if the light is irradiated, and the film thickness and film thickness on the drain electrode 2 1 and the storage electrode 73 are formed on the drain electrode 12 as on the signal line 12. The anodized layer is only insufficient to extend the oxidation time. However, even if the anodic oxide layer formed on the gate electrode 2 1 is somewhat incomplete, it is practically possible to obtain unreliable reliability. Since the driving signal applied to the liquid crystal cell is substantially AC, in order to reduce the DC voltage component between the counter electrode 14 and the pixel electrode 2 2 (the drain electrode 2 1 ), the counter electrode is Since the voltage is adjusted during image inspection (reduction of flicker adjustment), it is only necessary to form an insulating layer without flowing a DC component on the signal line. -46 - 1281999 (44) Although the liquid crystal display device described above uses a TN type liquid crystal cell, it controls a lateral electric field by forming a pair of counter electrode and a pixel electrode at a predetermined distance from the pixel electrode. In the liquid crystal display device of the IPS (In-Plain-Swticing) type, the project deletion proposed by the present invention is also effective, and will be described in the following embodiments. (Fourth Embodiment) In the fourth embodiment, first, a vacuum film forming apparatus such as SPT is used on one main surface of the glass substrate 2, and the coating film is thick. 1~0. The first metal layer of about 3/zm, as shown in Fig. 7 (〇 and Fig. 8(a), is selectively formed by microfabrication technology and also serves as the scan line 1 1 of the gate electrode 1 1 A and is common. Capacitor line 16. Then, using a PCVD device on the entire surface of the glass substrate 2, for example, 0. 3-0. 2-0. The film thickness of about 05/zm is sequentially coated to form the first SiNx layer 30 of the gate insulating layer, and the first amorphous germanium layer 31 which is a channel of the insulating gate type transistor which contains almost no impurities, and It is a three-type thin film layer of the second amorphous germanium layer 3 3 which is a source/drain of the insulated gate-type transistor containing impurities. Then, on the electrode terminal forming region of the scanning line 11, a formation region having an opening portion 63A while insulating the gate-type transistor, that is, a region 82A on the gate electrode 1 1 A is formed by a halftone exposure technique. The film thickness is, for example, 2 // m, and the photosensitive resin patterns 82A and 82B which are thicker than the film thickness of the other regions 82B by 1 // m, as shown in Figs. 7(b) and 8(b), The photosensitive resin patterns 82 A and 82B are selected as a mask. • 47-(45) 1281999 The second amorphous germanium layer 3 3 and the first amorphous germanium layer 3 in the opening portion 6 3 A are removed. And the gate insulating layer 30 exposes a portion 7 2 of the scanning line 1 1 . Next, when the photosensitive resin patterns 8 2 A and 8 2 B are cut by a film thickness of 1 / im or more by an ashing means such as oxygen plasma, as shown in Figs. 7(c) and 8(() As shown in c), the photosensitive resin pattern 82B disappears, and the second amorphous germanium layer 3 3 is exposed, and the photosensitive resin pattern 82C can be selectively formed only on the gate electrode Η A. Here, as shown in FIGS. 7(d) and 8(d), the second amorphous germanium layer 3 3 and the first amorphous layer are selectively selected by using the photosensitive resin pattern 8 2 C as a mask. The ruthenium layer 31 remains as wide as the width of the electrode 11 of the gate electrode 11 and serves as the island shape 31A, 33A to expose the gate insulating layer 30. After the photosensitive resin 82C is removed, a heat-resistant metal thin film layer 34 such as Ti or Ta is sequentially coated as a film thickness by using a vacuum film forming apparatus such as SPT. a heat resistant metal layer of about 1/zm, and a film thickness of A1 as a film thickness of 0. 3 / m low resistance wiring layer. Then, as shown in FIGS. 7(e) and 8(e), the source/drain wiring material composed of the thin films is sequentially etched by a microfabrication technique using a photosensitive resin pattern. The formation of a drain electrode (wiring) 2 1 of an insulating gate type transistor which is a pixel electrode composed of a laminate of 34A and 35A, and a signal line 12 which also serves as a source electrode (wiring), but This is the same as the prior example, sequentially etching the second amorphous germanium layer 3 3 A and the first amorphous germanium layer 3 1A, and the first amorphous germanium layer 31 A is etched into the remaining germanium. 〇5~0. 1 / i m degree. Further, generally, when the source/drain wirings 1 2 and 2 1 are formed, the electrode terminals 5 - 48 - (46) 1281999 of the scanning lines including a part of the scanning lines 11 in the opening portion 6 3 A are simultaneously formed and the signal lines are formed. The electrode terminal 6 formed by one part of 1 2 . In addition, if the structure of the source/drain wiring 1 2 and 2 1 is limited by the resistance, it can be simplified as a single layer of Ta, Cr, which can be anodized. After the formation of the source/drain wirings 1, 2 and 2, the same as the conventional mask process, the entire surface of the glass substrate 2 is covered with 0. 3//] The second SiNx layer of the film thickness is used as a protective insulating layer, and is selectively formed on the electrodes and 6 of the scanning line and the signal line 12 as shown in Fig. 7 (f8 (f)). The opening portions 63 and 64 expose most of the electrode terminal , to complete the active substrate 2. The active substrate 2 and the color filter thus obtained are bonded to each other to form a panel, and the fourth embodiment of the present invention is completed. As apparent from the above description, the device does not require the electrical pixel electrode 22 on the active substrate 2. Therefore, the intermediate conductive layer of the source and the drain is not required. Regarding the configuration of the storage capacitor 15, although f (f) In the example in which the gate electrode insulating layer 30 is interposed between the counter electrode (storage capacitor line) 16 and the pixel electrode layer 21 (the lower left oblique line portion 52), the configuration of the storage capacitor 15 is not limited. Even if it is an insulating layer in which the gate insulating layer 30 is interposed between the pixel electrode 21 and the scanning line 1 1 of the front stage. Further, in FIG. 7 , the electrostatic gas countermeasure between the electrode terminals 5 connected to the electrode terminal 5 of the scanning line is not shown, although a high-resistance member such as an insulating gate crystal or an elongated conductive line in an OFF state is used. However, the opening 63A is exposed to expose a portion 72 of the scanning line 11, and the five terminals of the light is not strict, and the fifth terminal 5:5, 6 is liquid crystal opaque conductive wiring. (The 汲 往 往 存 存 〔 〔 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f In the fourth embodiment, since the protective layer of the active substrate 2 is made of a tantalum nitride layer (SiNx) which is produced by using a PCVD apparatus in the same manner as in the prior art, there are few process change points in the conventional mass production plant. In the same manner as in the third embodiment, the engineering and cost reduction of the protection technique of the anode and the anodic oxidation by the source and the drain can be further reduced, and the fifth and sixth embodiments will be described. (Fifth Embodiment) In the fifth embodiment, a vacuum film forming apparatus such as SPT is used first on one main surface of the glass substrate 2, and the thickness of the coating film is 0. 1 ~ 〇. The first metal layer of about 3/m is selectively formed by the microfabrication technique as the scanning line 1 of the gate electrode 1 1 A as shown in Fig. 9 (a) and Fig. 10 (a). And the counter electrode 16. Next, using a PCVD apparatus on the entire surface of the glass substrate 2, for example, 0. 3-0· 1-0. The film thickness of about 05 / m is sequentially coated with the first SiNx layer 30 which becomes the gate insulating layer, and the first amorphous germanium layer 3 which becomes the channel of the insulating gate type transistor which contains almost no impurity. And three types of thin film layers of the second amorphous germanium layer 3 3 which are sources and drains of the insulated gate type transistor including impurities. Next, as shown in FIGS. 9(b) and 10(b), the second amorphous germanium layer 3 3 and the first amorphous sand layer 31' are selectively removed by a microfabrication technique and are gated. An island-shaped semiconductor layer 3] A, 3 3 A wider than the width of the gate electrode A of the gate 11 is formed on the electrode 11A to expose the gate insulating layer 3 0 - 50 - (48) 1281999 Next, as shown in Fig. 9(c) As shown in Fig. 1(c), a mouth portion 6 3 A is formed on the electrode terminal forming region of the scanning line 11 by a microfabrication technique, and the gate insulating layer 3 0 in the opening portion 6 3 a is selectively removed. A portion 7 2 of the scanning line 1 1 is exposed. Further, a vacuum film forming apparatus such as SPT is used to sequentially coat Ti, a heat resistant metal thin film layer 34 as a film-thick anodic heat-resistant metal layer, and an A1 film layer 35 as a film thickness of 0. A low-resistance wiring layer that can be anodized around 3/^m. Then, as shown in FIG. 9(d), FIG. 10(d), the source/germanium wiring materials composed of the thin films are sequentially etched by the micro-processing technique using the photosensitive tree patterns 85A to 85D. A drain electrode 2 1 of an insulating gate type transistor which is a pixel electrode composed of a laminate of 3 4 A and 3 5 A and a signal line 1 2 which also serves as a source electrode 1 1 A are selectively formed. At the same time as the formation of the source/drain electrodes 12 and 21, the electrode terminal including the electrode terminal 5 of the scanning line and the signal line portion is formed at the same time. 6. In this case, however, in the same manner as in the third embodiment, the film thickness (black area) of the regions 8 5 A and 8 5 B forming the electrode terminals 5 and 6 is, for example, 3 // m, and the ratio according to the halftone exposure technique. Corresponding to the film of the region 8 5 C, 8 5 D (intermediate adjustment region) of the pole wiring 1 2, 2 1 5/im is also thick photosensitive resin patterns 85A to 85D. When the source/drain wirings 1 and 2 are formed, when the photosensitive resin patterns 85 A to 85D are reduced by a thickness of / m or more by the ashing means of oxygen plasma, the photosensitive resin pattern 85C '85D disappears from the open and Ta and the fat pole will also be lined up in the same phase. 5 and • 51 - (49) 1281999 Exposed source/drain wiring 1 2, 2 1, and the photosensitive resin patterns 8 5 E, 85F can be selectively formed only on the electrode terminal 5 and the electrode terminal 6. Here, as shown in Fig. 9 (e) and Fig. 10 (e), the photosensitive resin patterns 8 5 E and 8 5 F are used as a mask, and the surface is anodized while the light is irradiated. Wirings 1 2 and 2 1 form anodized layers 6 8 and 6 9 on the surface, and anodization is exposed to the second amorphous germanium layer 3 3 A and the first between the source and drain wirings 2 and 2 1 1 A portion of the amorphous germanium layer 3 1 A forms a cerium oxide layer 66 containing impurities and a cerium oxide layer (not shown) containing no impurities. After the completion of the anodization, when the photosensitive resin patterns 85E and 85F are removed, the electrode terminals composed of the low-resistance film layer are exposed as shown in Fig. 9 (f) and Fig. 10 (f). 5 and electrode terminal 6. However, although the anodized layer 6 9 and 6 8 are formed on the side of the electrode terminal 6 of the signal line 12 in the same manner as the signal line 12, it is noted that anodization is not formed on the side of the electrode terminal 5 of the scanning line. Floor. This is to anodize the electrode terminal 5 of the scanning line independently. As in the second embodiment, in order to resist static electricity, the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line are connected by a resistive member. At the time of anodization, only a slight anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line. In the case of a resistive member, since the IP S-type liquid crystal display device does not require a transparent conductive layer, any one of a scan line material, a signal line material, and a semiconductor layer is required, but there is a useful connection to the scan line 1 1 Since the opening portion 6 3 A is not limited to which one is selected, a detailed description thereof will be omitted. The active substrate 2 and the color filter thus obtained were bonded together to form a liquid crystal -52-(50) 1281999, and the fourth embodiment of the present invention was completed. The configuration of the storage capacitor 15 is exemplified in FIG. 9(f), in which a counter electrode (storage capacitor line) 16 and a pixel electrode (drain electrode) 2 1 are provided with a gate insulating layer 30. example. In addition to the rationalization of the formation of the opening portion of the semiconductor layer used in the fourth embodiment and the formation of the opening portion of the gate insulating layer, the rationalization of the formation of the protective insulating layer by the source/drain wiring in the fifth embodiment can be simultaneously employed. In the embodiment, this will be described as a sixth embodiment. (sixth embodiment) The sixth embodiment is a project for the islanding process of the semiconductor layer and the formation of the contact engineering as shown in Figs. 1 (d) and 12 (d). 4 The process of the same embodiment is carried out. Next, in the formation of the source/drain wiring, a vacuum film forming apparatus such as Ti or Ta is sequentially applied as a film thickness using a vacuum film forming apparatus such as SPT. An anodized heat-resistant metal layer of about 1/zm, and an A1 thin film layer 35 as an anodizable low-resistance wiring layer having a film thickness of about the same. Then, as shown in FIGS. 1(e) and 12(e), the source/drain wiring composed of the thin films is sequentially etched by the microfabrication technique using the photosensitive resin patterns 85A to 85D. a material, and selectively formed of a laminate of 3 4 A and 3 5 A, which will become the drain electrode 2 1 of the insulating gate type transistor of the pixel electrode and the signal line 1 which also serves as the source electrode 2. At the time of formation of the source/drain wirings 1, 2 and 2, a portion of the scanning line including the opening portion 6 3 A is also formed, and the electrode end of the scanning line is -53-(51) 1281999 sub 5 And an electrode terminal 6 formed by one of the signal lines. At this time, as in the embodiment, the film thickness of the regions 8 5 A, 8 5 B formed on the electrode terminals by the halftone exposure technique is, for example, 3 // m, and the region 8 5 of the corresponding pole wirings 1 2, 2 1 . C, 8 5 D film thickness 1 · 5 ym also thick photosensitive resin pattern 8 5 A~8 5 D. After the source/drain wirings 1 and 2 are formed, the photosensitive resin patterns 8 5 A to 8 5 D are reduced by 1 by oxygen plasma ashing means. · When the film thickness is larger than the above, the photosensitive resin pattern is formed. 8 5 C, 8 5 D disappears and the source/drain wirings 1 2, 2 1, and the photosensitive resin pattern 85E can be selectively formed only on the electrode terminal 5 electrode terminal 6. Here, as shown in Fig. 11 (〇 and Fig. 12 (f), the resin patterns 8 5 E and 85 F are used as masks, and the anode source and drain wirings 12 and 21 are irradiated while the light is being irradiated. The oxide layers 68 and 69 are formed, and at the same time, one of the second amorphous 3 3 A and the first amorphous germanium layer 3 1 A exposed between the source/drain wirings 2 and 2 1 is oxidized to form a portion. The yttrium oxide layer 66 containing impurities and the ruthenium oxide layer containing no impurities are shown. After the anodic oxidation is completed, when the photosensitive resin pattern 8 5 E is removed, the electrode terminal 5 and the electrode terminal formed of the resistive film layer are exposed as shown in FIGS. 1 to 1 (g) and 12 (g). 6. The obtained active substrate 2 and color filter are bonded to each other to form a liquid crystal panel. The fifth embodiment of the present invention. The configuration of the storage capacitor 15 is shown as a configuration example in which the gate insulating layer 30 is interposed between the counter electrode (storage capacitor line) 6 and the pixel (drain electrode) 2 1 . < 5th, 5th, 6th, 5th, 6th, 6th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th, 5th The photomasks used in the sixth embodiment are four or three, but the obtained liquid crystal display device has almost no difference. The difference is merely exposed to the electrode terminal formation region formed on the scanning line. A part of the film of the scanning line in the opening portion is reduced or the surface is deteriorated. In other words, the sixth embodiment can be further reduced. [Effect of the Invention] As described above, one part of the liquid crystal display described in the present invention is At the same time, anodizing is performed by a source/drain wiring composed of an anodizable source and drain wiring material, and a channel surface of an insulating gate type transistor, thereby forming a protective layer (passivation layer), so that no additional heating is required. An insulating gate type transistor in which amorphous germanium is used as a semiconductor layer does not require excessive heat resistance. In other words, an effect of not causing deterioration in electrical performance is added to form a protective effect. Furthermore, for the anodization of the source/drain wiring, by introducing a halftone exposure technique, the electrode terminals of the scanning line or the signal line can be selectively protected, and the effect of preventing the number of photoetching projects can be prevented. By anodizing an amorphous tantalum layer containing impurities, the electrochemical separation of the source and the drain of the insulating gate-type transistor is performed on the insulating separation of the amorphous germanium layer containing impurities, so As in the past, the electrical characteristics of the insulating gate type transistor may be deteriorated due to damage during etching of the channel semiconductor layer, and further, the amorphous layer containing no impurities may be formed as a channel. The film thickness is reduced to the most appropriate film thickness, so the operating rate and particle generation of the PCVD device are also significantly improved. • 55- (53) 1281999 In addition to the same light by introducing halftone exposure technology The islanding process for processing the semiconductor layer and the opening portion of the gate insulating layer form a 'cut-off engineering' by using the same pseudo-pixel electrode to form the pixel electrode and the scanning line at the same time. Rationalization, by cutting down the rationalization of the work, the number of uranium engraving projects can be reduced to four or three masks to produce liquid crystal display devices, even from the cost point of the liquid display device. Important features of the IP S-type liquid crystal display in the fifth and sixth embodiments In the middle, the electric field generated between the counter electrode and the pixel electrode is applied to the gate insulating layer and the anodized layer, so that the conventional insulating layer is not present, and the display image is not easily burned. The advantage of the focal image is that the anodized layer of the drain wiring (pixel electrode) functions as a high-resistance layer without using an insulating layer, so that no load is generated. Moreover, the requirements of the present invention are apparent from the above description. In an etched type of gate-type transistor, an anodizable source-drain wiring material is used, and an amorphous layer containing impurities is also applied to the source. The surface of the pole wiring is anodized, and the insulation layer is formed by any one of the other components. The material of the pixel electrode, the gate insulating layer, or the like is different from that of the liquid crystal display device or the manufacturing method. It is also within the scope of the invention. Even if it is a reflective liquid crystal display device, the nature of the present invention will not change. Furthermore, the semiconductor layer cover of the insulated gate type transistor can be used for engineering photomasks and low, and the crystal display engineering has a high display. The application of the applied image is limited to the amorphous sand when the storage channel is extremely polar and the film thickness is not used in this application. -56- (54) 1281999. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device for a display device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the first embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device for a display device according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the second embodiment of the present invention. Fig. 5 is a plan view showing a semiconductor device for a display device according to a third embodiment of the present invention. Figure 6 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a third embodiment of the present invention. Figure 7 is a plan view showing a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 8 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 9 is a plan view showing a semiconductor device for a display device according to a fifth embodiment of the present invention. Fig. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device for a display device according to a fifth embodiment of the present invention. Fig. 1 is a plan view showing a semiconductor device used in a display device -57-(55) 1281999 according to a sixth embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the sixth embodiment of the present invention. Fig. 13 is a view showing a state in which the liquid crystal panel is mounted. Figure 14 is an equivalent circuit diagram of the liquid crystal panel. Fig. 15 is a cross-sectional view showing a conventional liquid crystal panel. Figure 16 is a plan view of the active substrate of the prior art. Figure 17 is a cross-sectional view showing the manufacturing process of the active substrate of the prior art. Figure 18 is a plan view of the rationalized active substrate. Figure 19 is a cross-sectional view showing the manufacturing process of the rationalized active substrate. [Description of symbols] 1 : Liquid crystal panel 2 : Active substrate (glass substrate) 3 _• Semiconductor integrated circuit wafer 4 : TCP film 5 , 6 : Electrode terminal 9 : Color filter (opposite glass substrate ) 1 〇 : Insulation Gate type transistor 1 1 : Scanning line (gate wiring, gate electrode) 1 2 : Signal line (source wiring, source electrode) 16 : Common capacitance line (opposite electrode in IPS type) 1 7 : Liquid crystal I 9 : polarizing plate - 58 - (56) 1281999 20 : alignment film 21 : drain electrode (dip wiring, IPS type is pixel electrode 22 : (transparent conductive) pixel electrode 3 〇 = gate Insulation layer 3 1 : (1) amorphous germanium layer 3 3 containing no impurities (2) amorphous germanium layer 34 containing impurities (heat-resistant metal layer 35 (anodable): (anodable) Low-resistance metal layer (A1) 3 6 : (anodable) intermediate conductive layer 3 7 : protective insulating layer

Claims (1)

128193⁄4 il09959, revised shoulders in January 1995: (1) Pickup, Patent Application No. 1 · A bottom gate type insulated gate type transistor on an insulating substrate, comprising: at least one first a gate electrode of the metal layer; at least one gate insulating layer on the gate electrode; an island-shaped first semiconductor layer on the gate insulating layer, and the first semiconductor layer contains no impurities; a pair of second semiconductor layers on the first semiconductor layer and containing impurities, and a portion of the second semiconductor overlaps with the gate electrode to form a source or a drain; a gate on the second semiconductor layer and the gate a source/drain wiring on the pole insulating layer, and the source/drain wiring includes a heat resistant metal layer and at least one anodizable metal layer; An anodic oxide layer on the source/drain wiring and the first semiconductor layer, and the anodic oxide layer is outside the electrical connection region of the source wiring. 2. A liquid crystal display device comprising: a first transparent insulating substrate having an insulating gate type transistor and a pixel electrode; - a second transparent insulating layer opposed to the first transparent insulating substrate And a liquid crystal interposed between the first transparent insulating substrate and the second transparent insulating substrate; wherein the insulating gate type transistor comprises: -60-1281999 (2) one having a metal And a gate electrode of a transparent conductive layer, the transparent conductive layer is located on a main surface of the first transparent insulating substrate, and the metal layer is located above the transparent conductive layer; a gate on the gate electrode An insulating layer; a plasma protective layer on the gate insulating layer; an island-shaped first semiconductor layer on the plasma protective layer, wherein the first semiconductor layer contains no impurities; - the first semiconductor layer a second semiconductor layer containing impurities, wherein a portion of the second semiconductor layer overlaps with the gate electrode to become a source or a drain of the insulating gate type transistor; and a second semiconductor layer or the Gate insulation The source wiring or the drain wiring, wherein the source wiring or the drain wiring layer comprising a heat-resistant metal and at least one layer of metal may be anodized layer. 3. The liquid crystal display device of claim 2, further comprising a protective insulating layer having an opening on the pixel electrode, wherein the protective insulating layer is formed on the first transparent insulating substrate on. 4. The liquid crystal display device of claim 2, wherein the first transparent insulating substrate further comprises a plurality of scanning lines, and the scanning line is electrically connected to the gate. The liquid crystal display device according to claim 2, wherein the first transparent insulating substrate further includes a plurality of signal lines that also serve as the source wiring or the drain wiring. The liquid crystal display device according to claim 2, wherein the pixel electrode is arranged in a quadratic-61 - (3) 1281999 matrix on the first transparent insulating substrate. The liquid crystal display device of claim 5, further comprising an anodized layer on the source wiring or the drain wiring, and a portion of the anodized layer is formed on the source wiring or The first semiconductor layer t of the drain wiring. 8. The liquid crystal display device of claim 7, wherein the anodized layer is a hafnium oxide layer. A liquid crystal display device comprising: a first transparent insulating substrate having an insulating gate type transistor and a pixel electrode; and a second transparent insulating layer opposed to the first transparent insulating substrate a substrate; and a liquid crystal that is interposed between the first transparent insulating substrate and the second transparent insulating substrate; wherein the insulating gate type transistor comprises: a gate electrode having a metal layer, the transparent a conductive layer on one of the main surfaces of the first transparent insulating substrate; a gate on the gate electrode, an insulating layer; an island-shaped first semiconductor layer on the gate insulating layer, and the first The semiconductor layer does not contain impurities; a second semiconductor layer ′ on the first semiconductor layer and containing impurities; wherein a portion of the second semiconductor layer overlaps with the gate electrode to become a source or a drain of the insulating wide-polarity transistor a source, the source of the second semiconductor layer or the gate insulating layer is provided with a -62-1281999 (4) line or a drain wiring, wherein the source wiring or the drain wiring comprises a heat resistant metal layer and At least 1 layer or more An anodized metal layer; and an anodized layer on the source wiring or the drain wiring, and partially forming the anodized layer and forming the first semiconductor layer between the source wiring or the drain wiring on. 10. The liquid crystal display device of claim 9, wherein the anodized layer is a hafnium oxide layer. The liquid crystal display device of claim 9, wherein the first transparent insulating substrate further comprises a plurality of scanning lines, and the scanning line is electrically connected to the gate. 1. The liquid crystal display device of claim 9, wherein the first transparent insulating substrate further comprises a plurality of signal lines that also serve as the source wiring or the drain wiring. The liquid crystal display device according to claim 9, wherein the pixel electrodes are arranged in a matrix of two elements on the first transparent insulating substrate. A liquid crystal display device comprising: a first transparent insulating substrate having an insulating gate type transistor and a pixel electrode; • a second transparent insulating layer opposed to the first transparent insulating substrate And a liquid crystal that is interposed between the first transparent insulating substrate and the second transparent insulating substrate; wherein the insulating gate type transistor comprises: -63-1281999 (5) one having a metal a gate electrode of the layer, the transparent conductive layer is located on one main surface of the first transparent insulating substrate; a gate insulating layer on the gate electrode; and an island-shaped first semiconductor on the gate insulating layer a layer, wherein the first semiconductor layer does not contain impurities; a second semiconductor layer on the first semiconductor layer and containing impurities, wherein a portion of the second semiconductor layer overlaps with the drain electrode to form the insulating gate type a source or a drain of the crystal; and a source wiring or a drain wiring on the second semiconductor layer or the gate insulating layer, wherein the source wiring or the drain wiring includes a heat resistant metal layer and at least 1 or more layers An anodically oxidizable metal layer. The liquid crystal display device of claim 14, further comprising a protective insulating layer formed entirely on the first transparent insulating substrate. 16. The liquid crystal display device of claim 14, wherein the first transparent insulating substrate further comprises a plurality of scanning lines, and the scanning line is electrically connected to the gate. 17. The liquid crystal display device of claim 14, wherein the first transparent insulating substrate further comprises a plurality of signal lines that also serve as the source wiring or the drain wiring. The liquid crystal display device according to claim 14, wherein the pixel electrodes are arranged in a matrix of two elements on the first transparent insulating substrate. The liquid crystal display device of claim 14, further comprising an opening in an area other than the image display portion and a gate in the opening portion of the scanning line. The insulating layer is removed. 20. The liquid crystal display device of claim 14, further comprising an anodized layer, wherein the anodized layer is outside the electrode terminal region of the signal line, and the source wiring or the anode Forming on the surface of the pole wiring; and an anodized layer on the source wiring or the drain wiring, and partially forming the anodized layer on the first semiconductor layer between the source wiring or the drain wiring . 2. The liquid crystal display device of claim 20, wherein the anodized layer is a hafnium oxide layer. 2. A method of manufacturing a lower substrate for a liquid crystal display device, comprising the steps of: forming a scanning line composed of a transparent conductive layer and a first metal layer on one main surface of the first transparent insulating substrate; a pseudo-pixel electrode; sequentially coated with a plasma protective layer, a gate insulating layer, a first amorphous germanium layer containing no impurities, and a second amorphous germanium layer containing impurities; forming an electrode terminal at the scan line a photosensitive resin pattern having an opening and having a film thickness on the gate electrode thicker than that of the other regions is formed on the region and the pseudo-pixel electrode; the second amorphous germanium layer and the first non-deposited portion in the opening portion are removed a crystalline germanium layer, a gate insulating layer, a plasma protective layer, and a first metal layer' to expose a portion of the transparent conductive scan line and a pixel electrode; -65- 1281999 (7) reducing the film thickness of the photosensitive resin pattern The second amorphous germanium layer is exposed to form a second amorphous germanium layer and a first amorphous germanium layer wider than the gate electrode width on the gate electrode, and the second metal layer is coated with one or more layers. To the gate insulating layer and the second amorphous layer a source wiring (signal line) or a drain wiring formed on the gate electrode portion, an electrode terminal including the scan line of the opening portion, and an electrode terminal formed by a signal line formed by a portion of the signal line; a second amorphous germanium layer in the source/drain wiring; forming a protective insulating layer over the entire first transparent insulating substrate; and selectively removing the protective insulating layer on the electrode terminal and the pixel electrode In order to form an opening on the protective insulating layer. A method of manufacturing a lower substrate for a liquid crystal display device, comprising the steps of: forming a scan line composed of one or more metal layers on at least one main surface of a first transparent insulating substrate; The gate insulating layer of one or more layers and the first amorphous germanium layer containing no impurities and the second amorphous germanium layer containing impurities are sequentially coated; and an opening portion and a gate are formed on the electrode terminal forming region of the scanning line a photosensitive resin pattern having a film thickness on the electrode electrode that is thicker than the film thickness in the other regions; removing the second amorphous germanium layer, the first amorphous germanium layer, and the gate insulating layer in the opening portion; drying 66-1281999 (8) The film thickness of the photosensitive resin pattern is reduced to expose the second amorphous germanium layer 9. The second amorphous germanium layer and the first amorphous layer having a width wider than the gate electrode are formed in an island shape on the gate electrode. a source layer (signal line) composed of one or more layers of anodizable metal layers on a gate insulating layer and a second amorphous layer on a gate insulating layer Or bungee wiring; on the gate insulating layer and the bungee a portion of the line, in a region other than the transparent conductive pixel electrode and the image display portion, forming a transparent conductive electrode terminal on the signal line; and a selective pattern to be used for the pixel electrode and the electrode terminal The photosensitive resin pattern acts as a mask to protect the electrode terminals of the pixel electrodes and the signal lines, and anodically oxidizes the source wiring, or the drain wiring, and the amorphous sand layer between the source wiring or the drain wiring. A method for manufacturing a lower substrate for a liquid crystal display device, comprising the steps of: forming a scan line and a pseudo-conformation composed of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate a pixel electrode; sequentially coating a plasma protective layer, a gate insulating layer, a first amorphous germanium layer containing no impurities, and a second amorphous germanium layer containing impurities; forming an electrode terminal region and a pseudo-like in the scan line A photosensitive resin pattern having an opening and having a film thickness on the gate electrode thicker than that of the other regions is formed on the pixel electrode; the second amorphous germanium layer and the first amorphous germanium in the opening are removed Layer-67-1281999 (9), gate insulating layer, plasma protective layer and metal layer, and partially exposing a transparent conductive scan line and a pixel electrode; reducing the film thickness of the photosensitive resin pattern to expose the second non- The crystalline germanium layer forms a second amorphous germanium layer and a first amorphous germanium layer wider than the gate electrode width on the gate electrode; after coating one or more layers of the anodizable metal layer, Included with this transparent conductivity sweep The electrode terminal of a part of the trace line and the electrode terminal formed by the signal line formed by the signal line overlap with the gate electrode, and the film thickness on the electrode terminal corresponding to the scan line and the signal line is thicker than other regions. a photosensitive resin pattern; the photosensitive resin pattern is used as a mask, and the anodizable metal layer is selectively removed to form a source wiring or a drain terminal and an electrode terminal of the scan line and an electrode terminal of the signal line; The thickness of the resin pattern is such that the source wiring or the drain wiring is exposed; and the electrode terminal is protected, and the source wiring or the amorphous germanium layer between the drain wiring and the source wiring or the drain wiring is anodized. 25. A method of manufacturing a lower substrate for a liquid crystal display device, comprising the steps of: forming a scan line and a counter electrode formed of a metal layer of one or more layers on at least one main surface of the first transparent insulating substrate; A gate insulating layer of one or more layers and a first amorphous germanium layer containing no impurities and a second amorphous germanium layer containing impurities are sequentially coated; -68-1281999 (10) Forming at electrode terminals of the scanning lines a photosensitive resin pattern having an opening and having a film thickness on the gate electrode thicker than that of the other regions is formed in the region; the second amorphous germanium layer and the first amorphous germanium layer in the opening are removed, a gate insulating layer; a second amorphous ruthenium layer is formed on the gate electrode to form a second amorphous ruthenium layer having a width wider than the gate electrode width and a first non-existence in the second amorphous ruthenium layer a crystalline germanium layer; a source wiring composed of at least one or more second metal layers on the gate insulating layer and having a second metal layer of one or more layers (signal) Line) or bungee wiring (pixel electrode), including the opening scanning An electrode terminal of the signal electrode formed by the electrode terminal of the line and a signal line, wherein the second amorphous germanium layer overlaps with a portion of the gate electrode; and the second amorphous portion between the source wiring and the drain wiring is removed The protective layer is formed on the entire surface of the first transparent insulating substrate except for the electrode terminals of the scanning line and the signal line. 26. A method of manufacturing a liquid crystal display device comprising the steps of forming a scan line and a counter electrode composed of a metal layer of one or more layers on at least one main surface of a first transparent insulating substrate; 1 or more gate insulating layers and a first amorphous germanium layer containing no impurities and a second amorphous germanium layer containing impurities; 69 - 1281999 (11) forming a gate electrode on the gate electrode in an island shape a second amorphous tantalum layer and a first amorphous tantalum layer having a wide width to expose the gate insulating layer; and an opening portion is formed in the electrode terminal forming region of the scanning line to remove the gate insulating layer in the opening portion After coating one or more layers of the anodizable metal layer, a portion of the electrode terminal of the signal line including the scanning line of the opening portion and the signal line formed by one of the signal lines is partially overlapped with the gate electrode, and a photosensitive resin pattern having a film thickness corresponding to other regions on the electrode terminals of the scanning lines and the signal lines; using the photosensitive resin pattern as a mask to selectively remove the anodizable metal layer An electrode terminal of the source wiring or the drain wiring and the scanning line and an electrode terminal of the signal line; reducing the film thickness of the photosensitive resin pattern to expose the source wiring or the drain wiring; and protecting the electrode terminal while anodizing the source Amorphous germanium between the pole wiring, the drain wiring, and the source wiring or the drain wiring. 27. A method of manufacturing a lower substrate for a liquid crystal display device, comprising the steps of: forming a scan line and a counter electrode formed of a metal layer of one or more layers on at least one main surface of the first transparent insulating substrate; A gate insulating layer of one or more layers and a first amorphous germanium layer containing no impurities and a second amorphous germanium layer containing impurities are sequentially coated; and an opening portion is formed in an electrode terminal forming region of the scanning line Further, the photosensitive resin on the gate electrode is thicker than the film thickness in the other regions - 70-1281999 (12); the second amorphous germanium layer and the first amorphous germanium layer in the opening are removed. a gate insulating layer; a film thickness of the photosensitive resin pattern is reduced to expose the second amorphous germanium layer, and a second amorphous germanium layer wider than the gate electrode width and the first one are formed on the gate electrode in an island shape An amorphous germanium layer; after coating one or more layers of the anodizable metal layer, a part of the electrode terminal of the signal line including the scanning line of the opening portion and the signal line formed by one of the signal lines is formed on the electrode terminal The pole electrodes overlap and correspond The photosensitive resin pattern is thicker than the other regions on the electrode terminals of the scanning lines and the signal lines; the photosensitive resin pattern is used as a mask to selectively remove the anodizable metal layer to form source wiring or germanium Electrode terminals of the electrode wiring and the scanning line and electrode terminals of the signal line; reducing the film thickness of the photosensitive resin pattern to expose the source wiring or the drain wiring; and protecting the electrode terminal while anodizing the source wiring and the drain wiring And an amorphous layer between the source wiring or the drain wiring. -71 -