TWI300873B - - Google Patents

Description

1300873 (1) Field of the Invention The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device. [Prior Art] In recent years, with the advancement of technologies such as microfabrication technology, liquid crystal material technology, and high-density mounting technology, TV images of various liquid crystal display devices of 5 to 50 cm diagonal or various image display devices are on a commercial basis (base ) is provided in large quantities. Further, by forming the RGB coloring layer in advance on one side of the two glass substrates constituting the liquid crystal panel, color display can be easily realized. In particular, in the so-called active liquid crystal panel with switching elements in each pixel, the inter-signal crosstalk (c Γ 〇ss _ ta 1 k ) is small, and the response speed is also fast, ensuring high contrast. A portrait of a donkey. In general, these liquid crystal display devices (liquid crystal panels) are composed of a matrix of 200 to 1 200 scanning lines and a signal line of about 300 to 1,600, and recently, large screens and high definitions corresponding to an increase in display capacity. The process is in progress at the same time. Fig. 23 is a view showing a state in which the liquid crystal display panel is mounted, and an electric signal is supplied to the image display unit by means of a mounting means such as a COG (Chip-On-Glass) method or a TCP (Tape-Carrier-Package) method. In the COG method, a semiconductor integrated circuit wafer 3 for supplying a driving signal to the scanning line electrode terminal group 5 is connected by using a conductive adhesive, and the scanning line electrode terminal group 5 is formed on one side of the liquid crystal panel 1. Transparency (2) 1300873 The edge substrate is, for example, a glass substrate 2. In the TCP method, a TCP film 4 having a gold or a copper-plated copper foil terminal is crimped to an electrode terminal group 6 of a signal line by using a polyimide-based resin film as a base and a suitable adhesive containing a conductive medium. And fixed. Here, for the sake of explanation, two types of mounting methods are illustrated at the same time, and any one of them may be appropriately selected. The pixels for connecting the pixels in the image display portion located at the substantially central portion of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the scanning lines and the signal lines are 7 and 8, and the electrode terminal groups 5 and 6 are not necessarily used. It is composed of the same conductive material. 9 is a counter-glass substrate or a color filter of another transparent insulating substrate having a transparent conductive opposite electrode which is common to all liquid crystal cells on the opposite surface. Fig. 24 is an equivalent circuit diagram showing an active liquid crystal display device in which an insulating gate type transistor 10 is disposed as a switching element, and 1 1 (Fig. 23 is 7) is a scanning line, 12 (23th) The figure is 8) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is treated as a capacitive element. The components depicted by the solid line are formed on one of the glass substrates 2 constituting the liquid crystal panel, and the counter electrode 14 which is common to all the liquid crystal cells 12 as indicated by a broken line is formed on the opposite main surface of the other glass substrate 9. on. When the OFF resistance of the insulated gate type transistor 1 or the resistance of the liquid crystal cell 13 is low, or when the gray scale of the image is emphasized, it is possible to increase the circuit setting, that is, the auxiliary storage capacitor 15 and the liquid crystal cell 1 3 is added in parallel, and the auxiliary storage capacitor 15 can increase the time constant of the liquid crystal cell 13 as a load. Further, 16 is a common bus of the storage capacitor 15. FIG. 25 is a cross-sectional view of a main portion of the image display unit of the liquid crystal display device (3) 1300873, and the two glass substrates 2 and 9 constituting the liquid crystal panel 1 are formed of resin fibers, particles, or color filters. A spacer (not shown) such as a pillar-shaped spacer on the sheet 9 is formed at a predetermined interval of several μm or so, and a gap is formed in the peripheral portion of the glass substrate 9 to be composed of an organic resin. In the sealed space sealed by the sealing material and/or the sealing material (none of which is not shown), the liquid crystal is filled in the sealed space, and the color display is performed on the sealed space side of the glass substrate 9. An organic thin film having a thickness of about 1 to 2/m thick, which is called a dye or a pigment of either or both of the dyed layer 18, is applied to impart a color display function. Therefore, the glass substrate 9 may be referred to as color at this time. Filter (Color Filter is abbreviated as CF). Further, the polarizing plate 19 is adhered to either or both of the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2 in accordance with the properties of the liquid crystal material 17, so that the liquid crystal panel 1 has the function of an electro-optical element. At present, most of the liquid crystal panels sold on the market use a TN (twist nematic) structure on a liquid crystal material, and therefore generally require two polarizing plates. Although not shown in the drawing, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below. The polyimine-based resin film 20, which is formed on the two glass substrates 2, 9 and which is in contact with the liquid crystal 17 and has a thickness of about ο. ίμιη, is an alignment film for aligning the liquid crystal molecules in a specific direction. 2 1 is a drain electrode (wiring) for connecting the drain of the insulating gate type transistor 1 and the transparent conductive pixel electrode 22, and is mostly formed at the same time as the signal line (source line) 12. Between the signal line 12 and the drain electrode 21 is a semiconductor layer 23, and the -6 - 1300873 (4) semiconductor layer 23 will be described in detail later. A Cr film layer having a thickness of about 0.1/m at the boundary of the colored layer 18 on the color filter 9 serves to prevent external light from entering the light shielding member of the semiconductor layer 23 and the scanning lines 11 and 12, which is a conventional black. Matrix (Black, BM for short) technology. Here, an insulating gate type electrical structure and a manufacturing method as a switching element will be described. At present, the commonly used insulated gate type transistor has been introduced into the dry etching technique by one of them as a channel etching type. The current use of eight channels is currently reduced to five channels, which is a process cost ( The process cost is quite helpful. Figure 26 is a diagram of a unit pixel surface of a conventional liquid crystal panel substrate (semiconductor device for a display device). Figure 26: Figure A (A) A - A, B - The cross-sectional view of B and C c / line, the following is a brief description of the manufacturing process. First, as shown in Fig. 26 (a) and Fig. 27 (a), the glass substrate 2 of 〇·5 to Ι.Ι/zm 2 For example, on the main surface of Corning's name 1737, a vacuum is used, such as SPT (sputtering), to coat a first metal layer with a thickness of about 0.1 to 0.3/m, which is high in workability, chemical resistance and transparency. The insulating substrate is selectively formed by a micro-technology to form a scanning line that also serves as the gate electrode 1 1 A: a storage capacitor line 16. In terms of the material of the scanning line, comprehensive consideration is given to heat-resistant chemical properties, hydrogen fluoride resistance, and conductivity. After the sex, it is generally used, and the heat resistance is high such as MoW alloy. Metal or alloy. In order to respond to the large screen and high definition of the liquid crystal panel, the formation of 24 is the signal line of the Matrix crystal, which is the active picture of the drop mask. In the thickness of the product film device for heat-resistant fine processing 1 and storage, Cr, Ta low scan (5) 1300873 line resistance 値, the use of A1 (aluminum) as the material of the scan line is combined but due to A1 monomer Since the heat resistance is low, the technical layer currently used is Cr, Ta, Mo or a telluride of the above-mentioned heat resistant metal, or an anodized additional oxide layer (ai2〇3) is used on the surface of A1. It is also said that the scanning line 11 is composed of one or more metal layers. Further, on the entire surface of the glass substrate 2, a pCVD (Electrical Vapor Deposition) device is used, for example, a film thickness of about 〇.3 /im, 0.05 // m, respectively, and three kinds of thin film layers are sequentially coated: as a gate a first SiNx (nitriding chopped) layer 30; and a first amorphous germanium (a-Si) layer 31 as a substantially free impurity gate-type transistor channel as a second SiNx layer of the insulating layer of the protective via 32, and as shown in FIG. (b) and FIG. 27(b), the second SiNx layer 32 on the gate electrode 1 1 A is left by the microfabrication technique to make the wide gate electrode 11A more 32D is formed thin to expose the first amorphous 矽f 〇 Next, a PCVD device is also used, for example, a left film thickness of 0.05 // m, and the entire surface is covered with a second amorphous germanium layer 33 containing impurities such as phosphorus, such as the 26th As shown in Fig. 3(c) and Fig. 27(c), a thin film layer 34 such as Ti or Cr having a thickness of about 0.1 m is used as a heat-resistant metal layer and a film thickness 使用.3 using a film apparatus such as SPT. The A1 film layer 35 of about //m is used as the low-resistance wiring layer, and the film thickness is about 1 // m, such as the Ti film layer 36 as the intermediate conductive layer, and Fine addition, selective formation · The insulating gate type electro-crystallography consisting of the laminate of the three films 34A, 35A, and 36A as the source/drainage wiring material is the accumulator, that is, pulping '0.1 The edge layer is: and g 26 selects the width ratio |31 right after the empty system, Μ 〇, for example, the thin-formed (6) 1300873 drain electrode 2 1 , and the signal line 1 which also serves as the source electrode 2. The selective pattern is formed by using a photosensitive resin pattern used for forming the source/drain wiring as a mask, and sequentially etching the Ti thin film layer 36, the A1 thin film layer 35, and the Ti thin film layer 34. Thereafter, the table-amorphous sand layer 33 between the source and drain electrodes 丨2, 2 1 is removed, and the second SiNx layer 32D is exposed, and the first amorphous germanium layer 3 1 is removed in other regions. Gate insulation layer 3 0 . As described above, since the second SiNx layer 3 2D is provided as the channel protective layer, the etching of the second amorphous germanium layer 3 3 is automatically ended, so this method is called an etching termination method. The source/drain electrodes 1 2, 2 1 and the etch stop layer 3 2 D are partially overlapped (number μm) in a plane so that the insulating gate type transistor does not form an offset structure. Since the overlapping portion electrically has a parasitic capacitance, the smaller the better, but it is determined by the alignment accuracy of the exposure machine, the accuracy of the mask, the expansion coefficient of the glass substrate, and the temperature of the glass substrate during exposure. Therefore, the actual number of domes is about 2/m. Further, after removing the photosensitive resin pattern, a Si Vx layer having a thickness of about 3 vm is used as a transparent insulating layer on the entire surface of the glass substrate 2 by using a PC VD device in the same manner as the gate insulating layer. The passivation insulating layer 37 is formed, and then, as shown in FIGS. 26(d) and 27(d), the passivation insulating layer 3 is selectively removed by a microfabrication technique to form: the opening portion 62 is located at the bungee The electrode 21 is exposed; the opening portion 63 is located at a position other than the image display portion and the electrode terminal 5 of the scanning line 11 is formed; and the opening portion 64 is located at a portion where the electrode terminal 6 of the signal line 12 is formed, and is exposed. The drain electrode 21 and the scanning line 1 1 and part of the signal line 1 2 -9 - 1300873 (7). An opening portion 65 is formed on the storage capacitor line 16 (the pattern electrode that is bundled in parallel), and a portion of the storage capacitor line 16 is exposed. Finally, a vacuum film forming apparatus such as SPT is used, and, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) is coated, as shown in FIGS. 26(e) and 27(e), In the microfabrication technique, the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening portion 62, and the active substrate 2 is completed. A part of the scanning line 1 1 exposed in the opening 63 may be the electrode terminal 5, and part of the signal line 12 exposed in the opening 64 may be the electrode terminal 6, or may include openings 63 and 64 as shown in the drawing. Electrode terminals 5A and 6A made of ITO are selectively formed on the passivation insulating layer 37. Generally, the transparent conductive short-circuit lines 40 connecting the electrode terminals 5A and 6A are simultaneously formed. Though it is not shown here, the reason is that the electrode terminals 5A and 6A and the short-circuit line 40 are formed in a slender shape, and the resistance can be increased to form a high resistance for electrostatic countermeasures. Similarly, the electrode terminal of the storage capacitor line 16 may be formed to include the opening portion 65. When the wiring resistance of the signal line 12 does not cause a problem, it is not necessary to use the low-resistance wiring layer 35 composed of A1. In this case, if a heat-resistant metal material such as Cr, Ta, or Mo is selected, the source can be used. The pole wirings 12 and 21 are single-layered and simplified. According to this configuration, it is important to ensure that the source/drain wiring uses a heat-resistant metal layer to ensure electrical connection with the second amorphous germanium layer, and the heat resistance of the insulated gate transistor is described in detail. Japanese Laid-Open Patent Publication No. Hei 7-74368. Further, in Fig. 26(c), the storage capacitor line 16 and the drain electrode 2 1 are interposed with a region 50 (lower right oblique line portion) in which the gate insulating layer 30 is in a plane of 10 - 1300873 (8), The storage capacitor 15 is formed, but a detailed description thereof will be omitted herein. The above-mentioned five mask processes are the rationalization of the islanding process of the semiconductor layer, and the result obtained by reducing the contact engineering once, and the detailed description thereof is omitted here. At the beginning, seven to eight masks were needed, which could be reduced to five by the introduction of dry etching technology, which is quite helpful for the reduction of process cost. In order to reduce the production cost of the liquid crystal display device, an effective method is to reduce the process cost in the production process of the active substrate, and further, to reduce the component cost in the panel assembly project and the module installation project, which is a well-known development goal. In addition, in order to reduce the cost of the process, for example, there is a reduction in the number of engineering processes for reducing the number of processes, a process development of a low-cost process, or a replacement of a process. Here, a four-mask process for producing an active substrate by using four masks is exemplified to illustrate the engineering. Reduction. The four-mask process reduces the photographic etching process by the introduction of the halftone exposure technique, and the figure 28 is the unit pixel plan of the active substrate corresponding to the four-mask process, and the figure 29 is shown in Figure 28. e) A section of the A-, B-β/ and C-C^ lines. As described above, there are two types of insulating type transistors which are currently used more frequently, and a channel-etching type insulating gate type transistor is used here. First, in the same manner as the five mask processes, a vacuum film forming apparatus such as SPT is used on one main surface of the glass substrate 2 to coat a first metal layer having a thickness of about 1 to about 3 μm. As shown in Fig. 28(a) and Fig. 29(a), the scanning line 11 and the storage capacitor line 16 which also serve as the gate electrode 11A are selectively formed by the microfabrication technique. Next, on the entire surface of the glass substrate 2, a PCVD (plasma chemistry-11 - (9) 1300873 vapor deposition) device is used, for example, film thicknesses of 〇·3 // m, 0.2 mbar, and 0.05 # m, respectively. Three thin film layers are sequentially coated: a SiNx layer 30 as a gate insulating layer, a first amorphous germanium layer 31 as an insulating gate type transistor channel containing almost no impurities, and an insulating gate type containing impurities The source of the transistor • the second amorphous layer 33 of the drain. Then, a vacuum film forming apparatus such as SPT is used to sequentially coat, for example, a film thickness of about 1/min, such as a Ti film layer 34, as a heat-resistant metal layer; and an A1 film layer 35 having a film thickness of about 3/m. The low-resistance wiring layer; and the Ti thin film layer 36 having a film thickness of about 0.1 // m is used as the intermediate conductive layer, that is, the source/drain wiring material is sequentially coated. The gate electrode 2 1 of the insulating gate type transistor and the signal line 12 which also serves as the source electrode are selectively formed by the microfabrication technique, and when the selection pattern is formed, the maximum characteristic is as shown in FIG. 28(b) As shown in Fig. 29(b), the film thickness of the channel formation region 80B (hatched portion) formed between the source and the drain is, for example, 1.5 Ω, which is larger than the source/drain wiring formation region 80A. (12) 80A (21) photosensitive resin patterns 80A and 80B having a film thickness of 3/im. Since the photosensitive resin patterns 80A and 80B are generally made of a positive photosensitive resin in the production of the substrate for a liquid crystal display device, the source/drain wiring formation region 80A is black, that is, a Cr film is formed; the channel region 80B It is gray, that is, a Cr pattern of, for example, a line and a space having a width of about 0.5 to 1 // m is formed; other areas are white, that is, a mask for removing the Cr film is used. Due to the gray area, the resolution of the exposure machine is insufficient, so the line and space cannot be resolved, so that the illuminating light from the light source can be transmitted through about half of the light, so according to the positive sense -12 - 1300873 (10) light The residual film characteristics of the resin can obtain the photosensitive resin patterns 80A and 80B having the surface shape of Fig. 29(b). The photosensitive resin patterns 80A and 80B are used as a mask pattern (sequential etching: Ti thin film layer 36, A1 thin moon Ti thin film layer 34, second amorphous germanium layer 33, and first amorphous), After the gate insulating layer 30 is exposed, as shown in FIG. 28(c) and c), the film thickness of the photosensitive layers 80A and 80B is reduced by, for example, 3 // by means of ashing means such as oxygen plasma. When m is reduced by 1.5 //, the photosensitive resin pattern 80B disappears, and the channel region is exposed, and 80C (12), ) remains in the source/drain wiring formation region. Here, the Ti thin film layer, the A1 thin film layer, and the Ti thin film amorphous germanium are sequentially etched by the photosensitive resin pattern 80C 80C ( 21 ) having a reduced film thickness as a mask and sequentially etching the source/drain formation formation region). The layer 33A and the first amorphous germanium layer 31A leave the first layer 31A at about 0.05 to 0.1/m. Further, in order to change the pattern size during the oxygen plasma treatment, the reason for the anisotropy is enhanced, and the reason will be described in detail later. Further, after removing the photosensitive resin pattern 80C ( 12 ) 21 ), the entire surface of the glass substrate 2 is covered as shown in Fig. 28 (29), as in the case of the five mask processes. The SiNx layer of the right film thickness serves as a transparent insulating layer, and forms a blunt 3-7. On the region where the gate electrode 2 1 and the scanning line 1 1 and the signal line: terminal are formed, openings 62, 63, and 04' are respectively formed. The passivation insulating layer 37 in the opening portion 63 and the gate insulating layer are shown as a cross section, such as the 2nd 9th layer, and the sand layer 3 1 ^ 29 (the resin pattern m or more can only be 80C (21 (12) at the same time). Between the lines (the pass layer, the second amorphous yttrium suppresses the above properties, 80C (:d) and the third) · 3 // m left the insulating layer 1 2 electrode, then go to 30, and dew - 13-1300873 (11) A part of the scanning line η is removed, and the passivation insulating layer 3 7 in the openings 62 and 64 is removed to expose a part of the drain electrode 2 1 and a part of the signal line. Finally, a vacuum film forming apparatus such as SPT is used. Coating, for example, IT Ο or IZO, as a transparent conductive layer having a film thickness of about 0.1 to 2.2 μηη, as shown in Figs. 28(e) and 29(e), In the fine processing technique, the transparent conductive pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening portion 62, and the active substrate 2 is completed. The electrode terminal is here on the passivation insulating layer 37, The transparent conductive electrode terminals 5A and 6A made of ITO are selectively formed by the openings 63 and 64. [Explanation] [Problems to be Solved by the Invention] By this, due to the five-mask process and four masks In the process, the formation contact process of the drain electrode 2 1 and the scanning line 11 is completed at the same time, so the thickness and type of the insulating layer in the openings 62 and 63 corresponding thereto are different. The passivation insulating layer 3 7 Compared with the gate insulating layer 30, the film forming temperature is lower and the film quality is lower. When the etching is performed by using the hydrofluoric acid-based uranium engraving solution, the etching rates of the two are respectively several thousand A/min and several hundred A/min. The difference between the one-digit number and the cross-sectional shape of the opening portion 6 2 on the gate electrode 2 1 causes excessive etching in the upper portion and the reason why the aperture cannot be controlled. Therefore, dry-etching using a fluorine-based gas is employed. Even when dry etching is used, Since the opening portion 62 on the drain electrode 2 1 is only the passivation insulating layer 3 7, compared with the opening portion 63 on the scanning line 11, it is impossible to avoid excessive uranium engraving, and depending on the material, there may be - 14- 1300873 (12) When the intermediate conductive layer 3 6 A is reduced in thickness due to etching gas, generally, after removing the photosensitive resin pattern, the polymer is removed to remove the polymer on the fluorinated surface. Oxygen plasma ashing, the surface of the photoreceptor pattern is reduced by about 0.1 to 0.3 // m, and then an organic peeling liquid, for example, a liquid 106 manufactured by Tokyo Chemical Industry Co., Ltd., is used for chemical treatment. When the film thickness of the intermediate conductive layer 36A is in a state in which the underlying aluminum layer 35A is exposed, Al2〇3 as an insulator is formed on the surface of the aluminum layer 35A by oxygen plasma ashing, so that ohmic is not obtained between the element electrodes 22. contact. Here, the film thickness may be, for example, 0·2 μm, and the thickness of the intermediate conductive layer 36A may be reduced to avoid problems. Alternatively, when the openings 62 to 65 are formed, the aluminum layer is removed to expose the Ti thin film layer 34A as the base heat resistant metal layer, and the re-pixel electrode 22 is also a countermeasure, and at this time, there is no intermediate conductive layer from the beginning. The advantages of A. However, in the countermeasures of the former, when the uniformity of the film thickness of these films is poor, the compounding does not necessarily work effectively, and when the in-plane uniformity of the etching rate is poor, the same is true. Although the intermediate conductive layer 36A is not required for the countermeasure, the removal of the layer 35 A is increased, and when the cross section of the opening 62 is controlled enough, there is a fear that the pixel electrode 22 is broken.

Further, in the channel-etched insulating gate type transistor, the first amorphous germanium layer 3 1 containing no impurities in the pass region is not covered with a thickness (generally 0 · 2 // m or more) It has a great influence on the uniformity of the glass substrate, and the transistor characteristics are particularly OFF. In addition, after the first feeling, the peeling reduction processing is set to avoid the need for the 35A formation. The aluminum-filled non-filled area thicker in-plane current -15- (13) 1300873 is prone to inconsistency. This is greatly affected by the operating rate of the PC VD and the occurrence of particles, and it is also very important from the viewpoint of production cost. Furthermore, since the channel forming process for the four-mask process is to selectively remove the source/drain wiring material and the impurity-containing semiconductor layer between the source and drain wirings 1, 2, 2, it is used. To determine the length of the channel length of the ON gate of the insulated gate transistor (currently, the product is 4 to 6 // m). Since the variation in the length of the channel causes a large change in the ON current of the insulated gate transistor, strict manufacturing management is generally required. However, the current situation is that the channel length, that is, the pattern size of the halftone exposure region, is subjected to exposure (light source intensity and pattern accuracy of the mask, especially line/pitch size), coating thickness of the photosensitive resin, development processing of the photosensitive resin. And the influence of many parameters such as the amount of reduction in the thickness of the photosensitive resin film in the etching process, and the in-plane uniformity of these amounts, it is not always possible to produce in a high-yield and stable state. More rigorous manufacturing management, so can not be said to have achieved a high level of completion. In particular, when the channel length is 6/m or less, the influence on the pattern size is more pronounced as the thickness of the photoresist pattern is reduced. The present invention has been invented in view of the related art, and its purpose is not only to avoid the conventional five mask process or four mask processes, but also to jointly produce a problem in contact, by using a manufacturing margin of a larger half. Tone exposure technology to reduce manufacturing engineering. In addition, in order to realize the low price of the liquid crystal panel, in order to increase the demand, it is necessary to deliberately pursue a smaller number of manufacturing projects, and to simplify or reduce the cost by adding to other major manufacturing projects, Jane-16-(14) 1300873. The present invention can further improve the present invention. [Means for Solving the Problem] In the present invention, the formation and engineering of an etch stop layer which is easy to implement by using a halftone exposure technique and precision management is firstly employed to achieve a reduction in manufacturing engineering. . Next, in order to effectively passivate the drain wiring, an anodic oxidation technique for forming an insulating layer on the surface of a source made of aluminum is disclosed in Japanese Patent Publication No. 2-2 1612, which incorporates a conventional technique, to realize the low temperature and low temperature. Chemical. Further, the pixel electrode forming structure is applied to the present invention as disclosed in Japanese Laid-Open Patent Publication No. Hei 5-268726. Further, in order to further reduce the formation of the anodized layer of the engineered wiring, it is also suitable to rationalize the formation of the protective layer of the halftone exposure technique. The bottom gate type transistor according to the first aspect of the invention is characterized in that, on the main surface of the insulating substrate, an insulating layer is formed on a side surface of the gate electrode, and one or more gates are formed on the pole. An insulating layer and a layer containing no impurities, forming a protective insulating layer having a width ratio of the gate on the first semiconductor layer, and forming a second impurity-containing layer on the partial protective insulating layer and the upper and insulating substrates A source/drain wiring formed by laminating a metal layer on a semiconductor; using a halftone exposure technique, a photomask can be used to process the formation process and the formation of the channel protective layer. The price of the gate is very low. Applicable to the shape of the pattern scan line only rationalizes the reasonable range of the source · Kaiping · 汲 配线 wiring project, the source 汲 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The electrode electrode is further thinned by a semiconductor layer and a layer of -17-1300873 (15) insulating layer which is formed by the side of the pole of the gate electrode. The inorganic material and the organic material can be selected, and the patent application scope is 2nd. 3 items to explain. The insulating gate type transistor described in the second paragraph of the patent application is an etch-stop type insulated gate type transistor characterized in that the insulating layer is an organic insulating layer, and is not limited to the material of the gate electrode. Applied to a liquid crystal display device. Relationship with liquid crystal display devices, in the scope of patent applications Nos. 5, 6, 7, 8, 9, 10, 11, 12 and 13, and first, second, third, fourth, fifth, sixth, The seventh, eighth and ninth embodiments are clear. The insulated gate type transistor described in the third paragraph of the patent application is characterized in that the gate electrode is composed of an anodizable metal layer, and the insulating layer is an etch-stop type insulating gate characterized by an anodized layer. Type transistor, relationship with liquid crystal display device, in the scope of patent application Nos. 5, 6, 10, 11, 12, 13 and 14, and first, second, sixth, seventh, eighth, ninth And the tenth embodiment is clearly explained. The insulating gate type transistor described in claim 4 is characterized in that the gate electrode is composed of a laminate of a transparent conductive layer and a metal layer, and the insulating layer is an etch-stop type insulating feature characterized by an organic insulating layer. The gate type transistor is constructed by using a mask to form a gate electrode (scanning line) and a pixel electrode to achieve engineering reduction. The relationship with the liquid crystal display device is clearly explained in the claims 7, 7 and 9 and the third, fourth and fifth embodiments. The liquid crystal display device according to claim 5, comprising at least an insulating gate type transistor and a gate electrode serving as the insulating gate -18-(16) 1300873 pole type transistor on one main surface. a first transparent insulating substrate in which a scanning line, a signal line serving as a source wiring, a pixel electrode connected to a drain wiring, or the like is arranged in a two-dimensional matrix; and the first transparent insulating substrate a liquid crystal display device comprising: a liquid crystal display device in which a liquid crystal is interposed between a second transparent insulating substrate or a color filter; wherein at least one layer of the first transparent insulating substrate is formed on one main surface a scan line composed of a first metal layer and having an insulating layer on its side surface, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and formed on the first semiconductor layer a protective insulating layer having a wider width than the gate electrode, and an opening portion formed in the gate insulating layer on the scanning line in a region other than the image display portion, on the partial protective insulating layer, the first half a source (signal line) formed by laminating a second semiconductor layer containing impurities and one or more anodizable metal layers on the bulk layer and the first transparent insulating substrate, a drain wiring, and the opening portion An electrode terminal of a scan line formed by laminating a peripheral first semiconductor layer and a second semiconductor layer and one or more anodizable metal layers is formed on a portion of the drain wiring and the first transparent insulating substrate A transparent conductive pixel electrode and a transparent conductive electrode terminal formed on a signal line in a region other than the image display portion. In addition to the region of the above-described drain wiring overlapping the pixel electrode and the signal line -19-1300873 (17) Outside the area of the electrode terminal, an anodized layer is formed on the surface of the source/drain wiring. With this configuration, the gate insulating layer is formed in the same pattern width as the scanning line, and an insulating layer other than the gate insulating layer is provided on the side surface of the scanning line, and the intersection of the scanning line and the signal line becomes possible. This is common to the structural features of the present invention. Moreover, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the same time, an anodic oxide layer (Ta20 5 ) which is an insulating anodized layer is formed on the surface of the signal line and the drain wiring or Alumina (A 1 203 ) imparts a passivation function, so that it is not necessary to coat the entire surface of the glass substrate with the passivation insulating layer, and the heat resistance of the insulating gate type transistor does not cause a problem. Thus, a TN type liquid crystal display device having a transparent conductive electrode terminal can be obtained. In the liquid crystal display device of the sixth aspect of the invention, a scanning line composed of one or more first metal layers and having an insulating layer on its side surface is formed on one main surface of the first transparent insulating substrate. Forming one or more gate insulating layers and a first semiconductor layer containing no impurities on the gate electrode, and forming a protective insulating layer having a wider width than the gate electrode on the first semiconductor layer, in the protective insulating layer a source (signal line) and a drain wiring formed on a portion of the first semiconductor layer and the first transparent insulating substrate, which are formed by laminating a second semiconductor layer containing impurities and a second metal layer or more. A transparent insulating layer having an opening in an electrode terminal forming region of the scanning line and the signal line is formed on the first transparent insulating substrate of the -20-1300873 (18) on the drain wiring and the region other than the image display portion. The gate insulating layer on the electrode terminal forming region from which the scanning line is removed includes the opening portion on the above-described drain wiring, and transparent conductive is formed on the transparent insulating layer Its characteristic pixel electrode. With this configuration, in the same manner as the conventional example, the formation of the opening portion of the passivation insulating layer can be used as a connection forming process for electrically connecting the scanning lines, and the manufacturing process is reduced. Therefore, the TN type can be produced by using four masks. Liquid crystal display device. On the other hand, when a transparent transparent resin layer is used as the passivation insulating layer as the transparent insulating layer, a TN type liquid crystal display device having a high aperture ratio can be obtained. In the liquid crystal display device of the seventh aspect of the invention, a scanning line composed of a laminate of a transparent conductive layer and a first metal layer and having an insulating layer on its side surface is formed on one main surface of the first transparent insulating substrate. And a transparent conductive pixel electrode and an electrode terminal of the signal line, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a wide width is formed on the first semiconductor layer a protective insulating layer which is thinner than the gate electrode, and an opening portion is formed in the gate insulating layer on the scanning line in a region other than the image display portion, and a transparent conductive layer as an electrode terminal of the scanning line is exposed in the opening portion, a portion of the protective insulating layer and the first semiconductor layer and the first transparent insulating substrate are formed with a second semiconductor layer containing impurities and a second metal layer of a layer of -21 - !3〇0873 (19) a source wiring (signal line) formed by the buildup, and a source of the second metal layer formed on one of the electrode terminals of the signal line And a portion of the partial protective insulating layer and the first semiconductor layer and the first transparent insulating substrate are formed by laminating a second semiconductor layer containing impurities and a second metal layer or more. The drain wiring and a portion of the drain wiring formed of one or more first metal layers on the partial pixel electrode are characterized in that a photosensitive organic insulating layer is formed on the source/drain wiring. With this configuration, since a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and a photosensitive organic insulating layer is formed on the surface of the source/drain wiring to impart a passivation function, no passivation is required. The insulating layer is coated on the entire surface of the glass substrate, and the heat resistance of the insulating gate type transistor does not cause a problem. Thus, a TN type liquid crystal display device having a transparent conductive electrode terminal can be obtained. In the liquid crystal display device of the eighth aspect of the invention, a scanning line formed by laminating a transparent conductive layer and a first metal layer and having an insulating layer on its side surface is formed on one main surface of the first transparent insulating substrate. And a transparent conductive pixel electrode, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a wide width is formed on the first semiconductor layer than a gate electrode Protective insulating layer, -22- (20) 1300873 An opening is formed in the gate insulating layer on the scanning line in a region other than the book image display portion, and a transparent conductive layer is exposed in the opening portion' on one of the protective insulating layers a 'source wiring (signal line) formed by laminating a second semiconductor layer containing impurities and one or more second metal layers on the first semiconductor layer and on the first transparent insulating substrate: and in the above portion Forming a second semiconductor layer containing impurities and one or more second metal layers on a portion of the protective insulating layer, on the second semiconductor layer, and on the first transparent insulating substrate a drain wiring formed of a laminate; and a portion of the drain wiring formed of one or more second metal layers on one of the pixel electrodes; and a first semiconductor layer including the periphery of the opening a semiconductor layer and a transparent conductive layer in the opening portion form an electrode terminal of a scanning line formed of a second metal layer; and an electrode terminal of a signal line composed of a partial signal line in a region other than the image display portion, except for the signal line In addition to the electrode terminals, a photosensitive organic insulating layer is formed on the signal lines. With this configuration, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and a photosensitive organic insulating layer is formed on the surface of the signal line (source wiring) to impart a passivation function. The same effect as the liquid crystal display device described in claim 7 of the patent application. Further, a TN type liquid crystal display device having electrode terminals having the same metallicity as the signal lines can be obtained. In the liquid crystal display device of the ninth aspect of the invention, the transparent conductive layer and the -23-(21) 1300873 metal layer are formed on the main surface of the first transparent insulating substrate, and a scanning electrode having an insulating layer on the side thereof and a pixel electrode having a transparent conductive position, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and the first semiconductor layer is formed on the first semiconductor layer a protective insulating layer having a wider width than the gate electrode, and an opening portion formed in the gate insulating layer on the scanning line in a region other than the image display portion, and a transparent conductive layer is exposed in the opening portion, in a portion of the protective insulating layer a source wiring (signal line) formed by laminating a second semiconductor layer containing impurities and one or more anodizable metal layers on the upper, first semiconductor layer and the first transparent insulating substrate; Forming a second semiconductor layer containing impurities and one or more layers of anodic oxygen on the partial protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate a drain wiring formed by laminating a metal layer; and a portion of the above-described drain wiring formed of an anodizable metal layer on a portion of the pixel electrode; and a first semiconductor layer including the periphery of the opening a second semiconductor layer and a transparent conductive layer in the opening portion form an electrode terminal of a scanning line formed of an anodizable metal layer; and a signal line formed by a portion of the signal line is formed in a region other than the image display portion The electrode terminal is characterized in that an anodized layer is formed on the source/drain wiring in addition to the electrode terminal of the signal line. By this, a protective insulating layer is formed on the channel between the source and the drain to protect the channel while forming a surface on the signal line and the drain wiring. 24-(22) 1300873 is an insulating anodized layer. The pentoxide oxide (Ta205) or the aluminum oxide (A1 203) is provided with a passivation function, and the same effects as those of the liquid crystal display device described in claim 7 can be obtained. Further, a TN type liquid crystal display device having an electrode terminal having the same metallicity as the signal line can be obtained. The liquid crystal display device according to claim 10, wherein a scanning line composed of one or more first metal layers and having an insulating layer on its side surface is formed on one main surface of the first transparent insulating substrate. Forming more than one gate insulating layer and a first semiconductor layer containing no impurities on the gate electrode, and forming a protective insulating layer having a wider width than the gate electrode on the first semiconductor layer, in a portion of the protective insulating layer On the upper, first semiconductor layer and the first transparent insulating substrate, a source (signal line) and a drain wiring formed by laminating a first semiconductor layer containing impurities and one or more second metal layers are formed. a transparent resin layer having an opening formed on the drain wiring and the electrode terminal forming region of the scanning line and the signal line on the first transparent insulating substrate, and the gate insulating layer on the electrode terminal forming region where the scanning line is removed includes The conductive pixel electrode of the opening portion and the conductive counter electrode including the scanning line and the signal line are formed on the transparent resin layer Characterized. 25-(23) 1300873 With this configuration, since a layer is formed on the active substrate to impart a passivation function, not only the same effect as the liquid crystal display device described in the application can be obtained, but also the counter electrode can be disposed in a transparent manner. In the resin layer, the opening ratio is high, and the liquid crystal display described in the first aspect of the first transparent insulating substrate is formed of a metal layer. a scan that has an insulating layer on its side

J. More than one gate insulating layer and no semiconductor layer are formed on one or more gate electrode electrodes formed on the opposite electrode.  Forming a wide aspect ratio gate insulating layer on the first semiconductor layer,  In an area other than the image display unit, Forming an opening on the scanning line,  On a portion of the above protective insulating layer portion, On the first first transparent insulating substrate, A line formed of a layer containing an impurity and a second metal layer of an upper layer or more is formed) • a drain wiring (pixel electrode), And an electrode terminal including the first semiconductor layer and the second semiconductor layer and the second gold scan line, The electrode terminal of the signal line formed by the line other than the image display unit,  In addition to the above-mentioned electrode terminals of the signal line, the pixel electrode and the alignment treatment in the thick transparent resin patent range are also very suitable.  Display device, The first line above the same layer and the opposite electrode edge layer, And a gate insulating layer semiconductor layer and a second semiconductor layer source wiring which are finely protected on the gate-containing impurity-containing first electrode (the region formed by the peripheral layer of the opening portion is formed by the partial signal line -26- (24) 1300873 is characterized by a photosensitive organic insulating layer.  By this, Forming a protective insulating layer on the channel between the source and the drain To protect the channel, At the same time, a photosensitive organic insulating layer is formed on the surface of the signal line to impart a passivation function. Forming a gate insulating layer on the opposite electrode, Therefore, the same effects as those of the liquid crystal display device described in claim 7 can be obtained. and, An IPS type liquid crystal display device having electrode terminals having the same metallicity as the signal lines can be obtained.  The liquid crystal display device described in claim 12, Similarly, one or more first metal layers are formed on one main surface of the first transparent insulating substrate, And a scanning line and an opposite electrode having an insulating layer on the side thereof form one or more gate insulating layers on the opposite electrode; And forming more than one gate insulating layer and the first semiconductor layer without impurities on the gate electrode,  Forming a protective insulating layer having a wider width than the gate electrode on the first semiconductor layer,  In an area other than the image display unit, Opening a gate insulating layer on the scan line,  On one of the above protective insulating layers, On the first semiconductor layer and on the first transparent insulating substrate, Forming a source wiring (signal line) • a drain wiring (pixel electrode) composed of a layer of an impurity-containing second semiconductor layer and one or more anodizable metal layers; And an electrode terminal forming a scan line formed of an anodizable metal layer, comprising a first semiconductor layer and a second semiconductor layer including the periphery of the opening; And an electrode terminal for forming a signal line composed of one of the signal lines in the -27-1300873 (25) region other than the key display portion,  In addition to the electrode terminals of the above signal lines, An anodized layer is formed on the surface of the source/drain wiring.  By this, Forming a protective insulating layer on the channel between the source and the drain To protect the channel, At the same time, on the surface of the signal line and the surface of the drain, an anodic oxide layer (Ta20) or aluminum oxide (ai2〇3) which is an insulating anodized layer is formed. To impart a passivation function, Forming a gate insulating layer on the counter electrode, Therefore, the same effects as those of the liquid crystal display device described in claim 7 can be obtained. and, An IPS type liquid crystal display device having an electrode terminal having the same metallicity as the signal line can be obtained.  Patent Document No. 13 of the patent application, Similarly, one or more first metal layers are formed on one main surface of the first transparent insulating substrate, And a scanning line and an opposite electrode having an insulating layer on the side thereof form one or more gate insulating layers on the opposite electrode; And forming more than one gate insulating layer and the first semiconductor layer without impurities on the gate electrode,  Forming a protective insulating layer having a wider width than the gate electrode on the first semiconductor layer,  On one of the above protective insulating layers, On the first semiconductor layer and on the first transparent insulating substrate, a source wiring (signal line) formed by laminating a second semiconductor layer containing impurities and a second metal layer of ~ or more layers, Bungee wiring (pixel electrode),  In an area other than the image display unit, On the first transparent insulating substrate, 28-(26) 1300873 is formed with a transparent insulating layer having an opening on the electrode terminal forming region of the scanning line and the electrode terminal of the signal line formed by the partial signal line.  An electrode terminal that exposes a part of the scanning line and the signal line of the electrode terminal as the scanning line in the opening portion is characterized.  By this, Providing a passivation insulating layer composed of a transparent insulating layer on the active substrate, If a thick transparent resin is used in the transparent insulating layer, Very easy to align, Not only can the IPS type liquid crystal display device with high image quality be obtained. The same mask can also be used to process the opening portion of the gate insulating layer on the scan line and the opening portion of the passivation insulating layer on the gate electrode. Reduce the number of projects, The liquid crystal display device can be fabricated using only three photomasks.  Patent Document No. 14 of the patent application, Similarly, one or more first metal layers are formed on one main surface of the first transparent insulating substrate, And the scanning line and the opposite electrode having the insulating layer on the side thereof form an insulating layer on the opposite electrode,  Forming a gate insulating layer on the gate electrode, a first semiconductor layer free of impurities and a protective insulating layer smaller than the first semiconductor layer,  Near the intersection of the scan line and the signal line, A first semiconductor layer and a protective insulating layer which are smaller than the gate insulating layer and the gate insulating layer are formed on the vicinity of the intersection of the counter electrode and the signal line and in the vicinity of the intersection of the counter electrode and the pixel electrode,  At the intersection of the scan line and the signal line, a first semiconductor layer and a second semiconductor layer containing impurities are formed on the gate insulating layer at the intersection of the counter electrode and the signal line and at the intersection of the counter electrode and the pixel electrode, Forming a second semiconductor layer containing impurities on the protective layer of the protective layer 29, (27) 1300873,  On a portion of the protective insulating layer on the gate electrode, On the first semiconductor layer and on the first transparent insulating substrate, Forming a source wiring (signal line) composed of a second semiconductor layer containing impurities and one or more anodized metal layers, • a drain wiring (pixel electrode), And an electrode terminal of a signal line composed of a part of signal lines, And an electrode terminal including a scanning line formed by laminating a second semiconductor layer containing impurities and one or more anodizable metal layers on the first transparent insulating substrate in a region other than the image display portion;  In addition to the above electrode terminals, An anodized layer is formed on the surface of the source/drain wiring.  By this, Forming a protective insulating layer on the channel between the source and the drain To protect the channel, At the same time, molybdenum pentoxide (Ta205) or aluminum oxide (Al2〇3), which is an insulating anodized layer, is formed on the surface of the signal line and the drain wiring. To impart a passivation function, An anodized layer is also formed on the scan line and the counter electrode. Therefore, the same effects as those of the liquid crystal display device described in claim 7 can be obtained. and, An IPS type liquid crystal display device having electrode terminals having the same metallicity as the signal lines can be obtained.  The liquid crystal image display device described in claim 15 of the patent application,  The invention is characterized in that the insulating layer formed on the side of the scanning line is an organic insulating layer. 6, 7, 8, 9, 10. 1 1. Liquid crystal display devices as recorded in items 12 and 13.  By this, Can be free from the material or composition of the scan line, An organic -30- (28) 1300873 insulating layer can be formed on the side of the scanning line by electro-plaling. And can use halftone exposure technology, The forming process of the scanning line and the formation of the etch stop layer are continuously processed by a mask.  The liquid crystal image display device described in claim 16 of the patent application,  For example, if the scope of patent application is 5th. 6 ' 1 0, 1 1. 1 2 The liquid crystal display device recorded in 1 3 and 1 4, among them, The first metal layer is composed of an anodizable metal layer. The insulating layer formed on the side of the scanning line is an anodized layer.  By this, An anodic oxide layer can be formed on the side of the scan line by anodization. And halftone exposure technology is available. The forming process of the scanning line and the formation of the etch stop layer are continuously processed by a mask.  Patent Application No. 17 is a method of manufacturing a liquid crystal display device as recited in claim 5, It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  More than one layer of metal, More than one layer of gate insulation, a first amorphous germanium layer containing no impurities and a project for protecting the insulating layer;  A process of forming a photosensitive resin pattern having a thickness larger than that of other regions on the protective insulating layer forming region corresponding to the scanning line;  The protective insulating layer is sequentially etched by using the photosensitive resin pattern as a mask, The first amorphous layer, a gate insulating layer and a first metal layer;  Reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer having a wider width than the gate electrode on the gate electrode to expose the first amorphous germanium layer;  -31 - (29) 1300873 A process of forming an insulating layer on the side of the scanning line after the above-mentioned photosensitive resin pattern having a reduced film thickness is removed;  a process of covering a second amorphous sand layer containing impurities on the entire surface;  In an area other than the image display unit, Forming an opening in the electrode terminal forming region of the scanning line and selectively removing the second amorphous germanium layer in the opening portion, a first amorphous germanium layer and a gate insulating layer to expose a portion of the scan line;  In a manner partially overlapping the above protective insulating layer, Formed by a second non-crystalline layer, Source (signal line) and drain wiring of one or more layers of anodizable metal layers And including the opening portion to form a second amorphous layer, Engineering of electrode terminals of scan lines formed by lamination of one or more layers of anodizable metal layers;  a pixel electrode having a transparent conductive position formed on one of the first transparent insulating substrates and the drain wiring, And in the area other than the image display section, Forming a transparent conductive electrode terminal on the signal line, And a process of forming a transparent conductive electrode terminal on the electrode terminal of the scanning line; And a photosensitive resin pattern formed using the selection pattern of the pixel electrode and the electrode terminal as a mask, Protecting the transparent conductive pixel electrode and the transparent conductive electrode terminal, At the same time, anodizing the source and drain wiring works.  By this, A mask can be used to process the formation of the etch stop layer and the formation of the scan lines. To achieve a reduction in the number of lithography etching projects.  and, The etch stop layer is formed by self-integration with the gate electrode. The side of the scan line is provided with an insulating layer other than the gate insulating layer. This allows the scan of the -32-1300873 (30) line and the signal line to form an intersection. This is a feature common to the method of the present invention. and, When the pixel electrode is formed, By applying source and drain wiring to anodization, It can also reduce unnecessary manufacturing engineering when the passivation insulating layer is formed. result, A four-mask can be used to fabricate a TN type liquid crystal display device.  Patent Application No. 18 is a method of manufacturing a liquid crystal display device as described in claim 6 of the patent application scope. It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  More than one layer of the first metal layer, More than one layer of gate insulation, a first amorphous ruthenium layer free of impurities and a protective insulating layer;  Corresponding to the scan line, A process of forming a photosensitive resin pattern having a thicker film thickness on a protective insulating layer forming region than other regions;  Using the above photosensitive resin pattern as a mask, Etching the above protective insulating layer in sequence, The first amorphous layer, a gate insulating layer and a first metal layer;  a process of reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer having a wider width than the gate electrode on the gate electrode to expose the first amorphous germanium layer;  After the photosensitive resin pattern having a reduced film thickness is removed, a process of forming an insulating layer on the side of the scanning line;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  Forming a second amorphous germanium layer in such a manner as to partially overlap the above protective insulating layer a source (signal line) and a drain wiring formed by laminating one or more second metal layers;  -33- (31) 1300873 is formed on the first transparent insulating substrate on the drain wiring, And an electrode terminal forming region of the scanning line in a region other than the image display portion, And a process of having a transparent insulating layer with an opening on the electrode terminals of the signal lines formed by the partial signal lines;  a process of removing a gate insulating layer on an electrode terminal forming region of the scan line to expose a portion of the scan line; And a transparent conductive pixel electrode including an opening in the drain wiring. A process formed on the above transparent insulating layer.  By this, A mask can be used to process the formation of the etch stop layer and the formation of the scan lines. To achieve a reduction in the number of lithography etching projects.  and, As in the conventional example, The formation of the opening portion of the passivation insulating layer also serves as a connection forming process for the connection of the scanning lines. Manufacturing engineering is reduced, Therefore, a four-mask can be used to fabricate a TN type liquid crystal display device. and, If a thick transparent resin layer is used for the transparent insulating layer belonging to the passivation insulating layer, A TN type liquid crystal display device having a high aperture ratio can be obtained.  Patent Application No. 19 is a method of manufacturing a liquid crystal display device as recited in claim 7 of the patent application scope, It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  Transparent conductive layer, First metal layer, More than one layer of gate insulation, a first amorphous tantalum layer containing no impurities and a protective insulating layer;  Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, a process of forming a photosensitive resin pattern having a film thickness on a protective insulating layer forming region that is thicker than other regions;  Using the above photosensitive resin pattern as a mask, Sequentially engraved protective insulation -34- (32) 1300873 layers, The first amorphous layer, Gate insulation layer, Engineering of the first metal layer and the transparent conductive layer;  a process of reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer having a wider width than the gate electrode on the gate electrode to expose the first amorphous germanium layer;  a process of forming an insulating layer on the side of the scanning line after the photosensitive resin pattern having a reduced film thickness is removed;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  A photosensitive resin pattern having an opening is formed on the pixel electrode and the region other than the image display portion on the analog electrode terminal of the scanning line and the signal line, And selectively removing the second amorphous germanium layer in the opening portion, a second amorphous layer, a gate insulating layer and a first metal layer, The project of exposing the transparent conductive pixel electrode and the electrode terminal; And after coating more than one layer of the second metal layer, In a manner partially overlapping the above-mentioned protective insulating layer composed of a laminate of the second amorphous germanium layer and the second metal layer, a source wiring (signal line) having an electrode terminal including a signal line and having a photosensitive organic insulating layer on a surface thereof, And a process of forming a drain wiring including a pixel electrode and having a photosensitive organic insulating layer on the surface thereof.  By this, Use a reticle, Reduction of the number of lithography processes for processing the pixel electrodes and the scan lines, And using a mask, The reduction of the number of lithography processes for forming the etch stop layer and the formation of the scan line can be simultaneously achieved. and, When source/drain wiring is formed, Selectively forming a photosensitive organic insulating layer only on the source/drain wiring, In this way -35- 1300873 (33), It can also reduce unnecessary manufacturing engineering when the passivation insulating layer is formed. The result, A three-mask can be used to fabricate a TN type liquid crystal display device.  Patent Application No. 20 is a method of manufacturing a liquid crystal display device as recited in claim 8 of the patent application. It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  Transparent conductive layer, First metal layer, More than one layer of gate insulation, a first amorphous tantalum layer containing no impurities and a protective insulating layer;  a process of forming a photosensitive resin pattern having a thickness larger than that of other regions on the protective insulating layer forming region corresponding to the scanning line and the pixel electrode;  Using the above photosensitive resin pattern as a mask, And sequentially etching: Protective insulation, The first amorphous layer, Gate insulation layer, Engineering of the first metal layer and the transparent conductive layer;  a process of reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer having a wider width than the gate electrode on the gate electrode to expose the first amorphous germanium layer;  a process of forming an insulating layer on the side of the scanning line after the photosensitive resin pattern having a reduced film thickness is removed;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  Selectively removing the second amorphous germanium layer in the opening portion by forming a photosensitive resin pattern having an opening on the dummy electrode terminal of the scan line on the pixel electrode and the region other than the image display portion. First amorphous layer, a gate insulating layer and a first metal layer, And exposing the transparent conductive pixel electrode and part of the scanning line;  -36- 1300873 (34) After being coated with more than one second metal layer, the formation:  a source wiring (signal line) that overlaps the protective insulating layer and a drain wiring in which the portion of the dad overlaps the protective insulating layer, Dad, the electrode terminal of the scanning line of the conductive part of the scanning line, A signal layer composed of a part of signal lines in a region other than the display portion and a photosensitive layer pattern having a thicker film thickness on the signal line than other regions;  Taking the above-mentioned photosensitive organic insulating layer pattern as a mask,  a second metal layer above one layer, a second amorphous layer and a layer of tantalum, And forming a scan line, Electrode terminal of signal line and wiring work; And reducing the film thickness of the photosensitive organic insulating layer pattern,  line, The electrode terminal of the signal line and the work of the drain wiring.  By this, Use a reticle, Processing of pixel electrodes, the reduction of the number of lithography engraving projects, And using a mask, There is less lithography etching of the formation of the layer and the formation of the scanning line. Can be achieved at the same time. and, Source•bungee wiring type halftone exposure technology, Selectively leaving the insulating layer only on the signal line, In this way, It can also reduce the formation of passivation insulation layers, result, Three reticle can be used to make the TN device.  Patent Application No. 21 is a method of manufacturing a liquid crystal display device as claimed in the patent application. Characterized by having at least one major surface of the first transparent insulating substrate,  The portion and the above-mentioned pixel-receiving electrode have the above-mentioned transparency. The electrode is selectively removed at the electrode end of the image line to selectively remove the first amorphous source and the drain to expose the scanning and scanning lines. Time, The type of liquid crystal display that is not necessary when using photosensitive organic is recorded in the 9th item:  •37- (35) 1300873 transparent conductive layer, First metal layer, Gate insulation layer, The first amorphous sand layer containing no impurities and the engineering of protecting the insulating layer;  Corresponding to the scan line and the pixel electrode, a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the protective insulating layer forming region;  The above-mentioned photosensitive resin pattern is used as a mask. Protect the insulation layer, The first amorphous layer, Gate insulation layer, Engineering of the first metal layer and the transparent conductive layer;  Reducing the film thickness of the above-mentioned photosensitive resin pattern, And expose the protective insulation layer;  Leaving a protective insulating layer on the gate electrode that is wider than the gate electrode, And exposing the first amorphous layer;  After the photosensitive resin pattern having the above film thickness is removed, a process of forming an insulating layer on the side of the scanning line;  a process of coating a second amorphous layer containing impurities on the entire surface;  On the pixel electrode and the area other than the image display unit, The photosensitive resin pattern having an opening formed in the dummy electrode terminal of the scanning line selectively removes the second amorphous layer in the opening, First amorphous layer, a gate insulating layer and a first metal layer, a project in which a transparent conductive pixel electrode and a divided scan line are exposed;  After coating more than one layer of anodizable metal, Forming a source wiring (signal line) partially overlapping the protective insulating layer, a drain wiring including a pixel electrode forming portion overlapping the above protective insulating layer, a partial scan line including the above transparent conductivity forms an electrode terminal of the scan line, In an area other than the image display section, The electrode terminal corresponding to the signal line -38- (36) 1300873 composed of a part of the signal line forms a photosensitive resin pattern thicker than a predetermined area on the electrode terminal of the scanning line and the signal line;  Using the above photosensitive resin pattern as a mask, Selectively anodized metal layer, a second amorphous layer and a layer of enamel, And forming an electrode terminal and a source line of the scan line and the signal line;  Reducing the film thickness of the above-mentioned photosensitive resin pattern, The project that exposes the source wiring; And protecting the above electrode terminals, At the same time anodizing source • 汲 engineering.  By this, Use a reticle, Processing the reduction of the number of pixel electrodes and lithography engineering, And using a mask, There are few lithography etching processes for the formation of the processing layer and the formation of the scanning line. Can be achieved at the same time. and, The pass between the source and the drain forms a protective insulating layer to protect the channel. At the same time, the source and the pole are matched, Using halftone exposure technology, Select an anodized layer on the source and drain wiring. In this way, It also reduces the number of manufacturing processes necessary to form passivation. result, A three-mask can be used to make a crystal display device.  Patent Application No. 22 is a method of manufacturing a liquid crystal display device as set forth in Patent Application No. 1, It is characterized by:  At least on one main surface of the first transparent insulating substrate, According to the first metal layer above one layer, a layer of more than one gate insulating layer of the first amorphous germanium layer and a protective insulating layer;  The film thickness is greater than the cul-de-sequence of the scan line of the first amorphous pole drain electrode and the drain wire. When the line is formed, the edge layer is not covered by the TN type liquid.  , No miscellaneous -39- (37) 1300873 corresponds to the scan line, A process of forming a photosensitive resin pattern having a thicker film thickness on a protective insulating layer forming region than other regions;  Using the above photosensitive resin pattern as a mask, Sequential etching: Protect the insulation layer, The first amorphous layer, a gate insulating layer and a process of the first metal layer;  a process of reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer having a wider width than the gate electrode on the gate electrode to expose the first amorphous germanium layer;  After the photosensitive resin pattern having a reduced film thickness is removed, a process of forming an insulating layer on the side of the scanning line;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  In a manner partially overlapping the above protective insulating layer, Forming a source (signal line) • drain wiring composed of a laminate of a second amorphous germanium layer and one or more second metal layers;  On the bungee wiring, On the electrode terminal forming region of the scanning line in the region other than the image display portion and on the electrode terminal of the signal line composed of the partial signal lines, a transparent resin layer having openings, respectively a process formed on the second transparent insulating substrate;  a process of removing a gate insulating layer on an electrode terminal forming region of the scan line to expose a portion of the scan line; And a conductive pixel electrode including the opening on the above-described drain wiring, And a counter electrode comprising a conductive line on the scan line and the signal line, The work on the above transparent resin layer is formed.  -40 - (38) 1300873 By this, A reticle can be used to handle the formation of the scan line and the formation of the uranium engraved layer. In order to achieve the reduction of the number of lithography engraving projects. and, As in the conventional example, The forming process of the opening portion of the passivation insulating layer also serves as a connection forming process for connecting the scanning lines. Manufacturing engineering is also reduced, Therefore, an IPS type liquid crystal display device can be fabricated using four masks.  Patent Application No. 23 is a method of manufacturing a liquid crystal display device as recited in claim 11 of the patent application. It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  More than one layer of the first metal layer, More than one layer of gate insulation, a first amorphous ruthenium layer free of impurities and a protective insulating layer;  Corresponding to the scan line and the counter electrode, a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the protective insulating layer forming region;  Using the above photosensitive resin pattern as a mask, Sequential etching: Protect the insulation layer, The first amorphous layer, a gate insulating layer and a process of the first metal layer;  a process of reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer;  Leaving a protective insulating layer on the gate electrode that is wider than the gate electrode, And exposing the first amorphous layer;  After the photosensitive resin pattern having a reduced film thickness is removed, a process of forming an insulating layer on a side of a scanning line and a counter electrode;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  In an area other than the image display unit, Forming an opening in the electrode terminal forming region of the scanning line, Selectively removing the second amorphous -41 - (39) 1300873 layer in the opening portion, a first amorphous germanium layer and a gate insulating layer, a project that exposes part of the scan line;  After covering more than one layer of the second metal layer, A source wiring (signal line) and a drain wiring (pixel electrode) which are partially overlapped with the above-mentioned protective insulating layer are formed, An electrode terminal including the opening portion to form a scanning line, An electrode terminal of a signal line composed of a part of signal lines is formed in a region other than the image display portion, Forming a photosensitive organic insulating layer pattern having a film thickness on the signal line that is thicker than other regions;  Taking the above-mentioned photosensitive organic insulating layer pattern as a mask, Selective removal of the second metal layer, a second amorphous germanium layer and a first amorphous germanium layer, The electrode terminals that form the scan lines and signal lines and the source/drain wiring work: And reducing the film thickness of the photosensitive organic insulating layer pattern, The project of the electrode terminals and the drain wiring of the scanning line and the signal line is exposed.  By this, A mask can be used to handle the formation of the etch stop layer and the formation of the scan lines. To achieve a reduction in the number of lithography engineering projects. and, When source/drain wiring is formed, Using halftone exposure technology,  Selectively leaving the photosensitive organic insulating layer only on the signal line, In this way, It also reduces unnecessary manufacturing engineering when forming a passivation insulating layer. result,  A three-mask can be used to fabricate a TN type liquid crystal display device.  Patent Application No. 24 is a method of manufacturing a liquid crystal display device as recited in claim 12 of the patent application. It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  More than one layer of the first metal layer, More than one layer of gate insulation, No impurity 42_ (40) 1300873 quality first amorphous enamel layer and protective insulation layer works;  Corresponding to the scan line and the counter electrode, And a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the protective insulating layer forming region;  Using the above photosensitive resin pattern as a mask, Sequential etching: Protect the insulation layer, The first amorphous layer, a gate insulating layer and a process of the first metal layer;  Reducing the film thickness of the photosensitive resin pattern having reduced the film thickness described above, And the project of revealing the protective insulation layer;  Leaving a protective insulating layer on the gate electrode that is wider than the gate electrode, And exposing the first amorphous layer;  After the above photosensitive resin pattern is removed, a process of forming an insulating layer on a side of a scanning line and a counter electrode;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  In an area other than the image display unit, Forming an opening in the electrode terminal forming region of the scanning line, Selectively removing the second amorphous germanium layer in the opening, a first amorphous germanium layer and a gate insulating layer, a project that exposes part of the scan line;  After coating more than one layer of anodizable metal, A source wiring (signal line) and a drain wiring (pixel electrode) in which the corresponding portion overlaps with the protective insulating layer are formed, An electrode terminal including the opening portion forming a scanning line, The area outside the image display portion corresponds to the electrode terminal of the signal line composed of the partial signal lines, a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the electrode terminals of the scanning lines and the signal lines;  Using the above photosensitive resin pattern as a mask, Selective removal of the anode •43- (41) 1300873 oxidized metal layer, a second amorphous germanium layer and a first amorphous germanium layer' to form electrode terminals of the scan lines and signal lines and a source/drain wiring;  Reducing the film thickness of the above-mentioned photosensitive resin pattern, The project of exposing the source and the bungee wiring; And protecting the above electrode terminals, At the same time anodizing the source and drain wiring works.  By this, A mask can be used to handle the formation of the etch stop layer and the formation of the scan lines. To achieve a reduction in the number of lithography engineering projects. and, On the channel between the source and the bungee, A protective insulating layer can be formed to protect the channel, At the same time, when the source/drain wiring is formed, Using halftone exposure technology, Selectively forming an anodized layer on the source/drain wiring,  In this way, It can also reduce unnecessary manufacturing engineering when forming a passivation insulating layer. result, It is possible to manufacture a TN type liquid crystal display device using three photomasks.  Patent Application No. 25 is a method of manufacturing a liquid crystal display device as recited in claim 13 of the patent application. It is characterized by:  At least on one main surface of the first transparent insulating substrate, Suddenly covered:  More than one layer of the first metal layer, And more than one gate insulation layer, a first amorphous tantalum layer containing no impurities and a protective insulating layer;  Corresponding to the scan line and the counter electrode, a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the protective insulating layer forming region;  Using the above photosensitive resin pattern as a mask, Sequential etching: Protect the insulation layer, The first amorphous layer, a gate insulating layer and a process of the first metal layer;  -44 - (42) 1300873 The process of reducing the film thickness of the above-mentioned photosensitive resin pattern to expose the protective insulating layer;  A wide gate electrode is left on the gate electrode to further protect the insulating layer.  And exposing the first amorphous layer;  a process of forming an insulating layer on a side surface of a scanning line and a counter electrode after the photosensitive resin pattern having a reduced film thickness is removed;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  In a manner partially overlapping the above protective insulating layer, Forming a source wiring (signal line) • a drain wiring (pixel electrode) source and a drain wiring formed by laminating a second amorphous germanium layer and one or more second metal layers;  In an area other than the image display unit, Forming a transparent insulating layer having an opening on the electrode terminal forming region of the scanning line and the electrode terminal of the signal line composed of the partial signal line on the first transparent insulating substrate; And removing the gate insulating layer on the electrode terminal forming region of the scanning line, And the project of exposing part of the scan line.  By this, Use a reticle, Processing the formation of the etch stop layer and the formation of the scan line, To achieve a reduction in the number of lithography etching projects. And, As in the conventional example, Forming an opening for the passivation insulating layer, The connection forming process for connecting the scanning lines can also be reduced. Therefore, the IPS type liquid crystal display device can be fabricated by using three masks.  Patent Application No. 26 is a method of manufacturing a liquid crystal display device as recited in claim 14 of the patent application, which is characterized by having:  -45- (43) 1300873 at least on one main surface of the first transparent insulating substrate, Sequential etching:  More than one layer of the first metal layer, More than one layer of gate insulation, a first amorphous ruthenium layer free of impurities and a protective insulating layer;  Corresponding to the scan line and the counter electrode, Formed on the gate electrode, On the intersection of the scan line and the signal line, a project of a photosensitive resin pattern having a thicker film thickness than the other regions on the intersection of the counter electrode and the signal line and at the intersection of the counter electrode and the pixel electrode;  Using the above photosensitive resin pattern as a mask, Sequential etching: Protect the insulation layer, The first amorphous layer, a gate insulating layer and a process of the first metal layer;  a process of forming an insulating layer on a side of a scan line and a counter electrode;  Reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer,  Removing the protective insulating layer on the scan line and the counter electrode, The first amorphous layer, Gate insulation layer, And exposing the scanning line and the opposite electrode;  And further reducing the film thickness of the above-mentioned photosensitive resin pattern having a reduced film thickness, Leaving a protective insulating layer on the gate electrode that is wider than the gate electrode, And exposing the first amorphous layer;  Engineering of coating a second amorphous layer containing impurities on the entire surface;  After coating more than one layer of anodizable metal, Forming a source wiring (signal line) partially overlapping the protective insulating layer, Bungee wiring (pixel electrode), The electrode terminal of the scanning line of the partial scanning line is included in a region other than the image display portion, Corresponding to a signal line formed by a part of signal lines forming an electrode terminal, a process of forming a photosensitive resin pattern having a film thickness on the electrode terminal that is thicker than other regions;  -46- (44) 1300873 using the above-mentioned photosensitive resin pattern as a mask, Selectively removing the oxidized metal layer and the second amorphous germanium layer and the first amorphous germanium to form scan electrode and signal line electrode terminals and source/drain configuration;  a process of reducing the film thickness of the photosensitive resin pattern to expose the source and the line; And protecting the above electrode terminals, At the same time anodizing the source and the drain of the opposite electrode.  By this, Use a reticle, Processing the formation of the uranium engraving layer and the formation of the scan line, And the reduction in the number of engineering works at the time of exposing the scanning line is achieved. In addition, Between the source and the bungee, A protective insulating layer can be formed to protect the channel, At the same time, when the source•汲 is formed, Using halftone exposure technology, Forming an anodized layer on the source and drain electrodes, In this way, It also reduces the unnecessary manufacturing work when forming a blunt layer. result, Use two masks, That is, an IPS type liquid crystal display device.  Article 27 of the scope of application for patents is as for the scope of patent application No. 1 7 19  20,  twenty one ,  twenty two ,  twenty three ,  twenty four ,  25,  The manufacturing method of the liquid device described in item 26, among them, An insulating layer of insulation formed on the side of the scanning line, And formed by electroplating (elechoplahing).  By this, Regardless of the material or composition of the scan line, The plating method forms an organic insulating layer on the side of the scanning line. And semi-light technology can be used. With a mask, The scanning line forming process and the stop layer forming process are continuously processed.  Anode layer, The wiring of the wire and the wiring of the micro-etched channel are selectively insulated and can be fabricated. 1 8,  The crystal display layer is etched by electro-optic g-external etching -47- (45) 1300873 Patent application scope 28 item is as claimed in the patent scope 1 8,  twenty two, twenty three, twenty four, 25, A method of manufacturing a liquid crystal display device according to item 26, among them, The first metal layer is composed of an anodizable metal layer.  The insulating layer formed on the side of the scanning line is formed by anodization.  By this, An anodic oxide layer can be formed on the side of the scan line by anodization. And halftone exposure technology is available. With a mask, The scanning line forming process and the uranium engraving stop layer formation process are continuously processed.

[Embodiment] [Embodiment of the Invention] An embodiment of the present invention will be described with reference to Figs. 1 to 22 . Fig. 1 is a plan view showing a semiconductor device (active substrate) for a display device according to a first embodiment of the present invention, and Fig. 2 shows AA/line and B-B/line and C-C/line on the first drawing. Sectional view of the manufacturing process. Similarly, the second embodiment is a third diagram and a fourth diagram, the third embodiment is a fifth diagram and a sixth diagram, and the fourth embodiment is a seventh diagram and an eighth diagram. The fifth embodiment is In the ninth and tenth drawings, the sixth embodiment is in Figs. 11 and 12, the seventh embodiment is in the thirteenth and fourteenth, and the eighth embodiment is in the fifteenth and fifteenth embodiments. 6 is a ninth embodiment which is a 17th view and a 18th figure. The tenth embodiment is a plan view and a cross-sectional view of a manufacturing process of the active substrate, respectively, in the 19th and 20th. In addition, the same portions as those of the conventional examples are denoted by the same reference numerals to omit the detailed description. (First Embodiment) • 48-(46) l3〇0873 The first embodiment is the same as the conventional example. First, a vacuum film forming apparatus such as SPT is used on one main surface of the glass substrate 2 to coat the film. An alloy such as Cr, Ta, Mo, or the like having a thickness of about 0.1 to 3·3 vm or a telluride as the first metal layer. As will be understood from the following description, when the present invention selects the organic insulating layer as the insulating layer formed on the side of the gate insulating layer, the scanning line material is hardly limited, however, the anodized layer is selected as the insulating layer formed on the side of the gate insulating layer. In the case of a layer, the anodized layer must have an insulating property. In consideration of the high resistance of the Ta monomer and the lack of heat resistance of the A1 monomer, in order to achieve a low resistance of the scanning line, the composition of the scanning line can be selected from A1. A single layer structure such as (Zr, Ta, Nd) alloy, or a laminated structure of Al/Ta, Ta/Al/Ta, Al/AL (Ta, Zr, Nd) alloy. Further, A1 (Ta, Zr, Nd) means that an A1 alloy having high heat resistance such as Ta, Zr or Nd of several % or less is added. Next, using a PCVD apparatus, the entire surface of the glass substrate 2 is sequentially coated with a film thickness of, for example, 0.3//11] and 0.05//111'0.1 "111, respectively: a first SiNx layer as a gate insulating layer. 30. The first amorphous germanium layer 31 to which the channel of the insulating gate type transistor containing almost no impurities belongs, and the third thin layer of the second SiNx layer 32 to protect the channel as the insulating layer, and then, for example, 1(a) and 2(a), the film thickness of the region 8 1 A on the gate electrode 1 1 A which forms the protective insulating layer forming region by the halftone exposure technique is, for example, 2 // m. The photosensitive resin pattern 8 1 A, 8 1 B having a thickness corresponding to the film thickness l//m on the scanning line 1 1 and the region 81B of the storage capacitor line 16 is a photosensitive resin pattern 8 1 A, 8 1 B as a mask selectively removes the channel protective layer 3, the first amorphous germanium layer -49 - (47) 1300873 3 1, the gate insulating layer 30, and the first metal layer to expose the glass substrate 2. Due to the width of the line on the scanning line 1, the relationship between the resistance 値 and the narrowest is generally 10//m or more, so the reticle used to form the 81B (intermediate adjustment area) or its processing size Precision management can be easily implemented. Then, when the film thickness of the photosensitive resin patterns 8 1 A and 8 1 B is reduced by 1 μm or more by means of an ashing means such as oxygen plasma, the photosensitive resin pattern 81B disappears, and the second SiNx layers 32A and 32B are exposed. (not shown), the photosensitive resin pattern 8 1 C can be selectively formed only on the protective insulating layer forming region. Since the photosensitive resin pattern 8 1 C (black area), that is, the pattern width of the channel protective layer, is the size of the source/drain wiring and the alignment accuracy of the mask, the source/drain wiring is set to 4 Up to 6 //m, when the alignment accuracy is set to ±3//m, the minimum is also 10 to 12//m, and the dimensional accuracy requirements are not strict. However, when the photoresist pattern 81A is changed to 8 1 C, when the film thickness isotropic of the photoresist pattern is reduced by 1 # m, the size is not only reduced by 2 // m, but when the subsequent source/drain wiring is formed, the light is formed. The aligning accuracy of the hood is reduced by l//m, and ±2//m is formed. The latter requirement is stricter than the former in the process. Therefore, in the above oxygen plasma treatment, when the change in the pattern size is suppressed, it is preferable to enhance the anisotropy. Specifically, it is preferable to use an RIE (Reactive Ion Etching) method, an ICP (Inductive Coupled Plasama) method having a high-density plasma source, or a TCP (Transfer Coupled Plasama) method. Alternatively, it is desirable to estimate the dimensional change amount of the photoresist pattern, to pre-design the pattern size of the photoresist pattern 8 1 A to be large, or to make the pattern of the photoresist pattern 81A -50-(48) 1300873 Increased exposure, development conditions, and the like of the process. Further, as shown in FIGS. 1(b) and 2(b), the second SiNx layer 32A is made thinner than the gate electrode 1 1 A with the photosensitive resin pattern 8 1C as a mask. Selectively applying etching to form a second SiNx layer 32D (uranium engraving stop layer, channel protective layer, protective insulating layer) while exposing the first amorphous germanium layer 3 1 A on the scan line 1 and the storage capacitor line 1 The first amorphous germanium layer 3 1 B on 6. The protective insulating layer forming region, that is, the size of the photosensitive resin pattern 8 1 C (黒 region), the minimum size of at least 10 // m, and the region other than the white region and the germanium region as the mask of the halftone exposure region The fabrication is easy. When compared with the channel-etched insulating gate transistor, the ON current of the insulated gate transistor is determined by the size of the channel protection insulating layer 32D, rather than by the source/drain wiring 12, 21 Process size is determined, so process management is easier. Specifically, for example, in the channel etching type, the size between the source and drain wirings is 5 ± 1 // m, and the size of the etch-stop type insulating insulating layer is 10 ± 1 // m, which is the same. Under the exposure and development conditions, the amount of change in the ON current is approximately halved. After the photosensitive resin pattern 81C is removed, as shown in FIGS. 1(c) and 2(c), an insulating layer 76 is formed on the side surface of the gate electrode 1 1 A. Therefore, as shown in Fig. 2, it is necessary to have the wiring 7 7 which is bundled in parallel with the scanning line 11 (the storage capacitor line 16 is the same, not shown here) and the plating or anode on the outer peripheral portion of the glass substrate 2. a connection pattern 7 for providing a potential during oxidation, and a film formation region of an appropriate masking method using an amorphous germanium layer 3 made of a plasma CV D and a tantalum nitride layer 30, 3 2 7 9, is limited to -51 - (49) 1300873 At least on the inner side of the connection pattern 78, at least the connection pattern 7 8 must be exposed. In the connection pattern 78, a + (positive) potential is applied by a connection means such as an alligator clip, and the glass substrate 2 is impregnated into a reaction liquid containing ethylene glycol as a main component to perform anodization, and if the scanning line 1 1 is A1 In the case of an alloy, for example, a reaction voltage of 200 V can be formed to form alumina (A1203) having a film thickness of 0.3 // m. At the time of electroplating, as shown in the monthly publication "Polymer Processing", the January 1st issue of the 002, the pentacarboxy-containing polyimine coating solution is formed to have a film thickness of 0.3/m by electroplating voltage of several v. Polyimine resin layer. Further, by forming the insulating layer 76, the pinholes of the gate insulating layer 30A on the scanning line 11 are embedded in the insulating layer of alumina or polyimide resin, so that it is also described later. The source/drain wiring 1 2, 2 1 between the interlayer short circuit is suppressed side effects. Then, using a PCVD apparatus, a second amorphous germanium layer 3 containing an impurity such as phosphorus is coated on the entire surface of the glass substrate 2 at a film thickness of, for example, about 0.05 // m, as shown in Fig. 1(d) and In the region other than the image display portion, the opening portion 63A is formed on the scanning line 1 1 in the region other than the image display portion, and the storage capacitor line 16 is bundled on the storage capacitor line 16 or in parallel. An opening 65A is formed on the electrode terminal of the electrode, and the first amorphous sand layer 33, the first amorphous layer 3 1 A, and the gate insulating layer 3 0 A ' in the opening 63A are selectively removed and selected Part of the scanning line 73, the second amorphous germanium layer 33 in the opening 65A, the first amorphous germanium layer 3 1 B, and the gate insulating layer 3 0 B are removed, and a portion of the storage capacitor line 16 is exposed. Then, in the process of forming the source/drain wiring, a vacuum film forming apparatus such as SPT is used to sequentially coat a heat-resistant metal film such as Ti-52-(50) 1300873 or Ta with a film thickness of about 0·1 V m. The layer 34 serves as a heat-resistant metal layer capable of performing anodization; and, for example, the A1 film layer 35 having a film thickness of about 3//m, as a low-resistance wiring layer which can be anodized as well; and a film thickness of about 0.1 // m, for example The heat resistant metal thin film layer 36 such as T a is used as an intermediate conductive layer which can also be anodized. Then, the source/drain wiring material composed of the three-layer thin film, the second amorphous germanium layer 3 3, and the first amorphous germanium layer are sequentially etched by a microfabrication technique using a photosensitive resin pattern. 3 1 A, 3 1 B, and the gate insulating layers 30A, 30B are exposed, and as shown in FIGS. 1(e) and 2(e), the layers formed by 34A, 35A, and 36A are selectively formed. The drain electrode 2 1 of the insulated gate type transistor and the signal line 12 2 also serve as the source electrode. In order not to bias the source/drain wirings 1, 2, 2 1 to operate, it is of course necessary to partially overlap the channel protective layer 3 2 D. Further, generally, in order to avoid side effects caused by the action of the battery, the source/drain wirings 1 2 and 2 1 are formed, and the electrode terminals 5 of the scanning lines are also formed at the same time as the partial scanning lines 73, but the electrode terminals 5 are formed. It is not necessary, so the transparent conductive electrode terminal 5 A can be directly formed in the subsequent work. In the case of the composition of the source/drain wirings 1, 2 and 2, when the limitation of the resistance 较 is loose, it is reasonable to simplify the formation of the Ta single layer. Further, in the A1 alloy to which Nd is added, the chemical potential is lowered, and the alkali is lowered. The chemical corrosion reaction with ITO in the solution is suppressed, so that the intermediate conductive layer 3 6 is not required at this time, and the laminated structure of the source/drain wirings 1 2 and 2 1 can be formed into two layers, and the source is formed. • The composition of the bungee wiring 1 2, 21 is somewhat simplified. This is the same situation when IZO is used instead of ITO. After the source/drain wirings 12 and 21 are formed, ITO, such as a film thickness of 0.1 to 0.2 /im, is coated on the entire surface of the glass substrate 2 using a vacuum-53-(51) 1300873 film device such as SPT as a transparent conductive layer. Further, as shown in Fig. 1(f), Fig. 2(f), a portion of the intermediate conductive layer 3 6 A including the drain electrode is selectively formed by the microfabrication technique, and the element electrode 2 2 is selectively formed on the glass substrate 2. At this time, in the region outside the pixel display portion, the transparent electrode layer pattern is formed on the scanning line electrode terminal 5 and the electrode terminal 6 of the partial signal line, and the transparent electrode terminals 5A and 6A are formed. As described above, the electrode terminal 5 is not formed, and the electrode terminal 5A may be formed by including the opening 63 A at this time. In addition, in the same manner as the conventional example, the transparent conductive short-circuit line 40 is provided, and the electrode terminals 5A and 6A are formed in a long line shape between the short-circuit lines 40, and the resistance is increased to form a high electrical countermeasure. resistance. Further, as shown in FIG. 1(g) and FIG. 2(g), the photosensitive resin pattern 83A which is selectively patterned using the pixel electrode 22 is used as a mask, and the light is irradiated while the source/drain wiring 1 is used. 2, 2 1 is anodized to form an oxide layer on the surface thereof. At this time, the electrode terminals 5A and 6A are protected by the photosensitive resin patterns 83B and 83C. Ta is exposed on the upper surface of the source/drain wiring 21, and a layer of Ta, Al, Ti, and the second crystalline germanium layer 33A is exposed on the side surface, and the second non-ferrous layer 33A is deteriorated into a content by anodization. The impurity ruthenium oxide layer (SiO 2 ) 66, Ti is a semiconductor titanium oxide (Ti02 ) 68, A1 is metamorphosed into an insulating oxide (AL2O3) 69, and Ta is degraded into an oxide giant (Ta205) 70 as an insulating layer. The titanium oxide layer 68 is not an insulating layer, the film thickness is extremely large, and the exposed area is also small, so that it does not pose a problem in passivation, and the direct and static oxygenation of the resistance is a 12 amorphous layer. Five thin heat • 54- (52) 1300873 Metal film layer 34A is also better to choose Ta. However, Ta differs from Ti in that it lacks the functional properties of the surface oxide layer of the absorbing substrate to make ohmic contact easier, which is to be noted. In order to form a good film anodized layer on the drain wiring 2, the simultaneous anodization of the irradiated light is an important point in the anodizing process and has been disclosed in the prior art. Specifically, if a sufficient intensity of light of about 10,000 metric lux is applied, and the leakage current of the insulated gate type transistor exceeds μ ,, the anodic oxidation of about 10 mA/cm 2 is calculated from the area of the drain electrode 21 . It can be used to obtain a current density of good film quality. Further, even if the film quality of the anodized layer on the drain wiring 21 is insufficient, the reason why sufficient reliability is generally obtained is that the driving signal applied to the liquid crystal cell is substantially a parent flow so that the counter electrode 14 and When the DC voltage component between the pixel electrodes 22 (the drain electrode 2 1 ) is reduced, the voltage of the counter electrode 14 is adjusted during the image inspection (the adjustment of the flash voltage is reduced), and the DC voltage component is reduced. In principle, as long as the insulating layer is formed in advance, the direct current component is not allowed to flow only on the signal line 12. The film thickness of each of the oxide layers of the molybdenum pentoxide 70, the alumina 69, the titanium oxide 68, and the yttrium oxide layer 66 formed by anodization is sufficient to form a passivation of about 1.1 to 〇.2//ηι. A reaction liquid such as ethylene glycol is used in which the applied voltage is also more than 100V. The anodization of the source/drain wirings 12 and 21 should be noted. Although not shown, all the signal lines 12 must be electrically connected in parallel or in series. In subsequent manufacturing processes, the parallel connection or When connected in series, not only the electrical inspection of the active substrate 2 but also the actual operation of the liquid crystal display device is hindered. -55 - (53) 1300873 As a means of releasing the electrical connection, it is quite simple to use fluoroscopy by laser irradiation or mechanical removal by scraping, but detailed description is omitted here. The reason why the pixel electrode 22 is first covered with the photosensitive resin pattern 83A is that it is necessary not only to anodize the pixel electrode 22 but also to pass through the insulating gate type transistor, and to ensure that the reaction current flowing to the gate electrode 2 1 is necessary.値 Above. Finally, the photosensitive resin patterns 83 A to 83C are removed, and the active substrate 2 (semiconductor device for display device) is completed as shown in Figs. 1(h) and 2(h). The active substrate 2 and the color filter obtained in this manner are bonded together and the liquid crystal is panelized to complete the first embodiment of the present invention. As for the configuration of the storage capacitor 15 as shown in Fig. 1(h), it is exemplified that the storage capacitor line 16 and the pixel electrode 2 2 form a plane overlap with the gate insulating layer 3 0 B (top left to bottom right). Although the configuration of the storage capacitor 15 is not limited to this, the insulating layer including the gate insulating layer 3 0 A may be interposed between the pixel electrode 22 and the front scanning line 1 1 . . Further, other configurations are also possible, but detailed description thereof will be omitted. Similarly, since the contact forming process with respect to the scanning line 11 is performed, it is easier to perform a countermeasure against static electricity by using a conductive material or a semiconductor layer other than the transparent conductive layer. In the first embodiment, since the pixel electrode forming process is performed in accordance with the source/drain wiring formation process, the yield of the source wiring and the pixel electrode is likely to be lowered, and the overlap with the scanning line is exerted. The effect of the parasitic capacitance makes the pixel electrode larger and the aperture ratio increases, which is not ideal. Then, 56-(54) 1300873', in order to increase the aperture ratio, a liquid crystal display device which uses a thick transparent resin to passivate the source/drain wiring is explained in the second embodiment. (Second embodiment)

In the second embodiment, as shown in FIGS. 3(c) and 4(c)), the insulating layer 76 is formed on the side surface of the gate electrode 1 1 A, and the same manufacturing process as in the first embodiment is performed. . Then, using a PCVD apparatus, the entire surface of the glass substrate 2 is, for example, 0. After a film thickness of about 05 m is coated with a second amorphous ruthenium layer 3 containing impurities such as phosphorus, a vacuum film forming apparatus such as SPT is used to sequentially coat a film layer 34 such as Ti or Ta having a film thickness of about As a heat resistant metal layer; and the film thickness is 0. The A1 film layer 3 5 of about 3 // m is used as a low-resistance wiring layer. Further, using a microfabrication technique, a photosensitive resin pattern is used, and a source/drain wiring material, a second amorphous germanium layer 3, and a first amorphous germanium layer composed of the three-layer thin film are sequentially left in sequence. 3 1 A ' 3 1B, and the gate insulating layers 30A, 30B are exposed. As shown in FIG. 3(d) and FIG. 4(d), a gate electrode 2 1 of an insulating gate type transistor composed of a laminate of 34A, 35A, and 36a and a source electrode are also selectively formed. Signal line 1 2. In addition, if the limitation of the resistance 较 is loose, the structure of the source and the drain can be simplified into a single layer of Ta, and the A1 alloy to which Nd is added is selected, and the laminated structure of the source/drain wirings 12 and 21 is formed. Two layers can also be constructed. Next, as shown in FIG. 3(e) and FIG. 4(e), a photosensitive polyacrylic resin 3 having excellent transparency and heat resistance of a thickness of 1·5 // m or more is applied to the entire surface of the glass substrate 2. 9 as a transparent edge layer, preferably -57- (55) 1300873 to 0. Applying a thickness of about 3//m, by selective ultraviolet irradiation using a photomask, on the surface of the drain electrode 21 and the image display portion, respectively, on a portion 5 of the scanning line and a portion of the signal line 6 Openings 62, 63, 64, and 65 are formed on the electrode terminal forming regions of the upper and lower storage capacitor lines. Further, after post-baking, the photosensitive polyacrylic resin 39 is used as a mask to selectively remove the gate insulating layers 30A and 30B in the openings 63 and 65, respectively, to expose a portion 73 (5) of the scanning line and the storage capacitor. Part of the line 7 5. In the openings 6 2, 6 4, after development, a portion 21 of the drain electrode and a portion 74 (6) of the signal line are exposed. Further, the aperture ratio is slightly lowered. However, the photosensitive polyacrylic resin 3 is not used, and the SiNx layer is used as the passivation insulating layer. Usually, the transparent insulating layer is used to form the openings 62, 63, 64, and 65 in the SiNx layer. . Finally, a vacuum film forming apparatus such as SPT is used on the entire surface of the glass substrate 2, for example, 0. a film thickness of about 1 to 2 // m, covering, for example, I TO as a transparent conductive layer, as shown in Figs. 3(f) and 4(f), by microfabrication technique, including inclusion in the opening On the polyacrylic resin 39 of the portion of the intermediate conductive layer 3 6 A of the gate electrode 2 1 in the portion 62, the pixel electrode 22 is selectively formed. Since the photosensitive polyacrylic resin 39 is thick, the pixel electrode 22 is formed as large as possible, and even if it partially overlaps the scanning line 11 or the signal line 12, image quality deterioration such as crosstalk does not occur. At this time, the transparent conductive electrode terminals 5A and 6A are formed by including the partial scanning line 73 in the opening 63 and the partial signal line 74' in the opening 64. Further, similarly to the conventional example, by providing the transparent conductive short-circuit line 40 outside the electrode terminals 5A, 6A, the electrode terminals 5 A, 6A and the short-circuit line 40 are formed. 1300873 is made into a slender line and has a high resistance, which is a countermeasure against static electricity. The active substrate 2 and the color filter obtained in this manner were bonded together and panelized to complete the second embodiment of the present invention. Regarding the configuration of the storage device, as shown in FIG. 3(e), the storage capacitor line 16 is illustrated as being interposed between the gate insulating layer 30B and the first amorphous germanium layer and the second amorphous germanium layer. The overlapping region 50 (the upper left to the lower right portion) constitutes an example of the storage capacitor 15 , and the drain electrode 2 1 and the front scan line 中介 intervene the gate insulating layer 3 〇 A to form the storage capacitor 15 'But detailed description thereof is omitted here. In the first and second embodiments, the formation precision of the so-called scanning line forming the protective layer of the engineering track (etching stop layer) is low, and the halftone exposure technique is applied to reduce the lithography etching process. Active substrate, but using a mask to process the formation of the pixel scanning line, can further reduce the engineering, using three masks as the active substrate, which will be explained in the third to fifth embodiments (the first Third Embodiment In the third embodiment, first, on one main surface of the glass substrate 2, a vacuum film forming apparatus such as SPT is coated with a film thickness of 0. 1 to 0. 2 / / m of transparent conductive layer 91, such as ITO; and film thickness is o. l to 〇. 2 / / right transparent conductive layer 91; and film thickness is 0. 1 to 0. A metal layer 92 of about 3/m. As will be understood from the subsequent description, in the third to fifth embodiments, the scanning line is a laminate of a transparent conductive layer and a metal layer, so that an insulating layer cannot be formed on the side surface of the scanning line by oxidation. Therefore, because it is through the liquid crystal 15 and 汲 3 1 B diagonal segments can also be used to pass the layer photopole and can be used to the left and right m left in the first example of anodizing -59- (57) 1300873 in the formation of organic layers Since the insulating layer is used, in the case of the scanning line material, a first metal layer which does not react with the ITO which is a transparent conductive layer, for example, a high melting point metal such as Cr, Ta or Mo, or an alloy or a telluride of these may be used. In order to achieve low resistance, if A1 is used, the single layer of A1 (Nd) alloy is the simplest, and then the layer of Ta/A1 (Zr, Hf) or Ta/AL/Ta composed of Ta is compared. To be complicated. Next, on the entire surface of the glass substrate 2, a PC VD device is used, for example, 0. 3/zm, 0. 05//m, 0. The film thickness of about 1/zm is sequentially coated: a first SiNx layer 30 as a gate insulating layer, a first amorphous germanium layer 31 as an insulating gate type transistor channel containing almost no impurities, and as a The second SiNx layer 32 of the insulating layer of the protection channel is then, as shown in FIGS. 5(a) and 6(a), a region of the protective insulating layer forming region, that is, the gate electrode 11A, is formed by a halftone exposure technique. The film thickness of 82A is, for example, 2 // m, and a film having a film thickness ratio corresponding to the scanning line 1 1 serving as the gate electrode 1 1 A, the pseudo pixel electrode 93, and the photosensitive resin pattern 82B of the analog electrode terminals 94 and 95 is formed. The photosensitive resin patterns 82A and 82B having a thickness of 1⁄4 m are thick, and the photosensitive resin patterns 82A and 82B are used as masks, and the second SiNx layer 32 (channel protective layer) and the first amorphous germanium layer 31 are added. The gate insulating layer 30 and the first metal layer 92 are also selectively removed from the transparent conductive layer 911 to expose the glass substrate 2. In the above manner, a multilayer film pattern corresponding to the scanning line 11 which is also used as the gate electrode 11A, the analog pixel electrode 93, and the analog electrode terminals 94, 95 is obtained, and then, ashing means such as oxygen plasma is used. When the film thickness of the photosensitive resin patterns 82A and 82B is reduced by 1 /μ or more, the photosensitive -60-(58) 1300873 resin pattern 82B disappears, and the second SiNx layers 33A to 33C are exposed, and the protective insulating layer can be used only. On the layer formation region, a photosensitive grease pattern 82C is selectively formed. The oxygen plasma treatment is preferably such that the mask alignment accuracy of the subsequent source/drain formation process is not reduced, and it is preferable to enhance the change in the anisotropy suppression pattern size, which is the same as the reason described above. Further, as shown in Figs. 5(b) and 6(b), the second SiNx layers 32 A to 32C are selectively etched by using the photosensitive resin pattern 82C as a mask to pattern the width wider than the gate electrode 1 1 A thin first SiNx layer 3 2D remains on the gate electrode 1 1 A while exposing the first amorphous sand layer 31A on the scan line 1 1 and the analog electrical terminal 94, respectively, and exposing on the dummy pixel electrode The first amorphous germanium layer 31B exposes the first amorphous germanium layer 3 1 C at the dummy electrode terminal 95. Next, after the photosensitive resin pattern 82C is removed, as shown in Fig. 5(c) and Fig. 6(c), a layer 76 is formed on the side surface of the gate electrode 1 1 A. Therefore, the connection pattern 78 shown in Fig. 21 is provided with a positive potential of the scanning line 11 by using a connection means such as a crocodile, but a - (negative) potential is also applied depending on the composition of the plating solution. Further, in the case of the insulating layer, a plating voltage of, for example, several V is applied to form a polyimide layer having a thickness of 〇·3 // m. The pseudo pixel electrode 93 is electrically independent, and the insulating layer 76 is not formed around the pseudo pixel electrode 93. Then, using a PCVD apparatus, the entire surface of the glass substrate 2 is, for example, 0. a film thickness of about 0 5 //m, coated with a second amorphous germanium layer 3 3 containing impurities such as phosphorus, as shown in Fig. 5 (d) and Fig. 6 (d), by using a fine of the inductive resin pattern 88 In the processing technique, when the pixel element 93 is simulated, the tree line is on the case of the hole 93 (the edge of the film can be made into a film-61-(59) 1300873 as the opening portion 38, and the area other than the image display portion The scanning line 1 has an opening 63A formed in the pseudo electrode terminal 94, and an opening 64A formed in the terminal 95 of the signal line, and the amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1 in the opening are added. A to 3 1 C and gate layers 3〇a to 30C, also selectively removing the first metal layer 92A to the electrode 5A of the scanning line formed by the transparent conductive layer and the transparent conductive layer, and the electrode terminal 6A of the signal line, drawing Prime electrode 22. Finally, using a vacuum film forming device such as SPT 'sequentially coated 0. A heat-resistant metal film layer 34 such as Ti or Ta around 1#m is used as a genus layer, and the film thickness is 〇. The A1 film layer 35 of about 3/zm serves as a resistance wiring layer. The gate insulating layer 30A is exposed by the microfabrication technique using a photosensitive resin chamber sequentially etching the second amorphous germanium layer 3 3 and the first amorphous layer 31A, as shown in Fig. 5(e) and e Illustrated, selectively formed: 汲2 1 of an insulating gate type transistor composed of a laminate of a portion 34A and 35A of the pixel electrode 22; and a portion of the electrode terminal 6 A also including a signal line and composed of 3 The insulating gate type transistor composed of 5 A laminates also serves as the source electric signal line 1 2 . The electrode terminal 5 A of the scanning line and the electrode terminal of the signal line are exposed on the glass 2 at the end of the etching of the source/drain wirings 1, 2, and 2 1 . In addition, in the case of the structure of the source/drain wirings 1, 2 and 21, if the resistance 値 is loose, the formation of a single layer such as Ta MoW can be simplified. The active substrate 2 and the color filter liquid crystal panel produced in this manner are panelized to complete the third embodiment of the present invention. The third-pole insulation 92C of the third embodiment 1 is simulated, and the electrode-thickness heat-resistant gold is the low-voltage 3 case 85-quality sand layer 6 (divided by the electrode 34A and the pole of the 6A glass substrate) e, Cr, bonding, in the example, • 62-(60) 1300873 Since the photosensitive resin pattern 8 5 is connected to the liquid crystal 'the photosensitive resin pattern 85 is not a general photosensitive material mainly composed of a novolac resin. As the resin, it is important to use a photosensitive organic insulating layer having high purity and a high heat resistance of the main component containing a propylene-based resin or a polyimide resin, and it is also possible to heat and fluidize the material according to the material. Covering the source and drain electrode wirings 1 and 2 1 side, the reliability of the liquid crystal panel can be further improved. The configuration of the storage capacitor 15 is as shown in Fig. 5(e), exemplifying The storage electrode 72 including the source/drain wirings 12, 21 and a part of the pixel electrode 22 and the protrusions provided on the front scanning line 11 interpose the gate insulating layer 30B, the first non- The crystalline germanium layer 31A and the second amorphous germanium layer form a flat layer The example of the surface overlap (the upper left to the lower right oblique line portion 5 2 ), but the configuration of the storage capacitor 15 is not limited thereto, and similarly to the first embodiment, the shared capacitor formed simultaneously with the scanning line 1 1 may be used. Between the line 16 and the pixel electrode 2, an insulating layer including the gate insulating layer 30 is interposed. The electrostatic countermeasure line 40 is composed of a transparent conductive layer connected to the electrode terminals 5 A and 6 A. Since the opening portion forming of the gate insulating layers 30A to 30C is provided, other electrostatic countermeasures can be taken. In the third embodiment, the electrode terminals of the scanning lines and the electrode terminals of the signal lines are generated. The arrangement of the devices which are all transparent conductive layers is limited, but a device and a process for releasing the restrictions can also be used, which will be explained in the fourth and fifth embodiments. (Fourth embodiment) -63- (61 1300873 The fourth embodiment is performed as shown in FIGS. 7(d) and 8(d), and is formed to be substantially the same as the third embodiment except for forming a contact project. However, the reason will be described later. It is known that the analog electrode terminal 9 5 is not necessarily required. Thereafter, In the source-drain wiring formation process, a vacuum film forming apparatus such as SPT is used to sequentially coat a heat-resistant metal thin film layer 34 such as Ti or Ta having a thickness of about 1#ΠΊ as a heat-resistant metal layer; and a film thickness of 0 . The A1 film layer 35 of 3 /i m is used as a low-resistance wiring layer. The source/drain wiring material, the second amorphous germanium layer 3 3 A, and the first amorphous sand layer 31A composed of the two thin films are sequentially etched by the microfabrication technique using the photosensitive resin pattern 86. The gate insulating layer 30A is exposed. As shown in Figs. 7(e) and 8(e), a gate electrode 2 of an insulating gate type transistor including a portion of the pixel electrode 22 and laminated by 34A and 35A is selectively formed. And a signal line 12 which also serves as the source wiring, and includes a part 5 A of the scanning line exposed when the source/drain wirings 1 2, 2 1 are formed, and the electrode terminal 5 of the scanning line and a part of the signal line The electrode terminals 6 thus formed are also formed at the same time. That is, it is not necessary to have the analog electrode terminal 915 as in the third embodiment. At this time, an important feature of the fourth embodiment is that the photosensitive resin patterns 86A and 86B are formed in advance by the halftone exposure technique, and the film thickness of the photosensitive resin patterns 86A and 86B is the film of the region 86A on the signal line 12. The film thickness is, for example, 3//m, larger than the film thickness of the 86B on the gate electrode 21, the electrode terminals 5, 6 and the storage electrode 72. 5/zm. The minimum size of 86B corresponding to the electrode terminals 5, 6 is 10/m, which is relatively large, and the mask manufacturing and finished product size management are relatively easy, and the minimum size of the area 8 6 A corresponding to the signal line 12 is 4 to 8 // m, size fine -64- (62) 1300873 degrees are relatively high, so the halftone area must form a thin slit pattern. However, as explained in the conventional example, compared with the source/drain wirings 1, 2, 2 1 formed by one exposure processing and two etching processes, since the source/drain wirings of the present invention are 1, 2, 2 1 It is formed by one exposure process and one etching process, so there are fewer factors affecting the variation of the pattern width, and the size management of the source/drain wirings 1, 2, 2 1 and the source/drain wiring 1 2, 2 1 The size management of the channel length is easier to manage the pattern accuracy than the conventional halftone exposure technique. Moreover, when compared with the channel-etched insulating gate transistor, the ON current of the insulating gate type transistor is determined to be the size of the channel protective insulating layer 32D, not the source/drain wiring 1 2, 2 1 The size of these points shows that process management is easier. After the source/drain wirings 1, 2 and 2 are formed, the film thickness of the photosensitive resin patterns 86A and 86B is reduced by an ashing means such as oxygen plasma. When 5 / m or more, the photosensitive resin pattern 86B disappears, and as shown in Fig. 7 (f) and Fig. 8 (f), the drain electrode 21 and the electrode terminals 5, 6 are exposed, and only at the signal line In the case of the photosensitive resin pattern 86C, the photosensitive resin pattern 86C is selectively formed. However, when the pattern width of the photosensitive resin pattern 86C is reduced by the oxygen plasma treatment, the upper surface of the signal line 12 is exposed, and the reliability is lowered. Enhance the anisotropy and suppress the change in the size of the pattern. Further, in the configuration of the source/drain wirings 12 and 2, if the resistance 値 is loose, the single layer such as T a, C r or Μ 。 can be simplified. The active substrate 2 and the color filter fabricated in this manner are bonded together, and the liquid crystal is panelized to complete the fourth embodiment of the present invention. In the fourth embodiment-65-(63) 1300873, since the photosensitive resin pattern 86C is connected to the liquid crystal, the photosensitive resin pattern 86C is not a general photosensitive resin containing a phenol resin as a main component, and the purity is high. It is important that the main component contains a photosensitive organic insulating layer having high heat resistance of a propylene-based resin or a polyimide resin, and may be heated and fluidized depending on the material, covering the side of the signal line 1 2 The way it is composed. At this time, the reliability of the liquid crystal panel can be further improved. The configuration of the storage capacitor 15 is as shown in Fig. 7(f), and the storage electrode 7 2 and the source electrode diodes 1 2 and 2 1 and the pixel electrode 22 are illustrated. The protrusion of the front scanning line 1 1 is an example in which the gate insulating layer 30B, the first amorphous germanium layer 31A, and the second amorphous germanium layer are formed to overlap each other (the upper left oblique line portion 52 to the lower right). Further, the transparent conductive pattern 6 A (the analog electrode terminal 9 1 C ) formed by connecting the partial scanning line 5 A and the signal line 1 2, and the transparent conductive layer pattern of the short-circuit line 40 are shaped. The high-resistance wiring can be formed in a slim line shape to form a countermeasure against static electricity. However, it is of course possible to use other conductive members as the static electricity. In the fourth embodiment of the present invention, the organic insulating layer is formed only on the signal line 12, and the drain electrode 21 is exposed in a state in which conductivity is ensured, whereby the reason why sufficient reliability can be obtained is due to the application. The driving signal of the liquid crystal cell is substantially alternating, and the voltage of the counter electrode 14 is adjusted during the image inspection between the counter electrode 12 and the pixel electrode 22 in such a manner that the DC voltage component is reduced. The adjustment is reduced. Therefore, the insulating layer is formed only on the signal line 12 so that the DC component does not flow. • 66- 1300873 (64) In the third and fourth embodiments of the present invention, the organic insulating layer is selectively formed only on the source wiring and the signal line, respectively, and the fabrication is reduced, but because of the thickness of the organic insulating layer When the pixel size of the high-definition panel is small, the alignment treatment using the flat alignment film may cause obstacles due to the difference in height or the gap precision of the liquid crystal cell. The embodiment has a passivation technique of insulating layers by adding a minimum number of engineering numbers. (Fifth Embodiment) The fifth embodiment is based on Fig. 9(d) and Fig. 10(d) until the formation of the contact project is performed substantially the same as the third and the first project. Then, at the source The pole and the bungee wire are formed into a vacuum film forming apparatus such as SPT, which is sequentially coated: the film thickness is 0. The heat-resistant metal thin film layer 34 such as 1# Ti or Ta is used as an anodic oxymetal layer; and the A1 thin film layer 35 having a film thickness of about 3 μm is used as a highly oxidized low-resistance wiring layer. Then, by using the microfabrication photosensitive resin pattern 87, the two layers of the thin film structure, the second amorphous germanium layer 33, and the first non-3 1 A are sequentially etched to expose the gate insulating. Layer 3 0 Α. As shown in Fig. 9 (e) and (e), 21 which is an insulating gate type transistor composed of a laminate of 34A and 35A including the pixel electrode 22, and a signal line which also serves as a source wiring are selectively formed. 12. The electrode terminal 5 is also formed at the same time, and includes a source/drain wiring 12, a pole and a drain to achieve a state in which the cloth is often used as a 1 grinding cloth. Here, as shown in the organic), in the four-implementation routine, the heat resistance of about m can be applied, and the source crystal sand layer is used. Part 10 of the figure and by the drain electrode: scan line • 21 The same as -67- (65) 1300873 part of the scanning line 5A exposed; and part of the signal line formed by the terminal 6. At this time, an important feature of the fifth embodiment is that the photosensitive resin patterns 87A and 87B are formed in advance by the exposure technique, and the film thickness of the optical resin patterns 87 A and 87B is the electrode terminals 5 and 6 of the field 8 7 A (black area). The film thickness is, for example, 3 /im, which is larger than the film thickness of the region 87B (middle) on the source electrode 12, 21 and the storage electrode 72. 5 // m. After the source/drain wirings 12 and 21 are formed, when the film thickness of the photosensitive resin patterns 87A and 87B is reduced by /m or more by the oxygen plasma means, the photosensitive resin pattern 8 7C disappears, and the source 汲12 The 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the scanning line 1. In addition, the characteristics of the photosensitive resin pattern 87C are thinned by the above-described oxygen plasma treatment, and since the anodized layer is formed only in the electrode terminal 5 having a large pattern size, it is hardly electrical. Characteristics and yield have an impact. Next, the photosensitive resin pattern 87C is used as the mask light, and as shown in FIG. 9(f) and FIG. 1(f), the source wirings 1 2, 2 1 are anodized to form an oxide layer 6 8 . , 6, 9, source and drain wirings 1, 2, 2, the second amorphous 3 3 A exposed on the lower side is anodized to form a layer of tantalum oxide as an insulating layer) 66 ° after the anodization is completed, remove In the photosensitive resin pattern 87C, as shown in Fig. (g) and Fig. 10(g), the electric halftone of the electrode terminal composed of the low-resistance thin film layer 35A of the electrode oxide layer is exposed on the side surface thereof. The upper area and the 汲 调 区域 area are less grayed. The 5 pole wiring 2 is selected, that is, the width of the pattern is around 6 and the quality, and the radiant and bungee layer is simultaneously placed on the enamel layer (Si02, such as the first forming yang 5, 6 ° -68- (66) 1300873, the scanning line electrode terminal 6 is known. On the side surface, the anodic oxidation current flows through the high-resistance short-circuit line 40 (9 1 C) through the static electricity countermeasure, so that the thickness of the anodized layer formed on the side surface is thinner than the electrode terminal 5 of the signal line. In the structure of the pole/drain wirings 1, 2 and 2, if the limitation of the resistor 较 is loose, it can be simplified into a single layer of Ta which can be anodized. The active substrate 2 and the substrate 2 are formed in this manner. The color filter is bonded and the liquid crystal is panelized to complete the fifth embodiment of the present invention. The configuration of the storage capacitor 15 is as shown in Fig. 9(g), and the source/drain wiring 12 is exemplified. a storage electrode 72 formed on a portion of the pixel electrode 22 and a portion of the pixel electrode 22, and a protrusion portion provided on the front scanning line 11, via the gate insulating layer 30A, the first amorphous germanium layer 3 1 A, and the second non- The crystalline germanium layer forms an example of plane overlap (the upper left to the lower right oblique line portion 52). In the embodiment, when the source/drain wirings 12 and 21 and the second amorphous germanium layer 33B are anodized, the pixel electrode 22 electrically connected to the gate electrode 21 is also exposed, so that The element electrode 22 is also anodized at the same time, which is quite different from the first embodiment. Therefore, as the film quality of the transparent conductive layer constituting the pixel electrode 22 is different, the resistance 有时 is sometimes anodized. In this case, it is necessary to appropriately change the film formation conditions of the transparent conductive layer to form a film having insufficient oxygen, but the transparency of the transparent conductive layer is not lowered by anodization. Further, the gate electrode 21 and the pixel electrode are provided. 22. The current anodized with the storage electrode 72 is also supplied through the passage of the insulated gate type transistor. However, since the area of the pixel electrode 22 is large, a large reaction current or a long-term reaction is required, regardless of the irradiation. Strong external light, the resistance of the channel portion is not hindered, and an anodized layer having the same film quality and film thickness as that on the signal line 12 is formed on the drain-69-(67) 1300873 electrode 2 1 and the storage electrode 72. , using only the reaction The extension between the two is difficult. However, even if the anodized layer formed on the drain wiring 21 is somewhat incomplete, it is actually more reliable without hindrance. The reason is that as described above, only in In the signal line 12, the insulating layer may be formed in advance so that the DC component does not flow. The liquid crystal display device described above is configured by using a TN type liquid crystal cell, and is separated from the pixel electrode by a specific In the liquid crystal display device of the IPS (In-Plain-Swt icing) method of controlling the lateral electric field between the pair of counter electrodes and the pixel electrodes formed, the engineering reduction proposed by the present invention is useful, and this part will be This is illustrated in the subsequent examples. (Sixth embodiment) The sixth embodiment has the above thickness, preferably 3/m, on the entire surface of the glass substrate 2 as shown in Figs. 1 (e) and 12 (e). The photosensitive polyacrylic resin 39 is applied as a transparent resin having excellent transparency and heat resistance to the left and right thicknesses, and is selectively irradiated on the surface of the drain electrode 21 and the image display portion by selective ultraviolet irradiation using a photomask. The opening portion 62, 63, 64, 65 is formed on a portion 5 of the scanning line and a portion 6 of the signal line and the electrode terminal forming region of the storage capacitor line, and after baking, the photosensitive polyacrylic resin 39 is used as a mask. Selectively removing the gate insulating layers 30A, 30B in the openings 63, 65 to expose a portion 73 (5) of the scanning line and a portion 75 of the storage capacitor line, respectively, using the same manufacturing process as in the second embodiment. of. In the opening * .  .   * - • 70- (68) 1300873 Parts 62, 64, after development, expose the drain electrode 2 1 and a portion 74 ( 6 ) of the signal line. Next, the entire surface of the glass substrate 2 is covered with a film thickness of 0 by using a vacuum film forming apparatus such as SPT. 1 to 0. 2 / m or so of ITO as a transparent conductive layer, as shown in the 1st (f) and 12th (f), using a microfabrication technique, including the gate electrode 2 1 exposed in the opening portion 62 A part of the transparent resin 319 of the intermediate conductive layer 3 6 A is selectively formed: a pixel electrode 41, and a counter electrode 42 on the scanning line 1 and the signal line 12. At this time, a part 73 of the scanning line in the opening 63 and a part 74 of the signal line in the opening 64 are used as the transparent conductive electrode terminals 5 A and 6 A, and a transparent conductive position is provided similarly to the conventional example. The short-circuit line 40 is formed in an elongated linear shape between the electrode terminals 5A and 6A and the short-circuit line 40, and can be formed with high resistance to form static electricity. In the IPS type liquid crystal display device, the influence of the gap between the pixel electrode 41 and the counter electrode 42 is displayed. However, the potential of the pixel electrode 4T and the counter electrode 42 in the electrode is constant, and the display is not affected, so that the transparent electrode is transparent. The formation of the pixel electrode 41 and the counter electrode 42 is not necessarily the most appropriate choice. When a transparent conductive layer is replaced with a metallic Ti, Cr, or MoW alloy, the resistance 値 is lowered, so that the film thickness of the pixel electrode 41 and the counter electrode 42 can be thinned, the alignment is improved, or the Ti is not required to be selected. / A1 alloy laminate, an intermediate metal layer such as Ti or Ta is placed in the upper layer of the source/drain wirings 1, 2, and 2, and the source/drain wirings 1 and 2 1 can be simplified. However, when a metallic electrode is selected, it is difficult to increase the resistance when an electrostatic countermeasure different from the above-described electrostatic countermeasure is not performed. The advantage of using a transparent conductive layer on the pixel electrode 41 and the opposite electrode 42-71 - (69) 1300873 is that in a mass production plant that simultaneously produces a TN type liquid crystal panel and an IPS type liquid crystal panel, there is no need to replace the sputtering apparatus. The target, or the reasons for not needing two kinds of sputtering devices. The active substrate 2 and the color filter fabricated in this manner are bonded together, and the liquid crystal is panelized to complete the sixth embodiment of the present invention. The configuration of the storage capacitor 15 is as shown in FIG. 11(d), exemplifying the storage capacitor line 16 and the drain electrode 2 1, interposing the gate insulating layer 3 0 B, and the first amorphous germanium. The layer 31B and the second amorphous germanium layer form an overlapping region 50 (the upper left to the lower right oblique line portion), constituting the storage capacitor 15 as an example, and the drain electrode 2 1 and the front scanning line 1 1 are interposed. The gate insulating layer 3 0 A may constitute the storage capacitor 15 . In the sixth embodiment, the opposite electrode can be disposed on the optically ineffective scanning line 1 1 and the signal line 12, and as a result, the area to be displayed can be enlarged, and an IPS type liquid crystal display having a high aperture ratio can be obtained. Panels, however, are not easy to reduce the number of manufacturing projects. Thus, the invention of rationalizing passivation formation and further reducing the number of manufacturing engineering is explained in the seventh and eighth embodiments. (Seventh embodiment) In the seventh embodiment, first, a vacuum film forming apparatus such as SPT is used to coat a film thickness 〇·1 to 〇 on one main surface of a glass substrate 2 as in the conventional example. An alloy or a telluride such as Cr, Ta, Mo or the like of about 3/m is used as the first metal layer. Next, using a PCVD apparatus, on the entire surface of the glass substrate 2, for example, 0. 3// m ' 〇. 〇5/rm, 〇. The film thickness of about 1 β m is sequentially covered by -72-(70) 1300873: the first SiNx layer 30 as a gate insulating layer; and the first non-insulating gate type transistor channel which is almost free of impurities a thin film layer such as a crystalline germanium layer 3 1 and a second SiNx layer 32 as an insulating layer of a protective channel, and then, as shown in FIGS. 13(a) and 14(a), using a halftone exposure technique, The film thickness of the region 84A on the gate electrode 1 1 A, which is the protective insulating layer forming region, is formed, for example, at 2 // m, which corresponds to the region 84B corresponding to the counter electrode 16 which also serves as the scanning line 11 and the storage capacitor line. The photosensitive resin 84A, 84B having a thickness of 1 / 4 m is thicker, and the second SiNx layer 32 (channel protective layer) and the first amorphous germanium are selectively removed by using the photosensitive resin patterns 84A and 84B as masks. The layer 3 1 , the gate insulating layer 30 and the first metal layer expose the glass substrate 2 . Then, when the film thickness of the photosensitive resin patterns 84A and 84B is reduced by 1 // m or more by the ashing means such as oxygen plasma, the photosensitive resin pattern 84B disappears, and the second SiNx layer 32A is exposed on the scanning line 11. Exposing the second SiNx layer 32B on the counter electrode 16 while selectively etching the second SiNx layer 32A as the second SiNx layer 32D only in a manner that the protective insulating layer forming region is wider than the gate electrode 11 A, At the same time, the first amorphous germanium layer 31A is exposed on the scanning line 11, and the first amorphous germanium layer 3 1 B is exposed on the counter electrode 16 to remove the photosensitive resin pattern 84C, as shown in FIG. c) and FIG. 14(c), an insulating layer 76 is formed on the side surface of the gate electrode 11A. Therefore, as shown in Fig. 25, it is necessary to have the wiring 7 7 bundled in parallel with the scanning line 1 1 (the same as the storage capacitor line 16 and not shown here), and the plating on the outer peripheral portion of the glass substrate 2 ( e 1 ectr ο p 1 ating ) or anode-73- (71) 1300873 is used to impart a potential connection pattern 78' during oxidation, and further uses an amorphous sand layer 31 and a nitrided sand layer 3 () according to plasma CVD, The film-forming region 7 9 ' of the appropriate electro-violet means of 32 is limited to the inner side of the connection pattern 78. At least the layer of the connection pattern 78 〇umm must be exposed. Using the P C V D device, the entire surface of the glass substrate 2 is, for example, 0. After the film thickness of about 05 μπι is coated with the second amorphous germanium layer 3 3 containing impurities such as a dish, as shown in Fig. 13 (d) and Fig. 14 (d), the 'area other than the image display portion' is fine. The processing technique 'forms the opening portion 63A and the storage capacitor line 16' on the scanning line 1 1 or in parallel, forming an opening portion 6 5 A ' on the electrode terminal of the electrode that bundles the storage capacitor line 16 and selectively removing the opening a second amorphous sand layer 33 and a first amorphous layer 3 1 A and a gate insulating layer 30 A in the portion 63A, and selectively removing a portion 73 of the scanning line and the opening portion 65 A The second amorphous germanium layer 3 3 , and the first amorphous germanium layer 3 1 B, and the gate insulating layer 30B' expose a portion 75 of the storage capacitor line 16 . Then, in the formation of the source/drain wiring, a vacuum film forming apparatus such as SPT is used to sequentially coat a heat-resistant metal thin film layer 34 such as Ti or Ta having a thickness of about ///m as a heat-resistant metal layer. Further, the A1 thin film layer 35 having a film thickness of about 3·3 // m is used as the low-resistance wiring layer. Then, using the microfabrication technique, the source/drain wiring layer and the second amorphous germanium layer 3 3 composed of the two thin films and the first amorphous material are sequentially etched using the photosensitive resin pattern 86. The germanium layer 3 1 A, 3 1 B exposes the gate insulating layers 30A, 30B, as shown in Fig. 13(e) and Fig. 4(e), and selects -74-(72) 1300873 to form sexually. : a drain electrode 2 1 composed of a laminate of 34A and 35A as a pixel electrically insulating gate type transistor; and a source wiring line 1 2, and also an electrode terminal 6 including a source · A portion of the scanning line 7 3 which is formed while the twist line 1 2, 2 1 is formed, is composed of the electrode terminal 5 of the line and a part of the signal line. At this time, the film thickness of 86A on the signal line 12 is //m, and the film of 86B on the drain electrode 21 and the electrode terminals 5, 6 is formed in advance by a half exposure technique. 5 / m thick photosensitive resin patterns 86A, 86B, which is an important feature of the first embodiment. After the source/drain wirings 1 and 2 are formed, when the film thickness of the photosensitive resin patterns 86A and 86B is reduced by 4 // m or more by means of oxygen plasma or the like, the photosensitive resin pattern 86B disappears. 1 and FIG. 14(f), the gate electrode 21 and the electrode terminal 6 are exposed, and the photosensitive pattern 86C can be selectively formed only on the signal line 12, but due to the use of the above oxygen In the plasma treatment, when the pattern width of the photosensitive grease pattern 86C is made thinner, the reliability of the upper surface of the signal line 12 is lowered, so that the change in the pattern size is suppressed by the enhanced anisotropy. Further, in the configuration of the source/drain wirings 12 and 2 1 , if the limitation of the crucible is loose, it is also possible to simplify the formation of a single layer such as T a, c r or M 0 w . The active substrate 2 and the color filter fabricated in this manner are panel-fitted to liquid crystal, and the seventh embodiment of the present invention is completed. As described above, the IP S-type liquid crystal device can be understood that the pixel electrode 22 which does not require conductivity is provided on the active substrate 2, and the scanning tone of the opposite surface of the color filter is 3 Thick case seven graying 1. 5 (f) Sub-5 resinous tree, which is a good resistance alloy, which is shown to be transparent -75- (73) 1300873 The counter electrode 14 which does not require transparent conductivity. Therefore, the intermediate conductive layer on the source drain wirings 1, 2, 2 1 is also not required. In the seventh embodiment, since the photosensitive resin pattern 8 6 C is connected to the liquid crystal, the photosensitive resin pattern 86C is not a general photosensitive resin containing novolac resin as a main component, and the purity is high and the main component is used. It is important that the photosensitive organic insulating layer having a high heat resistance containing a propylene base resin or a polyimide resin is used. The configuration of the storage capacitor 15 is as shown in Fig. 15(f), exemplifying a portion of the pixel electrode (drain wiring) 21 and a counter electrode 6 which also serves as a storage capacitor line. The insulating layer 30B, the first amorphous germanium layer 3 1 B, and the second amorphous germanium layer form an example in which planes are overlapped (the upper left oblique line portion 50 to the lower right). In addition, the description of "static countermeasures" is omitted. In the seventh embodiment of the present invention, the organic insulating layer is formed only on the signal lines, respectively, to achieve a reduction in manufacturing engineering. However, since the thickness of the organic insulating layer is usually 1 // m or more, the pixels of the high-definition panel are higher. Hour's use of the alignment treatment of the alignment film of the flat-grinding cloth may cause a non-alignment state due to the difference in height or an obstacle to the accuracy of the gap of the liquid crystal cell. Here, the eighth embodiment has a passivation technique of becoming an organic insulating layer by adding a minimum number of engineering numbers. (Eighth Embodiment) The eighth embodiment is as shown in Figs. 15(d) and 16(d), and is formed in a manufacturing process substantially the same as that of the seventh embodiment until the contact engineering is formed. . Then, in the source and drain wiring formation process, a vacuum film forming apparatus such as -76- (74) 1300873 SPT is used to sequentially cover the film thickness. i#m such as Ti, Ta, etc., the heat resistant metal film layer 34 as an anodic hot metal layer; and the film thickness is 0. A1 thin film layer of about 3/zm 35 rows of anodized low resistance wiring layers. Then, the photosensitive resin pattern 87 is finely applied, and the two thin source, the drain wiring, the second amorphous germanium layer 3, and the second germanium layers 31A and 31B are sequentially etched to expose the gate. The insulating layers 30A, 30B are shown in Fig. (e) and Fig. 6(e), selectively forming: an insulating gate type transistor of the pixel electrode formed by the E 35A layer, and a source wiring. The signal line 12 also forms a sub-piece 6, which is a portion of the scanning line 73 formed by the source and drain wirings 1, 2, 2, and is composed of the electrode terminals 5 and lines of the scanning line. At this time, by the halftone exposure technique, the film thickness of 8 7 A (black area) on the shape of 1 2 is, for example, 3 // m, the ratio is 2 1 and the area on the electrode terminals 5, 6 is 8 7 B (middle tone) Area 1 . 5 / m thick photosensitive resin patterns 86A, 86B, this is an important feature of the example. After the source/drain wirings 1 and 2 are formed, when the film thickness of the photosensitive resin patterns 87A and 87B is equal to or greater than m, the photosensitive resin pattern 8 7 B disappears, and the source 12 When the 21 is exposed, the photosensitive resin pattern 8 7 C can be selected only on the electrode terminals 5 and 6. Here, in the photosensitive resin pattern mask, the light is irradiated while the left and right sides are oxidized as shown in FIGS. 15(f) and 16(J, the source/drain wirings V2 and 21 are anodized). Resistant to the construction technology, the film is composed of an amorphous material, such as the film thickness of the first 5 from the 3 4 A and the drain electrode: the exposed part of the signal is the signal line drain electrode) Reduced by 1 5 汲 配线 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化The crystalline germanium layer 3 3 A is anodized to form an oxide sand layer (Si〇 2) 66 as an insulating layer. After the completion of the anodization, when the photosensitive resin pattern 8 7 C is removed, as shown in Figs. 15(g) and 16(g), the electrode terminals 5 and 6 having the low-resistance film layer 35A on the surface thereof are exposed. However, in FIGS. 15(f) and 16(f), the countermeasure against static electricity between the scanning line electrode terminal 5 and the signal line electrode terminal 6 by the high-resistance member is not shown in the figure, so the scanning is performed. The anodic oxide layer is not formed on the side surface of the electronic terminal 5 of the line. However, since the opening portion 63A is provided and the portion 73 of the scanning line 11 is exposed, the countermeasure against static electricity is easy. Further, in the configuration of the source/drain wirings 1, 2 and 2, if the resistance 値 is loose, the Ta single layer which is anodized can be simplified. The active substrate 2 and the color filter which were produced in this manner were bonded together, and the liquid crystal was panelized to complete the eighth embodiment of the present invention. Regarding the configuration of the storage capacitor 15, as shown in Fig. 15(g), a part of the pixel electrode 21 and the counter electrode 16 are illustrated, via the gate insulating layer 30B, and the first amorphous germanium layer 3 1 B. An area 50 (the lower right oblique line portion) overlapping the second amorphous germanium layer constitutes an example of the storage capacitor 15 . In the ninth embodiment of the present invention, the connection forming process of the gate insulating layer is rationalized. When the opening of the passivation insulating layer is formed, the IPS type liquid crystal display device having a further reduction in the number of manufacturing processes can be obtained. (Ninth Embodiment) -78 - (76) 1300873 The table nine embodiment is selectively formed on the glass substrate 2 as shown in Figs. 17(d) and 18(d): by 34A And a gate electrode 2 1 of an insulating gate type transistor which is a pixel electrode and a signal line 12 which also serves as a source line formed by a laminate of 35A, and an electrode terminal 6 composed of a partial signal line is formed at the same time. This is carried out in substantially the same process as the sixth embodiment. The difference is in the pattern shape of the storage capacitor line 16. In the ninth embodiment, the storage capacitor line 16 doubles as the counter electrode. Then, as shown in Fig. 17 (e) and Fig. 18 (e), the ratio is 0. 5// m is thicker, preferably 1. The photosensitive polyacrylic resin 3 is applied as a transparent resin having excellent transparency and heat resistance at a thickness of about 5//m. By selective ultraviolet irradiation using a photomask, the scanning lines are respectively in regions other than the image display portion. The portion 5 and the portion 6 of the signal line and the portion 75 of the storage capacitor line 16 form openings 62, 63, 64, 65. After the post-baking, the photosensitive polyacrylic resin 39 is used as a mask to selectively remove the gate insulating layers 30A and 30B in the openings 63 and 65 to expose a portion 5 of the scanning line and the storage capacitor line 16. A portion 7 5 serves as an electrode terminal 5 of the scanning line and an electrode terminal of the storage capacitor line, respectively. Further, in the ninth embodiment, it is known that the SiNx layer as the inorganic material is used instead of the photosensitive polyacrylic resin 39 as the transparent insulating layer, and the opening portion forming process using the photosensitive resin may be performed. The active substrate 2 and the color filter fabricated in this manner are bonded together, and the liquid crystal is panelized to complete the ninth embodiment of the present invention. When a thick photosensitive polyimide resin is used as the transparent insulating layer as the passivation insulating layer, the height difference between the counter electrode 16 and the pixel electrode 21 is absorbed, so that the alignment is 79-(77) 1300873. It is easy to 'no misalignment, and the contrast ratio is also high. Further, since the photosensitive polyacrylic resin 39 remains on the glass substrate 2, the number of manufacturing steps is further reduced, and the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line cannot be electrically connected. Therefore, for static electricity, it is a troublesome place to be treated with caution. The configuration of the storage capacitor 15 is as shown in Fig. 17(e), and a part of the pixel electrode 22 and the counter electrode 16 are interposed, and the gate insulating layer 30B and the first amorphous germanium layer 31A are interposed. The region 50 (the lower right oblique line portion) in which the second amorphous germanium layer overlaps constitutes an example of the storage capacitor 15 , and the pixel electrode 2 1 and the scanning line 1 1 of the preceding stage are interposed with the gate insulating layer 3 〇a , constituting the storage capacitor 1 5 is also possible. (Tenth Embodiment) In the ninth embodiment, a photosensitive polyacrylic resin or a SiNx layer having high transparency is used for the passivation insulating layer, but the application is carried out by a new rationalization technique in the connection forming process and the fifth and seventh embodiments. In the case of the passivation forming technique of the source/drain wiring and the anodization of the channel, an IPS type liquid crystal display device can be obtained by using two masks, and this portion is explained in the tenth embodiment. In the first embodiment, a vacuum film forming apparatus such as SPT is used on one main surface of the glass substrate 2 to coat the film. 1 to 〇. An anodized first metal layer of about 3/m. Next, on the entire surface of the glass substrate 2, a PCVD apparatus is used, for example, 0. 3 // m, 0. 05 // m, 0·1 // m film thickness, sequentially coated: first SiNx layer as gate insulating layer -80· (78) 1300873 3 〇, insulating gate type with almost no impurities The first amorphous germanium layer 31 to which the channel of the crystal belongs, and the third thin layer of the second SiNx layer 32 to protect the via as the insulating layer, and as shown in FIGS. 19(a) and 20(a) As shown, the semiconductor layer forming region, that is, the region 8 4 A 1 on the gate electrode 1 1 A, the region 84A2 on the proximal region where the scanning line Π and the signal line 12 intersect, and the counter electrode are shown by the halftone exposure technique. A region 84A3 on the near pupil region where the 16-friend signal line 12 intersects, and a storage capacitor formation region, that is, a region on the portion 84 A4 of the counter electrode 16 and the region on the near region intersecting the pixel electrode 21 and the counter electrode 16 The film thickness at 84A5 is, for example, 2 // m, which is thicker than the film thickness 1 /2 m corresponding to the scanning line 1 1 which also serves as the gate electrode 1 1 A and the photosensitive resin pattern 84B of the counter electrode 16 Resin patterns 84A1 to 84A5 and 85B, with photosensitive resin patterns 81 A to 84A5 and 81B as masks, plus a second SiNx The layer 32, the first amorphous germanium layer 31, and the gate insulating layer 30 are selectively removed from the first metal layer to expose the glass substrate 2. After the multilayer film pattern corresponding to the scanning line 1 1 and the counter electrode 16 which also serves as the gate electrode 1 1 A is formed in this manner, the upper photosensitive resin patterns 84A1 to 84A5 are then removed by means of ashing means such as oxygen plasma. When the film thickness of the film is reduced by 1/4 or more, the photosensitive resin pattern 84B disappears, and as shown in FIGS. 19(b) and 20(b), the second SiNx layer 32A is exposed on the scanning line 11, and The second SiNx layer 32B is exposed on the counter electrode 16 while being on only the gate electrode Η A, the near pupil region intersecting the scan line 1 Ϊ and the signal line 12, and the counter electrode 16 and the signal line 1 2 The photosensitive resin patterns 84C1 to 84C5 are selectively formed on the adjacent near pupil region and on the storage capacitor forming region, and in the vicinity of the pixel electrode 21 and the opposite-81 - (79) 1300873 electrode 16. The above-described oxygen plasma treatment is to enhance the anisotropy to suppress the change in the pattern size without lowering the alignment accuracy of the mask of the subsequent source/drain wiring formation, which is as described above. Different from the other embodiments, in the tenth embodiment, it is necessary to expose the scanning line 11 when the etching stopper layer is formed, and to perform the oxygen plasma treatment after the formation of the insulating layer 76, so that the film thickness is reduced with the insulating layer 76. The method is complicated, so it is recommended to use an anodized layer on the insulating layer 76. Therefore, in the connection pattern 78 shown in Fig. 22, the scanning line 11 and the counter electrode 16 (not shown) are given a + (positive) potential by a connecting means such as an alligator clip. After the insulating layer 76 is formed on the side of the scanning line 1 1 , as shown in FIGS. 19 (c ) and 20 ( c ), the photosensitive resin patterns 84C1 to 84C5 are used as masks on the gate electrode 1 1 A. And a layer of the second SiNx layer 32A, the first amorphous germanium 31A and the gate insulating layer 30A selectively remaining on the near germanium region intersecting the scan line 11 and the signal line 12, and at the opposite electrode 16 and The second SiNx layer 3 2B and the first amorphous germanium are selectively left on the near pupil region where the signal line 12 intersects, and the near region of the storage capacitor forming region intersecting the pixel electrode 21 and the opposite electrode 16 . 31B and a gate insulating layer 3 0 B are laminated, simultaneously etching the second S i NX layer 32A on the scan line 1 1 , the first amorphous germanium layer 31 A and the gate insulating layer 30A, and the counter electrode 16 The second SiNx layer 3 2B, the first amorphous germanium layer 31B, and the gate insulating layer 30B expose the scan line 1 1 and the counter electrode 16 respectively. Further, by applying an oxygen plasma treatment, the film thickness of the photosensitive resin patterns 84C1 to 84C5 is reduced isotropically by 0. 5 / m or so as the photosensitive -82- (80) 1300873 resin patterns 84D1 to 84D5, around the 84D1 to 84D5, the second SiNx layers 32A, 32B exposed a wide width of 0. 5//m or so. Thus, as shown in FIGS. 19(d) and 20(d), the second SiNx layer 32A on the gate electrode 11A is selectively removed by using the photosensitive resin patterns 84D1 to 84D5 as masks. The protective insulating layer (second SiNx layer) 32D partially exposes the first amorphous germanium layer 3 1 A. Then, after removing the above-described photosensitive resin patterns 84D1 to 84D5, using a PCVD apparatus, on the entire surface of the glass substrate 2, for example, 〇. The film thickness of 〇5 // m is covered with a second amorphous germanium layer 33 containing impurities such as phosphorus, and in the formation process of the source/drain wiring, a vacuum film forming apparatus such as SPT is used to sequentially cover the film thickness: The heat-resistant metal film layer 34 such as Ti or Ta is used as an anodizable heat-resistant metal layer, and the film thickness is 〇. The A1 film layer 3 5 of about 3 // m is also used as an anodizable low-resistance wiring layer. then,. The photosensitive resin pattern 87 is sequentially etched by a microfabrication technique: a source/drain wiring layer composed of two layers of thin films, a second amorphous germanium layer 3 3 and a first amorphous germanium layer 3 1 A, 3 1 B, exposing the gate insulating layers 30A, 30B, as shown in Figs. 19(e) and 20(e), selectively forming a pixel composed of the laminates of 34A and 35A The drain electrode 2 1 of the insulated gate type transistor of the electrode and the signal line 1 2 which also serves as the source wiring are formed on a part of the scanning line which is formed while the source/drain wirings 2 2 and 2 1 are formed. The electrode terminal 5 of the scanning line and the electrode terminal 6 formed by a part of the signal line. At this time, using the halftone exposure technique, the film thickness (black area) of 87A on the electrode terminals 5, 6 is formed, for example, 3 // m, which corresponds to the area of the source/drain wiring 1 2, 2 1 - 83-(81) 1300873 8 7 B (intermediate adjustment region) The case where the photosensitive resin patterns 87A and 87B having a thickness of 1 · 5 μm is also an important feature of the tenth embodiment. After the formation of the source/drain wirings 1, 2 and 2, the photosensitive resin patterns 87 A and 87B are reduced in film thickness by an ashing means such as oxygen plasma. When 5 / m or more, the photosensitive resin pattern 8 7B disappears, and the source/drain wirings 2 2 and 2 1 are exposed, and the photosensitive resin pattern 87C is selectively formed only on the electrode terminals 5 and 6. Here, the photosensitive resin pattern 87C is used as a mask to irradiate light, and as shown in FIGS. 19(f) and 20(f), the source/drain wirings 1, 2, 2 1 are used for anodization. The oxide layers 68 and 69 are formed, and the second amorphous germanium layer 3 3 A exposed on the lower side of the source/drain wirings 12 and 21 is anodized to form a hafnium oxide layer (SiO 2 ) as an insulating layer. . At this time, the exposed scanning line 1 1 and the counter electrode 16 are also anodized at the same time, and an oxide layer 71 is formed on the surface thereof. As shown in Fig. 22, the wiring 77 and the connection pattern 78 of the scanning line 1 1 are bundled in parallel on the active substrate 2, so that the source/drain wirings 1 2, 2 1 are anodized simultaneously, and the scanning line Π Anodizing is also easy to implement. Furthermore, anodization is also performed on the scan line 1 1 and the counter electrode 16 to form an insulating layer, and an anodizable metal is formed on the scan line, and a Ta single layer, Al (Zr, Ta) can be selected. In the case of a single layer structure such as an alloy or a laminated structure of Al/Ta, Ta/Al/Ta, Al/Al (Ta, Z〇 alloy, etc.), as described above, when the photosensitive resin pattern 87C is removed after the anodization is completed, Figs. 19(g) and 20(g) show an anodized layer on the side surface thereof, and an electrode terminal 5'6 composed of a low-resistance metal layer 35A is exposed.  - · -84- (82) 1300873. Furthermore, in the case of the configuration of the source/drain wirings 1, 2, 2 1 'the electrical limitation is loose, the active substrate 2 and the color obtained by forming the anodizable T a single layer in this manner can be simplified. The filter is bonded to the crystal panel to complete the tenth embodiment of the present invention. Regarding the configuration of the storage device ^, as shown in Fig. 19 (f), the display pixel electrode (drain) 21 and the counter electrode (storage capacitor line) 16 are interposed with the gate layer 3 0B, first. The laminated layers of the amorphous germanium layer 31B, the second SiNx layer 32E, and the amorphous germanium layer are formed by overlapping planes (the left and right oblique line portions 50), but the configuration of the storage capacitor 15 is not limited to the pixel. The electrode and the front scanning line are formed by interposing an insulating layer containing a gate. Further, other configurations are also possible, but detailed descriptions are omitted. [Effects of the Invention] As described above, in the liquid crystal display device of the present invention, since the absolute-type transistor has a protective insulating layer on the channel, it is only on the source/drain wiring in the image display, or only the signal Selectively apply an organic insulating layer on the line, or apply anodization to the source/drain wiring made of anodizable source/drain wiring, and form a layer on the surface. Substrate passivation function. In the other part of the liquid crystal display device of the invention, the yttrium oxide layer is formed on the via by oxidation, so that the source/drain wiring formed of the anodizable source wiring material is simultaneously applied to the channel. It is masculine and forms an insulating layer on its surface. In this way, the active barrier C► C can be imparted to the liquid. The 15 poles are electrically insulated to the right, and the edge of the edge layer is lightly insulated. Anode • Bipolar Oxygen Group 85- (83) 1300873 Plate passivation function. Therefore, it is not necessary to have a special heating process, and an amorphous gate layer is used as the insulating gate transistor of the semiconductor layer, and excessive heat resistance is not required. In other words, by passivation formation, there is an additional effect that electrical performance deterioration does not occur. In addition, when the source drain wiring is anodized, the introduction of the halftone exposure technique can selectively protect the electrode terminals of the scanning line or the signal line, thereby achieving an effect of preventing an increase in the number of lithography processes. The object of the present invention is to realize the reduction of engineering and the formation of organic insulation on the side of the exposed scanning line by processing the formation process of the scanning line and the formation of the etch stop layer by a mask by the introduction of the halftone exposure technique. In the case of the layer or the anodized layer, the gate insulating layer on the scanning line is also used to fill the existing pinhole with the organic insulating layer or the anodized layer, thereby reducing the interlayer short circuit between the scanning line and the signal line, and the additional effect is large. In addition, by introducing the analog pixel electrode, rationalizing the pixel electrode and the scan line by a mask, the number of the lithography process can be further reduced from the conventional 5 times, and 4 channels or The three-layer photomask is used to manufacture a liquid crystal display device, and the industrial price is extremely large from the viewpoint of cost reduction of the liquid crystal display device. Moreover, the pattern accuracy of these projects is not so high, so it does not have a large impact on yield or quality, so production management is easier to implement. Further, in the IPS type liquid crystal display device of the sixth embodiment, the electric field generated between the counter electrode and the pixel electrode is applied only to the liquid crystal layer, and the IPS type liquid crystal display device of the seventh embodiment can be similarly applied to The gate insulating layer and the liquid crystal layer on the counter electrode, in addition to the IPS type liquid crystal display -86-(84) 1300873 device of the eighth embodiment, the gate insulating layer and the pixel which are equally applied to the counter electrode The anodized layer of the electrode, and the IPS display device of the tenth embodiment, can also be applied to the anodized layer on the counter electrode and the anodized layer on the pixel electrode, so that none of the defects are known. The inferior passivation insulating layer has the advantage that it is difficult to produce a significant burnt afterimage phenomenon. This is because the anodic oxide layer (the anodized layer of the pixel exhibits no charge accumulation due to the high-resistance layer compared to the insulating layer. Moreover, in the liquid crystal display device of the ninth embodiment, if transparent is used The resin layer is used as a passivation, and the electric field generated between the counter electrode and the halogen electrode can be applied to the edge layer, the liquid crystal layer and the transparent resin layer, so that there is no inferior passivation insulating layer which is conventionally trapped. Since the transparent resin layer is hard and the burnt image phenomenon of the image is displayed, the active base surface is flat, so that a uniformity can be formed without alignment conditions, and an image with high contrast ratio without non-alignment can be obtained. Furthermore, the requirements of the present invention can be understood from the above description. In the stop type gate-type transistor, the formation process and the etching termination process of the scan line can be processed by a half mask by a halftone exposure technique. At the same time, at the point of the exposed scanning line and the side organic insulating layer or the anodized layer of the counter electrode, the material or film thickness of the other elemental electrode, gate insulating layer, etc. The difference between the display-mounted conductor device and the manufacturing method thereof is also known in the present invention. In the reflective liquid crystal display device, the semiconductor layer of the practical 'further' insulated gate type transistor of the present invention is not limited to liquid crystal. The layered liquid crystal layer and the liquid have the function of the image electrode. In the case of the IPS type layer, the gate of the IPS type has many defects, and the surface of the plate is processed to form the shape of the layer to be etched. Amorphous • 87- (85) 1300873 sand. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device for a display device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the first embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device for a display device according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the second embodiment of the present invention. Fig. 5 is a plan view showing a semiconductor device for a display device according to a third embodiment of the present invention. Figure 6 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a third embodiment of the present invention. Fig. 7 is a plan view showing a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 8 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a fourth embodiment of the present invention. Figure 9 is a plan view showing a semiconductor device for a display device according to a fifth embodiment of the present invention. Fig. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device for a display device according to a fifth embodiment of the present invention. Fig. 1 is a plan view showing a half-88-(86) 1300873 conductor device for a display device according to a sixth embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a sixth embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device for a display device according to a seventh embodiment of the present invention. Fig. 14 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a seventh embodiment of the present invention. Fig. 15 is a plan view showing a semiconductor device for a display device according to an eighth embodiment of the present invention. Figure 16 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to an eighth embodiment of the present invention. Fig. 17 is a plan view showing a semiconductor device for a display device according to a ninth embodiment of the present invention. Figure 18 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a ninth embodiment of the present invention. Figure 19 is a plan view showing a semiconductor device for a display device according to a tenth embodiment of the present invention. Figure 20 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a tenth embodiment of the present invention. Fig. 21 is a view showing the arrangement of the connection pattern formed by the insulating layer in the first to ninth embodiments of the present invention. Fig. 2 is a layout view showing a connection pattern of an insulating layer according to a tenth embodiment of the present invention. Fig. 23 is a perspective view showing a mounted state of the liquid crystal panel. -89- (87) (87) 1300873 Figure 24 is an equivalent circuit diagram of the liquid crystal panel. Figure 25 is a cross-sectional view of a conventional liquid crystal panel. Figure 26 is a plan view of a conventional substrate of a conventional example. Fig. 27 is a cross-sectional view showing the manufacturing process of the active substrate of the conventional example. Figure 28 is a plan view of a rationalized active substrate. Figure 29 is a cross-sectional view showing the manufacturing process of a rationalized active substrate. [Description of the figure] 1 : Liquid crystal panel 2 : Active substrate (glass substrate) 3 : Semiconductor integrated circuit wafer 4 : TCP film 5 : Electrode terminal of scanning line, part of scanning line 6 : Electrode terminal of signal line, signal Part of the line 9 : Color filter (opposing glass substrate) 1 〇: Insulated gate type transistor 1 1 : Scanning line (gate electrode) 1 1 A : Gate wiring, gate electrode 1 2 : Signal line (source wiring, source electrode) 16 : storage capacitor line (IPS type counter electrode) 1 7 : liquid crystal 18: polarizing plate 20: alignment film 21: drain electrode (IPS type pixel electrode) -90- ( 88) (88) 1300873 22 : (transparent conductive) pixel electrodes 30, 30A, 30B, 30C: gate insulating layer (ISiNx layer) 3 1 , 3 1 A, 3 1 B, 3 1 C : (No Impurity-containing) first amorphous germanium layer 32, 32A, 32B, 3 2C : second SiNx layer 3 2D : channel protective insulating layer (etch stop layer, protective insulating layer) 3 3, 3 3 A, 3 3 B, 3 3 C : (with impurities) 2nd amorphous bismuth layer 34, 34A: (anodable) refractory metal layer 35, 35A: (anodable) low-resistance metal layer (A1) 36, 3 6A :( Anodized) intermediate conductive layer 3 7 : passivation insulating layer 41 : pixel electrode 42 of IPS type liquid crystal display device: opposite electrode 50, 51, 52 of IPS type liquid crystal display device: storage capacitor forming region 62 : (drain electrode The upper openings 63, 63A: (on the scanning line) the openings 64, 64A: (on the signal line) the openings 65, 65A: the opening portion 66 (on the counter electrode): the impurity-containing yttrium oxide layer 68: Anodized layer (titanium oxide, TiO 2 ) 69 : anodized layer (alumina, Al 2 〇 3 ) 70 : anodized layer (penta pentoxide, Ta 205 ) 71 : anodized layer of (opposite electrode) 7 2 : storage electrode 7 3 : One 咅 β of the scanning line -91 - (89) 1300873 74 : Part of the signal line 7 6 : Insulation layers 80A , 80B , 81A , 81B , 82A , 82B , 84A , 84 B formed on the side of the scanning line , 87A, 87B: photosensitive resin pattern 83A (formed by halftone exposure): (general for photoreceptor electrode) photosensitive resin pattern 8 5 : photosensitive organic insulating layer 86A, 86B: (formed by halftone exposure) Photosensitive organic insulating layer 91: transparent conductive layer 92: first metal layer -92-

Claims (1)

(1) 1300873 Pickup, Patent Application Range 1. A bottom gate type insulated gate type transistor, characterized in that a gate electrode is formed on a main surface of an insulating substrate, and an insulating layer is formed on a side surface of the gate electrode. At the same time, one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a protective insulating layer having a width wider than the gate electrode is formed on the first semiconductor layer. A source/drain wiring formed by laminating a second semiconductor layer containing impurities and one or more metal layers is formed on one portion of the protective insulating layer and on the first semiconductor layer and the insulating substrate. 2. The bottom gate type insulated gate type transistor according to the first aspect of the invention, wherein the insulating layer is an organic insulating layer. 3. The bottom gate type insulated gate type transistor according to the first aspect of the invention, wherein the gate electrode is composed of an anodizable metal layer, and the insulating layer is an anodized layer. 4. The bottom gate type insulated gate type transistor according to the first aspect of the invention, wherein the gate electrode is composed of a laminate of a transparent conductive layer and a metal layer, and the insulating layer is an organic insulating layer. A liquid crystal display device having at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, a signal line serving as a source wiring, and a first transparent insulating substrate in which a unit pixel of a pixel electrode or the like is connected to a gate electrode, and a second transparent insulating substrate opposite to the first transparent insulating substrate or A -93 - (2) 1300873 liquid crystal display device comprising a liquid crystal between the color filters, wherein: at least one first metal is formed on one main surface of the first transparent insulating substrate a scan line composed of a layer having an insulating layer on a side thereof, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a width ratio is formed on the first semiconductor layer The gate electrode also has a fine protective insulating layer, and an opening portion is formed in the gate insulating layer on the scanning line in a region other than the image display portion, and the first semiconductor layer is formed on the partial protective insulating layer. And a source (signal line) formed by laminating a second semiconductor layer containing impurities and one or more anodizable metal layers on the first transparent insulating substrate, a drain wiring, and a periphery including the opening An electrode terminal of a scan line formed by laminating a first semiconductor layer and a second semiconductor layer and one or more anodizable metal layers, forming transparent conductivity on a portion of the drain wiring and the first transparent insulating substrate The pixel electrode and the 1S field other than the image display portion form a transparent conductive electrode terminal on the signal line, and the source is in addition to the region of the drain wiring overlapping the pixel electrode and the electrode terminal of the signal line. The surface of the pole • bungee wiring forms an anodized layer. A liquid crystal display device having at least an insulating gate type transistor and a scan line of a drain-electro-94-(3) 1300873 pole which serves as the insulating gate type transistor on one main surface, and serves as a source a signal line of the pole wiring, a unit pixel connected to the pixel electrode of the drain wiring, and the like, a first transparent insulating substrate arranged in a two-dimensional matrix; and a second opposite to the first transparent insulating substrate A liquid crystal display device comprising a transparent insulating substrate or a color filter filled with a liquid crystal, wherein at least one first metal layer is formed on one main surface of the first transparent insulating substrate A scanning line having an insulating layer on its side surface forms one or more gate insulating layers and a first semiconductor layer containing no impurities on the gate electrode, and a wider width is formed on the first semiconductor layer than a gate electrode a protective insulating layer, on a portion of the protective insulating layer and the first semiconductor layer and the first transparent insulating substrate, forming a second semiconductor layer containing impurities and a second gold layer or more A source (signal line) and a drain line formed by stacking layers of the constitutive layer, and electrodes formed on the first transparent insulating substrate on the scan line and the signal line on the drain wiring and the region other than the image display portion a transparent insulating layer having an opening in the terminal forming region, wherein the gate insulating layer on the electrode terminal forming region from which the scanning line is removed includes an opening portion on the drain wiring, and a transparent conductive pixel is formed on the transparent insulating layer electrode. 7 - A liquid crystal display device having at least: -95- (4) 1300873 insulated gate type transistor, and a scanning line serving as a gate electrode of the insulating gate type transistor, on both sides of a main surface a signal line of the source wiring, a unit pixel of a pixel electrode connected to the drain wiring, and the like, and a first transparent insulating substrate arranged in a two-dimensional matrix; and a surface opposite to the first transparent insulating substrate A liquid crystal display device comprising two transparent insulating substrates or a color filter interposed between liquid crystals, wherein: A scan line composed of a laminate of a transparent conductive layer and a first metal layer and having an insulating layer on a side surface thereof, and a transparent conductive pixel electrode and a signal line electrode are formed on at least one main surface of the first transparent insulating substrate a terminal, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a protective insulating layer having a width wider than that of the gate electrode is formed on the first semiconductor layer, and is displayed in an image. In a region other than the portion, an opening is formed in the gate insulating layer on the scanning line, and an electrode end as a scanning line is exposed in the opening portion a transparent conductive layer formed on a portion of the protective insulating layer and a layer of a second semiconductor layer containing impurities and a second metal layer on the first transparent layer and the first transparent insulating substrate a source wiring (signal line), and a part of the source wiring formed of one or more second metal layers on a part of the electrode terminal of the signal line, and a part of the protective insulating layer a drain wiring composed of a laminate of a second semiconductor layer containing impurities and a second metal layer on the first transparent insulating substrate, and a partial pixel electrode-96- (5) A part of the above-described drain wiring composed of one or more first metal layers is formed on 1300873, and a photosensitive organic insulating layer is formed on the source/drain wiring. 8.  A liquid crystal display device having at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, a signal line serving as a source wiring, and a connection to a main surface a unit transparent pixel of a pixel electrode or the like of the drain wiring is arranged in a two-dimensional matrix-shaped first transparent insulating substrate; and a second transparent insulating substrate opposite to the first transparent insulating substrate or color filter A liquid crystal display device comprising a liquid crystal display device between the sheets, wherein at least one main surface of the first transparent insulating substrate is formed by laminating a transparent conductive layer and a first metal layer, and the side surface thereof is insulated. a scanning line of a layer and a transparent conductive pixel electrode, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a wide aspect gate is formed on the first semiconductor layer The electrode further protects the insulating layer, and an opening is formed in the gate insulating layer on the scanning line in a region other than the image display portion, and the transparent conductive layer is exposed in the opening. a source wiring (signal line) formed by laminating a second semiconductor layer containing impurities and one or more second metal layers on a portion of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate And forming a second semiconductor layer containing impurities and a second metal layer of -97-(6) 1300873 or more on a portion of the above protective insulating layer, on the second semiconductor layer, and on the first transparent insulating substrate a drain wiring formed of a laminate; and a portion of the drain wiring formed of one or more second metal layers on one of the pixel electrodes; and a first semiconductor layer including the periphery of the opening a semiconductor layer and a transparent conductive layer in the opening portion form an electrode terminal of a scanning line formed of a second metal layer; and an electrode terminal of a signal line composed of a partial signal line in a region other than the image display portion, except for the signal line In addition to the electrode terminals, a photosensitive organic insulating layer is formed on the signal lines. 9.  A liquid crystal display device having at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, a signal line serving as a source wiring, and a connection line on a main surface a unit transparent element of a pixel electrode of a pole wiring or the like, a first transparent insulating substrate arranged in a two-dimensional matrix; and a second transparent insulating substrate or a color filter opposite to the first transparent insulating substrate A liquid crystal display device comprising a liquid crystal display device, wherein at least one main surface of the first transparent insulating substrate is formed by laminating a transparent conductive layer and a first metal layer, and the side surface thereof is insulated. a scanning electrode of the layer and a pixel electrode of a transparent conductive position, wherein one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode, and a wide specific gate is formed on the first semiconductor layer The electrode electrode further protects the insulating layer, and an opening portion is formed in the gate insulating layer -98-(7) 1300873 on the scanning line in a region other than the image display portion, and is formed in the opening portion. Exposing a transparent conductive layer ′ on a portion of the above-mentioned protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate, forming a layer of a second semiconductor layer containing impurities and one or more anodizable metal layers a source wiring (signal line); and forming a second semiconductor layer containing impurities and one or more anodizable metals on the partial protective insulating layer, the first semiconductor layer, and the first transparent insulating substrate a drain wiring formed of a layer of a layer; and a portion of the drain wiring formed of an anodizable metal layer formed on one of the pixel electrodes; and a first semiconductor layer including the periphery of the opening An electrode terminal of a scanning line formed of an anodizable metal layer and a electrode terminal formed of a signal line formed by a portion of the signal line in a region other than the image display portion; and a transparent conductive layer in the opening portion; An anodized layer is formed on the source/drain wiring in addition to the electrode terminal of the signal line. A liquid crystal display device is characterized in that it has at least an insulating gate type transistor on one main surface, a scanning line which also serves as a gate electrode of the insulating gate type transistor, a signal line which serves as a source wiring, and a connection. The first pixel of the pixel electrode of the drain gate type of the insulating gate type transistor and the counter electrode formed by the specific distance from the pixel electrode is arranged in a two-dimensional matrix. a liquid crystal display device comprising: an insulating substrate; and a second transparent insulating substrate or a color filter opposed to the first transparent insulating substrate; wherein: at least the first transparent insulating substrate A liquid crystal display device comprising a layer of -99-(9) 1300873 crystal formed on one main surface, wherein: at least one first metal layer is formed on one main surface of the first transparent insulating substrate A scan line and a counter electrode having an insulating layer on the side thereof, one or more gate insulating layers are formed on the counter electrode, and one or more gates are formed on the gate electrode In the insulating layer and the first semiconductor layer containing no impurities, a protective insulating layer having a wider width than the gate electrode is formed on the first semiconductor layer, and a gate insulating layer is formed on the scanning line in a region other than the image display portion. The opening portion is formed on a portion of the protective insulating layer portion, on the first semiconductor layer, and on the first transparent insulating substrate, and is formed by laminating a second semiconductor layer containing impurities and a second metal layer having an upper layer or more. Source wiring (signal line), drain wiring (pixel electrode), and electrode terminal of a scanning line including a first semiconductor layer and a second semiconductor layer around the opening and composed of a second metal layer, and In the region other than the image display portion, a photosensitive organic insulating layer is formed on the signal line, except for the electrode terminal of the signal line composed of the partial signal line and the electrode terminal of the signal line. 12.  A liquid crystal display device having at least an insulating gate type transistor on a main surface, a scanning line serving as a gate electrode of the insulating gate type transistor, a signal line serving as a source wiring, and a connection to the insulating layer The pixel electrode of the gate of the gate type transistor and the unit pixel of the counter electrode formed by the distance of the above-mentioned pixel electrode with a distance of 101-(10) 1300873 are arrayed first. a transparent insulating substrate; and a liquid crystal display device formed by a second transparent insulating substrate or a crystal of a color filter opposite to the first transparent plate; characterized in that: at least one main body of the first transparent insulating substrate a counter electrode formed on the surface of the first metal layer and having an insulating layer on the side thereof, and one or more gate insulating layers are formed on the opposite electrode; more than one gate insulating layer is formed on the electrode and is not included In the bulk layer of the impurity, a wide-width gate electrode insulating layer is formed on the first semiconductor layer, and a gate is formed on the scanning line in a region other than the image display portion. A portion of the insulating layer is formed on the first semiconductor-transparent insulating substrate by a laminate of an anodizable metal layer of a second half or more containing impurities (signal line) and a drain wiring (pixel) And an electrode terminal including a first semiconductor layer and an upper semiconductor layer and a second semiconductor layer forming a scan line formed of a positive metal layer; and a signal line formed by a portion of the signal line in the image-displayed region In addition to the electrode terminals of the above signal lines, an anodized layer is formed on the surface of the source line. . The two-dimensional rectangular insulating layer is filled with a layer of a portion of the gate insulating layer on the gate insulating layer and the first layer of the gate and the first layer of the gate and the source layer and the source wiring. External electrode terminal • Bungee with -102- 1300873 (11) 13.  A liquid crystal display device having at least an insulating gate type transistor on a main surface, a scanning line serving as a gate electrode of the insulating gate type transistor, a signal line serving as a source wiring, and a connection to the insulating gate a pixel electrode of a pole of a polar transistor, and a first transparent insulating substrate in which a unit pixel of a counter electrode or the like formed at a specific distance from the pixel electrode is arranged in a two-dimensional matrix; and a liquid crystal display device comprising a liquid crystal display device interposed between a second transparent insulating substrate or a color filter opposed to the first transparent insulating substrate, and characterized in that: at least one main surface of the first transparent insulating substrate Forming a scan line and a counter electrode having one or more first metal layers and having an insulating layer on the side thereof, forming one or more gate insulating layers on the counter electrode; and forming one or more layers on the gate electrode a gate insulating layer and a first semiconductor layer containing no impurities, and a protective insulating layer having a width wider than that of the gate electrode is formed on the first semiconductor layer, On one of the layers, on the first semiconductor layer, and on the first transparent insulating substrate, a source wiring (signal line) composed of a second semiconductor layer containing impurities and a second metal layer of one or more layers is formed. • Bipolar wiring (pixel electrode), an electrode terminal formed on the first transparent insulating substrate and formed on the electrode terminal forming region of the scanning line and the signal line formed by the partial signal line in a region other than the image display portion A transparent insulating layer having an opening is formed, and a portion of the electrode terminal as a scanning line is exposed in the opening portion. 103 (12) 1300873 An electrode terminal for drawing a line and a signal line. 14.  A liquid crystal display device is a gate electrode type transistor on a main surface, a scan line which also serves as the insulating gate type transistor, a signal line which also serves as a source wiring, and a picture of a bungee which is connected to a front type transistor. a first transparent insulating substrate in which a unit pixel and a counter electrode formed at a predetermined distance from the pixel are arranged in a matrix; and a second transparent insulating substrate opposite to the first transparent plate or a liquid crystal display device comprising a color filter crystal, characterized in that: at least a first metal layer formed on one main surface of the first transparent insulating substrate is formed, and a side surface of the first transparent insulating substrate has an insulating layer counter electrode, An insulating layer is formed on the counter electrode, a gate insulating layer is formed on the gate electrode, and the impurity-free body layer is formed, and the protective insulating layer smaller than the first semiconductor layer is on the opposite side of the intersection of the scanning line and the signal line. Forming a smaller body layer and a protective insulating layer than the gate insulating layer and the gate insulating layer on the vicinity of the intersection of the line and on the opposite electrode and the pixel electrode, at the intersection of the scanning line and the signal line Forming a first semiconductor layer and a second semiconductor insulating layer containing impurities on the upper layer of the intersection of the opposite electrode and the opposite electrode and the pixel electrode to form a second semiconductor layer containing impurities on the gate electrode The upper part of the protective insulating layer, the first at least one of the gate electrodes, the insulating gate electrode is interposed between the two-dimensional rectangular insulating layer and the first layer of the scan line a semi-conductive layer, a gate insulator layer of the first semi-conducting and signal line near the intersection of the electrode and the signal, formed on the semiconductor layer -104-(13) 1300873 and the first transparent insulating substrate, containing impurities a source wiring (signal line), a drain wiring (pixel electrode), and an electrode terminal of a signal line composed of a part of signal lines, which are formed by laminating a second semiconductor layer and one or more anodizable metal layers, And including a part of the scanning lines in a region other than the image display portion and forming a product of the second semiconductor layer containing impurities and one or more anodizable metal layers on the first transparent insulating substrate Scan line electrode terminal constituted, in addition to the electrode terminal, an anodized layer is formed on the source • drain wiring surface. 15. The liquid crystal display device of the fifth aspect, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. 1 6. The liquid crystal display device of claim 5, wherein the first metal layer is formed of an anodizable metal layer and is formed in a scan. The insulating layer on the side of the line is an anodized layer. 17.  A method of manufacturing a liquid crystal display device comprising: at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, and a signal line serving as a source wiring, on one main surface; a unit transparent pixel connected to a pixel electrode of the drain wiring or the like, a first transparent insulating substrate arranged in a two-dimensional matrix; and a second transparent insulating substrate opposite to the first transparent insulating substrate or colored A method of manufacturing a liquid crystal display device comprising a liquid crystal between filters, characterized in that: at least on one main surface of the first transparent insulating substrate, sequentially coated: • 105-(15) 1300873 is transparent a conductive pixel electrode and an electrode terminal having a transparent conductive position on a signal line and a transparent conductive electrode terminal formed on the electrode terminal of the scanning line in a region other than the image display portion; A photosensitive resin pattern formed by a selection pattern of a pixel electrode and an electrode terminal serves as a mask to protect a transparent conductive pixel electrode and a transparent conductive electrode Son, while anodizing source • drain wiring project. A manufacturing method of a liquid crystal display device comprising at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, and a source wiring a first transparent insulating substrate in which a unit line of a signal line, a pixel electrode connected to the drain wiring, and the like are arranged in a two-dimensional matrix; and a second transparent insulating substrate opposite to the first transparent insulating substrate Or a method of manufacturing a liquid crystal display device comprising a liquid crystal display device, wherein the method further comprises: sequentially coating at least one main surface of the first transparent insulating substrate: one or more layers of the first metal a layer, a gate insulating layer of more than one layer, a first amorphous germanium layer containing no impurities, and a protective insulating layer; a film thickness corresponding to the scan line 'forming a protective insulating layer to form a thicker film than other regions Engineering of a resin pattern; sequentially etching the protective insulating layer, the first amorphous germanium layer, the gate insulating layer, and the first metal layer by using the photosensitive resin pattern as a mask Engineering; reducing the film thickness of the above-mentioned photosensitive resin pattern to expose the protective insulating layer; -107- (16) 1300873 leaving a protective insulating layer wider than the gate electrode on the gate electrode to expose the first non- The operation of the crystalline germanium layer; the process of forming the insulating layer on the side of the scanning line after removing the photosensitive resin pattern having a reduced film thickness; the engineering of completely covering the second amorphous germanium layer containing impurities; Forming source (signal line) and drain wiring composed of a second amorphous sand layer and a layer of a second metal layer or more, and forming a protective insulating layer on the first transparent insulating substrate In the electrode terminal forming region of the scanning line in the drain wiring and in the region other than the image display portion, and the transparent insulating layer having the opening portion on the electrode terminal of the signal line formed by the partial signal line; The electrode terminal of the scan line forms a gate insulating layer on the region to expose a portion of the scan line; and includes an opening in the drain wiring to be transparent A conductive pixel electrode is formed on the above transparent insulating layer. 1 9 A manufacturing method of a liquid crystal display device having at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, and a signal serving as a source wiring on a main surface a unit, a pixel element connected to the pixel electrode of the drain wiring, and the like, a first transparent insulating substrate arranged in a two-dimensional matrix; and a second transparent insulating substrate opposite to the first transparent insulating substrate or The invention relates to a method for manufacturing a liquid crystal display device which is formed by charging a liquid crystal between color filters, and has the following features: at least in the first transparency. On one main surface of the edge substrate, sequentially coated: -108- 1300873 (17) Transparent conductive layer, first metal layer, more than one gate insulating layer, first amorphous germanium layer without impurities, and protective insulation a process of forming a photosensitive resin pattern having a film thickness thicker than other regions on the protective insulating layer forming region corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line; The pattern is used as a mask to sequentially etch the protective insulating layer, the first amorphous sand layer, the gate insulating layer, the first metal layer, and the transparent conductive layer; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer Engineering; leaving a protective insulating layer wider than the gate electrode on the gate electrode to expose the first amorphous germanium layer; the photosensitive resin pattern having a reduced film thickness is removed, and the scan line is Engineering for forming an insulating layer on the side; engineering for completely covering the second amorphous layer containing impurities; on the pixel electrode and the region other than the image display portion, in the scanning line and signal Forming a photosensitive resin pattern having an opening on the dummy electrode terminal, and selectively removing the second amorphous germanium layer, the second amorphous germanium layer, the gate insulating layer, and the first metal layer in the opening portion, and a process of exposing a transparent conductive pixel electrode and an electrode terminal; and coating the protective layer with a portion and a second amorphous layer and a second metal layer after coating one or more second metal layers In an overlapping manner, a source wiring (signal line) having a photosensitive organic insulating layer on the surface of the electrode terminal including the signal line is formed, and a pixel containing the pixel-109 - (18) 1300873 is formed and is sensitized on the surface thereof. Engineering of the bungee wiring of the organic insulating layer. 20. A method of manufacturing a liquid crystal display device comprising: at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, and a signal serving as a source wiring; a unit, a pixel element connected to the pixel electrode of the drain wiring, and the like, a first transparent insulating substrate arranged in a two-dimensional matrix; and a second transparent insulating substrate opposite to the first transparent insulating substrate or A method of manufacturing a liquid crystal display device comprising liquid crystals between color filters, characterized in that: at least on one main surface of the first transparent insulating substrate, sequentially coated: a transparent conductive layer, a first metal a layer, a gate insulating layer of more than one layer, a first amorphous germanium layer containing no impurities, and a protective insulating layer; the film thickness on the region where the protective insulating layer is formed corresponding to the scan line and the pixel electrode is larger than other regions Engineering of a thick photosensitive resin pattern; using the above-mentioned photosensitive resin pattern as a mask, and sequentially engraving: protective insulating layer, first amorphous sand layer, gate insulating layer, first Engineering of the metal layer and the transparent conductive layer; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; leaving a protective insulating layer wider than the gate electrode on the gate electrode to expose the first non- Engineering of crystalline germanium layer; engineering of forming an insulating layer on the side of the scanning line after removing the photosensitive resin pattern having a reduced film thickness; engineering of completely covering the second amorphous germanium layer containing impurities; at the pixel electrode A photosensitive resin pattern having an opening on the analog electrode terminal of the scanning-110-(19) 1300873 line is formed in a region other than the image display portion, and the second amorphous germanium layer in the opening portion is selectively removed. An amorphous germanium layer, a gate insulating layer and a first metal layer to expose a transparent conductive pixel electrode and a portion of the scan line; after coating a layer of the second metal layer, a portion is formed and protected a source wiring (signal line) in which an insulating layer overlaps, a drain wiring in which a portion including a pixel electrode overlaps the protective insulating layer, and a transparent conductive layer containing the transparent conductive property An electrode terminal of a scanning line of a part of the scanning line, an electrode terminal corresponding to a signal line composed of a partial signal line in a region other than the image display portion, and a photosensitive organic insulating layer pattern having a thickness larger than that of other regions on the signal line The electrode is formed by selectively removing one or more second metal layers, a second amorphous germanium layer, and a first amorphous germanium layer by using the photosensitive organic insulating layer pattern as a mask to form scan electrodes and signal lines The work of the terminal and the source/drain wiring; and the process of reducing the film thickness of the photosensitive organic insulating layer pattern to expose the electrode terminals of the scanning lines and signal lines and the drain wiring. 2 1 - A method of manufacturing a liquid crystal display device having at least an insulating gate type transistor, a scanning line serving as a gate electrode of the insulating gate type transistor, and a source wiring a first transparent insulating substrate in which a unit line of a signal line, a pixel electrode connected to the drain wiring, and the like are arranged in a two-dimensional matrix; and a first transparent insulating substrate opposite to the first transparent insulating substrate Or a method for manufacturing a liquid crystal display device comprising a liquid crystal display device, wherein: -111 - (20) 1300873 is sequentially coated on at least one main surface of the first transparent insulating substrate. : a transparent conductive layer, a first metal layer, a gate insulating layer, a first amorphous germanium layer containing no impurities, and a protective insulating layer; corresponding to the scan line and the pixel electrode, forming a protective insulating layer forming region Engineering of a photosensitive resin pattern having a thicker film thickness than other regions; using the above-mentioned photosensitive resin pattern as a mask, sequentially uranium engraving: protecting 'insulating layer, first amorphous germanium layer, gate insulating layer Engineering of the first metal layer and the transparent conductive layer; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; leaving a protective insulating layer wider than the gate electrode on the gate electrode, and a process of exposing the first amorphous germanium layer; a process of forming an insulating layer on the side of the scanning line after removing the photosensitive resin pattern having a reduced film thickness; and a process of completely covering the second amorphous germanium layer containing impurities; A photosensitive resin pattern having an opening on the analog electrode terminal of the scanning line is formed on the pixel electrode and a region other than the image display portion, and the second amorphous germanium layer and the first amorphous material in the opening portion are selectively removed. a layer of a gate layer, a gate insulating layer, and a first metal layer to expose a transparent conductive pixel electrode and a portion of the scan line; after coating more than one layer of the anodizable metal layer, forming a portion overlapping the protective insulating layer a source wiring (signal line), a drain wiring including a pixel electrode forming portion overlapping the protective insulating layer, and a partial scan including the transparent conductive portion The electrode terminal on which the scanning line is formed, and the film thickness on the electrode terminal forming the scanning line and the signal line corresponding to the electrode terminal of the signal line formed by the partial signal line in the area other than the image portion 112-2 (21) 1300873 Projecting a photosensitive resin pattern thicker than a predetermined region; selectively removing one or more anodizable metal layers, a second amorphous germanium layer, and a first amorphous material using the photosensitive resin pattern as a mask In the enamel layer, the electrode terminal and the source drain wiring of the scanning line and the signal line are formed, the film thickness of the photosensitive resin pattern is reduced, the source/drain wiring is exposed, and the electrode terminal is protected. Anodizing source • Deuterium wiring works. twenty two.  A method of manufacturing a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on one main surface, a scanning line which also serves as a gate electrode of the insulating gate type transistor, a signal line which serves as a source wiring, and a connection The first pixel of the pixel electrode of the drain gate type of the insulating gate type transistor and the counter electrode formed by the specific distance from the pixel electrode is arranged in a two-dimensional matrix. An insulating substrate; and a method of manufacturing a liquid crystal display device comprising a second transparent insulating substrate facing the first transparent insulating substrate or a color filter, wherein the liquid crystal display device comprises: at least first a main surface of the transparent insulating substrate is sequentially coated: one or more first metal layers, one or more gate insulating layers, a first amorphous germanium layer containing no impurities, and a protective insulating layer; Scanning line, forming a film thickness ratio on the protective insulating layer forming region -113· (22) 1300873 Projecting a photosensitive resin pattern thicker in other regions; using the above photosensitive resin pattern Etching, sequentially etching: protecting the insulating layer, the first amorphous germanium layer, the gate insulating layer, and the first metal layer; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; An operation of exposing the first amorphous germanium layer to the gate electrode by leaving a protective insulating layer thinner than the gate electrode; and removing the photosensitive resin pattern having a reduced film thickness and forming an insulating layer on the side of the scan line Engineering of the layer; engineering of completely covering the second amorphous germanium layer containing impurities; forming a layer of the second amorphous germanium layer and one or more second metal layers by partially overlapping the protective insulating layer The source (signal line) and the drain wiring of the structure; and the signal terminal line formed by the electrode terminal forming region of the scanning line in the region other than the image display portion on the drain wiring and the signal line a step of forming a transparent resin layer having an opening on the electrode terminal on the second transparent insulating substrate; removing the electrode terminal forming region of the scanning line a gate insulating layer to expose a portion of the scanning line; and a conductive pixel electrode including an opening on the drain wiring; and a conductive counter electrode including a conductive line on the scanning line and the signal line; Engineering on the resin layer. twenty three.  A manufacturing method of a liquid crystal display device is a scanning line of a gate electrode having at least an insulating gate type transistor and a gate electrode of the insulating gate type transistor on a main surface -114-(23) 1300873 a signal line of the pole wiring, a pixel electrode connected to the drain of the insulating gate type transistor, and a pixel of the opposite electrode formed by a predetermined distance from the pixel electrode are arranged in a one-dimensional matrix. a transparent dielectric substrate; and a method of manufacturing a liquid crystal display device comprising a liquid crystal display device formed by filling a liquid crystal between a second transparent insulating substrate or a color filter facing the first transparent insulating substrate The method has: at least on one main surface of the first transparent insulating substrate, sequentially covering: one or more first metal layers, one or more gate insulating layers, a first amorphous germanium layer containing no impurities, and protection Engineering of the insulating layer; corresponding to the scanning line and the counter electrode, forming a photosensitive resin pattern having a thicker film thickness on the protective insulating layer forming region than other regions; The grease pattern is used as a mask to sequentially etch: a process of protecting the insulating layer, the first amorphous germanium layer, the gate insulating layer, and the first metal layer; and reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer Having a protective insulating layer that is wider than the gate electrode on the gate electrode, and exposing the first amorphous germanium layer; the above-mentioned photosensitive resin pattern having a reduced film thickness is removed after the scan line A process of forming an insulating layer on the side surface of the counter electrode; a process of completely covering the second amorphous germanium layer containing impurities; forming a region of -115-(24) 1300873 at the electrode terminal of the scanning line in a region other than the image display portion The opening portion 'selectively removes the second amorphous germanium layer, the first amorphous germanium layer, and the gate insulating layer in the opening portion to expose a portion of the scanning line; and after coating the second metal layer or more, forming a source wiring (signal line)/dipper wiring (pixel electrode) partially overlapping the protective insulating layer, and an electrode terminal including the opening portion forming a scanning line, and drawing An electrode terminal of a signal line composed of a part of signal lines is formed in a region other than the display portion, and a photosensitive organic insulating layer pattern having a thickness larger than that of other regions on the signal line is formed; and the photosensitive organic insulating layer pattern is used as a mask a cover for selectively removing the second metal layer, the second amorphous germanium layer, and the first amorphous germanium layer to form electrode terminals of the scan lines and signal lines and source/drain wiring: and reducing the above-mentioned light sensitivity The film thickness of the organic insulating layer pattern, and the electrode terminal of the scanning line and the signal line and the wiring of the drain wiring. A manufacturing method of a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on one main surface, a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal which also serves as a source wiring. a line, a pixel electrode connected to the drain of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a predetermined distance from the pixel electrode, and the like are arranged in a two-dimensional matrix. a transparent insulating substrate; and a method of manufacturing a liquid crystal display device comprising a second transparent insulating substrate or a color filter opposed to the first transparent insulating substrate; wherein the liquid crystal display device comprises: 116- (25) 1300873 is sequentially coated on at least one main surface of the first transparent insulating substrate: - a first metal layer above the layer, one or more gate insulating layers, and a first amorphous material containing no impurities a layer of a germanium layer and a protective insulating layer; a project of forming a photosensitive resin pattern having a thickness larger than that of other regions on the protective insulating layer forming region corresponding to the scanning line and the counter electrode; The photosensitive resin pattern is sequentially etched as a mask: a process of protecting the insulating layer, the first amorphous germanium layer, the gate insulating layer, and the first metal layer; and reducing the film thickness of the photosensitive resin pattern having reduced the film thickness And exposing the protective insulating layer; leaving a protective insulating layer wider than the gate electrode on the gate electrode to expose the first amorphous germanium layer; after the photosensitive resin pattern is removed, a process of forming an insulating layer on the side surface of the scanning line and the counter electrode; a process of completely covering the second amorphous germanium layer containing impurities; forming an opening in the electrode terminal forming region of the scanning line in a region other than the image display portion, and selecting The second amorphous germanium layer, the first amorphous germanium layer and the gate insulating layer in the opening portion are removed to expose a part of the scanning line; after coating one or more anodizable metal layers, a corresponding portion is formed The source wiring (signal line) and the drain wiring (pixel electrode) in which the protective insulating layer overlaps, and the electrode terminal including the opening portion forming the scanning line, and the image display The portion outside the portion corresponds to the electrode terminal of the signal line composed of the partial signal lines, and the film-117- (26) 1300873 on the electrode terminal forming the scanning line and the signal line is thicker than other regions of the photosensitive resin pattern engineering;.   Selectively removing the anodizable metal layer, the second amorphous germanium layer, and the first amorphous germanium layer by using the photosensitive resin pattern as a mask to form electrode terminals and source lines of scan lines and signal lines. The work of the bungee wiring; the process of reducing the film thickness of the photosensitive resin pattern to expose the source/drain wiring; and the process of protecting the electrode terminal and anodizing the source and drain wiring. 25.  A method of manufacturing a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on one main surface, a scanning line which also serves as a gate electrode of the insulating gate type transistor, a signal line which serves as a source wiring, and a connection The first pixel of the pixel electrode of the drain gate type of the insulating gate type transistor and the counter electrode formed by the specific distance from the pixel electrode is arranged in a two-dimensional matrix. An insulating substrate; and a method of manufacturing a liquid crystal display device comprising a second transparent insulating substrate facing the first transparent insulating substrate or a color filter, wherein the liquid crystal display device comprises: at least first a main surface of the transparent insulating substrate is sequentially coated: one or more first metal layers, one or more gate insulating layers, a first amorphous germanium layer containing no impurities, and a protective insulating layer; In the scanning line and the counter electrode, a photosensitive resin pattern having a thickness larger than that of other regions on the protective insulating layer forming region is formed; and the photosensitive resin pattern is used as the photosensitive resin pattern The cover is sequentially etched: the protective -118- (27) 1300873 edge layer, the first amorphous germanium layer, the gate insulating layer and the first metal layer are processed; the film thickness of the photosensitive resin pattern is reduced to expose the protection The operation of the insulating layer; leaving a wide gate electrode on the gate electrode to further protect the insulating layer, and exposing the first amorphous germanium layer; after the above-mentioned photosensitive resin pattern having reduced film thickness is removed, a process of forming an insulating layer between the scan line and the side surface of the counter electrode; a process of completely covering the second amorphous germanium layer containing the impurity; forming a second amorphous germanium layer by partially overlapping the protective insulating layer Source wiring (signal line) and drain wiring (pixel electrode) formed by laminating one or more second metal layers; forming a scan on the first transparent insulating substrate in a region other than the image display portion Engineering of a transparent insulating layer having an opening portion on an electrode terminal forming region of a line and an electrode terminal of a signal line composed of a part of signal lines; and removing an electrode terminal shape on the scanning line A gate insulating layer on the area, exposed portions of the scanning lines of the project. 26.  A method of manufacturing a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on one main surface, a scanning line which also serves as a gate electrode of the insulating gate type transistor, a signal line which serves as a source wiring, and a connection The pixel elements of the drain electrode of the insulating gate type transistor, the counter electrode formed by a specific distance from the pixel electrode, and the like are arranged in a two-dimensional matrix. a transparent insulating substrate; and a method of manufacturing a liquid crystal display device comprising a second transparent insulating substrate or a color filter interposed between the first transparent 119-(28) 1300873 insulating substrate and a color filter; The method is characterized in that: at least on one main surface of the first transparent insulating substrate, sequentially etching: one or more first metal layers, one or more gate insulating layers, and the first amorphous germanium layer containing no impurities And a process for protecting the insulating layer; corresponding to the scan line and the opposite electrode, formed on the gate electrode, the intersection of the scan line and the signal line, the intersection area of the counter electrode and the signal line, and the opposite electrode and the pixel Engineering of a photosensitive resin pattern having a film thickness thicker than other regions in the intersection region of the electrode; etching with the above-mentioned photosensitive resin pattern as a mask: protective insulating layer, first amorphous germanium layer, gate insulating Engineering of the layer and the first metal layer; engineering of forming an insulating layer on the side faces of the scanning line and the counter electrode; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer, Except for the protective insulating layer on the scan line and the counter electrode, the first amorphous germanium layer, and the gate insulating layer to expose the scanning line and the opposite electrode; further reducing the above-mentioned photosensitive resin pattern having a reduced film thickness a film thickness, leaving a protective insulating layer that is wider than the gate electrode on the gate electrode to expose the first amorphous germanium layer; a process of completely covering the second amorphous germanium layer containing impurities; After coating one or more layers of the anodizable metal layer, a source wiring (signal line) and a drain wiring (pixel electrode) partially overlapping the protective insulating layer are formed, and a portion other than the image display portion includes a partial scanning line shape. 120-(29) 1300873 is an electrode terminal of a scanning line and an electrode terminal corresponding to a signal line composed of a part of signal lines, and a process of forming a photosensitive resin pattern having a thickness larger than that of other regions on the electrode terminal; The photosensitive resin pattern serves as a mask to selectively remove the anodizable metal layer, the second amorphous germanium layer, and the first amorphous germanium layer to form a scan line and The electrode terminal of the line and the gate of the source/drain wiring are not required, and the thickness of the photosensitive resin pattern is reduced to expose the source/drain wiring; and the electrode terminal is protected and the anodizing source is protected. Extreme • Bipolar wiring and counter electrode engineering. 2 7. The method of manufacturing a liquid crystal display device according to claim 17, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. , formed by electroplating. The method of manufacturing a liquid crystal display device according to claim 17, wherein the first metal layer is formed of an anodizable metal layer. The insulating layer on the side of the scanning line is formed by anodization. -121 -