TWI300868B - - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device. [Prior Art] In recent years, the meticulous processing technology has been improved by liquid crystal material technology and high-density mounting technology, and the liquid crystal display device with a diagonal scale of 5 to 50 cm has been widely supplied with TV portraits or various image display machines. In the commercial field. At the same time, color display can be easily realized by forming a color layer of RGB in advance on one of the two glass substrates constituting the liquid crystal panel. Especially in every painting. On the so-called active LCD panel with built-in switching elements, it is guaranteed that images with less crosstalk and faster response and higher contrast can be obtained. Such liquid crystal display devices (liquid crystal panels), although scanning lines 2 00 to 1 0 0 0 are used as scanning lines, grouping the signal lines 3 00 to 1 600 to the most common composition. However, recently, the large screen and high refinement corresponding to an increase in display capacity have been simultaneously performed. Fig. 17 shows a state in which the liquid crystal panel is mounted, and constitutes a transparent insulating substrate which is one of the liquid crystal panels 1. For example, the electrode terminal group 5 for the scanning lines formed on the glass substrate 2 is connected by using a conductive adhesive. A COG (Chip On Glass) method of a semiconductor integrated circuit chip 3 for driving signals or a TCP film (not shown) having a gold-plated or plated solder copper foil (2), for example, using a polyimide film as a base layer 1300868 4 'A mounting means such as a TCP (Package Carrier Package) method in which the electrode terminal group 6 fixed to the signal line is crimped by a suitable adhesive containing a conductive medium, and an electric signal is supplied to the image display portion. Although two types of mounting methods are illustrated at the same time, any one of them can be appropriately selected. 7,8 is a line connecting the pixels in the image display portion at the center of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the scanning lines and the signal lines, and the electrode terminal groups 5 and 6 are not necessarily made of the same conductive material. Composition. 9 is a counter-glass substrate or a color filter of another transparent insulating substrate having a counter electrode having transparent conductivity common to all liquid crystal cells on the opposite surface. Fig. 1 is an equivalent circuit diagram showing an active liquid crystal display device in which an insulating gate type transistor 1 is disposed per pixel as a switching element, and 1 1 (7 in Fig. 17) is a scanning line, 12 (8 in Figure 1) is the signal line '1 3 is the liquid crystal single 兀' liquid crystal single 兀 1 3 is considered as a capacitive element on the circuit. The components drawn by the solid line are formed on the glass substrate 2 constituting one of the liquid crystal panels, and the counter electrode 14 common to all the liquid crystal cells 13 drawn by broken lines is formed on the other glass substrate 9. On the opposite side of the main. In the case where the OFF resistance of the insulating gate type transistor 1 or the resistance of the liquid crystal cell 13 is low or the gray scale of the image is emphasized, it is increased. . The auxiliary capacitor 1 5 as the time constant of the liquid crystal cell 13 of the load is improved in parallel with the circuit such as the liquid crystal unit 13 . Fig. 19 is a key sectional view showing an image display portion of the liquid crystal display device, and two glass substrates 2, 9 constituting the liquid crystal panel 1 are formed of a resin - 5 - 1300868 (3) fiber 'bead or colored A spacer (not shown) such as a columnar spacer on the filter 9 is formed at a predetermined distance of a distance of #m, and the gap (interval) is formed on the peripheral portion of the glass substrate 9. The sealing material and the sealing material (not shown) made of the organic resin form a sealed closed space, and the closed space is filled with the liquid crystal 17 . When the color display is realized, the closed space of the glass substrate 9 covers an organic film having a thickness of 1 to 2 " m of any one or both of the dyes or pigments of the colored layer 18, and provides a color display function, in this case The glass substrate 9 is also referred to as a color filter (abbreviated as CF). Further, depending on the nature of the liquid crystal material 17, a polarizing plate is attached to either the upper surface of the glass substrate 9 or the lower surface of the glass substrate 2, or the liquid crystal panel 1 is attached as a photovoltaic element. Features. At present, most of the liquid crystal panels sold on the market use TN (Twisted Nematic) liquid crystal, and the polarizing plate 19 usually requires two. Although not shown, the transmissive liquid crystal panel is provided with a back light source as a light source to illuminate white light from below. Connected to the liquid crystal 17 and formed on the two glass substrates 2, 9 such as thickness 〇.  The polyimine film 20 of 1 / m level is used to align the liquid crystal molecules with the alignment film which determines the direction. 2 1 is a drain electrode (wiring) connecting the gate electrode of the insulating gate type transistor 10 and the transparent conductive pixel 22, and is formed at the same time as the signal line (source line) 12. Located between the signal line 1 2 and the drain electrode 2 1 is a semiconductor layer 23, which will be described in detail later. The thickness formed on the color filter 9 is formed at the boundary of the adjacent color layer 18. The C r thin film layer of 4 V m is a so-called black matrix of a light shielding member for preventing external light from entering the semi--6 - (4) 1300868 conductor layer 2 3 and the scanning line 1 1 and the signal line 1 2 Referred to as Β Μ ) is a customary technology. Here, as a switching element, an insulating gate type transistor fabrication and manufacturing method will be described. At present, one of the commonly used insulating gate type transistors is one of them as a conventional example (referred to as an etch-off type). Figure 20 is a plan view showing a unit pixel of an active substrate (display semiconductor device) constituting a conventional liquid crystal panel, and Figure 21 is a cross-sectional view showing (e) A - A, Β - Β ' and C - C, The following is a brief description of its manufacturing process. First, as shown in Fig. 20 (a) and Fig. 2 1 (a), the thickness 选用 is selected as an insulating substrate having high heat resistance and chemical resistance and high transparency.  The glass substrate 2 of the μ m degree, for example, on the main surface of the product name 1 7 3 7 manufactured by Corning CORNING, is selectively formed by a film forming apparatus such as SPT (sputtering), such as Cr, Ta, Mo, or the like. Covering alloy or metal ruthenium compound film thickness 〇·1~〇. The first layer of the 3#m level, and by the microfabrication technique, selectively forms the scan line 1 1 and the storage capacitor line 16 which also serve as the gate 1 1 A. The material of the scanning line is preferably selected in consideration of heat resistance and chemical resistance, and resistance to fluorine acidity and conductivity. In order to correspond to the large screen or high-definition of the liquid crystal panel, the resistance of the P-line is determined by using aluminum as the material of the scanning line, but the aluminum is in a single state, because the heat resistance is relatively low, Laminated heat resistant metal such as Cl. , Ta, Mo or these metal ruthenium compounds, on the surface of the anodized additional oxide layer (A] 2 〇 3), etc., so that the device is shown in Figure 20 single and 5~1 .  1 Division Vacuum These metal electrodes: Comprehensive selection Low-scan is the above or belongs to (5) 1300868. Also, the scanning layer n (four) is formed by a gold layer above the working layer. Next, on the entire surface of the glass substrate 2, PC VD devices are used respectively. 3-0. The film thickness of 5 // mi m sequentially covers the 1 S Νχ (矽 矽) layer 30 as the gate insulating layer, and the first amorphous 矽 which is the channel of the insulating gate type crystal without impurities ( a -Si) layer 3 1, and a second thin film layer such as the second S i NX layer 3 2 as an insulating layer of the protective track, as shown in (b) and FIG. 2 1 (b), by microfabrication technology The second S 1N X layer 3 2 of the gate electrode 1 1 A is selectively left to be thinner than the gate electrode j as 3 2 A, and the first amorphous germanium layer 31 is exposed. Secondly, the same PCVD device is used to cover the entire surface. After the film having a thickness of 5 μm, including the second amorphous germanium layer 3 3 such as germanium, as shown in Fig. 20 (c) and Fig. 21 (c), the vacuum film forming using SPT or the like is sequentially covered. . 1 # ni degree of Ti, Cr, Mo and other metal-resistant films 3 4 as a metal-resistant layer, film thickness 〇 · 3 / m degree of aluminum film layer 3 5 is a low-resistance wiring layer, film thickness 〇.  The titanium film layer 3 of 1 #m is used as an interlayer conductive layer, and the three kinds of thin film layers 3 4 A ' 3 5 A ' 3 6 of the source/germanium wiring material are selectively formed by microfabrication technology. The drain electrode 2 1 of the insulating pole type transistor and the signal 1 2 also serves as the source electrode. The selective pattern is formed by using a photosensitive resin pattern for forming a source/drain electrode as a mask, and sequentially etching the Ti film 36, the film layer 35, and the film layer 3 of the Ti film. Thereafter, the second amorphous germanium layer 33 between the source and the electrode 2 and 21 is removed to expose the second SiNx, and the first amorphous germanium layer 3 1 is removed in other fields. 1 A process such as layering for the middle pole line layer layer layer exposed (6) 1300868 gate insulator layer 30 formed. Thus, the etching of the second amorphous germanium layer 3 3 is automatically completed by the first layer 2 S iNX layer 3 2 A of the protective layer of the channel. This method is called an etch-off method. In order to prevent the insulating gate type transistor from becoming an offset structure, the source/drain electrodes 1 2, 2 1 are formed in a planar manner overlapping with the gate electrode 1 1 A (several μ μm). . This overlap has an electrical effect of parasitic capacitance', so the smaller the better, it is usually determined by the alignment precision of the exposure machine and the precision of the mask, the expansion coefficient of the glass substrate, and the temperature of the glass substrate during exposure. The maximum number is 2 // m. Next, on the entire surface of the glass substrate 2, a PCVD apparatus was used in the same manner as the gate insulating layer, and the film thickness as a transparent insulating layer was covered. The SiNx layer of 3 #m is used as a passivation insulating layer 37, as shown in Fig. 20 (d) and Fig. 2 1 (d), by selectively removing the passivation insulating layer 3 by microfabrication technique. The gate electrode 2 1 is formed with an opening portion 6 2, and an opening portion 63 is formed at a position where the electrode terminal 5 of the scanning line 11 is formed outside the image display portion, and the electrode terminal 6 at which the scanning line 12 is formed The opening portion 64 is formed at a position to expose the drain electrode 2 1, and a portion of the scanning line 1 and the signal line 1 2 . On the storage capacitor line 16 (electrode pattern to be collected in parallel), an opening portion 65 is formed to expose one of the storage capacitor lines 6.5. Finally, a vacuum film forming apparatus such as SPT is used to cover the film thickness. ;[~〇. 2 # m degree such as IT 0 (indium tin oxide) or 1Z 0 (indium zinc oxide) as a transparent conductive layer, as shown in Figure 20 (e) and Figure 2 (e), by microfabrication The technique includes an opening portion 6 2 and a passivation insulating layer 3 7 -9- 1300868 (7) to selectively form the pixel electrode 2 2 to complete the active substrate 2. One portion of the exposed scanning line in the opening portion 63 is used as the electrode terminal 5, and a portion of the signal line 1 2 exposed in the opening portion 64 is used as the electrode terminal 6 as shown in the figure. The opening portions 63, 64 are formed on the passivation insulating layer 37, and the electrode terminals 5 A, 6 A formed by IT 0 are selectively formed, but generally, the transparent conductivity between the electrode terminals 5A, 6A4 is also formed at the same time. Short circuit 4 0. The reason for this is that the electrode terminals 5 A, 6A and the short-circuit line 40 are formed in a stripe shape and are highly resistive, although they are not shown, and can be used as a high resistance for static electricity countermeasures. Similarly, the electrode portion of the storage capacitor line 16 is formed by including the opening portion 65. When the wiring resistance of the signal line 12 is not a problem, the low-resistance wiring layer 35 formed of aluminum is not necessarily required. In this case, if a heat-resistant metal material such as Ci, Ta, Μ or the like is selected, it can be single-layered. The source and drain wirings 1 2, 2 1 are simplified. Further, the heat resistance of the insulated gate type transistor has been described in detail in Japanese Laid-Open Patent Publication No. Hei 7-74 3 68. Meanwhile, in FIG. 20(c), the storage capacitor line 16 and the drain electrode 2 are interposed by the gate insulating layer 30 and overlap the field 50 (the upper left to the lower right oblique line), although the storage capacitor is formed] 5, but the detailed description thereof is omitted here. The five mask processes described above, although the detailed description is omitted, are the result of a one-way reduction of the islanding project and the contact formation project of the semiconductor layer. Therefore, the project of 7 to 8 degrees was originally required. The introduction of dry etching technology has been reduced to five lanes today, which has greatly contributed to the reduction of process costs. In order to reduce the production cost of the liquid crystal display device, the manufacturing process of the active substrate reduces the process cost, and in the panel assembly engineering and module installation -10- 1300868 (8) The reduction of component cost is an effective development practice. In order to reduce the cost of the process, there are also process development or replacement processes that use the process of shortening the process to reduce the size of the process and the production process. However, the four mask processes of the active substrate with four masks are used as engineering reductions. Explain by way of example. The four-mask process introduces a halftone (ha丨ft 〇η ^ ) exposure technique and reduces the photo-touching process. Therefore, Figure 22 is a plan view of the unit pixel corresponding to the active substrate of the four-mask process. Figure 23 shows Figure 22(e) is a cross-sectional view taken along line A - A ', B - B ' and C - C '. As described earlier, there are two types of insulating gate type crystals which are commonly used, and a channel-etch type insulating gate type transistor is used here. First, as in the case of the five mask processes, the first metal layer of the film thickness is covered on the main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, as shown in Fig. 22 (a) and Fig. 23 (a). The scanning line 1 1 serving as the gate electrode 1 1 A and the storage capacitor line 16 are selectively formed by a micromachining technique. Next, in the entire glass substrate 2, the p C v 〇 device is used to sequentially cover the thickness of the film, and the S iN X layer 30 which becomes the gate insulating layer is almost free of impurities and becomes an insulating gate type transistor. The first amorphous germanium layer 3 1 of the channel and the impurity of the impurity become the source of the insulating gate type transistor. Three kinds of thin film layers such as the second amorphous germanium layer 3 3 of the bungee. Then, a vacuum film forming apparatus such as SPT is used to sequentially cover, for example, a film thickness 〇 1 " m of the Ti film layer 34 as a ruthenium metal layer 35, and a film thickness 〇 · 3 /im degree, for example, for example The aluminum thin film layer 35 is used as a low resistance wiring layer and has a film thickness of 0.  1 # m degree, for example, film thickness 0.  ] μ m degree, for example, Ti -11 - 1300868 (9) The thin film layer 36 is used as an intermediate conductive, that is, sequentially covering the source and drain wiring materials, and selectively forms an insulating gate type transistor by a microfabrication technique. The signal line 12 of the drain electrode 2 1 and the source electrode is characterized by a halftone exposure technique when forming the selection pattern, as shown in FIGS. 22(b) and 23(b). It is shown that the channel thickness of the channel between the source and the drain wiring is 80 C (the lower left oblique line), for example, 1. 5 m, photosensitive resin patterns 80A to 80C which are thinner than the source/drain wiring formation areas 80A and 80B and having a film thickness of 3 m are formed. In the photosensitive resin patterns 80 A to 80C, the positive photosensitive resin is usually used for the production of the substrate for a liquid crystal display device. Therefore, the source/drain wiring formation regions 80 A and 80B are black, that is, the Cr film is formed. The channel area 80C is gray, such as forming a width of 0. The line pattern of the line and space of 5 to 1 μm is white, and the other areas are white, that is, the mask for removing the Cr film can be used. In the gray field, because the resolution of the exposure machine is insufficient, the line and S pace are not imaged, and the illumination light from the light source to the reticle can be transmitted through about half, so it is suitable for the positive photosensitive resin. The photosensitive resin patterns 80 A to 80C having the cross-sectional shape as shown in Fig. 23 (b) can be obtained by the residual film characteristics. The photosensitive resin patterns 80A to 80C are used as masks, and as shown in FIGS. 22(b) and 23(b), the Ti thin film layer 36, the A1 thin film layer 35, and the Ti thin film layer 34 are sequentially etched. After the amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1 are exposed to the gate insulating layer 30, as shown in FIG. 22 (c) and FIG. 23 (c), by oxygen plasma or the like The ashing means makes the film thickness of the photosensitive resin patterns 80A to 80C, for example, from 3 vm]. 5 " m or more 1300868 (10) 8 1 A, 8 1 B, 8 0 C disappears to reveal the channel area. Here, the photosensitive resin patterns 80 A to 80C of the film are reduced as a mask, and the T丨 film layer 3 6 A of the source/drain wiring line (channel formation region) is sequentially etched again, and the film layer 3 is formed. 5 A, T i thin film layer 3 4 A, second amorphous germanium layer 3 3 A and first amorphous germanium layer 3 1 A, first amorphous germanium layer 3 ] A is etched to residual 0. 0 5~0 „ 1 // m degree. The reason for the channel etching is formed by etching the semiconductor into the channel. In addition, it is preferable to suppress the anisotropy of the pattern size in the above oxygen plasma treatment. The reason for this will be described later. Further, after removing the photosensitive resin patterns 8 1 A, 8 1 B, the five mask processes are also shown in Fig. 22 (d) and Fig. 23 (d), in the glass. The SiNx layer of the substrate 2 having a total thickness of #·3 # m is used as a transparent insulating layer, and the electrode terminals 5 and 6 forming the gate electrode 2 1 and the scanning line 1 1 and the signal line 1 2 are formed. The opening portions 62, 63, 6 4 ' are respectively formed to remove the passivation insulating layer 37 and the gate insulating layer 30 in the opening portion. Finally, the film thickness is covered by a vacuum film forming apparatus such as SPT. 1~0. 2 μ ηι degree such as I τ 0 or IZ 0 as a transparent conductive layer, as shown in 2 2 (e ) and FIG. 23 (e), the micro-processing technique is used to include an opening in the passivation insulating layer 37 The portion 6 2 selectively forms the transparent conductive pixel electrode 22 to complete the active substrate 2 with respect to the electrode terminal, and includes openings 63 and 64 therein to selectively form the electrode terminal 5 A formed of ITO on the passivation insulating layer 37. , 6 A. Thus, in the five mask process and the four mask process, since the contact hole forming process of the gate electrode 2 1 and the scanning line 11 is simultaneously performed, 13-1300868 (11) corresponds to the opening portion of the same. The thickness of the insulation layer in 62, 63 is different from the type. The passivation insulating layer 37 has a lower film forming temperature than the gate insulating layer 30 and has a poor film quality. When etching by a fluoric acid-based oxygen etching solution, the etching rate is several thousand angstroms (A)/minute and several hundreds, respectively. An angstrom (A)/min, which differs by an order of magnitude, and the cross-sectional shape of the opening portion 6 2 on the drain electrode 2 1 cannot be controlled by excessive etching of the upper portion, so dry etching using a fluorine-based gas (dry etching) is employed. . Even if the dry etching is used, since the opening portion 62 of the drain electrode 2 1 is only the passivation insulating layer 3 7, the overetching cannot be avoided compared to the opening portion 63 of the scanning line, and the intermediate conductive layer is different depending on the material. 3 6 A is sometimes thinned by etching gas. Further, when the photosensitive resin pattern is removed after the etching is completed, first, in order to remove the polymer of the surface to be fluorinated, the surface of the photosensitive resin pattern is reduced by oxygen plasma ashing.  1~〇.  3 / m degree, after that, generally, an organic stripping liquid, such as a liquid stripping liquid 106 manufactured by Tokyo Yinghua Co., Ltd., is used, but when the intermediate conductive layer 36A is thinned to expose the base aluminum layer 3 5 A At the time, Al2〇3 which forms an insulator on the surface of the aluminum layer 35A by oxygen plasma ashing treatment cannot obtain an ohmic contact with the pixel electrode 22. Therefore, in order to make the intermediate conductive layer 36A even if the film thickness is reduced, the film thickness is set to 0. A thick film thickness of 2 A m to avoid this problem. Alternatively, when the openings 62 to 6 5 are formed, the aluminum layer 35A may be removed, and the mask electrode 2 may be removed from the thin film layer 34A of the underlying heat resistant metal layer, and the countermeasure may be avoided. In this case, there is no The benefit of the intermediate conductive layer 3 6 A is required. However, in the countermeasures of the former, when the film thickness of these films is 14-1300868 (12), the uniformity is not good, and when the uniformity within the etching rate is not good, It is also identical. In the latter countermeasure, although the intermediate conductive layer 3 6 A is required, the process of removing the aluminum layer 35 A is increased, and when the cross-section control of the opening portion 62 is insufficient, the pixel electrode may be broken. In addition, on the channel-etched insulating gate type transistor, the first amorphous germanium layer 3 1 containing no impurities in the channel region is not covered in advance (the channel etching type is usually 〇.  When 2 / m or more, the in-plane uniformity of the glass substrate is greatly affected, so that the characteristics of the transistor, particularly the current holding current, tend to be jagged. This matter will have a considerable impact on the working rate of P C V D dust, which is also very important from the point of view of production cost. In addition, the channel formation process applied in the 4-mask process is due to the selective removal of the source of the source/drain wiring 1 2, 2 1 . 配线 The wiring material and the semiconductor layer are the projects that determine the channel length (4 to 6 m in current quantities) that greatly affects the ON (ON) characteristics of the insulated gate type. The change in the length of this channel, due to the large change in the on-state current of the insulating gate transistor, usually requires strict manufacturing management, which is the channel length, that is, the size of the exposure in the field of halftone (ha]ftone). The amount (the intensity of the light source and the pattern precision of the mask, the line and the blank line size), the coating thickness of the photosensitive resin, the development processing of the photosensitive resin, and the film thickness of the photosensitive resin in the etching process, and the like The influence of the in-plane uniformity of these quantities may not be able to improve the yield and stabilize the production, compared to the conventional manufacturing surface and the cross-section of the 22-thickness is the 5 pole body β pole but the figure is Reducing this pipe -15- 1300868 (13) requires more stringent manufacturing management, and it is still not a high level of completion. Especially when the channel length is less than 6〆m, the tendency is more obvious. The invention has been completed in view of the present situation, and not only avoids flaws in the formation of contact holes common to the conventional five-mask process or four-mask process, but also employs a halftone exposure with a large manufacturing tolerance. Technology to achieve reduced manufacturing engineering. At the same time, in order to reduce the cost of liquid crystal panels, it is easy to understand the need to more carefully pursue the reduction of manufacturing engineering in response to the increase in demand. By simplifying or reducing the cost of other major manufacturing engineering technologies, The price of the present invention. SUMMARY OF THE INVENTION In the present invention, a halftone exposure technique is first applied to a formation process of an etch stop layer in which pattern precision management is easy, and a contact hole formation process is performed to reduce a manufacturing process. Next, in order to effectively passivate only the source/drain wiring, the anode of the insulating layer formed on the surface of the source/drain wiring formed of aluminum is disclosed in Japanese Laid-Open Patent Publication No. Hei 2-2 16 129. Oxidation technology to achieve process rationalization and low temperature. Further, the formation of a pixel electrode disclosed in Japanese Patent Application Laid-Open No. Hei No. Hei. In order to further reduce the engineering, the anodized layer of the source and the drain wiring is formed, and the halftone (halftone) exposure technique is also used to rationalize the protective layer formation process of the electrode terminal. The insulated gate type transistor described in claim 1 is characterized in that it has a protective insulating layer on the channel to include a conductive material different from the source · -16- (14) 1300868 bungee wiring material. An insulating gate type transistor having a bottom gate type of a photosensitive organic insulating layer formed on a source/drain wiring formed by one of the electrical connection areas of the source wiring formed, and having a photosensitive organic Since the insulating layer functions as a passivation protection, it is not necessary to provide a protective insulating layer such as SiNx, and the correlation of the liquid crystal display device is clearly described in the fifth and second embodiments of the patent application. The insulated gate type transistor described in the second paragraph of the patent application is characterized in that it has a protective insulating layer on the channel, and a photosensitive organic insulation is formed only on the source wiring except for the electrical connection field of the source wiring. The gate-type insulated gate type transistor of the bottom layer of the layer has a passivation function, so that it is not necessary to provide a protective insulating layer such as SiNx, and the correlation with the liquid crystal display device is in the scope of patent application. The 8, 10, and 3, 5, and 7 embodiments are clearly described. The insulated gate type transistor described in the third paragraph of the patent application is characterized in that it has a protective insulating layer on the channel, and the source/drain wiring is formed by an anodizable metal layer, and at the same time, the electric source except the source wiring In addition to the connection field, an insulating gate type transistor of the bottom gate type of the anodized layer is formed on the source/drain wiring, and the anodized layer is provided with a passivation function, so that it is not necessary to provide a protective insulating layer such as SiNx. Further, the liquid crystal display device is clearly described in the fourth, seventh, ninth, and eighth embodiments of the patent application, and the first, fourth, sixth, and eighth embodiments. The insulated gate type transistor of the fourth aspect of the patent application has a minimum of an insulated gate type transistor on a main surface, and a scan line which also serves as a gate electrode of the insulated gate type transistor, and It also serves as a signal line for the source wiring (15) 1300868, and a second transparent dielectric substrate in which the unit pixels connected to the pixel electrodes of the drain wiring are arranged in a two-dimensional matrix, and The second transparent insulating substrate of the first transparent insulating substrate or the liquid crystal display device in which the color filter and the optical sheet are filled with crystals; the feature is at least one main surface of the first transparent insulating substrate a scanning line formed of one or more metal layers is formed; one or more gate insulating layers are interposed on the gate electrode, and the semiconductor layer containing no impurities is formed into an island shape; a protective insulating layer having a width wider than the gate is formed on the first semiconductor layer on the electrode; and a second semiconductor layer containing impurities is formed on a portion of the protective layer and the first semiconductor layer Lamination with an anodically oxidizable metal layer The source/drain wiring is formed on one of the drain wirings and the gate insulating layer, and is formed on the signal line in a field outside the transparent conductive pixel electrode and the pixel display portion. An electrode terminal having a transparent conductivity; an anodized layer is formed on the surface of the source/drain wiring except for the region overlapping the pixel electrode of the drain wiring and the electrode terminal region of the signal line. With this configuration, a protective insulating layer is formed on the channel between the source and the drain, and at the same time as the protective channel, an insulating anodized layer is formed on the surface of the signal line and the drain wiring. a 2 0 5 ) ' or alumina (A 12 0 3 ) provides a passivation function. Therefore, it is not necessary to cover the passivation insulating layer on the entire surface of the glass substrate, so the heat resistance of the insulated gate type transistor is no longer a problem. A TN type liquid crystal display device having transparent conductive electrode terminals can be obtained. The liquid crystal display device of the fifth aspect of the invention is characterized in that the layer 18-1300868 (16) is formed of a layer of a transparent conductive layer and a first metal layer on at least one main surface of at least the first transparent insulating substrate. a scan line composed of a product and a transparent conductive pixel electrode and a same signal line electrode terminal; a first semiconductor layer containing no impurity is formed on the gate electrode by a plasma protective layer and a gate insulating layer in an island shape a protective insulating layer which is wider than the gate electrode is formed on the first semiconductor layer on the gate electrode; a plasma protective layer and a gate insulating layer on the pixel electrode form an opening portion; a portion of the protective insulating layer and a portion of the first semiconductor layer and the electrode terminal of the signal line are formed by laminating a second semiconductor layer containing impurities and a second metal layer or more. a source (signal line) wiring, and a portion of the protective layer on the first semiconductor layer and a portion of the pixel electrode in the opening portion, also forming a drain wiring; Polar wiring A photosensitive organic insulating layer. With this configuration, a protective insulating layer is formed on the channel between the source and the drain, and a photosensitive organic insulating layer is formed on the surface of the signal line and the drain wiring to provide a passivation function while protecting the channel. Therefore, the heat resistance of the insulated gate type transistor is no longer a problem in that the entire surface of the glass substrate does not need to cover the passivation insulating layer. Further, a TN type liquid crystal display device having transparent conductive electrode terminals can be obtained. The liquid crystal display device of claim 6 is characterized in that at least one of the main surfaces of the first transparent insulating substrate forms a scan formed by laminating the transparent conductive layer and the metal layer. a line and a transparent conductive pixel electrode; a plasma protective layer and a gate insulating layer are interposed on the gate electrode to form an impurity-free first semiconductor layer; and the gate electrode is -19-1300868 (17) a protective insulating layer which is wider than the gate electrode is formed on the semiconductor layer of the upper electrode; the plasma protective layer and the gate insulating layer on the pixel electrode form an opening; and the protective insulating layer a source (signal line) wiring formed by laminating a second semiconductor layer containing impurities and a second metal layer containing one or more layers on the first and second semiconductor layers, and one of the protective layers A portion of the pixel electrode is formed on the first semiconductor layer and a portion of the pixel electrode in the opening portion, and a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the signal line. With this configuration, a protective insulating layer is formed on the channel between the source and the drain to form a photosensitive organic insulating layer on the surface of the signal line while providing a passivation function while protecting the channel. Therefore, the heat resistance of the insulated gate type transistor is no longer a problem in that the entire surface of the glass substrate does not need to cover the passivation insulating layer. A TN type liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained. A liquid crystal display device according to claim 7 is characterized in that at least one of the main surfaces of the first transparent insulating substrate is formed with a scanning line and a transparent conductive layer formed by laminating a transparent conductive layer and a metal layer. a pixel electrode; a first semiconductor layer containing no impurities is formed on the gate electrode via a plasma protective layer and a gate insulating layer; and the gate is formed on the first semiconductor layer on the gate electrode a protective insulating layer having a wider electrode; and a plasma protective layer and a gate insulating layer on the pixel electrode; forming an opening; and forming a portion of the protective insulating layer and the first semiconductor layer a source (signal line) wiring composed of a second semiconductor layer containing impurities and a layer of an anodizable metal layer, and a portion of the protective layer -20-1300868 (18) and the first semiconductor On the layer and on the first transparent insulating substrate and on a portion of the pixel electrode in the opening, a drain wiring is also formed; except for the electrode terminal of the signal line, anodization is formed on the surface of the source/drain wiring. Floor. With this configuration, a protective insulating layer is formed on the channel between the source and the drain, and at the same time as the protective channel, the insulating anodic oxide layer 5 is formed on the surface of the signal line and the drain wiring (Ta2). 〇5), or alumina (Α12 Ο 3 ) provides passivation. Therefore, it is not necessary to cover the passivation insulating layer on the entire surface of the glass substrate, so the heat resistance of the insulated gate type transistor is no longer a problem. Further, a TN type liquid crystal display device having an electrode terminal having the same metallicity as the signal line can be obtained. The liquid crystal display device of claim 8 is characterized in that it has at least an insulating gate type transistor on one main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source. a signal line of the pole wiring, and a pixel pixel connected to the drain of the source gate type transistor, and a pixel of the opposite electrode formed by a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix. A liquid crystal display device in which a first transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with a liquid crystal; and is characterized in that at least A scanning line and a counter electrode formed of one or more metal layers are formed on one main surface of the first transparent insulating substrate, and one or more gate insulating layers are formed in an island shape on the gate electrode. An i-th semiconductor layer containing no impurities; a protective insulating layer which is wider than the gate electrode is formed on the semiconductor layer on the gate electrode; and a portion of the protective layer is 21 - 1300868 (19 ) and the first semiconductor a source (signal line, and a drain wiring (pixel electrode)) formed by laminating a second metal layer having one or more second semiconductor layers containing impurities; and a signal other than the electrode of the signal line A photosensitive organic insulating layer is formed on the line; the sub-layer of the scanning line is formed in the field outside the image display portion, and includes a second metal layer formed on the opening of the scanning gate insulating layer. On the channel between the drains, a rim layer is formed to protect the channel, and the signal line and the drain are also matched to form an insulating anodized layer of molybdenum oxide (TasOf alumina (A 1 2 0 3 )). The passivation function is provided. Therefore, the passivation insulating layer is not required to be covered on the glass surface, so that the resistance of the insulating gate type transistor is further problematic, and an IPS type liquid crystal display device having the same metallicity as the signal line can be obtained. The liquid crystal display device of the ninth aspect is characterized in that at least one of the main surfaces of the first transparent insulating substrate is formed with a scanning line and a counter electrode formed of the upper metal layer; and one or more layers are electrically connected to the gate. Extremely Forming a conductor layer containing no impurities in an island shape; forming a protective insulating layer which is wider than the electrode electrode on the first semiconductor layer on the gate electrode; on one of the protective layer and the first semiconductor layer, Forming a source (signal line) and a drain wiring (pixel electrode) composed of a laminate of a metal layer oxidized by the second semiconductor containing impurities; the electrode terminal except the signal line is formed on the surface of the source/drain wiring An anodized layer; a sub-electrode of the scanning line, in the field outside the image display portion, a table comprising a protective line formed on the electrode end line formed on the scanning line body layer and the wire), or a full thermal non-electrode end of the substrate The layer is composed of an upper layer of the first half of the upper portion of the pole and an anodizable metal layer which is formed by wiring the opening and the opening of the gate insulating layer 22-1300868 (20). With this configuration, a protective insulating layer is formed on the channel between the source and the drain, and at the same time as the protective channel, the insulating anodic oxide layer 5 is formed on the surface of the signal line and the drain wiring (Ta2). 0 $ ), or alumina (Α12 Ο 3 ) provides passivation. Therefore, the heat resistance of the insulated gate type transistor is no longer a problem in that the glass substrate does not need to cover the passivation insulating layer in its entirety. Further, an I P S type liquid crystal display device having an electrode terminal having the same metallicity as the signal line can be obtained. The liquid crystal display device of the first aspect of the invention, characterized in that the scanning line and the counter electrode formed of one or more metal layers are formed on at least one main surface of the first transparent insulating substrate; One or more layers of the gate insulating layer are interposed in the gate electrode to form a first semiconductor layer containing no impurities; and the first semiconductor layer on the gate electrode is formed to have a finer width than the gate electrode. An insulating layer; a source (signal line) wiring formed by laminating a second semiconductor layer containing impurities and a second metal layer containing one or more layers on a portion of the protective layer and the first semiconductor layer And a drain wiring (pixel electrode); a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the signal line; and the electrode terminal of the scanning line is outside the image display portion, and is formed on the scanning line. The second metal layer formed by the opening of the gate insulating layer is formed by lamination with the second metal layer. With this configuration, it is approximately the same structure as the liquid crystal display device described in the eighth item of the patent application, and an I P S type liquid crystal display device having a short manufacturing process can be obtained. -23- 1300868 (21) A liquid crystal display device according to the πth item of the patent application, characterized in that a scanning line composed of a metal layer of at least one layer is formed on at least one main surface of the first transparent insulating substrate And a counter electrode; a gate insulating layer is formed on the gate electrode to form a first semiconductor layer containing no impurities; and a first semiconductor layer on the gate electrode is formed on the first semiconductor layer a protective insulating layer having a wider electrode; and a source formed by laminating a second semiconductor layer containing impurities and an anodizable metal layer on a portion of the protective layer and the first semiconductor layer (signal line) wiring and drain wiring (pixel electrode); an anodized layer is formed on the surface of the source/drain wiring except for the electrode terminal of the signal line; the electrode terminal of the scanning line is outside the pixel display portion The field is formed by laminating a second semiconductor layer and an anodizable metal layer including an opening portion of a gate insulating layer formed on a scanning line. With this configuration, it is approximately the same structure as the liquid crystal display device of the ninth application of the patent application, and an IPS type liquid crystal display device having a short manufacturing process can be obtained. The method of manufacturing a liquid crystal display device according to claim 4, wherein the method of manufacturing a liquid crystal display device according to claim 4 is characterized in that at least one metal layer is formed on one main surface of the first transparent insulating substrate. The construction of the scan line formed by the layer; sequentially covering the gate insulating layer of one or more layers, and the first amorphous germanium layer containing no impurities, and the process of protecting the insulating layer; in the field of electrode terminal formation of the scan line, Forming a photosensitive resin pattern having an opening portion and a thickness of a protective insulating layer formed on the gate electrode in a field of thickness greater than that of other fields; removing the protective insulating layer in the opening portion and the first! -24- (22) 1300868 Amorphous germanium layer and gate insulating layer, which exposes the electrode terminal forming field of the scanning line; reduces the film thickness of the photosensitive resin pattern to expose the protective insulating layer; a process of exposing the insulating layer to a first amorphous layer on the electrode, and a process of completely covering the second amorphous layer containing impurities after removing the photosensitive resin pattern; a method of forming a source (signal line) and a drain wiring formed by laminating a second amorphous germanium layer and one or more layers of anodizable metal layers, in a manner overlapping the protective layer portion; a part of the gate insulating layer and the drain φ wiring, in the field of the transparent conductive pixel electrode and the image display portion, forming a transparent conductive electrode terminal on the signal line; The photosensitive resin pattern formed by the selective pattern of the element electrode and the electrode terminal serves as a mask to protect the pixel electrode and the electrode terminal 'and to oxidize the source and drain wiring. With this configuration, the formation of the etch-off layer and the islanding process of the semiconductor layer can be processed by using one mask, and the number of photographic etching processes can be reduced. Further, when the pixel electrode is formed, the source/drain wiring φ can be anodized without the need to form a passivation insulating layer, and the TN liquid crystal display device can be manufactured by using four photomasks. Patent Document No. 13 is a manufacturing method of a liquid crystal display device according to claim 5; characterized in that at least one of the main surfaces of the first transparent insulating substrate is formed of a transparent conductive layer and The pseudo-electrode terminal of the scanning line and the signal line formed by the lamination of the metal layer of I and the pseudo-pixel electrode; the plasma protective layer and the gate insulating layer and the first amorphous germanium layer containing no impurities are sequentially covered. And the protection of the insulating layer; on the scan line -25-1300868 (23) and the electrode terminal of the signal line form a field and a pseudo-pixel electrode, forming a film having an opening portion and a protective insulating layer formed on the gate electrode Thick, thicker than other areas of the photosensitive resin pattern; remove the protective insulating layer in the opening and the first amorphous layer and the gate insulating layer and the plasma protective layer and the first metal layer, and transparent The conductive scan line and the electrode terminal of the signal line form the same field to expose the pixel electrode; the film thickness of the photosensitive resin pattern is reduced to expose the protective insulating layer; on the gate electrode, a process of exposing the first amorphous germanium layer by a protective insulating layer having a wider width than the gate electrode; and removing the photosensitive resin pattern to cover the entire second amorphous germanium layer containing impurities; covering one layer or more After the second metal layer, an electrode terminal forming region including a second amorphous germanium layer and a second metal layer of one or more layers and having a signal line partially overlapped with the protective insulating layer is formed on the surface thereof. A pixel electrode having the same source wiring (signal line) as the photosensitive organic insulating layer is formed to form a drain wiring. With this configuration, the number of photolithographic processes for processing the pixel electrodes and the scanning lines can be reduced by using one mask, and the formation of the etching-cut layer and the islanding process of the semiconductor layer can be processed by using one mask, thereby achieving reduction. Photography etching engineering number. Further, when the source/drain wiring is formed, the photosensitive organic insulating layer to be used is reduced, and the manufacturing process for forming the passivation insulating layer is no longer required. As a result, a TN liquid crystal display device can be produced by using three masks. Patent Application No. 14 is a manufacturing method of a liquid crystal display device described in claim 6; characterized in that it is at least one of the main surfaces of the transparent insulating substrate -26-1300868 (24) Forming a scan line composed of a transparent conductive layer and a metal layer of the first layer and a pseudo-pixel electrode; sequentially covering the plasma protective layer and the gate insulating layer and the first amorphous germanium containing no impurities The layer and the protective insulating layer are processed; on the electrode terminal forming region of the scanning line, the surface of the electrode with the pseudo-like pixel is formed with an opening portion and the protective insulating layer on the electrode forms a film thickness, which is thicker than other fields. The resin pattern is formed by removing the protective insulating layer in the opening portion, the first amorphous germanium layer and the gate insulating layer, the plasma protective layer and the first metal layer, and forming the field with the electrode terminal of the transparent conductive scan line The same process of exposing the pixel electrode; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; leaving a protective insulating layer thinner than the gate electrode on the gate electrode a process of the first amorphous germanium layer; a process of completely covering the second amorphous germanium layer containing impurities after removing the photosensitive resin pattern; and covering the second metal layer of one or more layers, respectively corresponding to the protective insulating layer a partially overlapping source wiring (signal line) 'and a drain wiring including a pixel electrode partially overlapping the protective insulating layer and an electrode terminal of a scanning line forming an electrode terminal of a transparent conductive scanning line 'and the electrode terminal of the signal line formed by one of the signal lines' to form a pattern of the photosensitive organic insulating layer pattern in which the thickness of the four kinds of signal lines is thicker than other fields; the photosensitive organic insulating layer pattern is formed Selectively removing the second metal layer and the second amorphous germanium layer and the first amorphous germanium layer as a mask, and forming an electrode terminal and a source/drain wiring of the scanning line and the signal line; The film thickness of the organic insulating layer pattern is exposed to the electrode terminals and the drain wiring of the scanning lines and the signal lines. -27- 1300868 (25) With this configuration, the number of photolithographic processes for processing the pixel electrodes and the scanning lines can be reduced by using one mask, and the formation of the etching cut-off layer and the islanding of the semiconductor layer can be processed by using the mask. Engineering, in turn, to reduce the number of photography etching projects. In addition, when the source/drain wiring is formed, a halftone (halftone) exposure technique is used, and only the signal line is selectively left as a result of the manufacturing process reduction of the photosensitive organic insulating layer without forming the passivation insulating layer. A three-layer photomask is used to fabricate a TN-type liquid crystal display device. The method of manufacturing a liquid crystal display device according to claim 7 is characterized in that the transparent conductive layer and the metal are formed on at least one main surface of the first transparent insulating substrate. The scanning line composed of the layers and the engineering of the pseudo-pixel electrodes; the steps of covering the plasma protective layer and the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; In the field of electrode terminal formation, a project of forming a photosensitive resin pattern having an opening portion and protecting a thickness of a region in which an insulating layer is formed is thicker than other fields, and removing a protective insulating layer in the opening portion 1 an amorphous germanium layer and a gate insulating layer and a plasma protective layer and a metal layer, exposing the same as the electrode terminal forming the electrode terminal of the transparent conductive scan line; reducing the film thickness of the photosensitive resin pattern Excluding the work of protecting the insulating layer; leaving a protective insulating layer wider than the gate electrode on the gate electrode to expose the first amorphous germanium layer; removing the aforementioned photosensitive layer After the resin pattern, the entire second amorphous germanium layer containing impurities is covered; after covering one or more layers of the anodizable metal layer, respectively, corresponding to the source wiring (signal line) partially overlapping the protective insulating layer And a drain wiring of the same pixel-containing electrode, and an electrode terminal of the scan line including the electrode terminal forming field of the scanning line of -28-1300868 (26) transparent conductivity, and a part of the signal line The electrode terminal of the signal line forms a photosensitive resin pattern thicker than the electrode terminal of the scanning line and the signal line, respectively; the photosensitive resin pattern is used as a mask, and the anode is selectively removed. The oxidized metal layer and the second amorphous germanium layer and the first amorphous germanium layer form an electrode terminal and a source/drain wiring of the scanning line and the signal line; and the film thickness of the photosensitive resin pattern is reduced, Excavation of source and drain wiring, and protection of the electrode terminals, and anodization of source and drain wiring. With this configuration, the number of photolithographic processes for processing the pixel electrodes and the scanning lines can be reduced by using one mask, and the formation of the etching-cut layer and the islanding process of the semiconductor layer can be processed by using one mask, thereby achieving reduction. Photography etching engineering number. In addition, in forming the source. In the case of the bungee wiring, a halftone mask can be used to selectively form an anodized layer without forming a passivation insulating layer using a halftone exposure technique. TN type liquid crystal display device. Patent Document No. 16 is a manufacturing method of a liquid crystal display device according to Item 8 of the patent application; characterized in that it is formed of at least one layer on at least one main surface of the first transparent insulating substrate. The scanning line and the counter electrode formed by the first metal layer; sequentially covering one or more layers of the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities, on the electrode 'Residue is thinner than the wide electrode of the protective electrode layer to expose the first amorphous layer of the project; after covering the second amorphous sand layer containing impurities, 'on the electrode terminal formation area of the scan line, forming 1300868 (27) removing the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer in the opening portion to expose a part of the scanning line; covering the second metal layer of one or more layers Corresponding to a source wiring (signal line) and a drain wiring (pixel electrode) that partially overlap the protective insulating layer, and an electrode terminal 'and a portion of the signal line including the scanning line of the opening portion Signal line The terminal electrode is formed to form a photosensitive organic insulating layer pattern having a thicker thickness on the signal line than in other fields; and the second organic layer and the second non-selective are removed by using the photosensitive organic insulating layer pattern as a mask The formation of the electrode terminal and the source/drain wiring of the scanning line and the signal line by the crystal germanium layer and the first amorphous germanium layer'; reducing the film thickness of the photosensitive organic insulating layer pattern to expose the scanning line and the signal line The electrode terminal and the wiring of the drain. With this configuration, in the formation of the source/drain wiring, the halftone (halftone) exposure technique is used, and only the signal line is selectively left, and the photosensitive organic insulating layer is selectively removed without the need to form a passivation insulating layer. An IPS type liquid crystal display device can be manufactured using four photomasks. The method of manufacturing a liquid crystal display device according to claim 9 is characterized in that the first surface of one of the first transparent insulating substrates is formed of one or more layers. 1 The scanning line and the opposite electrode of the metal layer; sequentially covering one or more layers of the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; remaining on the gate electrode An operation of exposing the first amorphous germanium layer to a protective insulating layer which is thinner than the gate electrode; and covering the second amorphous germanium layer containing impurities in an entire manner, forming an opening portion in the field of electrode terminal formation of the scanning line -30 - 1300868 (28) removing the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer in the opening portion to expose a part of the scanning line; covering one or more layers of anodizable metal After the layer, respectively corresponding to the source wiring (signal line) partially overlapping the protective insulating layer. a drain wiring (pixel electrode), an electrode terminal of a scanning line including the opening portion, and an electrode terminal of a signal line formed by a portion of the signal line, and forming electrode terminals of the scanning line and the signal line, respectively a project of a photosensitive resin pattern having a thicker film thickness than other fields; and selectively removing the anodizable metal layer and the second amorphous germanium layer and the first amorphous germanium layer by using the photosensitive resin pattern as a mask; And forming an electrode terminal and a source/drain wiring of the scanning line and the signal line; reducing the film thickness of the photosensitive resin pattern to expose the source/drain wiring; and protecting the electrode terminal from the same anodizing source Extreme and bungee wiring works. With this configuration, in the formation of the source/drain wiring, a halftone (halftone) exposure technique is used to selectively form an anodized layer on the source/drain wiring without forming a passivation insulating layer. The IPS type liquid crystal display device can be manufactured by using four masks. The method of manufacturing a liquid crystal display device according to the first aspect of the invention is characterized in that: at least one of the main surfaces of the first transparent insulating substrate is formed by one or more layers. The scanning line and the counter electrode formed by the first metal layer; sequentially covering one or more layers of the gate insulating layer and the first amorphous sand layer and the protective insulating layer containing no impurities; and the electrode terminal of the scanning line In the field of formation, a photosensitive resin pattern having an opening portion and having a thicker thickness in the field of forming a protective insulating layer on the gate electrode than the other collars 31-1300868 (29) is formed; the protection in the opening portion is removed The insulating layer and the first amorphous germanium layer and the gate insulating layer expose the scanning line portion; the film thickness of the photosensitive resin pattern is reduced to expose the protective insulating layer; and the residual ratio on the gate electrode a process in which the gate electrode has a wider protective insulating layer to expose the first amorphous germanium layer; after removing the photosensitive resin pattern, the second amorphous germanium layer containing impurities is completely covered; covering one layer or more After the second metal layer, the source wiring (signal line) and the drain wiring (pixel electrode) partially overlapping the protective insulating layer and the scanning line including the second amorphous germanium layer in the opening portion are respectively formed. The electrode terminal and the electrode terminal of the signal line formed by one of the signal lines respectively form a pattern of a photosensitive organic insulating layer pattern having a thicker thickness on the signal line than other fields; and the photosensitive organic insulating layer pattern is As a light mask, the second metal layer and the second amorphous germanium layer and the first amorphous germanium layer are selectively removed to form an electrode terminal and a source/drain wiring of the scanning line and the signal line; The film thickness of the photosensitive organic insulating layer pattern is such that the electrode terminals and the drain wiring of the scanning lines and the signal lines are exposed. With this configuration, the formation of the etch-off layer and the formation of the opening portion to the gate insulating layer can be processed using the same mask, and the number of photographic etching processes can be reduced. Further, when the source/drain wiring is formed, the halftone (halftone) exposure technique is used, and only the photosensitive organic insulating layer is selectively left on the signal line without the need to form a passivation insulating layer. The reticle manufactures an IPS type liquid crystal display device. Patent application No. 9 is a manufacturing method of a liquid crystal display device described in the patent application No. 1300868 (30), which is characterized in that it is formed on at least one main surface of the first transparent insulating substrate. Engineering of scanning lines and counter electrodes composed of a first metal layer of one or more layers; sequentially covering one or more layers of the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; In the field of electrode terminal formation of the scanning line, a photosensitive resin pattern having an opening portion and a thickness of a protective insulating layer formed on the gate electrode is thicker than other fields is formed; and the protective insulating layer in the opening portion is removed 1 amorphous enamel layer and gate insulating layer, exposing part of the scanning line; reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; remaining on the gate electrode is wider than the gate electrode a finer protective insulating layer to expose the first amorphous germanium layer; after removing the photosensitive resin pattern, the entire second amorphous germanium layer containing impurities is covered; and one or more layers of the anode can be covered After oxidizing the metal layer, respectively, corresponding to the source wiring (signal line) and the drain wiring (pixel electrode) partially overlapping the protective insulating layer, and the scanning line including the second amorphous germanium layer in the opening portion An electrode terminal, and an electrode terminal of a signal line formed by a part of the signal line, and forming a photosensitive resin pattern having a thicker film thickness on the electrode terminal of the scanning line and the signal line than in other fields; The photosensitive resin pattern selectively removes the anodizable metal layer and the second amorphous germanium layer and the first amorphous germanium layer as a mask to form an electrode terminal and a source/drain wiring of the scan line and the signal line Reducing the film thickness of the photosensitive resin pattern to expose the source and drain wiring; protecting the electrode terminal while anodizing the source. Bungee wiring works. With this configuration, the formation of the etch-off layer -33 - 1300868 (31) and the formation of the opening portion to the gate insulating layer can be processed using the same mask, thereby reducing the number of photographic etching processes. In addition, in the case of forming a source/drain wiring, a halftone (halftone) exposure technique is used to selectively form an anodized layer without forming a passivation insulating layer. An IPS type liquid crystal display device can be manufactured using three photomasks. [Embodiment] An embodiment of the present invention will be described based on Figs. 1 to 16 . 1 is a plan view showing a semiconductor device (active substrate) for a display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a manufacturing process of AA, line, and BB, line and C-C' line of FIG. . Similarly, in the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, and the seventh embodiment, FIG. 3 and FIG. 4, FIG. 5 and FIG. 6, FIG. 8 and FIG. 9 and FIG. 11 and FIG. 12, FIG. 13 and FIG. 12, FIG. 15 and FIG. 16 are sectional views showing a plan view and a manufacturing process of the active substrate. Further, the same portions are denoted by the same reference numerals, and the detailed description thereof will be omitted. (First embodiment) A first embodiment of the present invention will be described. In the first embodiment, the same as the previous example, first, as shown in Fig. 1 (a) and Fig. 2 (a), a small vacuum is formed on the main surface of the glass substrate 2 by using SPT (sputtering) or the like. Zhuang, such as c〗, Ta, Mo, etc. or covering these alloys or metal ruthenium compounds to form a film thickness ] ·] ~ 0 · 3 degrees m of the metal layer, by -34 - 1300868 (32) The micromachining technique selectively forms a scan line J] which serves as both the gate electrode 1 1 A and a common capacitance line 16 . A more detailed description will be described in detail later, and in the present invention, the scanning line material will be almost unlimited. Next, in the entire glass substrate 2, a PCVD apparatus is used to sequentially cover, for example, a film thickness 〇·3 // m which will become the first s丨n X (germanium nitride) layer 30 of the gate insulating layer, and a film. Thickness 〇 · 5 // m degree, which is almost free of impurities and becomes the first amorphous germanium (a - S i ) layer 3 1, which is the channel of the insulating gate type transistor, and the film thickness is 0 · 1 // m Three kinds of thin film layers of the second SiNx layer 31 which are the insulating layers of the protection channel, and as shown in FIG. 1(b) and FIG. 2(b), in the field outside the image display portion, the electrodes of the scanning line 1 1 In the field of terminal formation, an opening portion 63 A is formed by a halftone exposure technique (an opening portion 6 5 a in the field of forming an electrode terminal of the common capacitance line 16), and at the same time, a protective insulating layer is formed, that is, a gate The film thickness of the field 8 2 A on the electrode 1 1 A is, for example, a photosensitive resin pattern 8 2 A, 8 2 B which is thicker than 2 / 4 m of other fields 8 2 B. Selectively removing the second SiNx layer 32 of the channel protective layer in the opening portion 63A (and the opening portion 65A) and the first amorphous germanium layer 3 and the gate with the photosensitive resin patterns 82A and 82B as masks The edge of the first layer 1 S i N X layer 30 to expose the scanning line] 1 (and the common capacitance line 16), one part 72. The pitch of the electrode terminals of the scanning line 1 is at most half of the electrode gap of the driving LSI, and since it is usually 20 0 / m or more, the fabrication of the mask for forming the opening portion 6 3 A (white area) is performed. And the precision management of the finished size is extremely easy. When the photosensitive resin-35-1300868 (33) pattern 82 A, 82B is reduced by a thickness of 1 // m or more by ashing means such as oxidizing plasma, the photosensitive resin pattern 82B disappears, as shown in the figure ( c) As shown in Fig. 2(c), while the second SiNx layer 32 is exposed, the photosensitive resin pattern 8 2 C can be selectively formed only in the field of protective insulating layer formation. Further, in the above oxygen plasma treatment, it is preferable to control the pattern size change to enhance the anisotropy, but it is not necessary when the pattern precision is low. The photosensitive resin pattern 8 2 C, that is, the pattern width of the etch-off layer is the size between the source and the drain wiring, and the precision of the reticle is matched, so the source/drain wiring is 4~ 6 am, and the precision of the fit is ± 3 // m, the dimensional precision is 1 0~1 2 // m, and the dimensional precision requirements are not strict. However, when the resist pattern is converted to 82 C, the photoresist pattern is uniformly and uniformly reduced by 1 // m, and the size is not only reduced by 2 # m, but also the precision of the mask when the source/drain wiring is formed. The reduction to 1 // m becomes ± 2 // m, which is more stringent than the former. Therefore, in the above oxygen plasma treatment, in order to control the change in the size of the pattern, it is preferable to enhance the anisotropy. Specifically, it is preferably an RIE (Reactive Ion Etching) method, or an ICP (Inductive Coupled Plasam a) method or a TCP (Transfer Coupled Plasam a) method having a high density plasma source. Plasma treatment is better. As shown in Fig. 1 (d) and Fig. 2 (d), the second SiNx layer 32 is etched to the gate electrode 11A by the photosensitive resin pattern 82C as a mask, and becomes a second SiNx layer. 3 2 A, at the same time, the first amorphous sand layer 31 is exposed. The field of protective insulating layer formation, that is, the size of the photosensitive resin pattern 8 2 C (black field), even the smallest size, I 〇Μ (7) size, the black field and the white field - 36-1300868 (34) field As a halftone exposure field, not only is the mask fabrication easier, but also compared to the channel-etched insulating gate transistor, the channel protection insulating layer 3 2 A is determined by the starting current of the insulating gate transistor. Dimensions, not the dimensions of the source and drain wirings 12, 2, make process management easier. Specifically, for example, the source of the channel etching type. The size of the drain wiring is 5 ± 1 // m, and the size of the protective insulating layer for the etch stop type is 10 ± 1 // m. Under the same development conditions, the variation of the on-current is approximately halved. At this time, a portion of the exposed scanning line 1 1 is exposed to the etching gas or the chemical of the protective insulating layer 3 2 A, so that the material of the scanning line n is different. In the case where, for example, the aluminum alloy is exposed, if Ti is selected as the source/drain wiring material in the lowermost layer, the influence of oxidation can be easily avoided. Others, as explained in the previous examples, for example, the scanning line 11 is previously formed as a laminate of aluminum/titanium/aluminum. Even if the titanium of the upper layer disappears, the aluminum may be removed to expose the titanium of the lower layer. After the removal of the photosensitive resin pattern 82C, the PCVD device is used on the entire surface of the glass plate 2, for example, at 0. Film thickness coverage of 0 5 # m 譬 After the second amorphous germanium layer 33 containing phosphorus as an impurity, a vacuum film forming apparatus such as SPT is used to sequentially cover a film thickness of 0.  1 #m degree as an anodized heat-resistant metal layer of Ti, Ta and other heat-resistant metal film layer 34; and film thickness of 0. The same level of 3 m is used as the aluminum film layer 3 5 of the anodizable low resistance wiring layer; and the film thickness is 0.  1 / m is the same as the heat-resistant metal thin film layer 36 such as Ta which can be anodized intermediate conductive layer. Then, the source/drain wiring material composed of the three-layer thin film and the second amorphous germanium layer 3 are sequentially etched by a micro-machining technique using a photosensitive resin pattern-37-1300868 (35). 3 and the first amorphous germanium layer 3 1, exposing the gate insulating layer 30, as shown in Fig. (e) and Fig. 2(e), selectively formed by lamination 3 4 A, 3 5 A, 3 The drain electrode 2 1 of the insulated gate type transistor formed by 6 A and the signal line 12 which also serves as the source. Further, in general, when the source/drain wirings 1 2, 2 1 are formed, the scanning line electrode terminals 5 are simultaneously formed in one portion of the scanning lines, but the materials of the source and the drain are different. There is also the possibility that the electrode terminals are not formed here as shown in the figure. If the limitation of the resistance 値 is loose, the structure of the source/drain wiring 1 2, 2 1 can be simplified to form a Ta single layer, and the chemical potential of the aluminum alloy to which Nd is added is lowered in the alkaline solution. The chemical corrosion reaction with ITO is suppressed. Therefore, the intermediate conductive layer 36 can be used to form a two-layer structure and source of the source/drain wiring 1 2, 2 1 without the intermediate conductive layer 36. The structure of the bungee wiring 1 2, 2 1 is somewhat simplified. After the source/drain wiring 1 2, 2 1 is formed, the glass substrate 2 is covered with a vacuum film forming apparatus such as SPT, such as ITO. 1~0. a transparent conductive layer of a degree of β m, as shown in Fig. 1 (f) and Fig. 2 (f), by means of a micromachining technique, a portion of the intermediate conductive layer 3 6 A including the drain electrode 2] is gated The pixel electrode 22 is selectively formed on the pole insulating layer 30. At this time, a transparent conductive film is formed on one of the scanning line portions 7 2 (or the electrode terminal 5) and the signal line 1 2 outside the image display portion to become the transparent conductive electrode terminals 5 A, 6 A. In addition, similarly to the short-circuit line 40 in which the transparent conductivity is provided from the previous example, the electrode terminals 5 A, 6 A and the short-circuit line 40 are formed in a long strip shape to increase the resistance, and it is easy to be static - 38- 1300868 (36) High resistance for electric countermeasures. Next, as shown in Fig. 1 (g) and Fig. 2 (g), the photosensitive resin pattern 83 for selectively forming the pattern of the pixel electrode 22 is used as a light mask, and the light is irradiated while anodizing the source and the drain Wiring 2, 2 1 forms an oxide layer on the surface. Ta is exposed on the upper surface of the source/drain wiring 1 2, 2 1 , and Ta, Al, Ti, and a layer of the second amorphous germanium layer 33A and the first amorphous germanium layer 3 ] A are exposed on the side surface. The anodic oxidation causes the second amorphous germanium layer 33A to be deteriorated into an impurity-containing yttrium oxide layer (SiO 2 ) 66 to deteriorate the first amorphous germanium layer 31 A into an impurity-free yttrium oxide layer (Si 02 ) 67. Ti is metamorphosed into titanium oxide (Ti02) 6.8 which is a semiconductor, and alumina (AL203) 69 which deteriorates AL into an insulating layer, and Ta is deteriorated into molybdenum pentoxide (Ta205) 70 in an insulating layer. Although the titanium oxide layer 68 is not an insulating layer, its film thickness is extremely thin and the exposed area is small. Therefore, in principle, the passivation is not problematic, but it is preferable that the heat-resistant metal thin film layer 34A is Ta selected in advance. However, since Ta is different from Ti, it lacks the surface oxide layer of the absorbing substrate, so that the characteristics of the ohmic contact function are brought to the attention. In the gate wiring 2 1 , in order to form an anodized layer of a good film quality, anodization is performed while irradiating light, which is an important point of the anodizing process and has been disclosed in the prior art. Specifically, if the leakage current of the insulating gate type transistor is more than /A when the light of the 10,000 lux is sufficiently strong, and the leakage current of the insulating gate type transistor is more than /A, it is calculated from the area of the drain electrode 2 1 , 1 〇 m / Anodizing to the extent of cm2 is the current density at which a good film quality can be obtained. However, even if the film quality of the anodized layer on the drain wiring 2 1 is insufficient, generally, sufficient reliability can be obtained, and the reason is that the driving signal applied to the liquid crystal single-39-1300868 (37) element is basically The upper side is an alternating current, so that the voltage of the counter electrode I 4 is adjusted during the image inspection in such a manner that the DC voltage component between the counter electrode 14 and the pixel electrode 2 2 (the drain electrode 2 1 ) is reduced (the flicker adjustment is lowered). In the basic principle, the insulating layer may be formed in advance so that only the DC component current is not present on the signal line 12.

The thickness of each oxide layer formed by anodic oxidation of pentoxide 70, alumina 69, titanium oxide 68, yttrium oxide layer 6 6, 6 7 is 〇. 1~〇. 2 # m degree as The passivation of the wiring is sufficient, and the voltage applied by using the reaction liquid such as ethylene glycol can be realized by the same voltage exceeding 1 〇〇V. Source. Bipolar wiring 1 2, 2 1 Anodizing should be noted, although not shown, all signal lines] 2 must be formed in electrical parallel or series, in the next part of the manufacturing process When the series/parallel is not released, there is a problem not only for the electrical inspection of the active substrate 2 but also for the actual operation of the liquid crystal display device. As the means for releasing, it is possible to cause evapotranspiration by irradiation of laser light, or it is a simple method of mechanically cutting by a line arranging device, and detailed description thereof will be omitted.

The fact that the pixel electrode 2 2 is covered with the photosensitive resin pattern 8 3 in advance does not require the anodized pixel electrode 22, and the reaction current flowing into the cathode electrode 21 via the insulating gate type transistor can be solved without securing the necessary degree or more. Finally, the photosensitive resin pattern 8 3 is removed, and as shown in Fig. 1 (h) and Fig. 2 (h), the active substrate 2 (display device semiconductor device) is completed. The active substrate 2 and the color filter thus obtained are liquid crystal panelized, and the first embodiment of the present invention is completed. As shown in Fig. (h), the accumulated capacitance is displayed as shown in Fig. (h), and the pixel electrode 2 2 - 40 - 1300868 (38) The spacer gate insulating layer 30 is planarly overlapped (top left) In the example of the lower right part, the structure of the storage capacitor 15 is not limited, and the structure of the insulating layer of the interposer insulating layer 30 may be between the pixel electrode 22 and the front scanning line 亦可. . In addition, other configurations are possible, but the description thereof is omitted. Similarly, since there is a connection forming process to the scanning line, it is easy to perform electrostatic countermeasures by using a conductive material or a half layer other than the transparent conductive layer. In the first embodiment, the layer of the low-precision precision is formed in the contact hole forming the trace protection layer (etching stop layer or protective insulating layer) in the contact hole of the scanning line, and a halftone exposure technique is applied to the photolithography process. The active substrate is formed by four masks. However, the formation of the pixel electrode and the scanning line can be processed by one mask, and the active substrate can be fabricated by using three masks. Therefore, the second embodiment will be described in detail. . (Second embodiment)

In the second embodiment, first, a vacuum film forming apparatus such as SPT is used on one main surface of the glass substrate 2 to increase the film thickness ο”~0. 2/im path Transparent conductive layer 91 such as ITO, and cover film thickness 〇. 1 ~ 〇. 3 / m m first metal layer 92, as shown in Fig. 3 (a) and Fig. 4 (a), selectively formed by lamination of a transparent conductive layer 9 1 A and a first metal layer by a processing technique Also, it also serves as the scanning line 11 of the gate electrode 1 1 A, the pixel electrode 9 3 ' formed by laminating the transparent conductive layer 91B and the first metal layer 92B, and the first electrode layer 9 1 C and the first metal layer 9 2 C slash This is the gate electrode and the pass-through conductor is made by cutting the fourth electrode, the degree of fineness 92 A and the quasi-like layer 1300868 (39) product of the signal line of the pseudo-like electrode terminal 94. For example, a high melting point metal such as Cr or Ta'Mo or an alloy or a metal ruthenium compound is selected as the first metal layer. The insulator gate insulation layer improves the insulation withstand voltage of the signal line. In order to improve the yield, the electrodes are preferably controlled by dry etch for the slope of the cross-sectional shape, but the dry etching technique of the IT 于 is etched. The technique of using HI (hydrogen iodide) or hydrogen bromide (HBr) for gas has been developed, but the amount of the reaction product in the exhaust system is too large to be put into practical use. Therefore, Ar is currently used. Splashing and etching of (argon) may be used. Secondly, in the whole of the glass substrate 2, to 0.  A film thickness of 1 / m is covered with a transparent insulating layer such as TaOx or SiO 2 as a plasma protective layer. The plasma protective layer 71 is a transparent conductive layer 9 1 A, 9 which is exposed at the margin of the scanning line 1 1 and the pseudo pixel electrode 13 in order to prevent SiNx of the gate insulating layer from being formed by a PC VD device to be described later. 1 B is reduced, and it is necessary to change the film quality of SiNx. For details, refer to the above-mentioned Japanese Patent Laid-Open Publication No. 59-99. After the plasma protective layer 71 is covered, it is the same as that of the first embodiment, and the PCVD apparatus is sequentially formed by 0. 2 ν m-0. 05 // m-0.  1 / m degree film thickness becomes the first S iNx layer 30 of the gate insulating layer, and the first amorphous germanium layer 3 1 ' which becomes a channel of the insulating gate type transistor containing almost no impurities and becomes protection Three kinds of thin film layers, such as the second SiNx layer 32 of the insulating layer of the channel, are formed on the pseudo-pixel electrode 93 in the field of the electrode terminal formation of the scanning line 11 in the field outside the opening portion 7 and the image display portion. It has an opening portion 63 3 A, and has an opening portion 6 4 A on the pseudo electrode terminal 94, and at the same time, a -42-1300868 (40) protective insulating layer forming field, that is, a field on the gate electrode 1 1 A The photosensitive resin pattern 84A, 84B having a film thickness of 8 4 A, such as 2 // m, is thicker than the film of other fields 8 4 B by 1 / 4 m, which is formed by a halftone exposure technique. The gate insulation layer becomes a plasma protective layer. . In combination with the i-SiNx layer, the SiC]nNx can be formed to be thinner than before. The photosensitive resin patterns 8 4 A, 84 B are used as masks, and as shown in FIG. 3 (b) and FIG. 4 (b), the second si NX layer 3 2 in the opening portion is sequentially etched, and the first amorphous germanium is used. The layer 3 1, the gate insulating layer 3, the plasma protective layer 71, and the first metal layer 92, expose a portion of the transparent conductive layer of the scanning line n, and form the electrode terminal 5A of the scanning line, similarly, The electrode terminal 6A which is a signal line is formed by exposing the transparent conductive layer of the electrode terminal 94, and the transparent conductive layer 91B of the pseudo pixel electrode 93 is exposed to form the pixel electrode 22. When the photosensitive resin patterns 84A and 84B are reduced in thickness by 1 m or more by the ashing means such as oxygen plasma, the photosensitive resin pattern 84B is removed, as shown in Fig. 3 (b) and Fig. 4 (b). As shown in the figure, the photosensitive resin pattern 84C can be selectively formed only in the field of formation of the protective insulating layer while exposing the second SiNx layer 3 2B. In the above oxygen plasma treatment, in order not to lower the source as described later. The mask of the bungee wiring forming engineering is matched with the precision, so it is better to enhance the anisotropy (the opposite sex) and suppress the change of the pattern size. As shown in FIG. 3(d) and FIG. 4(d), the second SiNx layer 32B is selectively etched by using the photosensitive resin pattern 84C as a mask to form a thinner pattern than the pattern of the gate electrode HA. The 2SiNx layer 32 A also exposes the first amorphous germanium layer 3 1 B. At this time, the electrode terminal 5A of the transparent conductive scanning line exposed in the opening 63A, and the electrode terminal 6A of the signal line of the 43-1300868 (41) and the pixel electrode 22 are exposed to the etching of the layer 3 2B. The gas is very suitable because it uses a fluorine-based etching gas and reduces the film thickness of such a transparent conductive layer, or changes the resistance, brightness, and the like. Then, the PC VD device of the photosensitive resin pattern 84C is removed to cover the entire surface of the glass substrate 2, and the thickness of the film is as follows: for example, the film thickness of the substrate is as small as the second amorphous material containing phosphorus as an impurity. Device, cover film thickness 0. 1# m such as Ti, Ta and other heat-resistant metal film layer 34 as a heat-resistant metal cover film thickness.  The aluminum thin film layer 3 of 3 / m is used as the low resistance, and the source/drain wiring 2nd amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1 B are formed by the two film thicknesses. And, by the technique, the photosensitive resin pattern 85 is sequentially etched to expose the layer 3 0 A, as shown in FIG. 3(e) and FIG. 4(e), selectively including a part of the pixel electrode 22 The drain electrode 2 1 of the laminated gate type transistor of 34A and 35A and the electrode terminal 5 A of the signal line 1 2 which serves as the source electrode and the signal line When the electrode terminal 6 A is etched during the etching of the gate-drain wiring 1 2, 2 1 and exposed to the glass substrate 2, the source/drain wiring 1 2 can be simplified to Ta, Cr, if the limitation of the resistance 不 is not critical. A single layer of Mo et al. In this manner, the active substrate 2 and the color filter panel obtained by bonding are laminated to complete the second embodiment of the present invention. In the first state, since the photosensitive resin pattern 85 is in contact with the liquid crystal, the photosensitive second SiNx is not generated or changed, and is used. 0 5 丨 layer 33, degree 譬 layer, and wiring layer. The material, and the micromachined gate are insulated to form the electrode of the wire formed by the package. Scan the beam source · up. Moreover, the shape of the light sheet of 2 1 and the liquid resin of the liquid 2 are -44 - 1300868 (42). The case 8 is not the use of a general photosensitive photosensitive material containing phenolic acid strontium resin as a main component, but the purity is used. In the main component, it is important to use a photosensitive organic insulating layer containing a polyacrylic acid resin or a poly n-imine resin with high heat resistance. Some materials may be fluidized by heating to cover the source depending on the material. The side of the NMOS wiring 1 2, 2 1 is formed. In this case, the reliability of the liquid crystal panel is further improved. As for the configuration of the storage capacitor 15 as shown in FIG. 3(e), the source/drain wirings 1 2, 2 1 and the storage electrode 7 3 including a part of the pixel electrode 2 2 are formed, and The structure of the protruding portion of the front scanning line 1 1 'the intermediate insulator's electric protective layer 7 1 A and the gate insulating layer 3 0 A, and the planar overlapping has been exemplified (the upper left to the lower right oblique portion 5 2 However, the structure of the storage capacitor 15 is not limited thereto. As in the first embodiment, the interposer includes the gate insulating layer between the scanning line and the simultaneously formed common capacitance line 16 and the pixel electrode 2 2 . 3 The insulation layer of 〇a can also be constructed. Further, other configurations are also possible, but detailed descriptions thereof will be omitted. In the second embodiment, the electrode terminal of the scanning line and the electrode terminal of the signal line have a limitation on the configuration of the device which is required to be a transparent conductive layer. However, it is also possible to remove the device and the process. The fourth embodiment will be described. (Third Embodiment) In the third embodiment, as shown in Fig. 5 (d) and Fig. 6 (d), the formation process of the contact formation process and the channel protective layer (etching stop layer) is approximated. Yu Di 2 is a process of the form of the form. However, it is not necessary to use the pseudo electrode terminal 94 as described below for the reason of -45-1300868 (43). Thereafter, the photosensitive resin pattern 84C is removed, and after the entire surface of the glass substrate 2 is covered with a film thickness of, for example, 〇·〇5 // m, the second amorphous germanium layer 3 3 containing impurities such as phosphorus is removed by using a PVCD device. Source. For the formation of the bungee wiring, a vacuum film forming apparatus such as S P T is used to sequentially cover the film thickness.  1 " m degree such as Ti' Ta _ heat resistant metal film layer 34 as a heat resistant metal layer, film thickness 0. The aluminum film layer 3 of 3 / m level is used as a low resistance wiring layer. Next, the source/drain wiring material composed of the two-layer thin film, and the second amorphous germanium layer 3 3 and the first amorphous germanium layer 3 1 B are used, and the photosensitive resin pattern 8 is used by the microfabrication technique. 6 sequentially etching to expose the gate insulating layer 30 A, as shown in FIG. 5(e) and FIG. 6(e), selectively forming a portion of the pixel-containing electrode 2 2 by 3 4 A and 3 The drain electrode 2 1 of the insulating gate type transistor formed by the stacking of 5 A and the signal line 12 which also serves as the source wiring are simultaneously formed when the source/drain wiring 1 2, 2 1 is formed. The electrode terminal 5 including the exposed scanning line electrode terminal forming region 5A and forming the scanning line and the electrode terminal 6 composed of one of the signal lines. That is, as in the second embodiment, the pseudo electrode terminal 94 is not necessarily required. At this time, the film thickness of 8 6 A on the signal line 1 2 is, for example, 3 m, which is thicker than the film thickness of the electrode on the electrode terminal 5, 6 and the electrode electrode 73 on the drain electrode 2 1 . The 5 # m thick photosensitive resin patterns 86A, 86B are formed in advance by a halftone exposure technique, which is an important feature of the third embodiment. The minimum size of 8 6 B corresponding to the electrode terminals 5, 6 is several ten # m, which is relatively large; although the mask manufacturing and manufacturing size management is extremely easy, it is the smallest corresponding to the signal line 2 field 8 6 A. The size is 1300868 (44) 4~8 // m 'The dimensional accuracy is high, so it is necessary to use a thinner gap as the halftone (ha 1 ft ο ne) field. However, as described in the previous example, the source of the present invention is compared to the source/drain wiring 1 2, 2 1 formed by one exposure treatment and two etching treatments. Since the drain wirings 1 2 and 2 1 can be formed by one exposure treatment and one etching treatment, there are few factors that affect the variation of the pattern width, and the size management of the source/drain wirings 1 2 and 2 1 is And the source/drain wiring 1 2, 2 1 , that is, the size management of the channel length is easier to manage the pattern precision than the previous halftone exposure technique. In addition, compared with the channel-etched insulating gate transistor, the conduction current of the insulating gate transistor is determined by the size of the channel protection insulating layer 3 2 A, instead of the source/drain wiring 1 2, 2 1 The size of the room is so easy to understand that it is easier to manage the process. After the source/drain wirings 1 2, 2 1 are formed, the photosensitive resin patterns 8 6 A, 8 6B are reduced in film thickness by an ashing means such as oxygen plasma. When the film is 5 m or more, the photosensitive resin pattern 8 6 B disappears, as shown in Fig. 5 (f) and Fig. 6 (f), the gate electrode 2 1 and the electrode terminals 5, 6 are exposed, and only the signal line When the photosensitive resin pattern 86C is selectively formed by the oxygen plasma treatment, the pattern width of the photosensitive resin pattern 86C is reduced, and the upper surface of the signal line 1 2 is exposed to reduce the reliability, so it is preferable to reduce the reliability. Enhance the anisotropy (the opposite sex) and suppress the change in the size of the pattern. Further, when the limitation of the resistance 値 is not critical, the structure of the source/drain wirings 1 2, 2 1 can be simplified to a single layer of Ta, Cr, Mo or the like. The active substrate 2 and the color filter obtained in this manner are bonded to each other to form a liquid crystal panel, and the third embodiment of the present invention is completed. Even in the third embodiment of the -47 - 1300868 (45) state, the photosensitive resin pattern 8 6 C is touched by the liquid crystal, so the photosensitive resin pattern 8 6 C does not use the ordinary component of the phenolic acid resin. Photosensitive resin, which is highly pure, and it is important to use a photosensitive organic insulating layer containing a polyacrylic resin or a polyimide resin with high heat resistance as the main component, and some may be heated by heating depending on the material. In addition, the surface of the source/drain wiring 1 2, 2 is covered, and in this case, the reliability of the liquid crystal panel is further improved. The configuration of the storage capacitor 15 is as shown in Fig. 5 (f), the source/drain wirings 1 2, 21, and the storage electrode 7 3 formed by including a part of the pixel electrode 2 2 , and The protrusion of the front scanning line 1 and the like, the intermediate plasma protective layer 7 1 A and the gate insulating layer 30 A, and the planar overlapping structure have been exemplified (the upper left to the lower right oblique portion 52). Further, the transparent conductive pattern 6 A (the pseudo electrode terminal 9 1 C ) formed under the electrode terminal forming region 5A and the signal line 12 and the transparent conductive layer pattern of the short-circuit line 40 are connected by making the shape into an elongated line The shape can be used as a high-resistance wiring for countermeasures against static electricity, but it is of course possible to use static electricity countermeasures using other conductive members. In the third embodiment of the present invention, the organic insulating layer is formed only on the signal line 12, and the drain electrode 2 1 is exposed while maintaining conductivity. Even in this case, sufficient reliability can be obtained. The driving signal of the liquid crystal cell is substantially an alternating current signal, and the direct current voltage is reduced between the counter electrode 14 and the pixel electrode 22 (the drain electrode 2 1 ), and the counter electrode is adjusted during the image inspection] 4 Since the voltage is lowered (the adjustment of the flash is reduced), the insulating layer may be formed in advance so that the DC component is only applied to the signal line 12. -48- 1300868 (46) In the second and third embodiments of the present invention, an organic insulating layer is formed only on the source/drain wiring and the signal line, respectively, and the manufacturing process is cut, but the organic insulating layer is Since the thickness is usually IM m or more, when the alignment film of the honing cloth is used for the alignment treatment, the height may cause a non-alignment state or may ensure the precision of the gap of the liquid crystal cell. Therefore, in the fourth embodiment, the passivation (p a s s i v a t i ο η ) technique is changed to the organic insulating layer by adding a minimum number of engineering numbers. (Fourth Embodiment) In the fourth embodiment, as shown in Fig. 7 (d) and Fig. 8 (d), the formation of the contact formation process and the channel protective layer (etching stop layer) is approximately the same as The process of the third embodiment is carried out. After the photosensitive resin pattern 84C is removed, a PVCD device is used on the entire surface of the glass substrate 2 to cover, for example, ruthenium. 〇5 / m m film thickness of the second amorphous layer 3 3 containing impurities, such as phosphorus, in the source and drain wiring formation project, using a vacuum film forming device such as SPT, sequentially covering the film thickness 0" / / The m-thickness such as Ti, Ta, and the like, the heat-resistant metal film layer 34 is used as an anodizable heat-resistant metal layer, and the film thickness is 0. The aluminum film layer 3 of 3 // m is used as the same anodizable low-resistance wiring layer. The source/drain wiring material composed of the two-layer thin film and the second amorphous germanium layer 3 3 and the first amorphous germanium layer are sequentially etched by the fine processing technique using the photosensitive resin pattern 87. 3 1 B, and the gate insulating layer 3 0 A is exposed, as shown in FIG. 7(e) and FIG. 8(e), selectively forming a part of the pixel-containing electrode 2 2 by 3 4 A and 3 5 The gate electrode 2 of the insulated gate type transistor formed by the layer A of A, and the signal line 1 2 which also serves as the source-49-1300868 (47) line; the source-drain wiring is formed at the same time. The scanning line electrode terminal which is exposed at the same time as 1 2, 2 1 forms the field 5 A, and also forms the electrode terminal 5 of the scanning line and the electrode terminal 6 composed of a part of the signal line. At this time, the film thickness (black area) of the 8 7 A on the electrode terminals 5, 6 is, for example, 3 μm, which corresponds to the field 8 b of the source/drain wiring 1 2, 2 1 and the storage electrode 7 3 . Film thickness (in the grayscale field) 1 .  The photosensitive resin pattern 8 7 A ′ 8 7 B which is thicker than v m is formed in advance by the half-color g-week (h a 1 f t ο n e ) exposure technique, and is an important feature of the fourth embodiment. After the source/drain wiring 1 2 ' 2 1 is formed, the photosensitive resin patterns 8 7 A, 8 7B are reduced in thickness by the oxygen electric ash ashing means. When 5 / m or more, the photosensitive resin pattern 8 7 B disappears, the source/drain wirings 1 2, 2 1 and the accumulation electrode 713 are exposed, and the photosensitive resin can be selectively formed only on the electrode terminals 5, 6 Pattern 8 7C. In the oxygen plasma treatment, even if the pattern width of the photosensitive resin pattern 87C is reduced, an anodized layer is formed only around the electrode terminals 5 and 6 having a large pattern size, and it has little effect on electrical characteristics, yield, and quality. A feature that is worth mentioning. The photosensitive resin pattern 8 7 C is used as a mask to illuminate, and as shown in FIGS. 7(f) and 8( f), the source/drain wirings 1 2, 2 1 are anodized to form an oxide layer 6 8 . 6 9, simultaneously anodizing exposed to the second amorphous germanium layer 3 3 A on the lower side of the source/drain wiring 1 2, 2 1 , and the first amorphous germanium layer 3 1 A to form an oxidation of the insulating layer矽 layer (S i 0 2 ) 6 6,6 7. After the anodization is completed, the photosensitive resin pattern 8 7 C is removed, and as shown in Fig. 7 (g) and Fig. 8 (g), the electrode terminal 5 composed of the low-resistance film layer on which the anodized layer is formed is exposed on the side surface thereof. ' 6. Scanning line power -50- 1300868 (48) The side of the pole 6 'flows through the snubber current 9' through the anti-static short-circuit line 9 1 C ', so it is understandable compared to the electrode terminal 5' of the signal line. The thickness of the insulating layer formed on the side is thin. Also, when the right resistance is not strict, the source. The structure of the drain wiring I 2, 2 1 can be simplified to be an anodizable T a single layer. The active substrate 2 and the color filter thus obtained are bonded to each other to form a liquid crystal panel. The table 4 of the present invention is completed. The structure of the storage capacitor 15 is 'as shown in FIG. 7( g )', and the source/drain wiring 1 2, 2 1 and the storage electrode 73 including a part of the pixel electrode 2 2 are provided, and The protrusion of the front scanning line 1 and the like, the intermediate plasma protective layer 7 1 A, and the gate insulating layer 30 A are planarly overlapped (the upper left to the lower right oblique portion 5 2 ). In the fourth embodiment, the source/drain wirings 1 2, 2 1 and the second amorphous germanium layer 3 3 A and the first amorphous germanium layer 3 1 A are anodized because of the gate electrode Since the pixel electrode 22 to which the electrical connection is 21 is also exposed, the pixel electrode 22 is also anodized at the same time, which is greatly different from that of the first embodiment. Therefore, the resistance 値 is increased by anodization as the film quality of the transparent conductive layer constituting the pixel electrode 22 is different. In this case, it is necessary to appropriately change the film formation conditions of the transparent conductive layer in advance. Membrane, but anodizing does not reduce the transparency of the transparent conductive layer. In addition, the current 'the anode of the anodized electrode 2 1 and the pixel electrode 2 2 is also supplied through the channel of the insulated gate type transistor, but since the area of the pixel electrode 22 is large, a large reaction current is required. Or a long-term reaction 'No matter how strong the external light is, the resistance of the channel portion will become an obstacle. On the drain electrode 2 1 and the accumulation electrode 73, it is formed on the signal line 1 2 -51 - 1300868 (49) The anodized layer of the same plasma film and film thickness is difficult to achieve only by the extension of the reaction time. However, even if the anodized layer formed on the drain wiring 2 1 is not sufficiently complete, it is likely to be practically unreliable and reliable. The reason is as follows: 'The driving signal applied to the liquid crystal cell is substantially alternating, and the image is formed between the counter electrode 14 and the pixel electrode 22 (the drain electrode 2 1 ) so that the DC voltage component is reduced. At the time of inspection, the voltage of the counter voltage 14 is adjusted (the adjustment of the flicker is lowered), that is, the insulating layer may be formed in advance so that the DC component flows only on the signal line 12. The liquid crystal display device described above is a TN type liquid crystal cell, but an IPS (In-Plain·S witching) which controls the lateral electric field by forming a pair of counter electrode and a pixel electrode at a predetermined distance from the pixel electrode. The liquid crystal display device of the present embodiment is also applicable to the engineering reduction proposed by the present invention, and will be described in the following embodiments. (Fifth Embodiment) In the fifth embodiment, first, a vacuum film forming apparatus such as SPT is used to cover a film thickness on one of the main surfaces of the glass substrate 2. 1~0. The first metal layer of 3#m degree, as shown in FIG. 9(a) and FIG. 10(a), selectively forms the scanning line 1 1 and the opposite electrode which serve as the gate electrode Π A by the micromachining technique] 6 〇 Next, on the entire surface of the glass substrate 2, using a PC VD device, for example, 0. 3 // m-0. 05 " 0. The film thickness of 1 / m is sequentially covered with the first S iNx (germanium nitride) layer 30 which becomes the gate insulating layer, and the first amorphous germanium which is almost free of impurities and becomes the insulating gate type transistor channel. (a - S i ) layer 3 1, 1300868 (50) and three kinds of thin film layers such as the second SiNx layer 32 which is an insulating layer of the protective channel are selectively formed by microfabrication technique as shown in FIG. 9(b) The second SiNx layer on the residual gate electrode 1 1 A is made thinner than the gate electrode 1 A to expose the first amorphous germanium layer 3 1 as 3 2 A. Next, as shown in FIG. 10(b), the second amorphous layer 33 containing impurities such as phosphorus is covered on the entire surface of the glass substrate by using a PVCD device, for example, at a film thickness of about 5 Å. As shown in Fig. 9 (c) and Fig. 10 (c), in the field outside the pixel display portion, in the field of electrode terminal formation of the scanning line U, an opening portion 63A is formed (which also serves as a storage capacitor). An opening portion 65 A ) is formed in the electrode terminal forming region of the opposite electrode of the line, and the second amorphous germanium layer 3 3 and the first amorphous germanium layer 3 and the gate in the opening portion 6 3 A are selectively removed. The insulating layer 30 is exposed to expose a portion 72 of the scanning line 11. Next, on the entire surface of the glass substrate 2, a vacuum film forming apparatus such as SPT is used, and the film thickness is sequentially covered by 0. For example, a heat-resistant metal thin film layer 34 such as Ti or Ta is used as the heat-resistant metal layer, and an aluminum thin film layer 35 having a thickness of about 0·3 // m is used as the low-resistance wiring layer. Then, the source/drain wiring material composed of the two-layer thin film and the second amorphous layer 3 and the first amorphous layer are sequentially etched by the fine resin technique using the photosensitive resin patterns 86A and 86B. The layer 3 1 is exposed to expose the gate insulating layer 30, as shown in FIG. 9(d) and FIG. 1(d), on the gate insulating layer 30, selectively formed by the stacking of 34A and 35A. The gate electrode 2 1 of the gate insulating type transistor which is a pixel electrode and the signal line I 2 which also serves as the source wiring form the source/drain wiring 2, 2], and include the opening portion 63. The electrode terminal 6 formed by the electrode terminal 5 of the scanning line and one of the signal lines 12 is also formed at the same time as the inner portion 1300868 (51). At this time, in the same manner as in the third embodiment, the film thickness of 8 6 A on the signal line 1 is, for example, 3 " m, and is formed on the gate electrode 21 and the electrode terminal 5 by a halftone exposure technique. 6 on the 86B film thickness 1. 5/im is also thicker than the photosensitive resin pattern 8 6 A, 8 6 B. After the source/drain wirings 1 2 and 2 1 are formed, the photosensitive resin patterns 84A and 84B are reduced in thickness by 1·5 // m or more by the ashing means such as oxygen plasma, and the photosensitive resin pattern 86B is used. Disappearing, as shown in Fig. 9(e) and Fig. 1(e), while the drain wiring 2 1 and the electrode terminals 5, 6 are exposed, the photosensitive resin pattern 8 6C is selectively formed only on the signal line 1 2 . In the oxygen plasma treatment, it is preferable to suppress the change in the size by suppressing the anisotropy (the anisotropy) so that the pattern of the photosensitive resin pattern 86 6C is not narrowed. Further, when the limitation of the resistance 値 is not critical, the structure of the source/drain wirings 12 and 21 can be simplified into a single layer of Ta, Cr, Mo or the like. In this manner, the obtained active substrate 2 and color filter are bonded to each other to form a liquid crystal panel, and the fifth embodiment of the present invention is completed. In the photosensitive resin pattern 8 6C, an ordinary photosensitive resin containing a phenolic strontium resin as a main component is not used, but high purity is required, and the heat resistance of the main component using a polyacrylic resin or a polyimide resin is high. The necessity of the photosensitive organic insulating layer has been previously described. As for the structure of the storage capacitor 15 as shown in FIG. 9(e), the counter electrode (accumulation capacitance line) 16 and the pixel electrode (drain electrode) 2 1 intermediate gate insulating layer 30 are exemplified. Planar weight -54- 1300868 (52) The field of the stack 5 0 (the upper left to the lower right oblique line) constitutes an example of the storage capacitor 15 as for the gate electrode 2 1 and the front scanning line 1 1 the intermediate gate insulating layer It is also possible to constitute the storage capacitor 15 by 30, but the detailed description thereof is omitted here. Further, in Fig. 9(e), the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line are connected by a high-resistance member, and in the case of an IP S-type liquid crystal display device, since a transparent conductive layer is not required, it is used. An electrostatic countermeasure or design technique in which any one of a scanning line material, a signal line material, or a semiconductor layer is connected by an insulated gate type transistor or an elongated conductive line in an OFF state, although not specifically illustrated, The opening portion 63 3 A is provided to expose a portion of the scanning line 1 1 to the portion 7 2 , so that the countermeasure against static electricity is easily achieved. According to the fifth embodiment of the present invention, the organic insulating layer is selectively formed only on the signal line to promote the reduction of the manufacturing process, but the thickness of the organic insulating layer is 1 // m or more, thereby ensuring the gap precision of the liquid crystal cell. There will be obstacles. Therefore, in the sixth embodiment, a passivation technique in place of the organic insulating layer is provided by adding a minimum number of processes. (Sixth Embodiment) In the sixth embodiment, as shown in Fig. 1 1 (c) and Fig. 1 2 (c), the opening portion 63 A is formed until the scanning line 1 is formed in the electrode terminal forming region of the scanning line]1. One of the portions 7 and 2 is almost the same as the fifth embodiment. Next, in the source/drain wiring formation process, the SPT Temple vacuum film is used to directly cover the film thickness (7), such as T i, T a and other heat-resistant metal film layer 34 as an anodizable heat-resistant gold. -55- 1300868 (53) genus layer, film thickness 0. The aluminum film layer 3 of 3 / m is used as the same low-resistance wiring layer which can be oxidized by the anode. Then, the source/drain wiring material composed of the two-layer thin film and the second amorphous sand layer 3 3 and the second amorphous sand layer 3 1 are formed by the fine processing technique using the photosensitive resin pattern 87. The exposed insulating layer 30 is exposed, as shown in FIG. 11 (d) and FIG. 2 (d), and a layer of 34A and 35A is selectively formed on the gate insulating layer 30 to form an insulating layer of the pixel electrode. The gate electrode 21 of the gate type transistor and the signal line 12 which also serves as the source wiring. When the source/drain wirings 1 2, 2 1 are formed, the electrode terminals 5 including the scanning lines of a portion 7 2 of the scanning lines 1 1 exposed in the openings 63 A are formed simultaneously and by the signal lines. A part of the electrode terminal 6 is formed. At this time, the film thickness (black area) of the 8 7 A on the electrode terminals 5, 6 is, for example, 3 // m, which corresponds to the field 8 7B (intermediate adjustment field) corresponding to the source/drain wiring 12, 2 1 . Film thickness 1 .  The light-sensitive resin pattern 87 A, 87B, which is 5 / m thick, is formed in advance by a halftone exposure technique, which is an important feature of the sixth embodiment. After the source/drain wirings 1 2, 2 1 are formed, the photosensitive resin patterns 87 A and 87B are reduced in film thickness by an ashing means such as oxygen plasma. When 5 / m or more, the photosensitive resin pattern 87B disappears, and the source/drain wirings 1 2, 2 1 are exposed, and the photosensitive resin patterns 87 A, 87B can be selectively formed only on the electrode terminals 5, 6. Then, the photosensitive resin pattern 8 3 is used as a mask to irradiate light, and the oxide layer 6 is formed by anodizing the source/drain wirings 1 2, 2 ] as shown in Fig. 1 1 (e) and Fig. 1 2 (e). 8,6 9, at the same time, the anodic oxidation is exposed to the second amorphous germanium layer 3 3 A and the third amorphous germanium layer 3 1 A on the lower side of the source/drain wiring] 2, 2 1 to form an insulating layer. -56- 1300868 (54) Cerium oxide layer (Si〇2) 66,67. After the completion of the anodization, when the photosensitive resin pattern 8 7 C is removed, as shown in Fig. 1 1 (f) and Fig. 12 (f), the electrode terminal 5'6 composed of the low-resistance film layer is exposed. Further, the structure of the S-header source/drain wiring 1 2 ' 2 1 which is not restricted by the resistance 亦可 can be simplified into an anodizable single layer. In this manner, the obtained active substrate 2 and color filter are bonded to each other to form a liquid crystal panel, and the sixth embodiment of the present invention is completed. Regarding the structure of the storage capacitor 15 as shown in FIG. 11 (f), the counter electrode (accumulation capacitance line) 16 and the pixel electrode (drain electrode) 2 1 intermediate gate insulating layer 3 0 are exemplified. The overlapping area 50 (the upper left to the lower right oblique line portion) constitutes an example of the storage capacitor 15. Further, in Fig. 11 (f) and Fig. 12 (f), the countermeasure against static electricity which is connected by the high-resistance member between the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line is not particularly shown, so the signal The electrode terminal 6 of the wire 12 is different from the source/drain wiring 1 2, 2 1 in that an anodized layer of an insulating layer is formed only on the side surface, and anodization is not formed on the side surface of the electrode terminal 5 of the scanning line 1 1 . The layer is provided with the opening portion 63 A to expose a portion 7 2 of the scanning line 11 as described above, so that it is easy to carry out the countermeasure against static electricity, and the electrode at the scanning line 1 1 is used for the countermeasure against static electricity. The side of the terminal 5 also forms a thin anodized layer, and it goes without saying. In the fifth and sixth embodiments, when the drain wiring is formed, a novel passivation method is applied by applying a halftone exposure technique, and engineering reduction is also performed, and the liquid crystal display device is realized by four masks. In the same manner as in the first to fourth embodiments, the halftone (halftone) exposure technique is formed by forming an opening portion of the engineering and gate insulating layer at -57-1300868 (55) of the etch-off layer. The liquid crystal display device for producing a reticle is described in the seventh and eighth embodiments because it is expected to further reduce the manufacturing process. (Seventh Embodiment) In the seventh embodiment, first, a vacuum film forming apparatus such as SPT is used to cover the film thickness on one main surface of the glass substrate 2. 1 ~ 〇. The metal layer of the 3/m level, as shown in Fig. 13 (a) and Fig. 14 (a), selectively forms the scanning line 1 1 and the pair which serve as the gate electrode 1 1 A by the micromachining technique. Next to the electrode 16 6 , on the entire surface of the glass substrate 2, a PC VD (plasma chemical vapor deposition) device is used to sequentially cover 〇·3 vm - 0 · 0 5 // m - 0 · 1 μm. a first S iN X (tantalum nitride) layer 30 that becomes a gate insulating layer, and a first amorphous germanium (a-Si) layer 31 that is substantially free of impurities and serves as a channel for the insulating gate type transistor. And three types of thin film layers, such as the second SiNx layer 3 2 which is an insulating layer of the protective channel, have an opening portion 6 3 A in the field of electrode terminal formation of the scanning line ij in the field outside the image display portion, and at the same time as the protective insulating layer In the field of formation, that is, the film thickness of the field 82A on the gate electrode A is 2 # m, and a photosensitive resin pattern thicker than the film thickness 1 β m of the other field 82B is formed by a halftone exposure technique. 82A, 82B, with the photosensitive resin pattern 8 2 A, 8 2 B as a mask, as shown in FIG. 3 (b) and FIG. 14 (b), selectively removing the opening 63A 2 SiNx layer 32, and 3], a first amorphous silicon layer and the gate insulating layer 3 billion electrode, is exposed scan -58- (56) 1300868 1 1 one part of the line 72. When the photosensitive resin pattern 8 2 A, 8 2 B is reduced by a thickness of 1 // m or more by the ashing means such as oxygen plasma, the photosensitive resin pattern 82B disappears, as shown in FIG. 13(c) and FIG. As shown in FIG. 4(c), the second SiNx layer 3 2B is exposed, and the photosensitive resin pattern 82C can be selectively formed only in the field of protective insulating layer formation. In the above oxygen plasma treatment, it is preferable to enhance the anisotropy (tropicality) in order to suppress the change in the pattern size, which has been described previously. Next, as shown in FIG. 13 (c) and FIG. 14 (c), the photosensitive resin pattern 8 2C is used as a mask, and the second SiNx layer 32 is selectively etched to be wider than the gate electrode 1 1 A. The second SiNx layer 32 is fine, and the first amorphous layer 31 is also exposed. At this time, a part of the exposed portion of the scanning line 1 1 is exposed to the etching gas or the etching of the second SiNx layer 32. Therefore, it is necessary to note that the scanning line 11 is included as the material of the scanning line 1 1 is different. The film thickness of a portion 72 is reduced, but the countermeasures are as described previously. Then, the photosensitive resin pattern 82C is removed, and the second amorphous germanium layer 3 containing impurities such as germanium is covered on the entire surface of the glass substrate 2 by a PCVD apparatus, for example, at a thickness of about 0.05 μm. A vacuum film forming apparatus such as SPT is used to sequentially cover a film thickness of m m such as Ti 'Cr, Mo, or the like, as a heat resistant metal film, and a film thickness 〇.  The aluminum film layer 3 of 3 / m is used as a low-resistance wiring layer. Next, the source/drain wiring material and the second amorphous germanium layer 3 and the first layer formed by the two-layer thin film are sequentially etched by the micro-machining technique using the photosensitive resin patterns 8 6 A, 8 6 B An amorphous germanium layer 3 1 is exposed to expose the gate insulating layer 30, and on the gate insulating layer 30, a layer of 34 A and -59-1300868 (57) 3 5 A is selectively formed into a pixel. The gate electrode 2 of the gate of the electrode and the signal line 12 which also serves as the source wiring also include the exposed opening portion 6 when the source/drain wiring 1 2, 2 1 is formed. An electrode terminal 6 composed of a portion of the electrode terminal 5 and the signal line 12 of the scanning line is formed by the second amorphous germanium layer 3 3 C in the vicinity of A. At this time, similarly to the third embodiment, the film thickness of 86 A on the signal line 12 is, for example, 3 // m, and the ratio is formed by the halftone (ha 1 ft ο s ) exposure technique and the gate electrode 2 1 . The film thickness of 86B on the electrode terminals 5, 6 is 1. 5 # m is also thick photosensitive resin pattern 86A, 86B. After the source/drain wirings 1 2, 2 1 are formed, the photosensitive resin patterns 86 A and 86B are reduced in film thickness by an ashing means such as oxygen plasma. When 5 / m or more, the photosensitive resin pattern 86B disappears, and as shown in FIG. 13 (f) and FIG. 4 (f), the gate electrode 21 and the electrode terminals 5, 6 are exposed, and only the signal line 1 can be used. The photosensitive resin pattern 8 6 C is selectively formed on 2. In the oxygen plasma treatment, it is preferable to enhance the anisotropy (tropicality) and to suppress the change in the pattern size so that the pattern of the photosensitive resin pattern 8 6 C is not narrowed. If the limitation of the resistance 値 of the source/drain wirings 12 and 2 is not critical, it can be simplified into a single layer. The obtained active substrate 2 and color filter are bonded to each other to form a liquid crystal panel, and the seventh embodiment of the present invention is completed. In the photosensitive resin pattern 8 6C, an ordinary photosensitive resin containing a bismuth phenolate resin as a main component is not used, but a high-sensitivity photosensitive material having a high purity and a high viscosity of a main component containing a polyacrylic resin or a polyimide resin must be used. The necessity of an organic insulating layer has been described previously in -60-1300868 (58). Regarding the structure of the storage capacitor 1 5, as shown in Fig. 13 (f), the counter electrode (accumulation capacitance line) 16 and the pixel electrode (drain electrode) 2 1 intermediate gate insulating layer 3 0 are illustrated. On the other hand, the planar overlapping field 10 field (the upper left to the lower right oblique line portion) constitutes an example of the storage capacitor 〖5, and the pole wiring 2 1 and the preceding scanning line 1 1 are the intermediate gate insulating layer 3 〇 to constitute the storage capacitor. It is also possible to use 1 5, and detailed description thereof is omitted here. Further, in Fig. 13 (f), between the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line, a high-resistance member such as an insulated transistor or an elongated conductivity in an OFF state is used. The static electricity countermeasures for the connection of the line are not shown in the figure. However, since the opening portion 6 3 A is provided and the part of the scanning line y j is exposed, the static electricity countermeasure is easy to adopt. According to the seventh embodiment of the present invention, the organic insulating layer is formed on the signal line to reduce the manufacturing process. However, since the thickness of the organic insulating layer is j // m or more, the gap precision of the liquid crystal cell may be ensured. There are obstacles. Therefore, in the eighth embodiment, a passivation technique in place of the organic insulating layer is provided by adding a minimum number of engineering numbers. (Eighth Embodiment) In the eighth embodiment, as shown in Fig. 15 (d) and Fig. 16 (d), the opening portion 6 3 A is formed until the electrode terminal forming region of the scanning line 1 1 is exposed. A portion of the scanning line 1 1 and a portion of the etched layer 3 2 A are formed in the same manner as in the seventh embodiment. Next, the above-mentioned photosensitive resin pattern 8 2 C is removed in order to fully use the glass substrate. 1300868 (59) PC VD device covers, for example, 0. The second amorphous layer 33 containing a film thickness of 5 μm, such as phosphorus, is covered with a vacuum film forming apparatus such as SPT. 〗 〖Vm degree such as Ti, Ta and other heat-resistant metal film layer 34 as an anodizable heat-resistant metal layer, followed by a film thickness of // 3 / m of aluminum film layer 35 as the same anodizable low-resistance wiring Floor. Next, the source/drain wiring material composed of the two-layer thin film and the second amorphous germanium layer 3 3 are sequentially sequentially etched using the photosensitive resin patterns 8 7 A, 8 7 B by a microfabrication technique. The first amorphous germanium layer 3 1, exposes the gate insulating layer 30, as shown in FIG. 15(e) and FIG. 16(e), on the gate insulating layer 30, selectively formed by 34A and 35 The gate electrode 2 of the insulating gate type transistor which becomes the pixel electrode and the signal line 12 which also serves as the source wiring is formed in the source and drain wiring 1 2, 2 At 1 o'clock, the second amorphous germanium layer 3 3 C in the vicinity of the opening portion 6 3 A is simultaneously formed to form the electrode terminal 5 of the scanning line and the electrode terminal 6 composed of a part of the signal line. At this time, the film thickness (black field) of the 8 7 A on the electrode terminals 5, 6 is, for example, 3 // m, and the ratio of the formation is previously formed by the halftone exposure technique to correspond to the source/drain wiring 1 2, 2 1 field 8 7 B (gray scale area) film thickness 1 · 5 // m Thick photosensitive resin patterns 8 7 A, 8 7 B are important features of the eighth embodiment. After the source/drain wirings 1 2, 2 1 are formed, the photosensitive resin patterns 87A, 87B are reduced in film thickness by an ashing means such as oxygen plasma. When 5 /i m or more, the photosensitive resin pattern 8 7 B disappears, and the source/drain wirings 1 2, 2 1 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the electrode terminals 5, 6. Here, the photosensitive resin pattern 87C is used as a cover 1300868 (60) to illuminate the light, and as shown in Fig. 15 (f) and Fig. 16 (f), the anode is oxidized. The drain wiring 1 2, 2 1 forms an oxide layer 6 8 ' 6 9 ·' while anodizing is exposed to the second amorphous germanium layer 3 3 A on the lower side of the source/drain wiring 1 2, 2 1 , and The first amorphous germanium layer 3 1 A forms a tantalum oxide layer (SiO 2 ) 66, 67 of an insulating layer.

After the anodization is completed, the photosensitive resin pattern 8 7 c ' is removed as shown in Fig. 15 (g) and Fig. 16 (g), and the electrode terminals 5, 6 composed of a low-resistance film are exposed. When the limitation of the resistance 并不 is not critical, the structure of the source/thin wiring 1 2, 2 ] can be simplified to an anodizable Ta single layer, as shown in Fig. 15 (g) and Fig. 16 (g). The countermeasure against static electricity connected between the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line by a high-resistance member is not particularly shown, and the electrode terminal 6 of the signal line 2 is only connected to the source/drain wiring 1 2, 2 1 different side, the anodized layer of the insulating layer is changed, but it is not necessary to explain that the electrode terminals of the static electricity are connected by appropriate conductive members, and a plurality of anodes are also formed on the side of the electrode terminal 6 of the scanning line. Oxide layer. In this manner, the obtained active substrate 2 and the color filter are bonded to each other to form a liquid crystal panel, and the eighth embodiment of the present invention is completed. As shown in FIG. 15 (g), the structure of the storage capacitor 15 is displayed, and the counter electrode (accumulation capacitance line) 16 is overlapped with the pixel electrode (drain electrode) 2 1 intermediate gate insulating layer 30. The field (the lower right oblique line portion) constitutes an example of the storage capacitor 15 . [Effect of the Invention] As described above, in the liquid crystal display device of the present invention, the insulating gate-63-1300868 (61) pole type transistor has a protective insulating layer on the channel, so that it is only in the source of the image display portion. Selectively forming a photosensitive organic insulating layer on the wiring, or only on the signal line, or anodizing the source/drain wiring formed of the anodizable source and the drain wiring to form an insulating layer. Passivation function. Therefore, the insulating gate type transistor which does not have a special heating process and which has an amorphous germanium layer as a semiconductor layer does not require excessive heat resistance. In other words, there is also an effect of passivation formation without deterioration of electrical properties. Further, when the source/drain wiring is anodized, the electrode terminal of the scanning line or the signal line can be selectively protected by introducing a halftone exposure technique, which can prevent an increase in the number of photo etching processes. In addition, by introducing a halftone exposure technique, a mask can be used to process the formation of the etch-off layer, and the engineering of the opening formation of the gate insulating layer is reduced by the pseudo-pixel electrode. The introduction of 'processing of the pixel electrode and the scanning line with a mask can rationalize the number of photographic etching processes from the previous five times, and the liquid crystal display device can be fabricated using four or three masks. This is the result of reducing the number of manufacturing processes for the active substrate. From the point of view of overall cost reduction, it is the biggest feature that has been specifically mentioned. Moreover, the pattern precision requirements of these projects are not very high, so they have little effect on yield or quality, and are also easy to produce and manage. Further, in the IP S-type liquid crystal display device produced in the fifth and seventh embodiments, the electric field generated between the counter electrode and the pixel electrode is applied only to the gate insulating layer, and the sixth and the sixth According to the eighth embodiment of the present invention, the PS-type liquid crystal display device is applied to the gate insulating layer and the anodized layer of the pixel electrode, so that the conventional defect of the intermediary is not so severe -64-1300868 (62) The advantage of purifying the insulating layer and having a phenomenon of scorching after the display image is not negligible. Since the anodization G of the drain wiring (pixel electrode) is inferior to the δ-bar insulating layer as it functions as a high-resistance layer, no charge accumulation is generated. In addition, the requirements of the present invention, as can be seen from the above description, are in the case of an insulated gate type transistor which is cut-off type, using anodizable source and drain wiring, and anodizing source and drain In addition to the other configuration, the semiconductor device for a display device such as a material or a film thickness of a different pixel electrode, a gate insulating layer, or the like, or a manufacturing method thereof, also belongs to the present invention. It is apparent in the field that the practicality of the present invention is constant even for a reflective liquid crystal display device, and the semiconductor layer of the insulated gate type transistor is not limited to an amorphous germanium. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device for a display device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device for display splicing according to the first embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device for a display device according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the second embodiment of the present invention. Fig. 5 is a plan view showing a crucible and a conductor device for a display device according to a third embodiment of the present invention. -65- 1300 868 (63) Fig. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the third embodiment of the present invention. Fig. 7 is a plan view showing a semiconductor device for a display device according to a fourth embodiment of the present invention. Fig. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device for a display device according to the fourth embodiment of the present invention. Fig. 9 is a plan view showing a semiconductor device for a display device according to a fifth embodiment of the present invention. Figure 10 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a fifth embodiment of the present invention. Fig. 11 is a plan view showing a semiconductor device for a display device according to a sixth embodiment of the present invention. Fig. 12 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a sixth embodiment of the present invention. Fig. 13 is a plan view showing a semiconductor device for a display device according to a seventh embodiment of the present invention. Figure 14 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to a seventh embodiment of the present invention. Fig. 15 is a plan view showing a semiconductor device for a display device according to an eighth embodiment of the present invention. Fig. 16 is a cross-sectional view showing the manufacturing process of a semiconductor device for a display device according to an eighth embodiment of the present invention. Fig. 7 is a perspective view showing a mounted state of the liquid crystal panel. Fig. 18 is an equivalent circuit diagram showing a liquid crystal panel. -66- 1300868 (64) Figure 19 is a cross-sectional view showing a conventional liquid crystal panel. Figure 20 is a plan view showing an active substrate of a conventional example. Fig. 21 is a cross-sectional view showing the manufacturing process of the active substrate of the conventional example. . Figure 22 is a cross-sectional view showing the rationalized active substrate. Figure 2 is a cross-sectional view showing the manufacturing process of the rationalized active substrate. [Description of Symbols] 1 Liquid crystal panel 2 active substrate (glass substrate) 3 Semiconductor integrated circuit wafer 4 TCP film 5, 6 electrode terminal 9 color filter (opposite glass substrate) 1 〇 Insulated gate type transistor 11 scanning Line (gate electrode) 12 signal line (source wiring, source electrode) 16 common capacitance line (opposite electrode among IPS type electrodes) 1 7 liquid crystal 1 9 polarizing plate 2 0 alignment film 21 drain electrode ( Among the IPS type electrodes, it is a pixel electrode) 22 (transparent conductive) pixel electrode 3 0 gate insulating layer (1st S i NX layer) -67- 1300868 (65) 3 1 (without impurities) 2 amorphous germanium layer 32 second SiNx layer 33 (containing impurities) second amorphous germanium layer 34 (anodable) heat resistant metal layer 3 5 (anodable) low resistance metal layer (aluminum) 36 (anode Oxidized) intermediate conductive layer 3 7 passivation insulating layer

5 0,5 1, 5 2 Accumulated capacitance field 62 (on the drain electrode) 6 3,6 3 A (on the scanning line) opening 64 (on the signal line) opening 6 5,6 5 A ( The oxidized ruthenium layer 67 containing impurities on the counter electrode 66 on the counter electrode does not contain impurities. The oxidized sand layer 68 is anodized (titanium oxide, TiO 2 )

69 anodized layer (alumina, Al2〇3) 70 anodized layer (molybdenum pentoxide, Ta205) 7 1 plasma protective layer 7 3 accumulation electrode 7 2 one of the scanning lines 83 (usual for forming a pixel electrode) Photosensitive resin pattern 8 2, 8 4, 8 7 (formed by halftone exposure) photosensitive resin pattern 8 5, 8 6 (formed by halftone exposure) photosensitive organic insulating layer - 68 - 1300868 (66) 9 1 transparent conductive layer 92 first metal layer

-69-

Claims (1)

ι·织, 1997, 6 Η 苜 苜 修 repair (more), this application, patent scope 1 · A liquid crystal display device having at least an insulated gate type transistor on one main surface, and also serves as the aforementioned insulating gate The scanning line of the gate electrode of the polar transistor, the signal line which also serves as the source wiring, and the unit pixel of the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix to form the first transparency. a liquid crystal display device in which an insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with liquid crystal; and the feature is at least first transparent One of the main surfaces of the insulating substrate is formed with a scanning line composed of one or more metal layers; one or more gate insulating layers are interposed on the gate electrode, and the first semiconductor layer containing no impurities is formed. In the form of an island; a protective insulating layer having a width wider than the gate is formed on the first semiconductor layer on the gate electrode; and a portion of the protective layer and the first semiconductor layer are formed by Second semiconductor layer and anode capable of containing impurities The layer of the oxidized metal layer constitutes a source/drain wiring; in a portion of the drain wiring and the gate insulating layer, in a field outside the transparent conductive pixel electrode and the pixel display portion, An electrode terminal having a transparent conductivity is formed on the signal line; an anodized layer is formed on the surface of the source/drain wiring except for the field overlapping the pixel electrode of the drain wiring and the electrode terminal of the signal line. 2. A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring. And a first transparent -70-1300868 (71) insulating substrate on which a unit pixel such as a pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix, and the first transparent insulating substrate facing the first transparent insulating substrate a liquid crystal display device in which a liquid crystal is filled between a second transparent insulating substrate or a color filter; and a transparent conductive layer and a first surface are formed on at least one main surface of the first transparent insulating substrate 1 scanning layer composed of a metal layer and a transparent conductive pixel electrode and the same signal line electrode terminal; on the gate electrode, a plasma protective layer and a gate insulating layer are formed in an island shape to form no impurities a first semiconductor layer; the gate electrode has a wider and finer protective insulating layer formed on the first semiconductor layer on the gate electrode; and the plasma protective layer and the gate insulating layer on the pixel electrode form an opening Ministry; a portion of the edge layer and a portion of the first semiconductor layer and the electrode terminal of the signal line are formed by forming a second semiconductor layer containing impurities and laminating with one or more second metal layers a pole (signal line) wiring, and a drain wiring is formed on a portion of the protective layer and a portion of the pixel electrode on the first semiconductor layer and the opening; and the source/drain wiring On top, a photosensitive organic insulating layer is formed. A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring And a first transparent insulating substrate in which a unit pixel such as a pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix, and a second transparent insulating substrate facing the first transparent insulating substrate Or a liquid crystal display device which is filled with liquid crystal between the color filters, and is characterized in that: at least one main surface of the first transparent insulating substrate, 1300868 (72) is formed by the transparent conductive layer and the first a scan line formed by laminating a metal layer and a transparent conductive pixel electrode; a plasma protective layer and a gate insulating layer are interposed on the gate electrode to form a first semiconductor layer containing no impurities; a protective insulating layer having a width wider than the gate electrode is formed on the first semiconductor layer on the gate electrode; and a plasma protective layer and a gate insulating layer on the pixel electrode form an opening; One of the protective insulation layers a source (signal line) wiring formed by laminating a second semiconductor layer containing impurities and a second metal layer containing one or more layers on the first semiconductor layer, and a portion of the protective layer On the first semiconductor layer and a part of the pixel electrode in the opening, a drain wiring is formed in the same manner, and a photosensitive organic insulating layer is formed on the signal line in addition to the electrode terminal of the signal line. A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and a signal line which also serves as a source wiring. And a first transparent insulating substrate in which a unit pixel such as a pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix, and a second transparent insulating substrate or color that faces the first transparent insulating substrate a liquid crystal display device in which a liquid crystal is filled between the filters; and characterized in that a scanning line composed of a layer of a transparent conductive layer and a metal layer is formed on at least one main surface of the first transparent insulating substrate And a transparent conductive pixel electrode; a plasma protective layer and a gate insulating layer are interposed on the gate electrode to form a first semiconductor layer containing no impurities; and the first semiconductor layer on the gate electrode is Forming a 72-1300868 (73) insulating layer which is thinner than the gate width; forming a opening portion of the plasma protective layer and the gate insulating layer on the pixel electrode; and forming a portion of the protective insulating layer And the first semiconductor layer a source (signal line) wiring formed by laminating a second semiconductor layer containing impurities and an anodizable metal layer, and a portion of the protective layer and the first semiconductor On the layer and the first transparent insulating substrate and a part of the pixel electrode in the opening, a drain wiring is also formed; in addition to the electrode terminal of the signal line, an anode is formed on the surface of the source/drain wiring. Oxide layer. #5 - A liquid crystal display device having at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source wiring signal a line, and a pixel element connected to the drain of the source gate type transistor, and a unit pixel such as a counter electrode formed by a predetermined distance from the pixel electrode, are arranged in a two-dimensional matrix. a transparent insulating substrate and a liquid crystal display device in which a liquid crystal is filled between a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate; β is characterized by being at least On one main surface of the first transparent insulating substrate, a scanning line and a counter electrode formed of one or more metal layers are formed, and one or more gate insulating layers are interposed on the gate electrode to form an island shape. a first semiconductor layer containing _ impurity; a protective insulating layer formed on the first semiconductor layer on the gate electrode and having a finer width than the gate electrode; and a portion of the protective layer and the first semiconductor On the layer The second source - the source (signal line) wiring composed of the semiconductor layer and the second metal layer of one or more layers, and the drain wiring (pixel electrode): CS except the signal line -73- 1300868 (74): a photosensitive organic insulating layer is formed on the signal line other than the electrode terminal; and the electrode terminal of the scanning line is formed by an opening portion including a gate insulating layer formed on the scanning line in a region outside the image display portion The second metal layer. 6 is a liquid crystal display device having at least an insulating _ gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a signal line of the source wiring And a pixel element connected to the drain electrode of the source gate type transistor, and a unit pixel of a counter electrode formed by a predetermined distance from the pixel electrode, and arranged in a matrix of two φ dimensional matrix A transparent liquid crystal display device in which a transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with liquid crystal; and is characterized in that it is at least first On one main surface of the transparent insulating substrate, a scanning line and a counter electrode composed of one or more metal layers are formed; and one or more gate insulating layers are interposed on the gate electrode to form an island-like shape without impurities. a first semiconductor layer; a protective insulating layer which is wider than the gate electrode is formed on the first semiconductor layer on the gate electrode; and a portion of the protective layer and the #1 semiconductor layer Formed by impurities Source (signal line) wiring formed by lamination of the second semiconductor layer and the anodizable metal layer, and drain wiring (pixel electrode); in addition to the electrode terminal of the signal line, at the source and the drain An anodized layer is formed on the surface of the wiring; an electrode terminal of the scanning line, which is outside the image display portion, is composed of an anodizable metal layer formed by an opening portion of the gate insulating layer formed on the scanning line. - 7 - A liquid crystal display device having at least an insulating gate type transistor on a main surface, and also serving as a gate electrode of the above-mentioned insulated gate type transistor (S) - 74 - 1300868 (75) * a scanning line, a signal line which also serves as a source wiring, and a pixel electrode connected to the drain of the source gate type transistor, and a counter electrode formed by a specific distance from the pixel electrode. The pixel is arranged in a two-dimensional matrix-shaped first transparent insulating substrate, and the second transparent insulating substrate or the color filter that faces the first transparent β-insulating substrate is filled with liquid crystal. a liquid crystal display device characterized in that a scanning line and a counter electrode composed of one or more metal layers are formed on at least one main surface of the first transparent insulating substrate; and one layer is interposed on the φ gate electrode The gate insulating layer is formed in an island shape to form a first semiconductor layer not containing impurities; and the first semiconductor layer on the gate electrode is formed with a protective insulating layer which is wider than the front electrode; and the protective layer is One part and the first half On the layer, a source (signal line) wiring and a drain wiring (pixel electrode) including a second semiconductor layer containing impurities and a second metal layer of one or more layers are formed, and an electrode terminal of the signal line is formed. In addition, a photosensitive organic insulating layer is formed on the signal line; the electrode terminal of the scanning line is a second metal layer formed by an opening including a gate insulating layer formed on the scanning line in a field outside the image display portion. And laminated with the second metal layer. 8 is a liquid crystal display device having at least an insulating-gate type transistor on a main surface, and also serving as a gate electrode of the insulating gate type transistor, and also serving as a source wiring. a signal line, and a pixel electrode connected to the drain of the source gate type transistor, and a unit pixel of a counter electrode formed by a specific distance from the pixel electrode are arranged in a two-dimensional matrix Liquid crystal display in which liquid crystal is filled between a first transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent -75-1300868 (76) insulating substrate The device is characterized in that a scanning line and a counter electrode composed of one or more metal layers are formed on at least one main surface of the first transparent insulating substrate, and one or more gates are interposed on the gate electrode. a first insulating layer containing no impurities is formed in an island shape in a pole insulating layer; a protective insulating layer having a wider width than the gate electrode is formed on the first semiconductor layer on the gate electrode; and one of the protective layers is formed on the first semiconductor layer And the first semiconductor layer Source (signal line) wiring and drain wiring (pixel electrode) composed of a laminate of a second semiconductor layer containing impurities and an anodizable metal layer: in addition to the electrode terminal of the signal line, at the source · The surface of the drain wiring forms an anodized layer; the electrode terminal of the scan line is outside the pixel display portion, and the second semiconductor layer and the anode are formed by including an opening portion of the gate insulating layer formed on the scan line It consists of a layer of oxidized metal layers. 9 A method of fabricating a liquid crystal display device on a main surface of a scan line having at least an insulating gate type transistor and also serving as a gate electrode of the insulated gate type transistor, and also serving as a source wiring The signal line and the unit pixel connected to the pixel electrode of the drain wiring are a first transparent insulating substrate arranged in a two-dimensional matrix shape, and a second transparent insulating layer facing the first transparent insulating substrate a liquid crystal display device in which a liquid crystal is filled between a substrate or a color filter; and a scanning line composed of a metal layer of one or more layers is formed on at least one main surface of the first transparent insulating substrate. Engineering; sequentially covering more than one layer of the gate insulating layer, and the first amorphous germanium layer containing no impurities, -76-1300868 (77) and the protective insulating layer; in the field of electrode terminal formation of the scan line' Forming a photosensitive resin pattern having an opening portion and a thickness of a protective insulating layer formed on the gate electrode to be thicker than other fields; removing the protective insulating layer and the first amorphous germanium layer in the opening portion and The gate insulating layer' is exposed to the electrode terminal forming field of the scanning line; the film thickness of the photosensitive resin pattern is reduced to expose the protective insulating layer; the residual width on the gate electrode is more than the gate electrode Finely protecting the insulating layer to expose the first amorphous germanium layer; after removing the photosensitive resin pattern, completely covering the second amorphous germanium layer containing impurities; in a manner overlapping the protective layer portion, Forming a source (signal line) and a drain wiring formed by laminating a second amorphous germanium layer and one or more layers of anodizable metal layers; and forming one of the gate insulating layer and the aforementioned drain wiring In part, in the field of the transparent conductive pixel electrode and the image display portion, a transparent conductive electrode terminal is formed on the signal line; and the selective pattern formed by the pixel electrode and the electrode terminal is formed. The resin pattern serves as a mask to protect the pixel electrode and the electrode terminal, and at the same time, the anodizing source and the drain are matched with the Lu wire. The method for manufacturing a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type electro-crystal body, and also serves as a source a signal line of the pole wiring, and a first transparent insulating substrate in which a unit pixel such as a pixel electrode connected to the drain wiring is arranged in a two-dimensional matrix, and the first transparent insulating layer is opposed to the first transparent insulating substrate. A method for manufacturing a liquid crystal display device in which a liquid crystal is filled between a second transparent insulating substrate or a color filter of a substrate; wherein: -77- one of the main surfaces of the substrate is formed of a transparent product The processing of the extremes of the scanning line and the signal line; the electrode terminal of the first amorphous germanium layer and the protective insulating wire which are covered with the plasma protective material is sequentially formed, and the field of the gate electrode and the protective electrode are formed in the field of the opening. Further, the protective insulating layer in the photosensitive opening portion and the first slurry protective layer and the first metal layer are thicker, and the thickness of the photosensitive resin pattern is the same as that of the electrode terminal of the wire, and remains on the gate electrode. a process of exposing the first amorphous germanium layer to the gate electrode; and completely covering the second amorphous metal layer containing the impurity, forming a second metal layer and forming an electrode terminal formed on the signal line The source wiring (signal line) phase wiring of the field and the edge layer. The manufacturing method is a signal line on the main surface and also serving as the insulated gate type and the source wiring, and the unit pixel of the electrode is arranged as the two substrates' and 1 through 1300868 (78) at least between the first transparent insulating conductive layer and the first metal layer of the pseudo-electrode terminal and the pseudo-pixel electrical layer and the gate insulating layer and does not contain the impurity layer; in the scan line and signal On the quasi-pixel electrode, the process of forming a film thickness in the field of formation of the edge layer is compared with the resin pattern; removing the amorphous germanium layer and the gate insulating layer and the transparent transparent conductive scan line and the signal pixel electrode Engineering; reduction and exposure of the protective insulation layer; extremely wide and finer protective insulation layer in addition to the aforementioned photosensitive resin pattern after the enamel layer; covering more than 1 layer 2 amorphous enamel layer and 1 or more layers of protective insulation The layer partially overlaps the surface of the pixel electrode having a photosensitive organic equivalent, and forms a drain electrode. 1 A liquid crystal display device has at least an insulating gate type transistor, and a scan line of the gate electrode of the body Liquid crystal is formed between the second transparent insulating substrate or the color filter of the first transparent insulating substrate-78· 1300868 (79), which is connected to the surface of the above-described drain wiring. A method of manufacturing a liquid crystal display device, characterized in that a scanning line and a pseudo-pixel element formed by laminating a transparent conductive layer and a first metal layer are formed on at least one main surface of the first transparent insulating substrate Engineering; sequentially covering the plasma protective layer and the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; in the field of electrode terminal formation of the scan line, on the pseudo-pixel electrode Forming a photosensitive resin pattern having an opening portion and a thickness of a protective insulating layer formed on the electrode to be thicker than other fields; removing the protective insulating layer and the first amorphous germanium layer and the gate insulating layer in the opening portion And the plasma protective layer and the first metal layer, and the electrode terminal of the transparent conductive scan line is formed in the same field to expose the pixel electrode; reducing the film thickness of the photosensitive resin pattern to be exposed The protection of the insulating layer; on the gate electrode, the protective insulating layer is thinner than the gate electrode to expose the first amorphous germanium layer; after removing the photosensitive resin pattern, the entire surface is covered with impurities. a second amorphous germanium layer; after covering the second metal layer of one or more layers, respectively, corresponding to a source wiring (signal line) partially overlapping the protective insulating layer, and a portion partially overlapping the protective insulating layer The electrode wiring of the element electrode, and the electrode terminal of the scanning line of the electrode terminal forming the transparent conductive scanning line, and the electrode terminal of the signal line formed by one part of the signal line, forming four kinds of signal lines Projection of a photosensitive organic insulating layer pattern having a thicker film thickness than other fields; and selectively removing the second metal layer and the second amorphous germanium layer and the first amorphous layer by using the photosensitive organic insulating layer pattern as a mask矽 layer, and form a sweep-79- 1300868: (80) The electrode terminal and the source/drain wiring of the trace and the signal line; reduce the film thickness of the photosensitive organic insulating layer pattern, and expose the sweep Drain electrode terminals of the wiring lines and signal lines of engineering. A method for manufacturing a liquid crystal display device, comprising: at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type electro-crystal body, and also serves as a source a signal line of the pole wiring, a unit pixel of a pixel electrode connected to the drain wiring, and the like, and a first transparent insulating substrate arranged in a two-dimensional matrix, and the opposite of the first transparent insulating substrate a liquid crystal display device in which a liquid crystal is filled between a second transparent insulating substrate or a color filter of a substrate; and a transparent conductive layer is formed on at least one main surface of the first transparent insulating substrate The scanning line and the pseudo-pixel electrode formed by the lamination of the metal layer; sequentially covering the plasma protective layer and the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; The electrode terminal of the scanning line is formed on the surface of the electrode and the pseudo-pixel electrode to form a photosensitive tree # grease pattern having an opening portion and protecting the insulating layer from being thicker than other fields; and removing the opening portion Protecting the insulating layer from the first amorphous germanium layer and the gate insulating layer and the plasma protective layer and the metal layer to expose the same pixel electrode as the electrode terminal of the transparent conductive scan line - engineering; reducing the aforementioned photosensitive The thickness of the resin pattern is exposed to expose the protective insulating layer. On the gate electrode, the residual gate electrode is wider and the insulating layer is exposed to expose the first amorphous layer; the photosensitive resin pattern is removed. Thereafter, a process of covering the second amorphous germanium layer containing impurities; after covering one or more layers of the anodizable metal layer, respectively, corresponding to the partial overlap of the above-mentioned protective <S)-80-1300868 (81) insulating layer a source wiring (signal line), a drain wiring including the same pixel electrode, and an electrode terminal of a scanning line including an electrode terminal forming a transparent conductive scanning line, and a part of the signal line The electrode terminal of the signal line forms a photosensitive resin pattern having a thicker thickness of the electrode terminal of the scanning line and the signal line than in other fields; the photosensitive resin pattern is formed For the mask, selectively removing the anodizable metal layer and the second amorphous germanium layer and the first amorphous germanium layer to form an electrode terminal and a source/drain wiring of the scan line and the signal line; The film thickness of the photosensitive resin pattern is such that the source/drain wiring is exposed, and the electrode terminal is protected, and the source and drain wiring are anodized. A method for manufacturing a liquid crystal display device, comprising: at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type transistor, and also serves as a source wiring a signal line, and a pixel element connected to the drain electrode of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a predetermined distance from the drawing electrode, and the unit pixel is arranged in a two-dimensional matrix. A method for manufacturing a liquid crystal display device in which a transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with liquid crystal; and the method is characterized in that: Forming a scanning line and a counter electrode composed of a first metal layer of one or more layers on at least one main surface of the first transparent insulating substrate; sequentially covering one or more layers of the gate insulating layer and containing no impurities The first amorphous germanium layer and the protective insulating layer are processed; on the gate electrode, a protective insulating layer having a wider width than the gate electrode is left to expose the first amorphous germanium layer-81 - 1300868 (82) Complete coverage After the second amorphous germanium layer is formed, an opening is formed in the electrode terminal formation region of the scanning line, and the second amorphous germanium layer, the first amorphous germanium layer, and the gate insulating layer in the opening are removed to be exposed. Part of the scanning line; after covering the second metal layer of one or more layers, 'corresponding to the source wiring (signal line) and the drain wiring (pixel electrode) partially overlapping the protective insulating layer, respectively, and including The electrode terminal of the scanning line of the opening portion and the electrode terminal of the signal line formed by one of the signal lines respectively form a project of a photosensitive organic insulating layer pattern having a thicker thickness on the signal line than other fields; The photosensitive organic insulating layer pattern is used as a mask to selectively remove the second metal layer and the second amorphous germanium layer and the first amorphous germanium layer, thereby forming electrode terminals and source electrodes of the scanning lines and the signal lines. The work of the pole wiring; the process of reducing the film thickness of the photosensitive organic insulating layer pattern to expose the electrode terminal and the drain wiring of the scanning line and the signal line. 1 a method of manufacturing a liquid crystal display device, comprising: a scanning line having at least an insulating gate type transistor and a gate electrode of the insulating gate type transistor, and also serving as a source wiring; The signal line, and the pixel element connected to the drain electrode of the insulating gate type transistor, and the pixel of the counter electrode formed by a predetermined distance from the drawing electrode are arranged in a two-dimensional matrix. a method for manufacturing a liquid crystal display device in which a transparent insulating substrate and a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate are filled with a liquid crystal; and the method is characterized in that at least On one main surface of the first transparent insulating substrate, a scanning line composed of one or more first metal layers and a counter electrode 82-1300868 (83) are formed; and one or more gates are sequentially covered. The insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; on the gate electrode, the residual insulating layer is thinner than the gate electrode to expose the first amorphous germanium layer. Full coverage package After the second amorphous germanium layer of the impurity, an opening is formed in the electrode terminal formation region on the scanning line, and the second amorphous germanium layer and the first amorphous germanium layer and the gate insulating layer ' in the opening portion are removed. Excluding a portion of the scan line; after covering more than one layer of the anodizable metal layer, respectively corresponding to the source wiring Lu (signal line) and drain wiring (pixels) partially overlapping the protective insulating layer An electrode), and an electrode terminal of the scanning line including the opening portion and an electrode terminal formed by a signal line formed by one of the signal lines, respectively forming a film thickness on the electrode terminal of the scanning line and the signal line, compared with other fields a project of a thicker photosensitive resin pattern; the photosensitive resin pattern is used as a mask, and the anodizable metal layer and the second amorphous germanium layer and the first amorphous germanium layer are selectively removed to form a scan line and Engineering of the electrode terminal and the source/drain wiring of the signal line; reducing the film thickness of the photosensitive resin pattern to expose the source/drain wiring; and simultaneously anodizing the electrode terminal before protection · Drain pole wiring of the project. A method for manufacturing a liquid crystal display device is characterized in that it has at least an insulating gate type transistor on a main surface, and a scanning line which also serves as a gate electrode of the insulating gate type electric crystal body, and also serves as a source a signal line of the pole wiring, and a pixel element connected to the drain of the insulating gate type transistor, and a unit pixel of a counter electrode formed by a predetermined distance from the front drawing electrode, and are arranged a first transparent insulating substrate having a two-dimensional matrix shape, and a second transparent insulating substrate facing the first transparent insulating substrate or a color filter <S) -83 - 1300868 (84) ' between the light sheets A method of manufacturing a liquid crystal display device comprising a liquid crystal display device; characterized in that: at least one of the first metal layers of the first transparent insulating substrate is formed with a scanning line composed of one or more first metal layers Engineering of the electrode; sequentially covering one or more layers of the gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; forming an opening portion in the field of electrode terminal formation of the scanning line 'And on the gate electrode The film thickness of the protective insulating layer is formed, and the photosensitive resin pattern is thicker than other fields; the protective insulating layer in the opening portion and the first amorphous germanium layer and the gate insulating layer are removed, and a scanning line is exposed. Engineering for reducing the film thickness of the photosensitive resin pattern to expose the protective insulating layer; leaving a protective insulating layer thinner than the gate electrode on the gate electrode to expose the first amorphous layer Engineering; after removing the photosensitive resin pattern, 'overall covering the second amorphous germanium layer containing impurities; after covering the second metal layer of one or more layers, respectively corresponding to the source wiring partially overlapping the protective insulating layer (signal line), drain wiring (pixel electrode)', electrode terminal of the scanning line including the second amorphous germanium layer in the opening, and electrode terminal of the signal line composed of a part of the signal line Forming a photosensitive organic insulating layer pattern having a thicker film thickness on the signal line than other fields; and selectively using the photosensitive organic insulating layer pattern as a mask The second metal layer and the second amorphous sand layer and the first amorphous germanium layer form an electrode terminal and a source/drain wiring of the scanning line and the signal line; and the light-sensitive organic insulating layer pattern is reduced. The thickness of the film exposes the electrical and terminal wiring of the scan line and the signal line. 16. A method of fabricating a liquid crystal display device comprising -84-1300868 (85) having a minimum of an insulating gate type transistor and a gate electrode of the insulating gate type transistor a line, a signal line which also serves as a source wiring, and a pixel element connected to the drain electrode of the insulating gate type transistor, and a counter pixel such as a counter electrode which is spaced apart from the drawing electrode by a specific distance A liquid crystal display device in which a first transparent insulating substrate is arranged in a two-dimensional matrix and a liquid crystal display device is formed by filling a liquid crystal between a second transparent insulating substrate or a color filter that faces the first transparent insulating substrate. And a method of forming a scanning line and a counter electrode composed of a first metal layer of one or more layers on at least one main surface of the first transparent insulating substrate; and sequentially covering one or more layers The gate insulating layer and the first amorphous germanium layer and the protective insulating layer containing no impurities; in the field of electrode terminal formation of the scanning line, a film having an opening portion and a protective insulating layer formed on the gate electrode is formed Than its Engineering of a thicker photosensitive resin pattern in the field; removing the protective insulating layer in the opening portion and the first amorphous chopped layer and the gate insulating layer to expose a portion of the scanning line; and reducing the film of the photosensitive resin pattern Thick, exposed to protect the insulating layer; on the gate electrode 'remaining thinner than the gate electrode to protect the insulating layer to expose the first amorphous layer; after removing the photosensitive resin pattern' comprehensive a process of covering the second amorphous germanium layer containing impurities; after covering one or more layers of the anodizable metal layer, respectively corresponding to the source wiring (signal line) and the drain wiring partially overlapping the protective insulating layer ( a pixel electrode 'and an electrode terminal ' including a scanning line of a second amorphous germanium layer in the opening portion and an electrode terminal of a signal line formed by a part of the signal line to form electrodes of the scanning line and the signal line, respectively The photosensitive film on the terminal is thicker than other fields. 85-1300868 (86) The process of the grease pattern; the selective photosensitive resin pattern is used as a mask to selectively remove the anodized gold. The layer and the second amorphous germanium layer and the first amorphous germanium layer form an electrode terminal and a source/drain wiring of the scanning line and the signal line; and the film thickness of the photosensitive resin pattern is reduced to expose the source • Engineering of bungee wiring; engineering to protect the above electrode terminals while anodizing source and drain wiring. -86-