JP2007193373A - Substrate for use in liquid crystal display and liquid crystal display using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for use in a liquid crystal display of a CF-on-TFT structure in which a color filter is formed on the side of an array substrate in which a switching element is formed, which enables simplification of a manufacturing process typified by a photolithography process and has high reliability. <P>SOLUTION: The substrate for use in the liquid crystal display has external connection terminals which include first terminal electrodes 52a electrically connected to gate bus lines 6 led out from a plurality of pixel regions P arranged on a glass substrate 3 in a matrix form, second terminal electrodes 52b formed of forming material of a pixel electrode and directly on the glass substrate 3, and electrode coupling regions 52c for electrically connecting the first and the second terminal electrodes 52a and 52b, and which electrically connects an external circuit and the gate bus lines 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a substrate for a liquid crystal display device, a manufacturing method thereof, and a liquid crystal display device using the same, and more particularly, to an active matrix liquid crystal display device using a switching element such as a thin film transistor (TFT). The present invention relates to a liquid crystal display device substrate and a manufacturing method thereof. Further, the present invention relates to a substrate for a liquid crystal display device having a CF-on-TFT structure in which a color filter (CF) is formed on the array substrate side on which switching elements are formed, a manufacturing method thereof, and a liquid crystal display device using the same.

  An active matrix type liquid crystal display (LCD) using a TFT as a switching element is disclosed in, for example, Japanese Patent Laid-Open No. 6-202153. The gazette discloses an inverted stagger type TFT-LCD in which a channel protective film is formed as outlined below.

  In the disclosed TFT-LCD, a passivation film made of an inorganic insulating material is formed on almost the entire surface of the substrate on which the TFT is formed. A pixel electrode formed of a transparent electrode material is formed on the passivation film. The pixel electrode is connected to the source electrode of the TFT through a contact hole having an opening in the passivation film.

An external connection terminal (hereinafter abbreviated as a drain terminal) connected to the drain bus line has a lower electrode formed of an n ⁺ -type a-Si layer and a metal layer. On the lower electrode, an upper electrode made of an oxide conductive film made of the same material as that of the pixel electrode is laminated through a contact hole opened in the passivation film to prevent the lower electrode from being oxidized. A connection terminal of a drain bus line driving circuit is connected to the upper electrode so that a predetermined gradation voltage is applied to each drain bus line.

  In addition, an external connection terminal (hereinafter abbreviated as a gate terminal) connected to the gate bus line has a lower electrode formed of a metal layer that forms a common layer with the gate electrode and the gate bus line. An upper electrode made of an oxide conductive film made of the same material as the pixel electrode is stacked on the lower electrode through a contact hole opened in the insulating film and the passivation film that form a common layer with the gate insulating film. Prevents oxidation. A connection terminal of a gate bus line driving circuit is connected to the upper electrode so that a predetermined gate pulse is sequentially applied to each gate bus line.

Next, an outline of a method for manufacturing an inverted stagger type TFT-LCD having the channel protective film formed thereon will be described. A plurality of gate bus lines and gate terminal lower electrodes are formed on a transparent insulating substrate such as a glass substrate. Next, an insulating film is formed on the entire surface. In this insulating film, the upper portion of the gate electrode is particularly called a gate insulating film. Subsequently, an a-Si layer is formed on the insulating film, and then a channel protective film is formed. Next, after forming an n ⁺ -type a-Si layer, a metal layer is formed, and the channel protective film is collectively etched as an etching stopper, and an a-Si layer operating semiconductor layer is formed on the gate insulating film of the TFT portion. At the same time, a source electrode and a drain electrode are formed on both sides of the channel protective film to complete the TFT.

At the same time, a drain terminal lower electrode composed of an n ⁺ type a-Si layer and a metal layer connected to the drain bus line is formed.

Next, a passivation film having a thickness of 400 nm made of an SiN film, an SiO ₂ film, or a composite film thereof, which is an inorganic insulating material, is formed on the entire surface. Next, after applying a resist, a resist pattern having openings on the source electrode, the drain terminal lower electrode, and the gate terminal lower electrode is formed by photolithography. Then, using this resist pattern as a mask, the passivation film or the passivation film and the insulating film are etched to open contact holes, respectively.

  Next, a transparent conductive film made of ITO or the like having a thickness of 100 nm is formed on the entire surface by sputtering or the like. Next, the transparent conductive film is patterned into a predetermined shape to form a pixel electrode connected to the source electrode through the contact hole. At the same time, a drain terminal upper electrode connected to the drain terminal lower electrode through another contact hole is formed, and a gate terminal upper electrode connected to the gate terminal lower electrode through another contact hole is formed.

  As described above, according to the above publication, when the gate terminal and the drain terminal are formed, the gate terminal lower electrode and the drain terminal lower electrode are formed, and the passivation film that covers the gate terminal lower electrode and the drain terminal lower electrode is formed. And forming a contact hole by etching the passivation film and comprising a transparent conductive film connected to the gate terminal upper electrode and the drain terminal lower electrode connected to the gate terminal lower electrode through the contact hole. The drain terminal upper electrode is formed simultaneously with the pixel electrode.

  Japanese Patent Laid-Open No. 2000-231123 discloses, on a pixel-by-pixel basis, a light-shielding film (black matrix; BM) that shields an inter-pixel region and a storage capacitor bus line crossing the pixel when viewed in the normal direction of the substrate surface. It is disclosed that the edge portions of the formed color filter are overlapped.

  Further, Japanese Patent Laid-Open No. 54-092022 discloses that a light shielding film is provided on an array substrate or a counter substrate in order to suppress the occurrence of leakage current due to photoconductivity of TFT.

  Furthermore, regarding a CF-on-TFT structure in which a color filter is formed on the array substrate side, for example, Japanese Patent Application Laid-Open No. 56-140324 discloses that spectral characteristics between adjacent pixels are different and color filters are overlapped between pixels. It is disclosed that columnar spacers are formed.

  In addition, in the CF-on-TFT structure, the color resin is overlapped to give a light shielding function, the wiring is used as a light shielding film to increase the aperture ratio, the structure in which the color resin is superimposed on the edge of the light shielding film, etc. This is a known technique.

  Japanese Patent Laid-Open No. 01-068726 discloses that pixels are formed on a flattened transparent insulating film that is thin on the TFT and thick in other regions.

  In addition, the frame area in the periphery of the display area composed of a plurality of pixels arranged in a matrix needs to function as a light shielding area that shields leakage light from the backlight. For this reason, in the case of an LCD in which CF is formed on the counter substrate side, a resin CF layer is laminated in the frame region, or a low reflection Cr (chromium) film is formed so as to have a light shielding function. Yes. In an LCD having a CF-on-TFT structure, a resin CF is laminated in the frame region so as to have a light shielding function.

  By the way, the case where an overcoat (OC) layer made of an insulating organic resin material is used instead of the passivation film of the inorganic insulating film disclosed in the above-mentioned JP-A-6-202153 will be examined. The thickness of an inorganic insulating film such as a silicon nitride film (SiN) is generally as thin as 300 to 400 nm, whereas the OC layer is characterized in that the film thickness is extremely thick as 1000 to 3000 nm. In addition, since the OC layer has a relatively small dielectric constant of about 3 or less, the OC layer has the advantage of being able to reduce parasitic capacitance that degrades TFT characteristics in combination with the thick film thickness. is doing.

On the other hand, the OC layer is inferior in adhesion to the electrode material formed in the upper layer compared to the passivation film made of an inorganic insulating material, and a large step is formed due to the thick film thickness. Therefore, problems of poor etching due to disconnection of the electrode material formed in the upper layer and problems of etching failure such as generation of electrode material residue or electrode width narrowing are likely to occur.
Furthermore, even when a contact hole is opened in the OC layer to make an electrical connection with the lower layer electrode, the shape of the contact hole formed in the thick resin layer of the OC layer and the positional relationship between the hole position and the upper and lower electrodes should be fully considered. Need arises.

  Further, in the inspection process of the wiring pattern formed on the substrate for the liquid crystal display device, since the resin CF layer is thick, the measurement is provided with an epi-illumination optical system so that the wiring pattern under the resin CF layer is focused. There is also a problem that it is difficult.

  When a BM film is used to shield the frame region, a low reflection Cr film or a black resin film is usually used as the BM film. However, these formation processes are a factor in increasing the cost of manufacturing the panel. When the resin CF layer is overlapped to form a light shielding layer, there is a three-layer structure of R, G, B in order to enhance the light shielding ability, or a CF resin layer two-layer structure in which the light shielding ability of the liquid crystal layer is used in combination. There may be a problem of leakage light.

  In addition, in the CF-on-TFT structure, for example, when a resin in which a pigment is dispersed as a color component is used for the CF layer, it is necessary to note that the inorganic component of the pigment may contaminate the liquid crystal layer and the semiconductor layer. is there. According to the CF-on-TFT structure, only the common electrode and the alignment film are basically formed on the counter substrate side, and the substrate can be simplified. However, the light shielding function on the counter electrode side is omitted. An important issue is how to optimally provide the light shielding function on the array substrate.

  Regarding the light blocking function in the CF-on-TFT structure, there is a problem of malfunction due to the photoconductivity of the TFT due to the incidence of outside light such as room light or sunlight, and leakage light from the backlight in the transmissive display device. Glittering of the peripheral frame and lowering of pixel contrast are problematic. As a result of experiments, it has been clarified that a light-shielding film in which at least two colors of resin CF layers are laminated is necessary for the frame portion around the display area because the light of the backlight is strong. However, when two resin CF layers are stacked on the frame portion and one CF layer is formed on each pixel in the display region, the height of the display region and the frame portion differs, and the cell gap thickness varies. The problem of end up occurs. Even if an OC layer is formed on the entire surface for flattening, a sufficient flattening effect cannot be obtained because the height of the resin CF layer 42 on which the frame portion is laminated is relatively large.

  An object of the present invention is to provide a substrate for a liquid crystal display device that can simplify a manufacturing process represented by a photolithography process and has high reliability, a manufacturing method thereof, and a liquid crystal display device using the same.

  An object of the present invention is to provide an insulative substrate that sandwiches a liquid crystal together with an opposing substrate disposed opposite to each other, pixel electrodes formed in a plurality of pixel regions arranged in a matrix on the insulative substrate, the pixel electrodes, and a bus line A switching element connected to each other, a first terminal electrode electrically connected to the bus line, a second terminal electrode formed on the insulating substrate with a material for forming the pixel electrode, An electrode connection region for electrically connecting the first and second terminal electrodes, and an external connection terminal for electrically connecting an external circuit and the bus line. Achieved by the substrate.

  When a resin layer is formed on the entire surface of the substrate and an electrode wiring made of, for example, a transparent oxide electrode material is formed on the resin layer, the adhesion with the resin layer such as the wiring is often inferior to that on the glass substrate. Separation may occur. For this reason, peeling of wiring etc. can be suppressed by opening a resin layer and making a wiring etc. contact a glass substrate directly, and patterning. Moreover, when the opening part of a resin layer has a linear shape, a level | step difference is intense and etching residues, such as a transparent oxide electrode material, may arise between electrode wiring. On the other hand, by forming the opening pattern of the resin layer between the electrode terminals into a shape with a sharp tip, it is possible to relax the step shape of the selection portion and suppress the generation of etching residues.

  In the CF-on-TFT structure in which the counter electrode does not have a light-shielding film, intense light leakage from the backlight unit becomes a problem in the frame region around the display region. Therefore, the frame area needs to be shielded from light by overlapping two or more color resins. However, in the configuration including the overcoat (OC) layer, the frame region has a film thickness in which the CF layer and the OC layer are stacked in two layers, and the film thickness in which the CF layer 1 layer and the OC layer are stacked in the display region. Becomes higher and the step becomes larger. As a result, the cell thickness of the liquid crystal fluctuates, causing display unevenness called frame unevenness. In order to cope with this, an opening region is provided so that three layers of CF resin are stacked in the frame region, and an OC layer is not formed in the region. Then, by exposing the frame region to the etching of the gate insulating film or the like, the uppermost CF layer of the CF resin overlapped portion is removed by etching, and the film thickness of the entire frame region is set to two resin CF layers + α. It is possible to prevent a significant step from being generated between the regions.

  Further, after setting the film thickness of the entire frame region to two resin CF layers + α, the exposed region of the color filter layer is covered with a transparent electrode pattern in the same process as the formation of the pixel electrode, if necessary. Further, since the liquid crystal layer on the frame region can be in a no-voltage application state by making the transparent electrode the same potential as the counter electrode (common electrode), normally black such as MVA (Multi-domain Vertical Alignment) -LCD In the (NB) type display method, sufficient light shielding is possible.

  In the NB type display system such as MVA-LCD, the liquid crystal layer substantially has a light shielding function against external light when the TFT is off. Therefore, the green resin CF layer having the highest transmittance among the resin CF layers is one. Even if the layer exists in the light-shielding region, the light-shielding function is sufficient, so that TFT malfunction due to photoconductivity does not occur.

  In recent years, the formation of a bank, which is an alignment regulating structure on the counter substrate side, has been omitted, and a voltage is applied between the common electrode and the pixel electrode after injecting a liquid crystal compounded with a monomer between the counter substrate and the array substrate. On the other hand, MVA-LCDs have been introduced that irradiate the liquid crystal with UV light to polymerize the monomer and give the liquid crystal molecules a pretilt angle. In the case of MVA-LCD using the pretilt angle imparting technology using this polymer, a transparent electrode pattern can be formed in the same process as the pixel electrode formation in the exposed region of the color filter layer on the surface of the light shielding region in the frame region. desirable. Furthermore, by setting the transparent electrode to the same potential as the counter electrode or the common electrode, the liquid crystal layer on the light-shielding region in the frame region can be in a voltage-free state so that no pretilt angle is given to the liquid crystal molecules in the region. Therefore, a sufficient light shielding ability can be obtained in the NB display method.

  The inverted stagger type TFT has two typical structures of an NSI (channel etch) type and an ISI (channel protective film) type. In either structure, the a due to the pigment component contained in the resin CF layer Contamination of the active semiconductor layer such as -Si becomes a problem. Regarding the problem of contamination in the case where the resin CF layer is directly formed on the TFT, it has been found that the degree of contamination varies depending on the volume resistivity of the resin CF layer forming material.

  A material having a small volume resistivity accumulates electric charge and causes seizure. Therefore, a CF material having as large a volume resistivity as possible is preferable. Furthermore, it is preferable to provide an inorganic insulating film such as SiN as an interlayer insulating film on the TFT. In this case, the film thickness may be extremely small compared to the film thickness of 300 to 400 nm, such as a gate insulating film or a protective film used in a conventional LCD, for example, about 10 to 150 nm, and preferably 50 to 120 nm. The degree is good.

  In the CF-on-TFT structure, there is an OC layer in which a step of several thousand nm is formed instead of the step of about several tens to several hundreds of nanometers in the conventional structure. Or defective pattern identification due to the presence of the CF resin.

  To solve these problems, for example, by providing an opening pattern in the storage capacitor electrode and further providing a similar opening pattern in the upper CF layer, absorption of incident light by the CF layer that hinders autofocusing is eliminated. In addition, it is possible to measure the superposition of the opening pattern of the storage capacitor electrode and the opening pattern opened in the pixel electrode.

  Regarding the shape of the contact hole that electrically connects the TFT source electrode and the pixel electrode, the relationship of the contact hole diameter of the CF layer, SiN layer, and OC layer existing on the source electrode is expressed as CF layer> SiN layer> OC layer. By doing so, a structure in which the CF resin is covered from above and below by the OC layer becomes possible, and the influence of contamination on the liquid crystal or TFT by the pigment in the resin CF layer can be eliminated.

  When the volume resistivity of the CF resin is large and there is no problem such as contamination, the contact hole diameter is preferably OC layer> CF layer> SiN layer for the purpose of preventing disconnection of the pixel electrode.

  The OC layer and the CF layer are made of an organic resin, and their thermal expansion coefficient is an order of magnitude smaller than that of glass. Further, since the thermal expansion coefficient differs by an order of magnitude with respect to the transparent oxide conductive film used for the pixel electrode, the pixel electrode may be cracked due to thermal stress.

  Since cracks resulting from different thermal expansion coefficients are likely to occur in contact holes that are stepped portions, a contact hole structure that can relieve stress is required.

  In order to reduce cracks in the contact hole, it is necessary to ensure a sufficient distance between the pixel electrode edge and the contact hole, and preferably 6 μm or more. This distance has a correlation with the film thickness of the resin film.

  The positional relationship between the resin film and the contact hole is important. The relationship between the film thickness of the OC layer and the distance between the pixel end portions should be 2.5 times or more. Generation of cracks can be suppressed by setting the angle to 5 times or more or to an angle of 45 ° or less.

  According to the present invention, a new resin is not used for the CF layer and the OC layer, the wiring layer and the pixel region end are not overlapped, and there is no special light shielding pattern. In addition, a high-performance liquid crystal display device having excellent display characteristics and high reliability can be realized.

  According to the present invention, since the resin CF layer is provided on the array substrate side and the light shielding function is provided, not only the manufacturing process of the liquid crystal display device can be simplified as a whole, but also the bonding accuracy with the counter substrate can be improved. High-definition panels with a high aperture ratio can be mass-produced even if slightly lower.

In addition, according to the present invention, the frame area can have a sufficient light shielding function without causing a significant step between the frame area and the display area. In addition, since the resin CF constituting the light shielding layer can be prevented from coming into direct contact with the liquid crystal layer, contamination of the liquid crystal can be prevented.
Further, according to the present invention, the liquid crystal layer on the frame region can be efficiently used as a light shielding layer.

  A substrate for a liquid crystal display device according to a first embodiment of the present invention, a manufacturing method thereof, and a liquid crystal display device using the same will be described with reference to FIGS. 1 to 45 and FIG. First, a schematic configuration of the liquid crystal display device according to the present embodiment will be described with reference to FIG. The liquid crystal display device according to the present embodiment has a structure in which a TFT substrate (array substrate) 1 on which TFTs 2 and the like are formed and a counter substrate 4 on which common electrodes and the like are opposed are bonded to each other, and liquid crystal is sealed between them. Have. The TFT substrate 1 has a CF-on-TFT structure in which, for example, a pigment-dispersed resin CF layer is formed on the TFT 2 formation surface side, and an OC layer made of an insulating organic resin material is formed thereon.

  FIG. 2 shows an equivalent circuit of the element formed on the TFT substrate 1. On the TFT substrate 1, a plurality of gate bus lines 6 extending in the horizontal direction in the drawing are formed in parallel to each other, and a plurality of drain bus lines 8 extending in the vertical direction in the drawing so as to intersect them substantially perpendicularly are formed. ing. Each region surrounded by the plurality of gate bus lines 6 and drain bus lines 8 is a pixel region. A TFT 2 and a pixel electrode 10 are formed in each pixel region. The drain electrode of each TFT 2 is connected to the adjacent drain bus line 8, the gate electrode is connected to the adjacent gate bus line 6, and the source electrode is connected to the pixel electrode 10. A storage capacitor bus line 12 is formed substantially in the center of each pixel region in parallel with the gate bus line 6. These TFT 2, pixel electrode 10, and each bus line 6, 8, 12 are formed by a photolithography process, and are formed by repeating a series of semiconductor processes of “film formation → resist application → exposure → development → etching → resist stripping”. Is done.

  Returning to FIG. 1, the TFT substrate 1 sealed with the liquid crystal and disposed opposite to the counter substrate 4 includes a gate bus line driving circuit 14 on which a driver IC for driving the plurality of gate bus lines 6 is mounted, and a plurality of A drain bus line driving circuit 16 on which a driver IC for driving the drain bus line 8 is mounted is provided. These drive circuits 14 and 16 are configured to output a scanning signal and a data signal to a predetermined gate bus line 6 or drain bus line 8 based on a predetermined signal output from the control circuit 18. A polarizing plate 20 is disposed on the surface of the TFT substrate 1 opposite to the element formation surface, and a backlight unit 22 is attached to the surface of the polarizing plate 20 opposite to the TFT substrate 1. A polarizing plate 24 disposed in crossed Nicols with the polarizing plate 20 is attached to the surface of the counter substrate 4 opposite to the common electrode formation surface.

  Next, the configuration of the TFT substrate 1 as the substrate for the liquid crystal display device according to the present embodiment will be described with reference to FIGS. 3 to 11 and FIG. FIG. 3 shows a state in which one pixel on the glass substrate 3 is viewed from the liquid crystal layer side. FIG. 4 shows a cross section taken along line AA of FIG. FIG. 5 shows a configuration in the vicinity of the frame region when the TFT substrate 1 is viewed from the liquid crystal layer side. FIG. 6 shows a structure near the gate terminal on the glass substrate 3. 7 and 8 show cross sections cut along lines CC and DD in FIG. FIG. 9 shows a structure near the drain terminal on the glass substrate 3. 10 and 11 show cross sections cut along lines EE and FF in FIG. FIG. 50 illustrates a cross-sectional configuration in the vicinity of the frame region 56 illustrated in FIG. 5, and illustrates a cross section along the extending direction of either the gate bus line 6 or the drain bus line 8.

First, as shown in FIGS. 3 and 4, a plurality of gate bus lines 6 (only one is shown in FIG. 3) are formed on the glass substrate 3 as a transparent insulating substrate. Has been. On the glass substrate 3, a plurality of drain bus lines extending in the vertical direction in FIG. 3 intersecting with the gate bus line 6 and an insulating film 32 (hereinafter referred to as “gate insulating film” immediately above the gate bus line 6). 8 (only two are shown in FIG. 3) are formed. A region defined by the gate bus line 6 and the drain bus line 8 is a pixel region. A TFT 2 is formed in the vicinity of the intersection of each gate bus line 6 and drain bus line 8. As shown in FIGS. 3 and 4, the drain electrode 26 of the TFT 2 composed of the upper metal layer 62 and the ohmic contact layer 36 is drawn out from the drain bus line 8 on the left side in FIG. 3, and its end is the gate bus line 6. It is formed so as to be positioned on one end side on the channel protective film 28 formed thereon. The source electrode 30 composed of the upper metal layer 62 and the ohmic contact layer 36 is formed on the other end side on the channel protective film 28 so as to face the drain electrode 26. In such a configuration, the gate bus line 6 region immediately below the channel protective film 28 functions as the gate electrode of the TFT 2. As shown in FIG. 4, a gate insulating film 32 is formed on the gate bus line 6, and a channel is formed between the gate insulating film 32 and the upper channel protective film 28, for example, amorphous silicon (a-Si) An operating semiconductor layer 34 is formed. The operating semiconductor layer 34 is connected to the ohmic contact layer 36 of, for example, an n ⁺ -type a-Si layer of the drain / source electrodes 26 and 30.

  Further, as shown in FIG. 3, a storage capacitor bus line 12 extending left and right substantially in the center of the pixel region is formed. A storage capacitor electrode 38 is formed above the storage capacitor bus line 12 in the pixel region via an insulating film 32.

  Predetermined resin CF layers 42R (red), 42G (green), and 42B (blue) are formed for each pixel over the entire pixel region including the upper layer of TFT 2 and the upper layer of the storage capacitor electrode 38 (not shown) shown in FIG.

  An OC layer 44 is formed on the resin CF layers 42R, 42G, and 42B in the pixel region. A pixel electrode 10 is formed on the OC layer 44 of each pixel by patterning a transparent oxide electrode material. The pixel electrode 10 is electrically connected to the source electrode 30 through a contact hole 46 formed by opening one of the OC layer 44 and the resin CF layers 42R, 42G, and 42B. Similarly, the pixel electrode 10 is electrically connected to the storage capacitor electrode 38 through a contact hole 48 formed by opening any one of the OC layer 44 and the resin CF layers 42R, 42G, and 42B.

  Next, the structure near the frame region of the TFT substrate 1 will be described with reference to FIGS. In FIG. 5, the ratio of dimensions of the display area 50, the frame area 56, the gate terminal / drain terminal formation areas 51, 53, etc. is different from the actual one in order to clearly display each component. As shown in FIG. 5, the TFT substrate 1 has a plurality of pixel regions P arranged in a matrix, and a TFT 2 is formed in each pixel region P. A plurality of pixel areas P constitute an image display area 50. Each gate bus line 6 is connected to a plurality of gate terminals 52 formed in the gate terminal formation region 51 on the outer periphery of the TFT substrate 1, and the gate bus line driving circuit 14 provided outside (see FIG. 1). To be connected to.

  Similarly, each drain bus line 8 is connected to a plurality of drain terminals 54 formed in the drain terminal formation region 53 on the outer periphery of the TFT substrate 1, and the drain bus line driving circuit 16 ( (See FIG. 1).

In FIG. 5, reference numeral 4 ′ indicates the edge position of the counter substrate 4 when the TFT substrate 1 and the counter substrate 4 are bonded together. The edge 4 ′ is positioned inward from the edge of the TFT substrate 1 by an amount corresponding to the gate terminal / drain terminal formation region.
At least one resin CF layer 42 is formed at the periphery of each pixel region P in the display region 50 so as to function as a light shielding layer (BM). The BM layer is used to define a plurality of pixel regions P in the display region 50 to increase the contrast, and to shield the TFT 2 and prevent the occurrence of light leakage current.

As shown in FIG. 50, in the frame area 56 around the display area 50, in order to block unnecessary light around the display area 50 from the backlight unit 22 (see FIG. 1), the resin CF layer 42R, A BM layer formed by stacking at least any two of 42G and 42B is provided. In the example shown in FIG. 50, resin CF layers 42R and 42G are laminated in this order, and a thin layer of resin CF layer 42B is further laminated.
A main seal (sealant) 58 made of a photocurable resin is formed around the frame region of the TFT substrate 1 in order to bond the TFT substrate 1 to the counter substrate 4.

  The OC layer 44 is not formed in the frame area 56 but is formed in the display area 50 shown in FIG. 5 and the area indicated by the double arrow 44 in the main seal 58 and the gate terminal / drain terminal formation areas 51 and 53. Has been.

In the region of the frame region 56 where the OC layer 44 is not formed, a protective film 70 is formed of a transparent conductive film material such as ITO used for the pixel electrode 10 in order to prevent liquid crystal contamination by the resin CF layer 42. ing.
The conductive protective film 70 is connected to a common electrode of the counter substrate 4 (not shown) when the two substrates are bonded together. The common electrode is electrically separated from the storage capacitor bus line 12 when the two substrates are bonded together, or at least connected in a high resistance state.
The common electrode of the counter substrate 4 and the storage capacitor bus line 12 of the TFT substrate 1 are kept at the same potential via the transfer by mounting the gate bus line driving circuit 14 and the drain bus line driving circuit 16. It has become.

  Next, the configuration of the gate terminal 52 will be described with reference to FIGS. FIG. 6 is an enlarged view of two of the plurality of gate terminals 52 shown in FIG. 5 and 6, the gate terminal 52 has a first terminal electrode 52a and a second terminal electrode 52b. In addition, an electrode connection region 52c that electrically connects both the electrodes 52a and 52b is provided. The first terminal electrode 52 a is formed of the material for forming the gate bus line 6 simultaneously with the formation of the gate bus line 6. On the other hand, the second terminal electrode 52 b is formed of the material for forming the pixel electrode 10 simultaneously with the formation of the pixel electrode 10 formed on the OC layer 44.

As shown in FIG. 8 representing a cross section taken along the line D-D of FIGS. 6 and 6, the OC layer 44 is opened in the electrode switching region 52c, and the lower gate insulating film 32 is also opened. The surface of the first terminal electrode 52a is exposed.
Further, the OC layer 44 between the adjacent gate terminals 52 has an end face that substantially coincides with the end face of the first terminal electrode 52a on the electrode connection region 52c side. Furthermore, the OC layer 44 has a protrusion 60 that protrudes from a substantially middle portion of the end face and has a cross-sectional shape that is parallel to the substrate surface of the glass substrate 3, for example, a triangular shape having an acute apex angle.

As shown in FIG. 8, in the electrode switching region 52c, a second terminal electrode 52b is formed immediately above the first terminal electrode 52a, and both electrodes 52a and 52b are electrically connected.
With such a configuration, since the OC layer 44 does not exist on the formation region of the second terminal electrode 52b in the gate terminal formation region 51, as shown in FIG. 7 showing a cross section taken along the line CC in FIG. The second terminal electrode 52b is directly formed on the glass substrate 3 in a direction from the electrode connection region 52c toward the edge of the glass substrate 3.

  Although the gate terminal formation region 51 has been described above, the drain terminal formation region 53 has a substantially similar structure. Next, the configuration of the drain terminal 54 will be described with reference to FIGS. FIG. 9 is an enlarged view of two of the plurality of drain terminals 54 shown in FIG. 5 and 9, the drain terminal 54 has a first terminal electrode 54a and a second terminal electrode 54b. In addition, an electrode connection region 54c that electrically connects both electrodes 54a and 54b is provided. The first terminal electrode 54 a is formed of the material for forming the drain bus line 8 simultaneously with the formation of the drain bus line 8. On the other hand, the second terminal electrode 54 b is formed of the material for forming the pixel electrode 10 simultaneously with the formation of the pixel electrode 10 formed on the OC layer 44.

As shown in FIG. 11 representing a cross section taken along line FF in FIGS. 9 and 9, the OC layer 44 in the electrode connection region 54c is opened, and the surface of the first terminal electrode 54a is exposed. .
Further, the OC layer 44 between the adjacent drain terminals 54 has an end face that substantially coincides with the end face of the first terminal electrode 54a on the electrode connection region 54c side. Furthermore, the OC layer 44 has a protrusion 60 that protrudes from a substantially middle portion of the end face and has a cross-sectional shape that is parallel to the substrate surface of the glass substrate 3, for example, a triangular shape having an acute apex angle.

As shown in FIG. 11, in the electrode connection region 54c, a second terminal electrode 54b is formed immediately above the first terminal electrode 54a, and the electrodes 54a and 54b are electrically connected.
With such a configuration, since the OC layer 44 does not exist on the formation region of the second terminal electrode 54b in the drain terminal formation region 53, as shown in FIG. 10 showing a cross section taken along line EE of FIG. The second terminal electrode 54b is directly formed on the glass substrate 3 in a direction from the electrode connection region 54c toward the edge of the glass substrate 3.

  The drain terminal 54 is not limited to the structure of the drain terminal 54 configured as described above. For example, the drain including the wiring layer of the same layer as the gate terminal 52 is formed in the drain terminal forming region 53 simultaneously with the formation of the gate terminal 52 using the gate bus line 6 forming material. A terminal 54 may be formed. In this case, there are two electrode connection regions, for example, a wiring formed of the same layer metal as the drain bus line 8 and extending from the drain bus line 8, and a first electrode connection region at the end of the wiring. The first terminal electrode 54a is constituted by the wiring formed of the material for forming the pixel electrode 10 which is connected and extends beyond the first electrode. Then, the formation material of the pixel electrode 10 extending from the first terminal electrode 54a is laminated on the upper surface of the terminal electrode formed of the formation material of the gate bus line 6 from the second electrode connection region toward the most distal portion. The second terminal electrode 54b is formed.

  Next, a method for manufacturing the liquid crystal display device shown in FIGS. 1 to 11 and 50 will be described with reference to FIGS. 12 to 45, the same components as those shown in FIGS. 1 to 11 and 50 are denoted by the same reference numerals. Here, among FIGS. 12 to 45, FIGS. 12 to 18 are cross-sectional views of manufacturing steps of the TFT formation region cut along the line AA of FIG. FIGS. 19 to 25 are sectional views of manufacturing steps of the storage capacitor formation region cut along the line BB in FIG. 26 to 29 are cross-sectional views of the manufacturing process of the region of the second terminal electrode 52b of the gate terminal 52 cut along the line CC in FIG. 30 to 34 are manufacturing process cross-sectional views of the electrode connection region 52c of the gate terminal 52 cut along the line DD in FIG. FIGS. 35 to 38 are sectional views of manufacturing steps of the second terminal electrode 54b of the drain terminal 54 cut along the line EE in FIG. 39 to 43 are manufacturing process sectional views of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG.

Now, after forming a protective film such as SiO _x directly on the glass substrate 3 as a transparent insulating substrate or as required, for example, an Al (aluminum) alloy film is formed with a film thickness of, for example, 130 nm and MoN (molybdenum nitride) film. A metal layer having a thickness of, for example, 70 nm and Mo (molybdenum) with a thickness of, for example, 15 nm is formed on the entire surface in this order by sputtering to form a metal layer having a thickness of approximately 215 nm. As an Al alloy, a material containing one or more of Nd (neodymium), Si (silicon), Cu (copper), Ti (titanium), W (tungsten), Ta (tantalum), Sc (scandium), etc. in Al. Can be used.

  Next, after forming a resist layer on the entire surface, a resist mask is formed by exposure using a first mask (photomask or reticle, hereinafter referred to as a mask), and gate bus lines are formed by wet etching using a phosphoric acid-based etchant. 6 (see FIG. 12) and the storage capacitor bus line 12 (see FIG. 19), and the first terminal electrode 52a (see FIG. 26) of the gate terminal 52 are formed.

  Next, for example, a silicon nitride film (SiN) is formed on the entire surface of the substrate with a thickness of about 400 nm by a plasma CVD method to form a gate insulating film (an interlayer insulating film depending on the film forming site; hereinafter, a gate insulating film or (Referred to as an insulating film) 32 is formed. Next, for example, an amorphous silicon (a-Si) layer 34 ′ for forming the active semiconductor layer 34 is formed on the entire surface of the substrate with a thickness of about 30 nm by plasma CVD. Further, for example, a silicon nitride film (SiN) 28 'for forming the channel protective film (etching stopper) 28 is formed on the entire surface with a film thickness of about 120 nm by plasma CVD (FIGS. 12, 19, 26, and FIG. 30, see FIGS. 35 and 39).

  Next, a photoresist (not shown) is applied to the entire surface by spin coating or the like, and then back exposure is performed on the transparent glass substrate 3 using the gate bus line 6 and the storage capacitor bus line 12 as a mask. By dissolving the resist layer in the exposed region, a resist pattern (not shown) is formed in a self-aligned manner on the gate bus line 6, the storage capacitor bus line 12, and the first terminal electrode 52 a of the gate terminal 52. The By further exposing the resist pattern from the forward direction using the second mask, a resist pattern in which the resist layer remains only on the formation region of the channel protective film 28 is formed. By using this as an etching mask, the silicon nitride film 28 ′ is dry-etched using a fluorine-based gas to form the channel protective film 28 (FIGS. 13, 20, 27, 31, 36, and 36). (See FIG. 40).

Next, after cleaning the surface of the amorphous silicon layer 34 ′ using dilute hydrofluoric acid (removing the natural oxide film), it is immediately shown in FIGS. 14, 21, 28, 32, 37, and 41. Thus, for example, an n ⁺ -type a-Si layer 36 ′ for forming the ohmic contact layer 36 is formed on the entire surface of the transparent glass substrate 3 to a thickness of about 30 nm by plasma CVD. Next, a metal layer 62 made of, for example, Ti / Al / Ti for forming the drain electrode 26, the source electrode 30, the storage capacitor electrode 38, the drain bus line 8, and the first terminal electrode 54a of the drain terminal 54 is formed by sputtering. Each film is formed to a thickness of 20/75/40 nm. In addition to the composite film such as Ti / Al / Ti, the metal layer 62 is, for example, a simple substance such as Cr (chromium), Mo (molybdenum), Ta (tantalum), Ti (titanium), Al (aluminum) or the like. Composite membranes can be used.

Next, a photoresist layer (not shown) is formed on the entire surface of the substrate, the resist is exposed using a third mask, and then developed to pattern the resist layer. Using the patterned resist layer as an etching mask (not shown), the metal layer 62, the n ⁺ -type a-Si layer 36 ′, and the amorphous silicon layer 34 ′ are subjected to dry etching using a chlorine-based gas, and FIG. 15, FIG. 22, FIG. 29, FIG. 33, FIG. 38, and FIG. 42, the drain bus line 8, the first terminal electrode 54a of the drain terminal 54, the drain electrode 26, the source electrode 30, and the storage capacitor electrode 38. And the ohmic layer 36 and the active semiconductor layer 34 are formed. In this etching process, the channel protective film 28 functions as an etching stopper, so that the underlying amorphous silicon layer 34 ′ remains without being etched, and a desired operation semiconductor layer 34 is formed.

When the above steps are completed, as shown in FIG. 42, the drain terminal 54 includes a first terminal electrode in which an amorphous silicon layer 34 ′, an n ⁺ -type a-Si layer 36 ′, and a metal layer 62 are stacked in this order. 54a is formed. Further, as shown in FIG. 15, an operating semiconductor layer 34 is formed on the gate bus line 6 via a gate insulating film 32, and a channel protective film 28, a drain electrode 26, and a source electrode 30 are formed on the operating semiconductor layer 34. A prototype of the provided TFT structure is formed. The drain electrode 26 and the source electrode 30 are formed as a structure in which an ohmic contact layer 36 and a metal layer 62 are laminated in this order. Further, as shown in FIG. 22, an amorphous silicon layer 34 ′ is formed on the storage capacitor bus line 12 via an insulating film 32, and an n ⁺ -type a-Si layer 36 ′ and a metal layer 62 are formed on the amorphous silicon layer 34 ′ in this order. A stacked storage capacitor electrode 38 is formed.

  Next, resin CF layers 42R, 42G, and 42B are formed for the pixel regions P of R, G, and B, respectively. Each resin CF layer 42R, 42G, 42B is formed in a stripe shape so as to have the same color in the vertical direction, as shown in the pixel region P of FIG.

  First, for example, an acrylic negative photosensitive resin in which a red (R) pigment is dispersed is applied to the entire surface of the glass substrate 3 with a film thickness of, for example, 170 nm using a spin coater, a slit coater, or the like. Next, the pattern is exposed so that the resin remains in stripes in a predetermined plurality of columns of pixel regions P by proximity exposure (proximity exposure) using a large mask. Subsequently, the red resin CF layer 42R is formed by developing using an alkaline developer such as KOH. As a result, red spectral characteristics are imparted to the red pixel region P, and a light blocking function that inhibits external light from entering the TFT 2 can be added (see FIGS. 16 and 23).

  In the same manner as described above, an acrylic negative photosensitive resin in which a blue (B) pigment is dispersed is applied and patterned, and a striped blue resin CF layer is formed in the pixel region P adjacent to the red resin CF layer 42R. 42B is formed. As a result, a blue spectral characteristic is imparted to the blue pixel region P, and a light blocking function for inhibiting external light from entering the TFT 2 is added.

  Further, an acrylic negative photosensitive resin in which a green (B) pigment is dispersed is applied and patterned, and a striped green resin is formed in the pixel region P adjacent to the red resin CF layer 42R and the blue resin CF layer 52B. A CF layer 42G is formed. As a result, a green spectral characteristic is imparted to the green pixel region P, and a light blocking function that inhibits external light from entering the TFT 2 is added.

  The resin CF layers 42R, 42G, and 42B are formed in the display area 50 and the frame area 56 inside the main seal shown in FIGS. In the frame region 56, three layers of resin CF layers 42R, 42G, and 42B are laminated.

  In the above process, any one of the resin CF layers 42R, 42G, and 42B is formed for each pixel region P. For example, it is preferable to adopt a laminated structure as shown in FIG. FIG. 44 shows a state in which the plurality of pixel regions P in which the resin CF layers 42R, 42G, and 42B are formed are viewed in the normal direction of the substrate surface of the glass substrate 3. The resin CF layer 42 illustrated in the (A) row of FIG. 44 has a hook-like (G-shaped) pattern protruding so as to cover the TFT 2 of the right adjacent pixel. Thereby, since the TFT 2 in each pixel region P has a two-layer laminated structure of resin CF layers, the light shielding ability can be further improved.

  In the example of the row (B) of FIG. 44, the green resin CF layer 42G having the highest visible light transmittance has a T-shaped (or cross-shaped) pattern projecting so as to cover the TFT 2 of the adjacent pixels. is doing. As a result, the TFT 2 in the red and blue pixel regions P has a two-layer stacked structure in which the green resin CF layer 42G overlaps, so that the light shielding ability can be further improved.

  The example of the (C) row in FIG. 44 has a pattern in which the green resin CF layer 42G having the highest visible light transmittance projects in the row direction so as to cover the TFT2. As a result, the TFT 2 in the red and blue pixel regions P has a two-layer stacked structure in which the green resin CF layer 42G overlaps, so that the light shielding ability can be further improved.

  With respect to the light shielding function, the problem of external light is not so important for LCDs in NB (normally black) mode, and an electric field is not applied between pixel wirings without overlapping pixels and bus lines, resulting in black display. There is almost no drop in. However, a minimum light shielding is necessary above the TFT 2 to prevent the influence of photoconductivity. As a result of the experiment, when realizing the three colors R, G, and B with the resin CF layer 42, even with the G (green) resin CF layer 42G having the highest visible light transmittance, only one layer is sufficient for photoconductivity. It has been found that there is a light shielding effect against

Accordingly, a green resin CF layer 42G having the highest visible light transmittance forms a ridge-shaped (t-shaped) pattern, a T-shaped pattern, or a cross-shaped pattern that protrudes to adjacent pixels. A light shielding layer having a single-layer structure including only the resin CF layer 42G in which the resin CF layers 42R and 42B are not formed may be used. The light shielding resin CF layer 42G single-layer pattern in this case covers only the necessary region in the vicinity of the gate bus line 6 when viewed in the normal direction of the substrate surface, and does not erode the formation region of the resin CF layers 42R and 42B in the pixel region. It is desirable to form as follows.
In view of the above, the TFT 2 may be selectively shielded by the resin CF layer 42 in order to satisfy the light shielding function.

The order in which the color resins are formed in such a laminated structure of the resin CF layers is arbitrary, and in this example, they are formed in the order of R, G, and B. However, it is necessary to consider the possibility that the resin CF may adversely affect the liquid crystal layer and the TFT 2. From this viewpoint, the resin CF layer that is in direct contact with the TFT 2 includes the resin CF layers 42R, 42G, and 42B. Of these, it is desirable to use a resin CF layer formed of a material having the largest volume resistance. A desirable resistivity is 10 ¹⁶ Ω · cm or more, and preferably 2.0 × 10 ^{16 to} 2.2 × 10 ¹⁶ Ω · cm or more.

  After the resin CF layers 42R, 42G, and 42B are formed, contact holes 46 are opened in the resin CF layers 42R, 42G, and 42B on the upper layer of the source electrode 30 of the TFT 2 (see FIG. 16). Similarly, contact holes 48 are opened in the resin CF layers 42R, 42G, and 42B on the storage capacitor electrode 38 (see FIG. 23).

  Next, as shown in FIGS. 17 and 24, an OC layer 44 is formed. In the same manner as the formation of the resin CF layer, an OC resin is applied to the entire surface of the glass substrate 3 using a spin coater, a slit coater, or the like, and heat-treated at a temperature of 140 ° C. or lower. The OC resin used is an acrylic resin having negative photosensitivity. Next, proximity exposure is performed using a large mask, and development is performed using an alkali developer such as KOH, whereby the OC layer 44 is formed.

  As shown in FIG. 34, the patterned OC layer 44 is opened in the electrode connection region 52c of the gate terminal terminal formation region 51, and the insulating film 32 is exposed at the bottom.

  The OC layer 44 has an end face between adjacent gate terminals 52 so as to substantially coincide with the end face of the first terminal electrode 52a on the electrode connection region 52c side. Further, a protrusion 60 is formed that protrudes from the substantially middle portion of the end face of the OC layer 44 and is patterned into a triangular shape having a cross-sectional shape parallel to the substrate surface of the glass substrate 3, for example, an acute apex angle.

  Similarly, as shown in FIG. 43, the OC layer 44 in the drain terminal formation region 53 is opened in the electrode connection region 54c, and the surface of the first terminal electrode 54a is exposed.

  The OC layer 44 has an end face between adjacent drain terminals 54 so as to substantially coincide with the end face of the first terminal electrode 54a on the electrode connection region 54c side. Further, a protrusion 60 is formed that protrudes from the substantially middle portion of the end face of the OC layer 44 and is patterned into a triangular shape having a cross-sectional shape parallel to the substrate surface of the glass substrate 3, for example, an acute apex angle.

  In the etching process using the OC layer 44 as a mask, the protrusion 60 is caused by a short circuit failure in the residue of the second terminal electrodes 52b and 54b serving as the upper wiring, such as between the gate terminals 52 and the drain terminals 54. It works effectively in such cases. In the etching process using not only the OC layer 44 as a mask but also a positive or negative resist pattern as a mask, the step shape is relaxed toward the tip due to the shape effect of the protrusion 60, so that the residue of the upper wiring The protrusion 60 is effective in suppressing the generation.

  Further, the OC layer 44 on the frame region 56 is peeled and removed by patterning of the OC layer 44, and the OC layer 44 does not exist in the frame region 56 (see FIG. 50). From the results of the experiment, it is clear from the experimental results that the light from the backlight unit 22 is strong for the frame area 56 in the outer peripheral portion of the display area, so that the resin CF layer 42 needs to be shielded with at least two colors. It has become. For this reason, if the resin CF layer 42 having a laminated structure is formed in the frame region 56 and the OC layer 44 is further laminated, the height of the display region 50 and the frame region 56 is different, which affects the liquid crystal cell thickness. The problem that it occurs will occur.

  Therefore, basically, in order for the resin CF layer 42 to have the same height in the display region 50 of one layer and the frame region of two or more layers, the frame of the resin CF layer 42 + the OC layer 44 in the display region 50 is the same. The region 56 may have a two-layer structure of the resin CF layer 42 or a structure slightly higher than that.

  Further, in the patterning of the OC layer 44, the contact hole 46 is also formed in the OC layer 44 in alignment with the contact hole 46 formed in the resin CF layer 42 on the source electrode 30 of the TFT 2 (see FIG. 17). . Similarly, the contact hole 48 is also formed in the OC layer 44 in alignment with the contact hole 48 formed in the resin CF layer 42 above the storage capacitor electrode 38 (see FIG. 24).

  Subsequently, the underlying insulating film 32 is removed by dry etching using a fluorine-based gas using the OC layer 44 as a mask. By this etching, the insulating film 32 in the formation region (including the electrode connection region 52c) of the second terminal electrode 52b of the gate terminal 52 and the formation region of the second terminal electrode 54b of the drain terminal 54 shown in FIG. Removed.

  When the insulating film 32 is etched, the frame region 56 is exposed to an etching process, so that the film is reduced. When the resin CF layer 42 is used, the film thickness of one layer is reduced in almost any color. As a result, the frame region in which the three resin CF layers are laminated is reduced to the thickness of the two resin CF layer laminates (see FIG. 50).

Further, Ti (or Mo) constituting the metal layer 62 of the source electrode 30 and the storage capacitor electrode 38 below the contact holes 46 and 48 has a low resistance to the fluorine-based gas, and thus Al is partially exposed mainly from the center side. However, since Ti (or Mo) remains in the peripheral portion, there is no problem in connection with the pixel electrode 10 thereafter. Similarly, the metal layer Ti (or Mo) of the first terminal electrode 52b of the electrode connection region 52b of the gate terminal formation region 51 and the first terminal electrode 54b of the electrode connection region 54b of the drain terminal formation region 54 is also fluorine. Al is barely exposed mainly from the central portion side because of low resistance to the system gas, but Ti (or Mo) remains in the peripheral portion, so each of the subsequent second terminal electrodes 52b and 54b There is no problem with the connection.
When the etching process is completed, heat treatment is performed within a range of 200 to 230 ° C.

  Subsequently, an ITO film (thickness 70 nm) for forming the pixel electrode 10 made of ITO (indium tin oxide), which is a transparent oxide conductive material, is formed on the entire surface of the substrate by a thin film forming method such as sputtering. The pixel electrode 10 electrically connected to the source electrode 30 and the storage capacitor electrode 48 through the contact holes 46 and 48 is formed by forming a resist mask having a pattern and performing wet etching using an oxalic acid-based etchant (see FIG. 18 and FIG. 25). At the same time, as shown in FIGS. 5 and 8, the second terminal electrode 52b connected to the first terminal electrode 52a and the electrode switching region 52b is patterned in the gate terminal formation region 51, and FIGS. 11, the second terminal electrode 54 b connected to the first terminal electrode 54 a and the electrode connection region 54 b is patterned in the drain terminal formation region 54. Thereafter, heat treatment is performed within a range of 150 to 230 ° C., preferably 200 ° C.

  At the same time, as shown in FIG. 50, the protective film 70 is patterned so as to cover the resin CF layer 42 exposed in the region of the frame region 56 where the OC layer 44 is not formed.

  FIG. 45 shows a modification near the contact hole 46. As shown in FIG. 45, after forming the resin CF layer 42, a wide contact hole 46 'is formed in the resin CF layer 42 in advance. Then, when the OC layer 44 is formed and the contact hole 46 is opened, the OC layer 44 is left on the inner wall of the contact hole 46 ′. By doing so, the resin CF layer 42 can be covered with the OC layer 44 also on the inner wall of the contact hole 46.

  Further, in this embodiment, the distance in the substrate surface direction from the edge of the contact hole 46 indicated by the width α in FIG. 3 to the gate bus line 6 is 6 μm or more when the size of the pixel region is about 300 μm vertically and 100 μm wide. It is important that they are separated.

  When the OC layer 44 remains on the inner wall of the contact hole 46 and the width α is set to 6 μm or more, cracks (cracks) due to stress due to the difference in thermal expansion coefficient occur in the contact hole 46 in the process. The possibility can be kept very low.

  When the pixel electrode 10 is disposed on the OC layer 44, crack defects are likely to occur due to the difference in the coefficient of thermal expansion as described above, but it is characteristically generated in the vicinity of a portion having a step such as a contact hole instead of a flat portion. To do. Therefore, the relationship between the OC layer 44 and the contact hole is important. By adjusting the relationship between the distance and area of the flat portion of the pixel region, the film thickness / hole diameter of the resin layer forming the contact hole, and the taper length of the contact hole. The above defects can be improved. Preferably, the relationship between the film thickness of the OC layer 44 and the distance between the pixel ends is 2.5 times or more, the distance between the taper portions at the contact hole ends is 1.5 times the film thickness, or the angle is 45 °. The following.

  Further, as shown in FIG. 3, the pixel electrode 10 in the pixel region according to the present embodiment, except for the source electrode 30 and the storage capacitor electrode 38 of the TFT 2, is a gate bus line 6 or a drain bus line when viewed in the normal direction of the substrate surface. The structure is such that it does not overlap with the lower electrode wiring such as the line 8. For this reason, generation | occurrence | production of crosstalk can fully be suppressed and the outstanding display quality can be acquired.

  Thus, the liquid crystal display substrate (TFT substrate 1) according to the present embodiment is completed. Thereafter, the liquid crystal display device shown in FIG. 1 is completed through a panel unit process. In order to make the light shielding function according to the present embodiment function more effectively, it is preferable to adopt a normally black (NB) mode, and it is more preferable to use a vertically aligned negative type liquid crystal represented by MVA. is there.

  According to the present embodiment using the above-described configuration and the manufacturing method thereof, the external connection terminals are directly formed on the glass substrate 3 with good contact with the second terminal electrodes 52b and 54b made of an oxidized conductive material. Short circuit failure between adjacent terminals due to peeling or the like can be prevented.

  Further, according to the light shielding structure of the present embodiment, since at least the green resin CF layer can be formed on all the TFTs 2 in the pixel region, a light shielding film with sufficient light shielding performance can be formed. Furthermore, since the resin CF layer 42 having a two-layer structure can be formed in the frame region 56, it is possible to sufficiently shield light from leakage from the backlight unit. On the other hand, since the pixel region P can have a laminated structure of one resin CF layer 42 and OC layer 44, the film thickness of the resin CF layer 42 having a two-layer structure, one resin CF layer 42, and an OC layer. If the film thickness of the layered structure of 44 is formed substantially the same, a substrate for a liquid crystal display device capable of obtaining a uniform cell gap can be realized.

In the panel unit process, when a pretilt angle is given to liquid crystal molecules using a polymer, a predetermined voltage is applied between the common electrode of the counter substrate 4 and the pixel electrode 10 of the TFT substrate 1 after the liquid crystal is sealed. While irradiating the liquid crystal with UV light, the monomer in the liquid crystal is polymerized. Thereby, a predetermined pretilt angle can be imparted to the liquid crystal molecules. At this time, if a voltage is also applied to the frame region 56, a pretilt angle is also given to the liquid crystal molecules on the frame region 56 by polymerization of the monomer, and in the NB mode, the light shielding performance by the liquid crystal layer is lowered. To do. In order to suppress this, the conductive protective film 70 on the frame region 56 is connected to the common electrode to create a state where no voltage is applied to the liquid crystal on the frame region 56.
Since the voltage applied to the storage capacitor bus line 12 when the pretilt angle is applied is different from the common voltage, is the protective film 70 on the frame region 56 electrically isolated from the storage capacitor bus line 12? It is important to have a high resistance connection.

  Next, a substrate for a liquid crystal display device according to a second embodiment of the present invention, a method for manufacturing the same, and a liquid crystal display device using the same will be described with reference to FIGS. 46 to 48, 51 and 52. FIG. In the present embodiment, a case where a SiN film 40 is formed as an interlayer insulating film between the TFT 2 and the resin CF layer 42 will be described. In addition, the same code | symbol is attached | subjected to the component which show | plays the same function effect | action as 1st Embodiment, and the description is abbreviate | omitted.

  First, the prototype of TFT 2 is completed through the same steps as FIGS. 12 to 15 showing the steps of manufacturing TFT 2 in the method for manufacturing a substrate for a liquid crystal display device according to the first embodiment. Next, an SiN film 40 of an inorganic insulating film is formed as a protective film by plasma CVD with a film thickness of 10 to 150 nm or less, preferably about 50 nm.

Suitable film formation conditions and film quality conditions for the SiN film 40 are as follows.
Deposition temperature: gate insulating film (SiN film) 32> 270 ° C. ≧ SiN film 40
Refractive index (RI): When the refractive index of the gate insulating film (SiN film) 32 is 1.82 to 1.92, the refractive index of the SiN film 40 exceeds 1.92. Etching rate (E R.): (SiN film 40) / (gate insulating film (SiN film) 32) ≧ 0.7

  Next, the process proceeds to a color resin forming process, which is the same as in the first embodiment, and a description thereof will be omitted. Subsequently, the OC layer 44 is formed. Since it is the same as that of the first embodiment, the description thereof is omitted, but the magnitude relationship in the contact hole 46 of the OC layer 44, the resin CF layer 42, and the SiN film 40 is as follows. 46, as shown in FIG. That is, the resin CF layer 42> the SiN film 40> the OC layer 44, and the resin CF layer 42 is covered with the OC layer 44. By doing so, it becomes possible to prevent the influence of contamination of the color resin.

  A characteristic configuration of the substrate for a liquid crystal display device according to the present embodiment is shown in FIGS. 46 to 48 correspond to FIG. 1, FIG. 8, and FIG. 11 in the first embodiment, respectively. As shown in FIGS. 46 to 48, the SiN film 40 is formed as an interlayer insulating film between the TFT 2 and the resin CF layer 42 for preventing contamination by the color resin.

  The liquid crystal display device substrate according to the present embodiment can provide the same effects as those of the first embodiment. Furthermore, since the contamination by the color resin can be prevented by disposing the interlayer protective film on the TFT 2, the degree of freedom in selecting the color resin can be expanded. Furthermore, it is suitable not only for the channel protection type (ISI) TFT structure according to the first and second embodiments but also for the TFT substrate of the etch back type (NSI) TFT structure which is more susceptible to contamination. is there. Further, since the OC layer 44 also covers the color resin with respect to the liquid crystal layer, it is possible to prevent contamination of the liquid crystal.

  51 shows a state in which the TFT substrate 1 and the counter substrate 4 according to the present embodiment are bonded to each other and the liquid crystal 84 is sealed, which is cut along a line passing through the AA line and the BB line in FIG. A cross section is shown. As shown in FIG. 51, when the TFT substrate 1 having the CF-on-TFT structure according to the present embodiment is used, the counter substrate 4 only needs to form the common electrode 80 and the alignment film (not shown) on the glass substrate. . The cell gap is obtained by a spherical spacer (bead) 82 made of glass or resin. FIG. 52 shows an LCD in which a columnar spacer 86 is formed by using a photolithography process instead of the spherical spacer 82 and a predetermined cell gap is obtained by the columnar spacer 86. In FIG. 52, the columnar spacer 86 is formed on the counter substrate 4 side, but may be formed on the TFT substrate 1 side. The configuration shown in FIGS. 51 and 52 is of course applicable to the first embodiment and the third embodiment to be described next.

  Next, a substrate for a liquid crystal display device according to a third embodiment of the present invention, a method for manufacturing the same, and a liquid crystal display device using the same will be described with reference to FIG. As shown in FIG. 49, the liquid crystal display device substrate according to the present embodiment is further added to the TFT substrate 1 described in the first and second embodiments, as shown in FIG. It has characteristics.

  As shown in FIG. 49, the vernier pattern for confirming misregistration is formed by opening a rectangular first opening pattern 64 formed by opening the storage capacitor electrode 38 and the pixel electrode 10 and opening the first opening. A rectangular second opening pattern 66 having a size that can be accommodated in the pattern, and a third rectangular opening having a size including the first and second opening patterns 64 and 66 formed by opening the resin CF layer 42. Pattern.

  By doing this, it is possible to eliminate the autofocus error of the dimension measuring machine equipped with the epi-illumination optical system and the epi-illumination absorption by the resin CF layer 42, and the overlay measurement between the pixel electrode 10 and the lower metal pattern can be easily performed. It will be possible to do accurately. Further, if the OC layer 44 and the contact hole 46 are separately formed, the OC layer 44 on the misregistration confirmation vernier pattern can be removed, and the focus shift of the inspection apparatus can be improved. it can.

The present invention is not limited to the above embodiment, and various modifications can be made.
For example, the present invention is not limited to the examples in the above embodiment, and the present invention can be applied even if the type and structure of the wiring metal, the film thickness, the formation method, or the etching method are different.

In the above embodiment, the TFT 2 is an ISI type. However, the present invention is not limited to this, and can be applied to an NSI, a positive stagger type, a coplanar type, and the like. Furthermore, the present invention is naturally applicable to the case where the semiconductor forming the TFT channel is polysilicon (P-Si) instead of a-Si. Further, the present invention is naturally applicable even if the structure of the insulating film and the insulating substrate are plastic substrates instead of glass substrates.
In the above embodiment, a so-called independent CS type pixel structure in which the storage capacitor (CS) bus line 12 crosses the center of the pixel is described as an example. However, the present invention is not limited to this, and the independent CS type is used instead. Of course, the present invention can also be applied to a so-called CS-on-gate pixel structure in which the next-stage gate bus line is used as a storage capacitor bus line.

The liquid crystal display device and the defect repair method thereof according to the embodiment described above can be summarized as follows.
(Appendix 1)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
Pixel electrodes formed in a plurality of pixel regions arranged in a matrix on the insulating substrate;
A switching element connected to the pixel electrode and the bus line;
A first terminal electrode electrically connected to the bus line; a second terminal electrode formed on the insulating substrate with a material for forming the pixel electrode; and the first and second terminal electrodes. A substrate for a liquid crystal display device, comprising: an electrode connection region for electrical connection, and an external connection terminal for electrically connecting an external circuit and the bus line.

(Appendix 2)
In the substrate for a liquid crystal display device according to appendix 1,
An overcoat layer made of an insulating resin material formed between the switching element and the pixel electrode;
The substrate for a liquid crystal display device, wherein the overcoat layer is not formed at least between the second terminal electrode and the insulating substrate.

(Appendix 3)
In the substrate for a liquid crystal display device according to appendix 2,
The substrate for a liquid crystal display device, wherein the overcoat layer has a protrusion in the vicinity of the electrode switching region.

(Appendix 4)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region comprising a plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements, resin color filter layers, and pixel electrodes formed in this order;
A frame region provided with a light shielding layer formed by laminating the resin color filter layer around the display region;
A substrate for a liquid crystal display device, comprising: an overcoat layer made of an insulating resin material formed between the resin color filter layer in the display region and the pixel electrode.

(Appendix 5)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements formed thereon;
A liquid crystal display substrate, comprising: at least one resin color filter layer formed on the pixel region so as to cover the switching element.

(Appendix 6)
In the substrate for a liquid crystal display device according to appendix 5,
A substrate for a liquid crystal display device, wherein the resin color filter layer has a plurality of color layers stacked above the switching element.

(Appendix 7)
In the substrate for a liquid crystal display device according to appendix 5 or 6,
At least one layer of the resin color filter layers of the plurality of colors is a T-shaped pattern or a ridge shape (truncated shape) protruding so as to cover the switching elements of adjacent pixels when viewed in the normal direction of the substrate surface. A substrate for a liquid crystal display device, characterized by having a pattern.

(Appendix 8)
In the substrate for liquid crystal display device according to appendix 6,
The substrate for a liquid crystal display device, wherein the resin color filter layer in direct contact with the switching element is formed of a material having the largest volume resistance among the resin color filter layers of the plurality of colors.

(Appendix 9)
In the substrate for liquid crystal display device according to appendix 8,
The resin color filter layer in direct contact with the switching element has a volume resistance of 2.0 × 10 ^{16 to} 2.2 × 10 ¹⁶ Ω · cm or more. .

(Appendix 10)
The substrate for a liquid crystal display device according to any one of appendices 5 to 9,
A substrate for a liquid crystal display device, wherein a SiN interlayer insulating film is provided between the switching element and the resin color filter layer.

(Appendix 11)
In the substrate for a liquid crystal display device according to appendix 10,
The substrate for a liquid crystal display device, wherein the refractive index of the interlayer insulating film exceeds 1.92 when the refractive index of the gate insulating film of the switching element is 1.82 to 1.92.

(Appendix 12)
In the substrate for a liquid crystal display device according to appendix 10 or 11,
The interlayer insulating film has a thickness of 10 nm to 150 nm.

(Appendix 13)
The substrate for a liquid crystal display device according to any one of appendices 10 to 12,
Etching rate at the time of patterning of the interlayer insulating film,
(Etching time of the interlayer insulating film) / (etching time of the gate insulating film) ≧ 0.7
A substrate for a liquid crystal display device.

(Appendix 14)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A resin color filter layer formed in a plurality of pixel regions arranged in a matrix on the insulating substrate;
A pixel electrode formed in an upper layer of the resin color filter layer;
A storage capacitor electrode formed under the resin color filter layer and connected to the pixel electrode;
A first opening pattern that opens to the storage capacitor electrode; a second opening pattern that opens to the pixel electrode above the first opening pattern and is included in the first opening pattern; and the resin color filter layer And a misregistration confirmation vernier pattern provided with a third opening pattern opened to a position and size including the first opening pattern.

(Appendix 15)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region composed of a plurality of pixel regions arranged in a matrix on the insulating substrate, wherein switching elements, silicon nitride films, resin color filter layers, and pixel electrodes are formed in this order;
An overcoat layer made of an insulating resin material formed between the resin color filter layer and the pixel electrode in the display region;
A substrate for a liquid crystal display device comprising: a contact hole opened on the switching element such that an opening area is the resin color filter layer> the silicon nitride film> the overcoat layer.

(Appendix 16)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region composed of a plurality of pixel regions arranged in a matrix on the insulating substrate, wherein switching elements, silicon nitride films, resin color filter layers, and pixel electrodes are formed in this order;
An overcoat layer made of an insulating resin material formed between the resin color filter layer and the pixel electrode in the display region;
A substrate for a liquid crystal display device comprising: a contact hole opened on the switching element so that an opening area is the overcoat layer> the resin color filter layer> the silicon nitride film.

(Appendix 17)
In the substrate for liquid crystal display device according to appendix 15 or 16,
The shortest distance between the end of the contact hole and the end of the pixel region is 6 μm or more.

(Appendix 18)
The substrate for a liquid crystal display device according to any one of appendices 15 to 17,
The contact hole has a taper portion distance of 1.5 times or more the film thickness of the overcoat layer, or a taper angle of 45 ° or less.

(Appendix 19)
The substrate for a liquid crystal display device according to any one of appendices 15 to 17,
The shortest distance between the contact hole end and the pixel region end is at least 2.5 times the film thickness of the overcoat layer.

(Appendix 20)
An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region comprising a plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements, resin color filter layers, and pixel electrodes formed in this order;
A frame region comprising: a light shielding layer formed by laminating the resin color filter layer around the outer periphery of the display region; and a protective film formed of a material for forming the pixel electrode and covering the color filter layer upper layer of the light shielding layer; A substrate for a liquid crystal display device, comprising:

(Appendix 21)
In the substrate for a liquid crystal display device according to appendix 20,
The substrate for a liquid crystal display device, wherein the protective film is electrically connected to a common electrode disposed on the counter substrate.

(Appendix 22)
In the substrate for a liquid crystal display device according to appendix 20,
The substrate for a liquid crystal display device, wherein the protective film is insulated or connected with a high resistance to a storage capacitor wiring constituting a storage capacitor provided in the pixel region.

(Appendix 23)
A liquid crystal display device having a pair of substrates and a liquid crystal sealed between the pair of substrates,
23. A liquid crystal display device, wherein the substrate for a liquid crystal display device according to any one of appendices 1 to 22 is used for one of the substrates.

(Appendix 24)
In the liquid crystal display device according to attachment 23,
The liquid crystal display device, wherein the liquid crystal contains a polymer that imparts a pretilt angle to liquid crystal molecules.

It is a figure which shows the structure of the liquid crystal display device by the 1st Embodiment of this invention. FIG. 3 is a diagram showing an equivalent circuit on the TFT substrate side of the liquid crystal display device according to the first embodiment of the present invention. It is a figure which shows the state which looked at 1 pixel on the glass substrate 3 in the substrate for liquid crystal display devices by the 1st Embodiment of this invention from the liquid crystal layer side. It is a figure which shows the cross section cut | disconnected by the AA line of FIG. It is a figure which shows the structure of the frame area | region vicinity in the state which looked at the TFT substrate 1 in the liquid crystal display device substrate by the 1st Embodiment of this invention from the liquid crystal layer side. It is a figure which shows the structure of the gate terminal vicinity on the glass substrate 3 in the substrate for liquid crystal display devices by the 1st Embodiment of this invention. It is a figure which shows the cross section cut | disconnected by the CC line | wire of FIG. It is a figure which shows the cross section cut | disconnected by the DD line | wire of FIG. It is a figure which shows the structure of the drain terminal vicinity on the glass substrate 3 in the board | substrate for liquid crystal display devices by the 1st Embodiment of this invention. It is a figure which shows the cross section cut | disconnected by the EE line | wire of FIG. It is a figure which shows the cross section cut | disconnected by the FF line | wire of FIG. FIG. 4 is a manufacturing process sectional view (No. 1) of the TFT formation region cut along the line AA of FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 6 is a manufacturing process cross-sectional view (No. 2) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display substrate according to the first embodiment of the present invention. FIG. 6 is a manufacturing process sectional view (part 3) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display substrate according to the first embodiment of the present invention; FIG. 4D is a manufacturing process sectional view (No. 4) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 5D is a manufacturing process cross-sectional view (No. 5) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 8 is a manufacturing process cross-sectional view (No. 6) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 10 is a manufacturing process cross-sectional view (No. 7) of the TFT formation region cut along the line AA in FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 6 is a manufacturing process sectional view (No. 1) of the storage capacitor forming region cut along the line BB in FIG. 3 in the substrate for a liquid crystal display device according to the first embodiment of the present invention and passing through the contact hole 48; . FIG. 7 is a manufacturing process sectional view (No. 2) of the storage capacitor forming region cut along the line BB in FIG. 3 and passing through the contact hole 48 in the liquid crystal display substrate according to the first embodiment of the present invention; . FIG. 7 is a manufacturing process sectional view (part 3) of the storage capacitor forming region cut along line BB in FIG. 3 in the substrate for liquid crystal display device according to the first embodiment of the present invention and passing through the contact hole 48; . FIG. 7 is a manufacturing process sectional view (part 4) of the storage capacitor forming region cut along the line BB in FIG. 3 in the substrate for a liquid crystal display device according to the first embodiment of the present invention and passing through the contact hole 48; . FIG. 7 is a manufacturing process sectional view (No. 5) of the storage capacitor forming region cut along the line BB in FIG. 3 and passing through the contact hole 48 in the liquid crystal display substrate according to the first embodiment of the present invention; . FIG. 6 is a manufacturing process sectional view (No. 6) of the storage capacitor forming region cut along the line BB in FIG. 3 and passing through the contact hole 48 in the liquid crystal display substrate according to the first embodiment of the present invention; . FIG. 8 is a manufacturing process sectional view (No. 7) of the storage capacitor forming region cut along the line B-B in FIG. 3 in the liquid crystal display device substrate according to the first embodiment of the present invention and passing through the contact hole 48; . FIG. 7 is a manufacturing process cross-sectional view (part 1) of the region of the second terminal electrode 52b of the gate terminal 52 cut along the line CC in FIG. 6 in the substrate for a liquid crystal display device according to the first embodiment of the present invention; FIG. 7 is a manufacturing process sectional view (No. 2) of the region of the second terminal electrode 52b of the gate terminal 52 cut along the line CC in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 7C is a manufacturing process sectional view (No. 3) of the region of the second terminal electrode 52b of the gate terminal 52 cut along the line CC in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the invention; FIG. 7D is a manufacturing process sectional view (No. 4) of the region of the second terminal electrode 52b of the gate terminal 52 cut along the line CC in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 7D is a manufacturing process sectional view (No. 1) of the electrode connection region 52c of the gate terminal 52 cut along the line DD in FIG. 6 in the liquid crystal display substrate according to the first embodiment of the present invention; FIG. 7D is a manufacturing process sectional view (No. 2) of the electrode connection region 52c of the gate terminal 52 cut along the line DD in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 7D is a manufacturing process cross-sectional view (No. 3) of the electrode connection region 52c of the gate terminal 52 cut along the line DD in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 7D is a manufacturing process cross-sectional view (No. 4) of the electrode connection region 52c of the gate terminal 52 cut along the line DD in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 7D is a manufacturing process sectional view (No. 5) of the electrode switching region 52c of the gate terminal 52 cut along the line DD in FIG. 6 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 10A is a manufacturing process sectional view (No. 1) of the second terminal electrode 54b of the drain terminal 54 cut along the line EE of FIG. 9 in the liquid crystal display device substrate according to the first embodiment of the invention; FIG. 10A is a manufacturing process sectional view (No. 2) of the second terminal electrode 54b of the drain terminal 54 cut along the line EE of FIG. 9 in the liquid crystal display device substrate according to the first embodiment of the invention; FIG. 10A is a manufacturing process sectional view (No. 3) of the second terminal electrode 54b of the drain terminal 54 cut along the line E-E in FIG. 9 in the liquid crystal display device substrate according to the first embodiment of the invention; FIG. 10D is a manufacturing process cross-sectional view (No. 4) of the second terminal electrode 54b of the drain terminal 54 cut along the line EE of FIG. 9 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 10 is a manufacturing process cross-sectional view (part 1) of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG. 9 in the liquid crystal display device substrate according to the first embodiment of the present invention; FIG. 10 is a manufacturing process sectional view (No. 2) of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG. 9 in the liquid crystal display substrate according to the first embodiment of the present invention; FIG. 11 is a manufacturing process sectional view (No. 3) of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG. 9 in the liquid crystal display substrate according to the first embodiment of the present invention; FIG. 11 is a manufacturing process cross-sectional view (part 4) of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG. 9 in the liquid crystal display substrate according to the first embodiment of the present invention; FIG. 10 is a manufacturing process cross-sectional view (No. 5) of the drain terminal 54 electrode connection region 54 cut along the line FF in FIG. 9 in the liquid crystal display substrate according to the first embodiment of the present invention; The figure which shows the state which looked at the several pixel area | region P in which resin CF layer 42R, 42G, 42B was formed in the substrate for liquid crystal display devices by the 1st Embodiment of this invention in the substrate surface normal direction of the glass substrate 3. It is. It is a figure which shows the modification of the contact hole 46 vicinity in the liquid crystal display substrate by the 1st Embodiment of this invention. FIG. 3 shows the magnitude relationship in the contact hole 46 of the OC layer 44, the resin CF layer 42, and the SiN film 40 in the liquid crystal display substrate according to the second embodiment of the present invention. It is a figure corresponding to. FIG. 9 shows a substrate for a liquid crystal display device according to a second embodiment of the present invention, in which a SiN film 40 is formed as an interlayer insulating film, corresponding to FIG. 8 of the first embodiment. FIG. 12 shows a substrate for a liquid crystal display device according to a second embodiment of the present invention, in which a SiN film 40 is formed as an interlayer insulating film, and corresponds to FIG. 11 of the first embodiment. It is a figure which shows the board | substrate for liquid crystal display devices by the 3rd Embodiment of this invention. 2 shows a cross-sectional configuration in the vicinity of the frame region 56 of the TFT substrate 1 in the substrate for a liquid crystal display device according to the first embodiment of the present invention, and a cross section along the extending direction of either the gate bus line 6 or the drain bus line 8 FIG. It is sectional drawing which shows the state which bonded the liquid crystal display device substrate and counter substrate by the 2nd Embodiment of this invention, and sealed the liquid crystal. It is sectional drawing which shows the other example of the state which bonded the liquid crystal display device substrate and counter substrate by the 2nd Embodiment of this invention, and sealed the liquid crystal.

Explanation of symbols

1 TFT substrate 2 TFT
3 Glass substrate 4 Counter substrate 4 ′ Edge 6 of counter substrate 4 Gate bus line 8 Drain bus line 10 Pixel electrode 12 Storage capacitor bus line 14 Gate bus line driving circuit 16 Drain bus line driving circuit 18 Control circuit 20, 24 Polarizing plate 22 Backlight unit 26 Drain electrode 28 Channel protective film 30 Source electrode 32 Gate insulating film 34 Operating semiconductor layer 36 Ohmic contact layer 38 Storage capacitor electrode 40 SiN film (interlayer insulating film)
42 Resin CF layer 44 OC layer 46, 48 Contact hole 50 Display area 51 Gate terminal formation area 52 Gate terminals 52a, 54a First terminal electrodes 52b, 54b Second terminal electrodes 52c, 54c Electrode switching area 53 Drain terminal formation Region 54 Drain terminal 56 Frame region 58 Main seal 60 Protrusion 62 Metal layer 64 First opening pattern 66 Second opening pattern 68 Third opening pattern 70 Protective film 80 Common electrode 82 Spherical spacer 84 Liquid crystal 86 Columnar spacer

Claims (9)

An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region comprising a plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements, resin color filter layers, and pixel electrodes formed in this order;
A frame region provided with a light shielding layer formed by laminating the resin color filter layer around the display region;
A substrate for a liquid crystal display device, comprising: an overcoat layer made of an insulating resin material formed between the resin color filter layer in the display region and the pixel electrode. An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements formed thereon;
A liquid crystal display substrate, comprising: at least one resin color filter layer formed on the pixel region so as to cover the switching element. The substrate for a liquid crystal display device according to claim 2,
At least one layer of the resin color filter layers of the plurality of colors is a T-shaped pattern or a ridge shape (truncated shape) protruding so as to cover the switching elements of adjacent pixels when viewed in the normal direction of the substrate surface. A substrate for a liquid crystal display device, characterized by having a pattern. An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A resin color filter layer formed in a plurality of pixel regions arranged in a matrix on the insulating substrate;
A pixel electrode formed in an upper layer of the resin color filter layer;
A storage capacitor electrode formed under the resin color filter layer and connected to the pixel electrode;
A first opening pattern that opens to the storage capacitor electrode; a second opening pattern that opens to the pixel electrode above the first opening pattern and is included in the first opening pattern; and the resin color filter layer And a misregistration confirmation vernier pattern provided with a third opening pattern opened to a position and size including the first opening pattern. An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region composed of a plurality of pixel regions arranged in a matrix on the insulating substrate, wherein switching elements, silicon nitride films, resin color filter layers, and pixel electrodes are formed in this order;
An overcoat layer made of an insulating resin material formed between the resin color filter layer and the pixel electrode in the display region;
A substrate for a liquid crystal display device comprising: a contact hole opened on the switching element such that an opening area is the resin color filter layer> the silicon nitride film> the overcoat layer. An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region composed of a plurality of pixel regions arranged in a matrix on the insulating substrate, wherein switching elements, silicon nitride films, resin color filter layers, and pixel electrodes are formed in this order;
An overcoat layer made of an insulating resin material formed between the resin color filter layer and the pixel electrode in the display region;
A substrate for a liquid crystal display device comprising: a contact hole opened on the switching element so that an opening area is the overcoat layer> the resin color filter layer> the silicon nitride film. An insulating substrate sandwiching the liquid crystal together with the opposing substrate disposed oppositely;
A display region comprising a plurality of pixel regions arranged in a matrix on the insulating substrate and having switching elements, resin color filter layers, and pixel electrodes formed in this order;
A frame region comprising: a light shielding layer formed by laminating the resin color filter layer around the outer periphery of the display region; and a protective film formed of a material for forming the pixel electrode and covering the color filter layer upper layer of the light shielding layer; A substrate for a liquid crystal display device, comprising: A liquid crystal display device having a pair of substrates and a liquid crystal sealed between the pair of substrates,
A liquid crystal display device comprising the substrate for a liquid crystal display device according to claim 1 as one of the substrates. The liquid crystal display device according to claim 8.
The liquid crystal display device, wherein the liquid crystal contains a polymer that imparts a pretilt angle to liquid crystal molecules.

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