JP4072015B2 - LIQUID CRYSTAL DISPLAY DEVICE SUBSTRATE, ITS MANUFACTURING METHOD, AND LIQUID CRYSTAL DISPLAY DEVICE EQUIPPED WITH THE SAME - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate for a liquid crystal display device, a method for manufacturing the same, and a liquid crystal display device including the same, and more particularly to an active matrix liquid crystal display device using a switching element such as a thin film transistor (TFT). The present invention relates to a substrate for a liquid crystal display device and a manufacturing method thereof. The present invention also relates to a substrate for a liquid crystal display device used in a liquid crystal display device in which a protective insulating layer (insulating resin layer) made of an insulating organic resin material is formed on an array substrate on which switching elements are formed, and a method for manufacturing the same. . Furthermore, the present invention provides a reflective liquid crystal display device in which pixel electrodes are formed of a light reflecting material, or a liquid crystal display device in a CF-on-TFT structure in which a resin color filter (CF) is formed on an array substrate. The present invention relates to a substrate for a liquid crystal display device and a manufacturing method thereof.
[0002]
[Prior art]
An active matrix type liquid crystal display (LCD) using a TFT as a switching element is disclosed in, for example, Japanese Patent Laid-Open No. 6-202153. In this publication, as outlined below, a transmissive LCD including an inverted staggered TFT in which a channel protective film is formed is disclosed.
[0003]
A passivation film made of an inorganic insulating material is formed on almost the entire surface of an array substrate (hereinafter also referred to as a TFT substrate) on which TFTs are formed. A pixel electrode made of a transparent electrode material is formed on the passivation film. The pixel electrode is connected to the source electrode of the TFT through a contact hole having an opening in the passivation film.
[0004]
An external connection terminal (hereinafter abbreviated as a drain terminal) connected to the drain bus line forms a common layer with the source / drain electrodes of the TFT and the drain bus line. ⁺ It has a lower electrode formed of an a-Si layer and a metal layer. On the lower electrode, an upper electrode made of an oxide conductive film made of the same material as the pixel electrode is stacked via a contact hole opened in the passivation film. A connection terminal of a drain bus line driving circuit is connected to the upper electrode so that a predetermined gradation voltage is applied to each drain bus line.
[0005]
In addition, an external connection terminal (hereinafter abbreviated as a gate terminal) connected to the gate bus line has a lower electrode formed of a metal layer that forms a common layer with the gate electrode and the gate bus line. On the lower electrode, an upper electrode made of an oxide conductive film made of the same material as the pixel electrode is stacked through a contact hole opened in an insulating film and a passivation film that form a common layer with the gate insulating film. A connection terminal of a gate bus line driving circuit is connected to the upper electrode so that a predetermined gate pulse is sequentially applied to each gate bus line. The gate terminal and the drain terminal improve the long-term reliability by preventing the lower electrode from being oxidized by the upper electrode, and prevent connection failure.
[0006]
Next, an outline of a method for manufacturing a transmissive LCD having an inverted stagger type TFT in which a channel protective film is formed will be described. A plurality of gate bus lines and gate terminal lower electrodes are formed on a transparent insulating substrate such as a glass substrate. Next, an insulating film (hereinafter also referred to as a gate insulating film depending on a film formation site) is formed over the entire surface of the substrate. Subsequently, an a-Si layer is formed on the insulating film, and then a channel protective film is formed. Then n ⁺ After forming the a-Si layer, a metal layer is formed. Next, using the channel protective film as an etching stopper, a metal layer, n ⁺ The a-Si layer and the a-Si layer are collectively etched. Thus, an a-Si active semiconductor layer is formed on the gate insulating film of the TFT portion, and a source electrode and a drain electrode are formed on both sides of the channel protective film to complete the TFT. Further, simultaneously with the formation of the source electrode and the drain electrode, the drain terminal lower electrode connected to the drain bus line and the drain bus line is formed.
[0007]
Next, a silicon nitride film (SiN film) and a silicon oxide film (SiO2) which are inorganic insulating materials ₂ Film) or a passivation film made of a composite film thereof having a thickness of 400 nm is formed on the entire surface of the substrate. Next, after applying a resist, a resist pattern having openings on the source electrode, the drain terminal lower electrode, and the gate terminal lower electrode is formed by photolithography. Using this resist pattern as a mask, the passivation film, or the passivation film and the insulating film are etched to open contact holes.
[0008]
Next, a transparent conductive film made of ITO (Indium Tin Oxide) or the like having a thickness of 100 nm is formed on the entire surface of the substrate by sputtering or the like. Next, the transparent conductive film is patterned into a predetermined shape to form a pixel electrode connected to the source electrode through the contact hole. At the same time, a drain terminal upper electrode connected to the drain terminal lower electrode through another contact hole is formed, and a gate terminal upper electrode connected to the gate terminal lower electrode through another contact hole is formed.
[0009]
As described above, according to the above publication, when the gate terminal and the drain terminal are formed, the gate terminal lower electrode and the drain terminal lower electrode are formed, and the passivation film that covers the gate terminal lower electrode and the drain terminal lower electrode is formed. A gate electrode upper electrode composed of a transparent conductive film connected to the gate terminal lower electrode through the contact hole, and a transparent conductive film connected to the drain terminal lower electrode. The drain terminal upper electrode made of is formed simultaneously with the pixel electrode.
[0010]
Japanese Patent Laid-Open No. 2000-231123 discloses a liquid crystal display device in which an overcoat layer (hereinafter referred to as an OC layer) made of an insulating organic resin material is formed on an array substrate on which switching elements are formed. ing. The passivation film is made of an inorganic insulating film such as a SiN film and is generally formed with a film thickness of 300 to 400 nm. On the other hand, the OC layer is characterized in that it is formed with an extremely thick film thickness of 1000 to 3000 nm as compared with the passivation film. In addition, the OC layer has a characteristic that the dielectric constant of the resin as a forming material is relatively small (about 3 or less). With these two characteristics, the liquid crystal display device in which the OC layer is formed has an advantage that parasitic capacitance that degrades TFT characteristics can be reduced. Further, the liquid crystal display device in which the OC layer is formed has an advantage that the manufacturing process can be simplified because the contact hole is opened using the OC layer made of a photosensitive material as an etching mask.
[0011]
FIG. 18 shows a configuration of a TFT substrate of a conventional reflective liquid crystal display device in which an OC layer is formed. FIG. 18A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the TFT substrate is viewed in a direction perpendicular to the substrate surface, and FIG. 18B is a cross section taken along line XX in FIG. Is shown. As shown in FIGS. 18A and 18B, a gate terminal lower electrode 130 made of the same material as that of the gate bus line is formed on the glass substrate 106. The gate terminal lower electrode 130 generally has a laminated structure, and an Al-based metal layer 130a having a relatively low resistance is formed in the lower layer, and a refractory metal layer 130b is often formed in the upper layer. An insulating film 132 is formed on the gate terminal lower electrode 130. A protective film 134 is formed on the insulating film 132. An OC layer 136 is formed on the protective film 134. The surface of the OC layer 136 is formed, for example, in an uneven shape or a bowl shape.
[0012]
The OC layer 136, the protective film 134, and the insulating film 132 on the gate terminal lower electrode 130 are opened, and an electrode switching region 138 is formed. On the OC layer 136, a gate terminal upper electrode 140 made of the same material as that of the pixel electrode (reflection electrode) is formed. The gate terminal upper electrode 140 has a laminated structure of, for example, an ITO layer 140a, a silver (Ag) alloy layer 140b, and an ITO layer 140a. Further, the gate terminal upper electrode 140 is connected to the gate terminal lower electrode 130 in the electrode switching region 138.
[0013]
FIG. 19 shows a configuration of a TFT substrate of a transmissive liquid crystal display device having a conventional CF-on-TFT structure. FIG. 19A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the TFT substrate is viewed in a direction perpendicular to the substrate surface, and FIG. 19B is a cross section taken along the line ZZ in FIG. Is shown. As shown in FIGS. 19A and 19B, a gate terminal lower electrode 130 made of the same material as that of the gate bus line is formed on the glass substrate 106. An insulating film 132 is formed on the gate terminal lower electrode 130. A protective film 134 is formed on the insulating film 132. On the protective film 134, a resin CF layer 144 of any one of red (R), green (G), and blue (B) is formed.
[0014]
The resin CF layer 144, the protective film 134, and the insulating film 132 on the gate terminal lower electrode 130 are opened, and an electrode connection region 138 is formed. On the resin CF layer 144, a gate terminal upper electrode 140 made of the same forming material (for example, ITO) as the pixel electrode is formed. The gate terminal upper electrode 140 is connected to the gate terminal lower electrode 130 in the electrode switching region 138.
[0015]
[Problems to be solved by the invention]
The resin layers such as the OC layer 136 and the resin CF layer 144 are inferior to the passivation film in adhesion to an electrode material such as ITO formed in the upper layer. For this reason, the gate terminal upper electrode 140 directly formed on the OC layer 136 or the resin CF layer 144 is peeled off, which causes a problem that conduction failure, short circuit between adjacent terminals, and the like occur. Further, when patterning the gate terminal upper electrode 140, there arises a problem that etching defects such as a residue of an electrode material that causes a short circuit between adjacent terminals and a narrow wiring width that causes a resistance increase are likely to occur. .
[0016]
The liquid crystal display device is manufactured through a TFT array process, a CF process, a paneling process, and a unit process. In the unit process, the driver IC is mounted on the gate terminal and the drain terminal, for example, TAB (Tape Automated Bonding). At this time, the liquid crystal display device in which the connection failure has occurred due to the positional deviation of the driver IC at the time of mounting is repaired by attaching the TAB terminal again after removing the TAB terminal. For this reason, when the TAB terminal is peeled off, there arises a problem that the upper electrode is peeled off together with the OC layer 136 or the resin CF layer 144.
[0017]
20 and 21 show the configuration of a TFT substrate that solves the above problem. FIG. 20 shows the configuration of the TFT substrate of the reflective liquid crystal display device on which the OC layer is formed. FIG. 20A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the TFT substrate is viewed in a direction perpendicular to the substrate surface, and FIG. 20B is a cross section taken along line YY in FIG. Is shown. As shown in FIGS. 20A and 20B, the OC layer 136, the protective film 134, and the insulating film 132 between the adjacent gate terminals substantially coincide with the end face of the gate terminal lower electrode 130 on the electrode connection region 138 side. It has an end face. In addition, a protrusion 142 formed in a triangular shape having an acute apex in a cross section parallel to the substrate surface at the substantially central portion between the adjacent gate terminals on the end surfaces of the OC layer 136, the protective film 134, and the insulating film 132. Is formed so as to protrude toward the substrate end side (left side in FIG. 20A). The protrusion 142 is provided to prevent a short circuit between adjacent gate terminals due to an etching residue when patterning the gate terminal upper electrode 140.
[0018]
FIG. 21 shows a configuration of a TFT substrate of a transmissive liquid crystal display device having a CF-on-TFT structure. FIG. 21A shows a configuration in which the vicinity of the electrode switching region of the TFT substrate is viewed in a direction perpendicular to the substrate surface, and FIG. 21B shows a cross section taken along line WW in FIG. Yes. As shown in FIGS. 21A and 21B, the resin CF layer 144, the protective film 134, and the insulating film 132 between adjacent gate terminals are displayed on the display region from the end surface of the gate terminal upper electrode 140 on the electrode connection region 138 side. It has an end face on the side (right side in FIGS. 21A and 21B). That is, the surface of the glass substrate 106 is exposed between the adjacent gate terminals on the substrate end side (left side in FIGS. 21A and 21B) from the end surfaces of the resin CF layer 144, the protective film 134, and the insulating film 132. Yes. In addition, a protrusion 142 formed in a triangular shape having an acute apex in a cross section parallel to the substrate surface at the substantially central portion between the adjacent gate terminals on the end surfaces of the OC layer 136, the protective film 134, and the insulating film 132. Is formed so as to protrude toward the end portion of the substrate. The protrusion 142 is provided to prevent a short circuit between adjacent gate terminals due to an etching residue when patterning the gate terminal upper electrode 140.
[0019]
In the TFT substrate shown in FIGS. 20A, 20B, 21A, and 21B, the OC layer 136 is opened and the gate terminal upper electrode 140 is formed in direct contact with the glass substrate 106. This prevents peeling of the gate terminal upper electrode 140. However, in the above configuration, due to the steep shape of the end surface of the gate terminal lower electrode 130 on the side of the electrode connection region 138 with respect to the substrate surface, the gate terminal upper electrode 140 is disconnected at the stepped portion on the end surface, and the resistance of the gate terminal The problem arises that becomes high. Further, since the lower Al-based metal layer 130a and the gate terminal upper electrode 140 made of ITO or the like are in contact with the end surface of the gate terminal lower electrode 130 on the electrode switching region 138 side, corrosion or the like is likely to occur, and the wire breaks. The problem arises that it may cause Thus, in the electrode connection region 138, it is necessary to sufficiently consider the disconnection of the gate terminal upper electrode 140 and the electrical connection between the gate terminal upper electrode 140 and the gate terminal lower electrode 130.
[0020]
An object of the present invention is to provide a substrate for a liquid crystal display device that can simplify the manufacturing process and has high reliability, a manufacturing method thereof, and a liquid crystal display device using the same.
[0021]
[Means for Solving the Problems]
The object is to provide a plurality of bus lines formed on a substrate so as to cross each other through an insulating film, an insulating resin layer formed on the bus lines, and pixel regions arranged in a matrix on the substrate. A pixel electrode formed on each insulating resin layer, a thin film transistor connected to the pixel electrode and the bus line, a first terminal electrode electrically connected to the bus line, and the first A structure formed of a different forming material from the insulating resin layer on the outer periphery of the terminal electrode, and a second formed of the same forming material as the pixel electrode on the first terminal electrode and the structure. A liquid crystal display comprising: a terminal electrode; and an electrode connection region for connecting the first and second terminal electrodes, and an external connection terminal for electrically connecting an external circuit and the bus line. By display device substrate It is achieved Te.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
A substrate for a liquid crystal display device according to a first embodiment of the present invention, a method for manufacturing the same, and a liquid crystal display device including the same will be described with reference to FIGS. FIG. 1 shows a schematic configuration of a reflective liquid crystal display device according to the present embodiment. As shown in FIG. 1, the liquid crystal display device has a TFT substrate 2 on which pixel electrodes and TFTs made of a light-reflective material are formed for each pixel region, and a counter substrate 4 on which common electrodes and the like are formed. And a liquid crystal sealed between them.
[0023]
On the TFT substrate 2, a gate bus line driving circuit 80 on which driver ICs for driving a plurality of gate bus lines 12 are mounted, and a drain bus line driving circuit 82 on which driver ICs for driving a plurality of drain bus lines 14 are mounted. And are provided. Both the drive circuits 80 and 82 are configured to output a scanning signal and a data signal to a predetermined gate bus line 12 or drain bus line 14 based on a predetermined signal output from the control circuit 84.
[0024]
The counter substrate 4 has a resin CF layer in which any one color of R, G, and B is formed for each pixel region. An alignment film for aligning liquid crystal molecules in a predetermined direction is formed on the opposing surfaces of both the substrates 2 and 4. A polarizing plate 87 is attached to the surface of the counter substrate 4 opposite to the counter surface.
[0025]
FIG. 2 schematically shows an equivalent circuit of elements formed on the TFT substrate 2. 3 shows a configuration of one pixel on the TFT substrate 2, and FIG. 4 shows a cross section of the TFT substrate 2 cut along the line AA in FIG. As shown in FIGS. 2 to 4, a plurality of gate bus lines 12 extending in the left-right direction in FIG. 2 or 3 are formed in parallel on the glass substrate 6 of the TFT substrate 2. The gate bus line 12 has a structure in which, for example, an Al-based metal layer 12a having a relatively low resistance and a refractory metal layer 12b, for example, are stacked in this order. An insulating film (gate insulating film) 32 is formed on the entire surface of the gate bus line 12. A plurality of drain bus lines 14 extending in the vertical direction in FIGS. 2 and 3 are formed in parallel with each other so as to intersect the gate bus line 12 via the insulating film 32. A TFT 20 is formed in the vicinity of the intersection of the gate bus line 12 and the drain bus line 14.
[0026]
The TFT 20 has an operating semiconductor layer 50 made of an a-Si layer on the insulating film 32. A channel protective film 23 is formed on the operating semiconductor layer 50. On the channel protective film 23, the drain electrode 21 drawn out from the adjacent drain bus line 14 and n serving as an ohmic contact layer below the drain electrode 21. ⁺ a-Si layer 51, source electrode 22 and n underneath it ⁺ The a-Si layer 51 is formed to face each other with a predetermined gap. In such a configuration, the gate bus line 12 immediately below the channel protective film 23 functions as a gate electrode of the TFT 20.
[0027]
A pixel electrode 16 is formed in each pixel region arranged in a matrix on the TFT substrate 2. A storage capacitor bus line 18 extending in the horizontal direction in FIGS. 2 and 3 is formed in parallel with the gate bus line 12 across substantially the center of each pixel region. The storage capacitor bus line 18 is formed of the same material as that of the gate bus line 12. On the storage capacitor bus line 18, a storage capacitor electrode (intermediate electrode) 25 is formed for each pixel region via an insulating film 32. The storage capacitor electrode 25 is formed of the same material as that of the drain bus line 14. A protective film 34 is formed on the drain bus line 14, the drain electrode 21, the source electrode 22, and the storage capacitor electrode 25. An OC layer 36 is formed on the protective film 34. The surface of the OC layer 36 is formed in, for example, an uneven shape or a bowl shape.
[0028]
On the OC layer 36, a pixel electrode (reflection electrode) 16 is formed for each pixel region. The pixel electrode 16 is formed of a light reflecting material and has a laminated structure of, for example, an ITO layer 16a, an Ag alloy layer 16b, and an ITO layer 16a. The surface of the pixel electrode 16 is formed in a concavo-convex shape or a bowl shape following the shape of the OC layer 36 surface. Good light display characteristics can be obtained by irregularly reflecting light incident from the display screen side on the uneven or bowl-shaped surface of the pixel electrode 16. The pixel electrode 16 is electrically connected to the source electrode 22 through a contact hole 24 in which the OC layer 36 and the protective film 34 on the source electrode 22 are opened. The pixel electrode 16 is electrically connected to the storage capacitor electrode 25 through a contact hole 26 in which the OC layer 36 and the protective film 34 on the storage capacitor electrode 25 are opened. The TFT 20 and the bus lines 12, 14, 18 and the like are formed by a photolithography process, and are formed by repeating a series of semiconductor processes of “film formation → resist application → exposure → development → etching → resist stripping”.
[0029]
FIG. 5A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the liquid crystal display device substrate according to the present embodiment is viewed in the direction perpendicular to the substrate surface, and FIG. 5B shows the configuration of FIG. The cross section cut | disconnected by the BB line is shown. As shown in FIGS. 5A and 5B, a plurality of gate terminals 8 (two are shown in FIG. 5A) are formed in the frame region of the TFT substrate 2. The plurality of gate terminals 8 are electrically connected to a plurality of gate bus lines 12 formed in a display area (not shown, but to the right in FIGS. 5A and 5B). The gate terminal 8 includes a gate terminal lower electrode 30 (first terminal electrode), a structure 39 formed on the outer periphery of the gate terminal lower electrode 30, and an electrode connection region formed inside the structure 39. 38 and a gate terminal upper electrode 40 (second terminal electrode).
[0030]
The gate terminal lower electrode 30 is formed by laminating an Al-based metal layer 12a and a refractory metal layer 12b, which are the same forming material as the gate bus line 12. On the gate terminal lower electrode 30, insulating films 32 and 32 ′ that are the same layer as the insulating film 32 shown in FIG. 4 are formed. The surface of the insulating film 32 ′ formed on the substrate end side from the vicinity of the electrode switching region 38 and the vicinity of the electrode switching region 38 is etched, and the film thickness is smaller than that of the insulating film 32 on the display region side. A gate terminal upper electrode 40 is formed on the insulating film 32 ′. The structure 39 is formed of an insulating film 32 ′ so as to cover the outer peripheral portion and the end surface of the gate terminal lower electrode 30 on the gate terminal upper electrode 40 side. The structure 39 is formed across a plurality of gate terminals 8. The gate terminal upper electrode 40 is formed by laminating three layers of an ITO layer 16a, an Ag alloy layer 16b, and an ITO layer 16a, which are the same forming material as the pixel electrode 16. The gate terminal upper electrode 40 is connected to the gate terminal lower electrode 30 through an electrode connection region 38 in which an insulating film 32 ′ on the gate terminal lower electrode 30 is opened. That is, the gate terminal upper electrode 40 rides on the insulating film 32 ′ of the structure 39 from the substrate end side and is connected to the gate terminal lower electrode 30. Thus, the ITO layer 16a of the gate terminal upper electrode 40 and the Al-based metal layer 12a of the gate terminal lower electrode 30 are not directly connected.
[0031]
A protective film 34 and an OC layer 36 are laminated in this order on the insulating film 32 closer to the display area than the structure 39. In the vicinity of the end surface of the OC layer 36 and the protective film 34 on the electrode switching region 38 side, between the insulating film 32 and the protective film 34, an a-Si layer 50 'that is the same layer as the operating semiconductor layer 50 of the TFT 20, A channel protective film 23 and a structure forming protective film 52 of the same layer are laminated in this order.
[0032]
Although not shown, the drain terminal has the same structure as the gate terminal 8. That is, the drain terminal lower electrode is formed in the same layer as the gate terminal lower electrode 30, and the drain terminal upper electrode is formed in the same layer as the gate terminal upper electrode 40. The drain bus line 14 and the drain terminal lower electrode are electrically connected to each other through another connection region formed by opening the insulating film 32, for example.
[0033]
According to the present embodiment, since the insulating film 32 ′ is formed as the structure 39 on the outer peripheral portion on the gate terminal lower electrode 30, the ITO layer 16 a of the gate terminal upper electrode 40 and the gate terminal lower electrode 30 are formed. The Al-based metal layer 12a is not in direct contact. For this reason, corrosion of a terminal part can be prevented and the disconnection resulting from corrosion can also be prevented.
[0034]
In the present embodiment, the gate terminal upper electrode 40 is formed on the insulating film 32 ′ with good adhesion, not on the OC layer 36. For this reason, peeling of the gate terminal upper electrode 40 can be prevented without using a new resin for the OC layer 36.
Further, in the present embodiment, since the insulating film 32 ′ is formed so as to cover the end face of the outer peripheral portion of the gate terminal lower electrode 30, the gate terminal upper electrode 40 is unlikely to be disconnected.
[0035]
Next, a method for manufacturing a substrate for a liquid crystal display device according to the present embodiment will be described with reference to FIGS. 3 and 4 and FIGS. 6A to 6E and FIGS. 7A to 7D are process cross-sectional views illustrating the manufacturing process of the TFT substrate, and show a cross section corresponding to FIG. 5B. First, as shown in FIG. 6 (a), directly on the glass substrate 6 which is a transparent insulating substrate, or if necessary, SiO. _X After forming a protective film such as, an Al alloy having a film thickness of 130 nm, a molybdenum nitride (MoN) film having a film thickness of 70 nm, and Mo film having a film thickness of 15 nm, for example, are formed on the entire surface in this order by sputtering. Thereby, a metal layer having a thickness of about 215 nm composed of the Al-based metal layer 12a and the refractory metal layer 12b is formed. As an Al alloy, one or more of neodymium (Nd), silicon (Si), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), scandium (Sc), etc. are added to Al. Materials can be used.
[0036]
Next, a resist is applied on the entire surface of the metal layer. Next, exposure and development are performed using a photomask or a reticle (hereinafter referred to as a mask) to form a resist pattern having a predetermined shape. Next, wet etching using a phosphoric acid-based etchant is performed. Thereby, the gate terminal lower electrode 30 is formed, and the gate bus line 12 and the storage capacitor bus line 18 (both not shown in FIG. 6A) are formed.
[0037]
Next, as shown in FIG. 6B, a SiN film having a film thickness of, for example, 400 nm is formed on the entire surface of the substrate by plasma CVD, and an insulating film 32 is formed. Next, an a-Si layer 50 ′ having a film thickness of, for example, 30 nm for forming the active semiconductor layer 50 is formed on the entire surface of the substrate by plasma CVD. Further, for example, a 120 nm-thickness SiN film 23 ′ for forming the channel protective film 23 is formed on the entire surface of the substrate by plasma CVD.
[0038]
Next, a resist is applied to the entire surface of the SiN film 23 ′ by spin coating or the like. Next, back exposure is performed from the back side of glass substrate 6 (downward in FIG. 6B) using a mask that shields the frame region where the gate terminal and drain terminal are formed, and using gate bus line 12 as a mask. . Subsequently, exposure is performed from the surface side of the glass substrate 6 (above in FIG. 6B) using another mask. Thereafter, development is performed, and the resist in the exposed area is dissolved and removed. As a result, a resist pattern (not shown) is formed in a self-aligning manner on the channel protective film 23 forming region on the gate bus line 12 and the resist is formed on the outer peripheral portions of the gate terminal lower electrode 30 and the drain terminal lower electrode. A pattern (not shown) is formed.
[0039]
Next, dry etching using a fluorine-based gas is performed using the obtained resist pattern as an etching mask. As a result, as shown in FIG. 6C, a structure forming protective film 52 is formed on the outer periphery of the gate terminal lower electrode 30 and the drain terminal lower electrode, and the channel protective film 23 (see FIG. 6 (c) (not shown) is formed.
[0040]
Next, as shown in FIG. 6 (d), the surface of the a-Si layer 50 ′ is cleaned (removal of the natural oxide film) using dilute hydrofluoric acid, and then quickly, for example, n having a thickness of 30 nm. ⁺ An a-Si layer 51 is formed on the entire surface by plasma CVD. Next, for example, a metal layer 53 made of a laminate of a Ti layer 53a, an Al layer 53b, and a Ti layer 53a for forming the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the drain bus line 14 is sputtered by sputtering. The film is formed to a thickness of / 40 nm. As the metal layer 53, in addition to the composite film such as Ti / Al / Ti, for example, a simple substance such as chromium (Cr), Mo, Ta, Ti, or Al, or a composite film thereof can be used.
[0041]
Next, a resist is applied on the entire surface of the metal layer 53. Next, the resist is exposed and developed using a mask to form a resist pattern having a predetermined shape. Next, as shown in FIG. 6E, dry etching using a chlorine-based gas is performed using the resist pattern as an etching mask. Thus, the drain bus line 14, the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the operating semiconductor layer 50 (all not shown in FIG. 6E) are formed. In this etching process, the structure-forming protective film 52 and the channel protective film 23 function as an etching stopper, and the underlying a-Si layer 50 'remains without being etched. The structure forming protective film 52 and the channel protective film 23 are thinned by this etching.
[0042]
Next, as shown in FIG. 7A, for example, a 300 nm-thickness SiN film is formed on the entire surface of the substrate by plasma CVD, and a protective film 34 is formed.
[0043]
Next, as shown in FIG. 7B, an insulating organic resin having photosensitivity is applied on the entire surface of the protective film 34 to form the OC layer 36. Next, the surface of the concavo-convex or bowl-shaped OC layer 36 is formed by using half exposure, double exposure, or the like, and the OC layer 36 is patterned. In the patterned OC layer 36, the vicinity of the electrode connection region 38 and the substrate end side from the electrode connection region 38 are removed, and the surface of the protective film 34 is exposed. The OC layer 36 is opened on the contact hole 24 and 26 formation region.
[0044]
Subsequently, as shown in FIG. 7C, the protective film 34 and the insulating film 32 are removed by dry etching using a fluorine-based gas using the patterned OC layer 36 as a mask. By this etching, the protective film 34 and the insulating film 32 are removed in the electrode connection region 38 in the region where the gate terminal upper electrode 40 is formed, and the surface of the refractory metal layer 12b of the gate terminal lower electrode 30 is exposed. However, since the structure-forming protective film 52 and the a-Si layer 50 ′ are formed between the protective film 34 and the insulating film 32 on the outer peripheral portion outside the electrode switching region 38, the electrode switching is performed. At the time when the etching in the region 38 is finished, the insulating film 32 'remains. That is, if the etching is completed when the etching end point in the electrode switching region 38 is detected, the insulating film 32 ′ whose surface is etched and the film thickness is reduced remains as the structure 39.
[0045]
In this example, the protective film 34 is patterned using the patterned OC layer 36 as an etching mask. However, the OC layer 36 may be formed after the protective film 34 is patterned.
[0046]
Since the Ti (or Mo) layer 53a on the surface of the source electrode 22 and the storage capacitor electrode 25 exposed from the contact holes 24 and 26 has low resistance to fluorine-based gas, a part of the Ti (or Mo) layer is mainly Al. The layer 53b may be exposed. However, since the Ti (or Mo) layer 53a remains in the peripheral portions of the contact holes 24 and 26, the reliability of the subsequent connection with the pixel electrode 10 does not deteriorate.
[0047]
Subsequently, as shown in FIG. 7D, a transparent oxide conductive material such as an ITO layer 16a having a thickness of 50 nm, an Ag alloy layer 16b having a thickness of 100 nm, and an ITO layer 16a having a thickness of 50 nm, for example, are sputtered. Films are formed in this order on the entire surface of the substrate by a thin film forming method such as Next, a resist pattern having a predetermined shape is formed, and wet etching using an oxalic acid-based etchant is performed using the resist pattern as a mask. As a result, the gate terminal upper electrode 40 connected to the gate terminal lower electrode 30 in the electrode switching region 38 is formed. At the same time, in the display region, a pixel electrode 16 electrically connected to the source electrode 22 through the contact hole 24 and electrically connected to the storage capacitor electrode 25 through the contact hole 26 is formed for each pixel region. . Then, it heat-processes within the range of 150-230 degreeC, Preferably it is 200 degreeC.
[0048]
As described above, in this embodiment, a highly reliable liquid crystal display device can be realized without complicating the manufacturing process.
[0049]
[Second Embodiment]
Next, a liquid crystal display substrate and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 8 shows a configuration of one pixel on the TFT substrate 2 of the transmissive liquid crystal display device according to the present embodiment, and FIG. 9 shows a cross section of the TFT substrate 2 cut along the line CC in FIG. As shown in FIGS. 8 and 9, the TFT 20 of the TFT substrate 2 according to the present embodiment is a channel etch type that does not have a channel protective film. Also, the TFT substrate 2 according to the present embodiment has a CF-on-TFT structure in which a pigment-dispersed resin CF layer 44 is formed and an OC layer 36 made of an insulating organic resin material is formed on the resin CF layer 44. It is.
[0050]
The TFT 20 has an operating semiconductor layer 50 on the insulating film 32. On the operating semiconductor layer 50, the drain electrode 21 and n below the drain electrode 21. ⁺ a-Si layer 51, source electrode 22 and n underneath it ⁺ The a-Si layer 51 is formed to face each other with a predetermined gap. The surface of the channel region of the operating semiconductor layer 50 is partially etched to ensure isolation and insulation between the electrodes 21 and 22.
[0051]
In each pixel region including the TFT 20 and the storage capacitor electrode 25, any one of the resin CF layers 44R (red), 44G (green), and 44B (blue) is formed. Since the TFTs 20 can be shielded by the resin CF layers 44R, 44G, and 44B, good display characteristics can be obtained even with a structure that does not have a special light shielding pattern. In addition, since it is not necessary to form a light shielding film on the counter substrate 4, not only can the manufacturing process of the counter substrate 4 be simplified, but high bonding accuracy between the TFT substrate 2 and the counter substrate 4 is not required. Accordingly, a high-definition liquid crystal display device with a high aperture ratio can be mass-produced without forming the wiring layer and the end portion of the pixel electrode 16 in an overlapping manner.
[0052]
An OC layer 36 is formed on the resin CF layers 44R, 44G, and 44B. A pixel electrode 16 made of a transparent oxide electrode material such as ITO is formed on the OC layer 36 of each pixel. The pixel electrode 16 is electrically connected to the source electrode 22 through the contact hole 24 in which the OC layer 36 on the source electrode 22, the resin CF layers 44R, 44G, and 44B and the protective film 34 are opened. The pixel electrode 16 is electrically connected to the storage capacitor electrode 25 via a contact hole 26 in which the OC layer 36 on the storage capacitor electrode 25, the resin CF layers 44R, 44G, and 44B and the protective film 34 are opened. Yes.
[0053]
FIG. 10A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the liquid crystal display device substrate according to the present embodiment is viewed in the direction perpendicular to the substrate surface, and FIG. 10B shows the configuration of FIG. The cross section cut | disconnected by the DD line is shown. As shown in FIGS. 10A and 10B, the gate terminal 8 includes a gate terminal lower electrode 30 (first terminal electrode) and a structure 39 formed on the outer periphery of the gate terminal lower electrode 30. And an electrode connection region 38 formed inside the structure 39 and a gate terminal upper electrode 40 (second terminal electrode).
[0054]
The gate terminal lower electrode 30 is formed by laminating an Al-based metal layer 12a and a refractory metal layer 12b, which are the same forming material as the gate bus line 12. On the gate terminal lower electrode 30, insulating films 32 and 32 ′ that are the same layer as the insulating film 32 shown in FIG. 9 are formed. The surface of the insulating film 32 ′ formed in the vicinity of the electrode switching region 38 is etched, and the film thickness is smaller than that of the insulating film 32 on the display region side. A gate terminal upper electrode 40 is formed on the insulating film 32 ′. The structure 39 is formed of an insulating film 32 ′ so as to cover the outer peripheral portion and the end surface of the gate terminal lower electrode 30 on the gate terminal upper electrode 40 side. The structure 39 is formed across a plurality of gate terminals 8. The gate terminal upper electrode 40 is formed of an ITO layer that is the same material as the pixel electrode 16. The gate terminal upper electrode 40 is connected to the gate terminal lower electrode 30 through an electrode connection region 38 in which an insulating film 32 ′ on the gate terminal lower electrode 30 is opened. That is, the gate terminal upper electrode 40 rides on the insulating film 32 ′ of the structure 39 from the substrate end side and is connected to the gate terminal lower electrode 30. As a result, the ITO layer of the gate terminal upper electrode 40 and the Al-based metal layer 12a of the gate terminal lower electrode 30 are not directly connected.
[0055]
On the insulating film 32 closer to the display area than the structure 39, a protective film 34, a resin CF layer 44 (44R), and an OC layer 36 are laminated in this order. In the vicinity of the end face of the protective film 34, the resin CF layer 44, and the OC layer 36 on the electrode connection region 38 side, a structure of the same layer as the operating semiconductor layer 50 of the TFT 20 is formed between the insulating film 32 and the protective film 34. A semiconductor film 54 is formed.
[0056]
The insulating film 32 ′ between the adjacent gate terminals 8 has an end face on the substrate end side (left side in FIGS. 10A and 10B) from the end face of the gate terminal lower electrode 30 on the electrode connection region 38 side. Yes. That is, the surface of the glass substrate 6 is exposed on the substrate end side (left side in FIGS. 10A and 10B) from the end face of the insulating film 32 ′ between the adjacent gate terminals 8. Further, a projection 42 formed in a triangular shape having a cross section parallel to the substrate surface and having an acute apex angle is formed at the end surface of the insulating film 32 ′ on the substrate end side. Protrusively formed. The protrusion 42 is provided in order to prevent the adjacent gate terminals 8 from being short-circuited due to etching residue when the gate terminal upper electrode 40 is patterned.
[0057]
According to the present embodiment, as in the first embodiment, the insulating film 32 ′ is formed as the structure 39 on the gate terminal lower electrode 30 in the outer peripheral portion of the electrode switching region 38. The ITO layer of the gate terminal upper electrode 40 and the Al-based metal layer 12a of the gate terminal lower electrode 30 are not in direct contact. For this reason, corrosion of a terminal part can be prevented and the disconnection resulting from corrosion can also be prevented.
[0058]
In the present embodiment, the gate terminal upper electrode 40 is formed on the insulating film 32 ′ or the glass substrate 6 with good adhesion, not on the OC layer 36. For this reason, peeling of the gate terminal upper electrode 40 can be prevented without using a new resin for the resin CF layer 44 and the OC layer 36.
Further, in the present embodiment, since the insulating film 32 ′ is formed so as to cover the end face of the outer peripheral portion of the gate terminal lower electrode 30, the gate terminal upper electrode 40 is unlikely to be disconnected.
[0059]
Next, a method for manufacturing a substrate for a liquid crystal display device according to the present embodiment will be described with reference to FIGS. 11 and 12 with reference to FIGS. FIGS. 11A to 11E and FIGS. 12A to 12D are process cross-sectional views showing the manufacturing process of the TFT substrate, and show a cross section corresponding to FIG. 10B. First, as shown in FIG. 11 (a), directly on the glass substrate 6 which is a transparent insulating substrate, or if necessary, SiO. _X After forming a protective film such as, an Al alloy having a thickness of 130 nm, MoN having a thickness of 70 nm, and Mo having a thickness of 15 nm, for example, are formed on the entire surface in this order by sputtering. Thereby, a metal layer having a thickness of about 215 nm composed of the Al-based metal layer 12a and the refractory metal layer 12b is formed. As the Al alloy, a material obtained by adding one or more of Nd, Si, Cu, Ti, W, Ta, Sc and the like to Al can be used.
[0060]
Next, a resist is applied on the entire surface of the metal layer. Next, the resist is exposed and developed using a mask to form a resist pattern having a predetermined shape. Next, wet etching using a phosphoric acid-based etchant is performed. Thereby, the gate terminal lower electrode 30 is formed, and the gate bus line 12 and the storage capacitor bus line 18 (both not shown in FIG. 11A) are formed.
[0061]
Next, as shown in FIG. 11B, for example, a SiN film having a film thickness of 400 nm is formed on the entire surface of the substrate by plasma CVD, and an insulating film 32 is formed. Next, an a-Si layer 50 ′ having a thickness of, for example, 150 nm for forming the active semiconductor layer 50 is formed on the entire surface by plasma CVD. Further, for example, n having a film thickness of 30 nm ⁺ An a-Si layer 51 is formed on the entire surface by plasma CVD.
[0062]
Next, n is applied by spin coating or the like. ⁺ A resist is applied on the entire surface of the a-Si layer 51. Subsequently, exposure is performed from the forward direction (upward in FIG. 11B) using a mask. Thereafter, development is performed, and the resist in the exposed area is dissolved and removed. As a result, a resist pattern (not shown) is formed in a region where the operating semiconductor layer 50 of the TFT 20 is formed, and a resist pattern (on the outer periphery of the gate terminal lower electrode 30 and the drain terminal lower electrode (not shown)) is formed. (Not shown) is formed.
[0063]
Next, dry etching using a fluorine-based gas is performed using the obtained resist pattern as an etching mask. As a result, as shown in FIG. 11C, the structure-forming semiconductor film 54 made of the a-Si layer 50 ′ is formed on the outer periphery of the gate terminal lower electrode 30 and the drain terminal lower electrode (not shown). N above it ⁺ The a-Si layer 51 is formed, and the region which becomes the channel region of the TFT 20 and the region where the drain electrode 21 and the source electrode 22 are formed are n. ⁺ The a-Si layer 51 and the operating semiconductor layer 50 are formed in an island shape.
[0064]
Next, as shown in FIG. 11 (d), n is diluted with dilute hydrofluoric acid. ⁺ After cleaning the surface of the a-Si layer 51, for example, a Ti layer 53a, an Al layer 53b, and a Ti layer 53a for quickly forming the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the drain bus line 14 are stacked. The metal layer 53 made of is formed into a film thickness of 20/75/40 nm by sputtering. As the metal layer 53, in addition to the composite film such as Ti / Al / Ti, for example, a simple substance such as Cr, Mo, Ta, Ti or Al, or a composite film thereof can be used.
[0065]
Next, a resist is applied on the entire surface of the metal layer 53. Next, the resist is exposed and developed using a mask to form a resist pattern having a predetermined shape. Next, as shown in FIG. 11E, dry etching using a chlorine-based gas is performed on the metal layer 53 using the resist pattern as an etching mask. Thus, the drain bus line 14, the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the operating semiconductor layer 50 (all are shown in the figure). 11 (E) (not shown) is formed. Subsequently, n remaining between the drain electrode 21 and the source electrode 22 ⁺ Dry etching using a chlorine-based gas is performed on the a-Si layer 51. In this etching, the drain electrode 21 and the underlying n ⁺ a-Si layer 51, source electrode 22 and n underneath it ⁺ In order to ensure separation from the a-Si layer 51, the surface of the operating semiconductor layer 50 is etched (channel etching). In addition, in this etching, the surface of the structure forming semiconductor film 54 is similarly etched, so that the thickness of the structure forming semiconductor film 54 is reduced.
[0066]
Next, as shown in FIG. 12A, for example, a SiN film having a film thickness of 300 nm is formed on the entire surface of the substrate by plasma CVD, and a protective film 34 is formed.
[0067]
Next, one of the resin CF layers 44R, 44G, and 44B is formed for each pixel region. The resin CF layers 44R, 44G, and 44B are formed in stripes so that, for example, pixels adjacent in the vertical direction in FIG. 8 have the same color. First, as shown in FIG. 12B, an acrylic negative photosensitive resin in which, for example, a red pigment is dispersed is applied on the entire surface of the protective film 34 to a film thickness of, for example, 170 nm using a spin coater, a slit coater, or the like. To do. Next, exposure is performed by proximity exposure (proximity exposure) using a large mask so that negative photosensitive resin remains in stripes in a plurality of pixel regions adjacent in the vertical direction in FIG. Next, development is performed using an alkaline developer such as KOH to form a red resin CF layer 44R. As a result, a red spectral characteristic is imparted to the red pixel region, and a light shielding function for preventing external light from entering the TFT 20 in the red pixel region can be added.
[0068]
Similarly, an acrylic negative photosensitive resin in which a blue pigment is dispersed is applied and patterned to form a striped blue resin CF layer 44B in a pixel region adjacent to the red resin CF layer 44R. As a result, a blue spectral characteristic is imparted to the blue pixel region, and a light blocking function for preventing external light from entering the TFT 20 in the blue pixel region is added.
[0069]
Furthermore, an acrylic negative photosensitive resin in which a green pigment is dispersed is applied and patterned to form a striped green resin CF layer 44G in the pixel region adjacent to the red resin CF layer 44R and the blue resin CF layer 44B. To do. As a result, green spectral characteristics are imparted to the green pixel region, and a light blocking function for preventing external light from entering the TFT 20 in the green pixel region is added.
[0070]
Next, contact holes 24 are opened in the resin CF layers 44R, 44G, and 44B on the source electrode 22 of the TFT 20. Similarly, contact holes 26 are opened in the resin CF layers 44R, 44G, and 44B on the storage capacitor electrode 25.
[0071]
Next, an OC resin is applied to the entire surface of the resin CF layers 44R, 44G, and 44B by using a spin coater, a slit coater, or the like, and heat-treated at a temperature of 140 ° C. or lower to form the OC layer 36. As the OC resin, for example, an acrylic resin having negative photosensitivity is used. Next, proximity exposure is performed using a large mask, and development is performed using an alkali developer such as KOH to pattern the OC layer 36. In the patterned OC layer 36, the vicinity of the electrode connection region 38 and the substrate end side from the electrode connection region 38 are removed, and the surface of the protective film 34 is exposed. In the OC layer 36, contact holes 24 and 26 aligned with the contact holes 24 and 26 of the resin CF layers 44R, 44G, and 44B are formed.
[0072]
Subsequently, as shown in FIG. 12C, the protective film 34 and the insulating film 32 are removed by dry etching using a fluorine-based gas using the patterned OC layer 36 as a mask. By this etching, the protective film 34 and the insulating film 32 are removed in the electrode connection region 38 in the region where the gate terminal upper electrode 40 is formed, and the surface of the refractory metal layer 12b of the gate terminal lower electrode 30 is exposed. However, since the structure forming semiconductor film 54 is formed between the protective film 34 and the insulating film 32 on the outer peripheral portion outside the electrode connection region 38, the etching in the electrode connection region 38 is completed. At that time, the insulating film 32 'remains. That is, if the etching is completed when the etching end point in the electrode switching region 38 is detected, the insulating film 32 ′ whose surface is etched and the film thickness is reduced remains as the structure 39.
[0073]
Since the Ti (or Mo) layer 53a on the surface of the source electrode 22 and the storage capacitor electrode 25 exposed from the contact holes 24 and 26 has low resistance to fluorine-based gas, a part of the Ti (or Mo) layer is mainly Al. The layer 53b may be exposed. However, since the Ti (or Mo) layer 53a remains in the peripheral portions of the contact holes 24 and 26, the reliability of the subsequent connection with the pixel electrode 10 does not deteriorate.
[0074]
Subsequently, as shown in FIG. 12D, an ITO layer having a thickness of, for example, 70 nm, which is a transparent oxide conductive material, is formed on the entire surface of the substrate by a thin film forming method such as sputtering. Next, a resist mask having a predetermined pattern is formed, and wet etching using an oxalic acid-based etchant is performed using the resist as a mask. As a result, the gate terminal upper electrode 40 connected to the gate terminal lower electrode 30 in the electrode switching region 38 is formed. At the same time, in the display region, a pixel electrode 16 electrically connected to the source electrode 22 through the contact hole 24 and electrically connected to the storage capacitor electrode 25 through the contact hole 26 is formed for each pixel region. . Then, it heat-processes within the range of 150-230 degreeC, Preferably it is 200 degreeC.
[0075]
As described above, in this embodiment, a highly reliable liquid crystal display device can be realized without complicating the manufacturing process.
[0076]
FIG. 13 shows a modification of the configuration of the substrate for a liquid crystal display device according to the present embodiment. FIG. 13A shows a configuration in the vicinity of the electrode switching region of the gate terminal of the liquid crystal display device substrate according to this modification, and FIG. 13B shows a cross section taken along the line EE of FIG. Show. As shown in FIGS. 13A and 13B, the TFT substrate 2 extends in a strip shape in the vertical direction of FIG. 13A and is formed so as to cover the end surface of the gate terminal lower electrode 30 on the substrate end side. A structure 39 made of the insulating film 32 is provided. The structure 39 is formed by patterning after the insulating film 32 is formed on the entire surface of the substrate and before the a-Si layer 50 'is formed. A protrusion 42 formed in a triangular shape having a cross section parallel to the substrate surface and having an acute apex angle is provided at an almost central portion between the adjacent gate terminals 8 on the end surface on the substrate end side of the structure 39. It protrudes to the side. The protrusion 42 is provided in order to prevent the adjacent gate terminals 8 from being short-circuited due to etching residue when the gate terminal upper electrode 40 is patterned. The effect similar to the said embodiment can be acquired also by this modification.
[0077]
[Third Embodiment]
Next, a substrate for a liquid crystal display device and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 14A shows a configuration in which the vicinity of the electrode switching region of the gate terminal of the transmissive liquid crystal display device substrate according to the present embodiment is viewed in the direction perpendicular to the substrate surface, and FIG. The cross section cut | disconnected by the FF line | wire of a) is shown. As shown in FIGS. 14A and 14B, the gate terminal 8 is formed on the gate terminal lower electrode 30 (first terminal electrode) and the end surface of the gate terminal lower electrode 30 on the substrate end side. It has a structure 39, an electrode connection region 38 formed on the display region side from the structure 39, and a gate terminal upper electrode 40 (second terminal electrode).
[0078]
The gate terminal lower electrode 30 is formed by laminating an Al-based metal layer 12a and a refractory metal layer 12b, which are the same forming material as the gate bus line 12. An insulating film 32 is formed on the gate terminal lower electrode 30. The structure 39 covers the insulating film 32, the a-Si layer 50 ′, and n so as to cover the end surface of the gate terminal lower electrode 30 on the substrate end side. ⁺ The a-Si layer 51 and the metal layer 53, which is the same material as the drain bus line 14, are stacked in this order. The metal layer 53 is formed by stacking a Ti layer 53a, an Al layer 53b, and a Ti layer 53a. The structure 39 is formed in an island shape independently for each gate terminal 8. On the metal layer 53, the gate terminal upper electrode 40 is formed. The gate terminal upper electrode 40 is formed of, for example, an ITO layer, which is the same material as the pixel electrode 16.
[0079]
The gate terminal upper electrode 40 is connected to the gate terminal lower electrode 30 through an electrode connection region 38 in which the protective film 34 and the insulating film 32 on the gate terminal lower electrode 30 are opened. Here, in the regions α and β, the gate terminal upper electrode 40 is disconnected. However, a part of the structure 39 is formed of a metal layer 53 that is a conductor. For this reason, if the gate terminal upper electrodes 40 on both sides sandwiching the structure 39 are in contact with the metal layer 53, the substrate end side of the gate terminal upper electrode 40 and the electrode connection region 38 side through the metal layer 53. Is conducted.
[0080]
The insulating film 32, the protective film 34, and the OC layer 36 between the adjacent gate terminals 8 have end faces that substantially coincide with the end face of the gate terminal lower electrode 30 on the substrate end side (left side in FIGS. 14A and 14B). Have. That is, the surface of the glass substrate 6 is exposed between the adjacent gate terminals 8 on the substrate end side from the end surfaces of the insulating film 32, the protective film 34, and the OC layer 36. In addition, a protrusion formed in a triangular shape having an acute apex in a cross section parallel to the substrate surface at the substantially central portion between the adjacent gate terminals 8 on the end surfaces of the insulating film 32, the protective film 34, and the OC layer 36. 42 protrudes toward the end of the substrate. The protrusion 42 is provided in order to prevent the adjacent gate terminals 8 from being short-circuited due to etching residue when the gate terminal upper electrode 40 is patterned.
[0081]
According to the present embodiment, as in the first and second embodiments, the structure 39 is formed on the gate terminal lower electrode 30 on the substrate end side of the electrode connection region 38, so that the gate The ITO layer of the terminal upper electrode 40 and the Al-based metal layer 12a of the gate terminal lower electrode 30 are not in direct contact. For this reason, corrosion of a terminal part can be prevented and the disconnection resulting from corrosion can also be prevented.
[0082]
Further, in the present embodiment, the gate terminal upper electrode 40 is formed on the metal layer 53 or the glass substrate 6 with good adhesion, not on the OC layer 36. For this reason, peeling of the gate terminal upper electrode 40 can be prevented without using a new resin for the OC layer 36.
Further, in the present embodiment, the structure 39 is formed so as to cover the end face of the outer peripheral portion of the gate terminal lower electrode 30, so that the gate terminal upper electrode 40 is unlikely to be disconnected.
[0083]
Next, a method for manufacturing a substrate for a liquid crystal display device according to the present embodiment will be described with reference to FIGS. 3 and 4 and FIG. 15 and FIG. FIGS. 15A to 15E and FIGS. 16A to 16D are process cross-sectional views showing the manufacturing process of the TFT substrate, and show a cross section corresponding to FIG. 14B. First, as shown in FIG. 15 (a), directly on the glass substrate 6 which is a transparent insulating substrate, or if necessary, SiO. _X After forming a protective film such as, an Al alloy having a film thickness of 130 nm, a molybdenum nitride (MoN) film having a film thickness of 70 nm, and Mo film having a film thickness of 15 nm, for example, are formed on the entire surface in this order by sputtering. Thereby, a metal layer having a thickness of about 215 nm composed of the Al-based metal layer 12a and the refractory metal layer 12b is formed. As the Al alloy, a material obtained by adding one or more of Nd, Si, Cu, Ti, W, Ta, Sc and the like to Al can be used.
[0084]
Next, a resist is applied on the entire surface of the metal layer. Next, the resist is exposed and developed using a mask to form a resist pattern having a predetermined shape. Next, wet etching using a phosphoric acid-based etchant is performed. As a result, the gate terminal lower electrode 30 is formed, and the gate bus line 12 and the storage capacitor bus line 18 (both not shown in FIG. 15A) are formed.
[0085]
Next, as shown in FIG. 15B, for example, a SiN film having a thickness of 400 nm is formed on the entire surface of the substrate by plasma CVD, and an insulating film 32 is formed. Next, an a-Si layer 50 ′ having a film thickness of, for example, 30 nm for forming the active semiconductor layer 50 is formed on the entire surface of the substrate by plasma CVD. Further, for example, a 120 nm-thickness SiN film 23 ′ for forming the channel protective film 23 is formed on the entire surface of the substrate by plasma CVD.
[0086]
Next, a resist is applied to the entire surface of the SiN film 23 ′ by spin coating or the like. Next, back exposure is performed from the back side of glass substrate 6 (below in FIG. 15B) using a mask that shields the frame region where the gate terminal and drain terminal are formed, and using gate bus line 12 as a mask. . Subsequently, exposure is performed from the surface side of the glass substrate 6 (above in FIG. 15B) using another mask. Thereafter, development is performed, and the resist in the exposed area is dissolved and removed. As a result, a resist pattern (not shown) is formed in a self-aligning manner on the channel protection film 23 forming region on the gate bus line 12.
[0087]
Next, dry etching using a fluorine-based gas is performed using the obtained resist pattern as an etching mask. Thereby, as shown in FIG. 15C, a channel protective film 23 (not shown in FIG. 15C) is formed for each TFT 20, and the SiN film 23 ′ in the vicinity of the gate terminal lower electrode 30 is removed. .
[0088]
Next, as shown in FIG. 15D, the surface of the a-Si layer 50 ′ is washed (removal of a natural oxide film) using dilute hydrofluoric acid, and then quickly, for example, n having a film thickness of 30 nm. ⁺ An a-Si layer 51 is formed on the entire surface by plasma CVD. Next, for example, a metal layer 53 made of a laminate of a Ti layer 53a, an Al layer 53b, and a Ti layer 53a for forming the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the drain bus line 14 is sputtered by sputtering. The film is formed to a thickness of / 40 nm. As the metal layer 53, in addition to the composite film such as Ti / Al / Ti, for example, a simple substance such as Cr, Mo, Ta, Ti or Al, or a composite film thereof can be used.
[0089]
Next, a resist is applied on the entire surface of the metal layer 53. Next, the resist is exposed and developed using a mask to form a resist pattern having a predetermined shape. Next, as shown in FIG. 15E, dry etching using a chlorine-based gas is performed using the resist pattern as an etching mask. Thus, the drain bus line 14, the drain electrode 21, the source electrode 22, the storage capacitor electrode 25, and the operating semiconductor layer 50 (all not shown in FIG. 15E) are formed. At the same time, the structure 39 is formed so as to cover the end surface of the gate terminal lower electrode 30 on the substrate end side. In this etching process, the channel protective film 23 formed for each TFT 20 functions as an etching stopper, and the underlying a-Si layer 50 ′ remains without being etched.
[0090]
Next, as shown in FIG. 16A, for example, a 300 nm-thickness SiN film is formed on the entire surface of the substrate by plasma CVD to form a protective film 34.
[0091]
Next, as shown in FIG. 16B, a photosensitive insulating organic resin is applied to the entire surface of the protective film 34 using a spin coater, a slit coater, or the like, and heat treatment is performed at a temperature of 140 ° C. or lower. Do. As the insulating organic resin, for example, an acrylic resin having negative photosensitivity is used. Thereby, the OC layer 36 is formed. Next, proximity exposure is performed using a large mask, and development is performed using an alkali developer such as KOH, and the OC layer 36 is patterned. In the patterned OC layer 36, the vicinity of the electrode connection region 38 and the substrate end side from the electrode connection region 38 are removed, and the surface of the protective film 34 is exposed. The OC layer 36 is opened on the contact hole 24 and 26 (both not shown in FIG. 16B) formation region.
[0092]
Subsequently, as shown in FIG. 16C, the protective film 34 and the insulating film 32 are removed by dry etching using a fluorine-based gas using the patterned OC layer 36 as a mask. By this etching, the protective film 34 and the insulating film 32 are removed in the electrode connection region 38 in the region where the gate terminal upper electrode 40 is formed, and the surface of the refractory metal layer 12b of the gate terminal lower electrode 30 is exposed. However, since the upper layer of the structure 39 on the end surface of the gate terminal lower electrode 30 on the substrate end side is formed of the metal layer 53, the lower insulating film 32 is not etched.
[0093]
In this example, the protective film 34 is patterned using the patterned OC layer 36 as an etching mask. However, the OC layer 36 may be formed after the protective film 34 is patterned.
[0094]
Since the Ti (or Mo) layer 53a on the surface of the source electrode 22 and the storage capacitor electrode 25 exposed from the contact holes 24 and 26 has low resistance to fluorine-based gas, a part of the Ti (or Mo) layer is mainly Al. The layer 53b may be exposed. However, since the Ti (or Mo) layer 53a remains in the peripheral portions of the contact holes 24 and 26, the reliability of the subsequent connection with the pixel electrode 10 does not deteriorate.
[0095]
Subsequently, as shown in FIG. 16D, an ITO layer having a thickness of, for example, 70 nm, which is a transparent oxide conductive material, is formed on the entire surface of the substrate by a thin film forming method such as sputtering. Next, a resist mask having a predetermined pattern is formed, and wet etching using an oxalic acid-based etchant is performed using the resist as a mask. As a result, the gate terminal upper electrode 40 connected to the gate terminal lower electrode 30 in the electrode switching region 38 is formed. At the same time, in the display region, a pixel electrode 16 electrically connected to the source electrode 22 through the contact hole 24 and electrically connected to the storage capacitor electrode 25 through the contact hole 26 is formed for each pixel region. . Then, it heat-processes within the range of 150-230 degreeC, Preferably it is 200 degreeC.
[0096]
As described above, in this embodiment, a highly reliable liquid crystal display device can be realized without complicating the manufacturing process.
[0097]
FIG. 17 shows a modification of the configuration of the substrate for a liquid crystal display device according to this embodiment. FIG. 17A shows a configuration in the vicinity of the electrode switching region of the gate terminal of the liquid crystal display device substrate according to this modification, and FIG. 17B shows a cross section taken along the line GG in FIG. Show. As shown in FIGS. 17A and 17B, the TFT substrate 2 has a structure 39 formed around the electrode connection region 38. The structure 39 includes an insulating film 32, an a-Si layer 50 ', n, so as to cover the end face of the gate terminal lower electrode 30. ⁺ The a-Si layer 51 and the metal layer 53, which is the same material as the drain bus line 14, are stacked in this order. A protrusion 42 formed in a triangular shape having a cross section parallel to the substrate surface having an acute apex angle at an almost central portion between the adjacent gate terminals 8 on the end surface of the protective film 34 and the OC layer 36 on the substrate end side. Is formed so as to protrude toward the end portion of the substrate. The protrusion 42 is provided in order to prevent the adjacent gate terminals 8 from being short-circuited due to etching residue when the gate terminal upper electrode 40 is patterned. The effect similar to the said embodiment can be acquired also by this modification.
[0098]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, transmissive and reflective liquid crystal display devices have been described as examples. However, the present invention is not limited to this and can be applied to a transflective liquid crystal display device.
[0099]
The substrate for a liquid crystal display device according to the embodiment described above, a method for manufacturing the same, and a liquid crystal display device including the substrate are summarized as follows.
(Appendix 1)
A plurality of bus lines formed crossing each other via an insulating film on the substrate;
An insulating resin layer formed on the bus line;
A pixel electrode formed on the insulating resin layer for each pixel region arranged in a matrix on the substrate;
A thin film transistor connected to the pixel electrode and the bus line;
A first terminal electrode electrically connected to the bus line; a structure formed of a forming material different from the insulating resin layer on at least a part of the outer periphery of the first terminal electrode; and the pixel A second terminal electrode formed on the first terminal electrode and the structure with the same material as the electrode, and an electrode switching region for connecting the first and second terminal electrodes; An external connection terminal for electrically connecting an external circuit and the bus line;
A substrate for a liquid crystal display device, comprising:
[0100]
(Appendix 2)
In the substrate for a liquid crystal display device according to appendix 1,
The structure is formed independently for each external connection terminal.
A substrate for a liquid crystal display device.
[0101]
(Appendix 3)
In the substrate for a liquid crystal display device according to appendix 1,
The structure is formed across a plurality of the external connection terminals.
A substrate for a liquid crystal display device.
[0102]
(Appendix 4)
In the substrate for liquid crystal display device according to appendix 3,
The structure has a protrusion between the external connection terminals.
A substrate for a liquid crystal display device.
[0103]
(Appendix 5)
The substrate for a liquid crystal display device according to any one of appendices 1 to 4,
The structure is made of the same material as the insulating film.
A substrate for a liquid crystal display device.
[0104]
(Appendix 6)
In the substrate for a liquid crystal display device according to appendix 5,
The structure is thinner than the insulating film
A substrate for a liquid crystal display device.
[0105]
(Appendix 7)
The substrate for a liquid crystal display device according to any one of appendices 1 to 4,
The structure is formed of the same material as the source / drain electrodes, the operating semiconductor layer, and the insulating film of the thin film transistor.
A substrate for a liquid crystal display device.
[0106]
(Appendix 8)
The substrate for a liquid crystal display device according to any one of appendices 1 to 7,
The insulating resin layer is an overcoat layer
A substrate for a liquid crystal display device.
[0107]
(Appendix 9)
The substrate for a liquid crystal display device according to any one of appendices 1 to 7,
The insulating resin layer is a resin color filter layer
A substrate for a liquid crystal display device.
[0108]
(Appendix 10)
In a liquid crystal display device comprising a pair of substrates arranged opposite to each other and a liquid crystal sealed between the pair of substrates,
The substrate for a liquid crystal display device according to any one of appendices 1 to 9 is used for one of the pair of substrates.
A liquid crystal display device.
[0109]
(Appendix 11)
At the same time as forming the gate electrode of the thin film transistor, the first terminal electrode of the external connection terminal for connecting the external circuit and the bus line is formed on the substrate,
Forming an insulating film on the first terminal electrode;
At the same time as forming the thin film transistor channel protective film on the insulating film, forming a structure forming protective film on the outer periphery of the first terminal electrode,
Etching the insulating film on the first terminal electrode to form an electrode connection region in which the surface of the first terminal electrode is exposed; and the protective film for forming a structure on the first terminal electrode; Etching the insulating film surface, forming a structure made of the same material as the insulating film on the outer periphery of the first terminal electrode,
Forming a second terminal electrode of the external connection terminal on the structure simultaneously with forming a pixel electrode;
A method for manufacturing a substrate for a liquid crystal display device.
[0110]
(Appendix 12)
At the same time as forming the gate electrode of the thin film transistor, the first terminal electrode of the external connection terminal for connecting the external circuit and the bus line is formed on the substrate,
Forming an insulating film on the first terminal electrode;
Forming an operating semiconductor layer of the thin film transistor on the insulating film and forming a semiconductor film for forming a structure on the outer periphery of the first terminal electrode;
Etching the insulating film on the first terminal electrode to form an electrode connection region where the surface of the first terminal electrode is exposed; and the structure-forming semiconductor film on the first terminal electrode; Etching the insulating film surface, forming a structure made of the same material as the insulating film on the outer periphery of the first terminal electrode,
Forming a second terminal electrode of the external connection terminal on the structure simultaneously with forming a pixel electrode;
A method for manufacturing a substrate for a liquid crystal display device.
[0111]
(Appendix 13)
At the same time as forming the gate electrode of the thin film transistor, the first terminal electrode of the external connection terminal for connecting the external circuit and the bus line is formed on the substrate,
Forming an insulating film on the first terminal electrode;
Forming a structure on the outer periphery of the first terminal electrode simultaneously with forming the source / drain electrodes of the thin film transistor;
Etching the insulating film on the first terminal electrode using the structure as a mask to form an electrode connection region where the surface of the first terminal electrode is exposed;
Forming a second terminal electrode of the external connection terminal on the structure simultaneously with forming a pixel electrode;
A method for manufacturing a substrate for a liquid crystal display device.
[0112]
(Appendix 14)
In the method for manufacturing a substrate for a liquid crystal display device according to appendices 11 to 13,
Further comprising forming an insulating resin layer on the thin film transistor;
The step of etching the insulating film uses the insulating resin layer as a mask.
A method for manufacturing a substrate for a liquid crystal display device.
[0113]
【The invention's effect】
As described above, according to the present invention, a manufacturing process can be simplified and a liquid crystal display device having high reliability can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a diagram schematically showing an equivalent circuit of the substrate for a liquid crystal display device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of one pixel of the substrate for a liquid crystal display device according to the first embodiment of the present invention.
4 is a cross-sectional view showing a configuration of a substrate for a liquid crystal display device taken along line AA in FIG. 3;
FIG. 5 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a substrate for a liquid crystal display device according to the first embodiment of the present invention.
FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the substrate for a liquid crystal display device according to the first embodiment of the present invention.
FIG. 7 is a process cross-sectional view illustrating the method for manufacturing the substrate for a liquid crystal display device according to the first embodiment of the present invention.
FIG. 8 is a diagram showing a configuration of one pixel of a substrate for a liquid crystal display device according to a second embodiment of the present invention.
9 is a cross-sectional view showing a configuration of a substrate for a liquid crystal display device taken along line CC in FIG.
FIG. 10 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a substrate for a liquid crystal display device according to a second embodiment of the present invention.
FIG. 11 is a process cross-sectional view illustrating a method for manufacturing a substrate for a liquid crystal display device according to a second embodiment of the present invention.
FIG. 12 is a process cross-sectional view illustrating the method for manufacturing the substrate for a liquid crystal display device according to the second embodiment of the present invention.
FIG. 13 is a diagram showing a modification of the configuration in the vicinity of the electrode switching region of the gate terminal of the substrate for a liquid crystal display device according to the second embodiment of the present invention.
FIG. 14 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a substrate for a liquid crystal display device according to a third embodiment of the present invention.
FIG. 15 is a process cross-sectional view illustrating the method for manufacturing the substrate for liquid crystal display device according to the third embodiment of the present invention;
FIG. 16 is a process cross-sectional view illustrating a method for manufacturing a substrate for a liquid crystal display device according to a third embodiment of the present invention.
FIG. 17 is a diagram showing a modification of the configuration in the vicinity of the electrode switching region of the gate terminal of the liquid crystal display substrate according to the third embodiment of the present invention.
FIG. 18 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a conventional liquid crystal display device substrate.
FIG. 19 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a conventional liquid crystal display device substrate.
FIG. 20 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a conventional liquid crystal display device substrate.
FIG. 21 is a diagram showing a configuration in the vicinity of an electrode switching region of a gate terminal of a conventional liquid crystal display device substrate.
[Explanation of symbols]
2 TFT substrate
4 Counter substrate
6 Glass substrate
8 Gate terminal
12 Gate bus line
12a Al-based metal layer
12b refractory metal layer
14 Drain bus line
16 pixel electrode
16a ITO layer
16b Ag alloy layer
18 Storage capacity bus line
20 TFT
21 Drain electrode
22 Source electrode
23 Channel protective film
24, 26 Contact hole
25 Storage capacitor electrode
30 Gate terminal lower electrode
32 Insulating film
34 Protective film
36 OC layer
38 Electrode changing area
39 Structure
40 Gate terminal upper electrode
42 Protrusions
44 Resin CF layer
50 Operating semiconductor layers
50 'a-Si layer
51 n ⁺ a-Si layer
52 Protective film for structure formation
53 Metal layer
53a Ti layer
53b Al layer
54 Semiconductor film for forming structure
80 Gate bus line drive circuit
82 Drain bus line drive circuit
84 Control circuit
86, 87 Polarizing plate
88 Backlight unit

Claims (5)

A plurality of bus lines formed crossing each other via an insulating film on the substrate;
An insulating resin layer formed on the bus line;
A pixel electrode formed on the insulating resin layer for each pixel region arranged in a matrix on the substrate;
A thin film transistor connected to the pixel electrode and the bus line;
A first terminal electrode electrically connected to the bus line, and a forming material different from the insulating resin layer on at least a part of the outer peripheral portion of the first terminal electrode and the same forming material as the insulating film A structure having a thickness smaller than that of the insulating film, a second terminal electrode formed on the first terminal electrode and the structure with the same forming material as the pixel electrode, An electrode connection region for connecting the first and second terminal electrodes, and an external connection terminal for electrically connecting an external circuit and the bus line ,
The substrate for a liquid crystal display device , wherein the external connection terminal includes the first terminal electrode, the structure, the second terminal electrode, and the electrode switching region . The substrate for a liquid crystal display device according to claim 1,
The substrate for a liquid crystal display device, wherein the structure is formed independently for each external connection terminal. In a liquid crystal display device comprising a pair of substrates arranged opposite to each other and a liquid crystal sealed between the pair of substrates,
While the of the pair of substrates, a liquid crystal display device characterized by being used is a liquid crystal display device substrate according to claim 1 or 2. At the same time as forming the gate electrode of the thin film transistor, the first terminal electrode of the external connection terminal for connecting the external circuit and the bus line is formed on the substrate,
Forming an insulating film on the first terminal electrode;
At the same time as forming the thin film transistor channel protective film on the insulating film, forming a structure forming protective film on the outer periphery of the first terminal electrode,
Forming an insulating resin layer on the thin film transistor;
Etching the insulating film on the first terminal electrode to form an electrode connection region in which the surface of the first terminal electrode is exposed; and the protective film for forming a structure on the first terminal electrode; Etching the insulating film surface, forming a structure made of the same material as the insulating film on the outer periphery of the first terminal electrode,
A method of manufacturing a substrate for a liquid crystal display device, wherein a second terminal electrode of the external connection terminal is formed on the structure simultaneously with forming a pixel electrode on the insulating resin layer . At the same time as forming the gate electrode of the thin film transistor, the first terminal electrode of the external connection terminal for connecting the external circuit and the bus line is formed on the substrate,
Forming an insulating film on the first terminal electrode;
Forming an operating semiconductor layer of the thin film transistor on the insulating film and forming a semiconductor film for forming a structure on the outer periphery of the first terminal electrode;
Forming an insulating resin layer on the thin film transistor;
Etching the insulating film on the first terminal electrode to form an electrode connection region where the surface of the first terminal electrode is exposed; and the structure-forming semiconductor film on the first terminal electrode; the insulating film surface is etched, the insulating film thickness than the same Do Ri and the insulating film from the forming material and form a thin structure on the outer peripheral portion of the first terminal electrodes,
A method of manufacturing a substrate for a liquid crystal display device, wherein a second terminal electrode of the external connection terminal is formed on the structure simultaneously with forming a pixel electrode on the insulating resin layer .

Images