JP4863667B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device having a switching element for each picture element.

With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, etc., television images and various image display devices have already been provided in large quantities on a commercial basis in a 5-75 cm diagonal liquid crystal display device. In addition, color display can be easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, a so-called active liquid crystal panel in which a switching element is built in for each picture element has been guaranteed from the beginning of commercialization of an image having little crosstalk, high response speed, and high contrast ratio.

These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 300 to 1600 signal lines, but recently, a large screen is required to cope with an increase in display capacity. And high definition are progressing simultaneously.

FIG. 8 shows a state of mounting on a liquid crystal panel, and a semiconductor integrated circuit chip for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, the electrode terminals 5 of the scanning lines formed on the glass substrate 2. A COG (Chip-On-Glass) system in which 3 is connected using a conductive adhesive, or a TCP film 4 having a terminal of gold foil or solder-plated copper foil based on a polyimide resin thin film, for example, as a signal line An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) method in which the electrode terminal 6 is fixed by being pressed with an appropriate adhesive containing a conductive medium. Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.

Wiring paths for connecting the pixels in the image display unit located almost at the center of the liquid crystal panel 1 and the electrode terminals 5 and 6 of the scanning lines and the signal lines are 7 and 8, which are not necessarily the same as the electrode terminals 5 and 6. It is not necessary to be made of a conductive material. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

FIG. 9 shows an equivalent circuit diagram of an active liquid crystal display device in which an insulated gate transistor 10 is arranged for each picture element as a switching element, 11 (7 in FIG. 8) is a scanning line, and 12 (8 in FIG. 8) is a signal. A line 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. Elements drawn with solid lines are formed on one glass substrate 2 constituting a liquid crystal panel, and the counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is the main electrode facing the other glass substrate 9. It is formed on the surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load is provided. A circuit device such as addition to the liquid crystal cell 13 in parallel is added. Reference numeral 16 denotes a storage capacitor line or a common electrode serving as a common bus for the storage capacitor 15.

FIG. 10 is a cross-sectional view of the main part of the image display unit of the liquid crystal display device. The two glass substrates 2 and 9 constituting the liquid crystal panel 1 are columnar spacers formed on resinous fibers, beads or color filters 9. Are formed at a predetermined distance of about several μm by a spacer material (not shown) such as a sealing material made of an organic resin and a sealing material (both shown in the figure) at the peripheral edge of the glass substrate 9. The liquid crystal 17 is filled in this closed space.

In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is also called a color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use a TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.

The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the source electrode 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. This is a light shielding member for fixing a black matrix (Black Matrix abbreviated as BM).

The active substrate (glass substrate) 2 on which the scanning line, the signal line, the insulated gate transistor as the switching element, and the pixel electrode are formed is produced by a plurality of times of photolithography using a photomask like a semiconductor integrated circuit. The (photo-etching) process is essential. Although detailed details are omitted, as a result of rationalizing the process of islanding the semiconductor layer and reducing the process of forming the contact to the scanning line, the photomask that originally required about 7 to 8 was also introduced by dry etching technology. At present, the number is reduced to five, which greatly contributes to the reduction of process costs. It is a well-known development target that it is effective to reduce the process cost in the manufacturing process of the active substrate and to reduce the material cost in the panel assembly process and module mounting process in order to reduce the production cost of the liquid crystal display device. Obviously, reducing the number of manufacturing processes including the engraving process greatly contributes to improving the productivity and cost reduction of the liquid crystal display device.

As described above, a manufacturing method that requires five photolithography steps in the production of the active substrate 2 is common, and some of the previous examples that have been proposed for further reduction in manufacturing cost have already been made. A four-mask process, which is mass-produced and disclosed in Japanese Patent Application Laid-Open No. 2002-206571 of Patent Document 1, will be introduced as a conventional example. As described below, this four-mask process is a process reduction technique or rationalization technique in which a semiconductor layer including a channel is formed into an island and a source / drain wiring process with a single photomask using a halftone exposure technique. It is. FIG. 11 is a plan view of a unit picture element of an active substrate corresponding to a four-mask process. AA ′ (insulated gate transistor region) and BB ′ (scan line electrode terminals) in FIG. Area) and CC ′ line (signal line electrode terminal area) are shown in FIG. At present, two types of insulated gate transistors are widely used, but here, channel-etched insulated gate transistors are employed.

First, as shown in FIGS. 11 (a) and 12 (a), a glass substrate 2 having a thickness of about 0.5 to 1.1 mm as an insulating substrate having high heat resistance, chemical resistance and transparency, for example, Corning A first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of a product name 1737 manufactured by using a vacuum film forming apparatus such as SPT (sputtering), and gates are formed by a fine processing technique. The scanning lines 11 and the storage capacitor lines 16 that also serve as the electrodes 11A are selectively formed. The material of the scanning line is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity, but in general heat resistant metal thin film layers such as Cr and Ta or heat resistance such as MoW alloy A highly alloy thin film layer is used.

It is reasonable to use AL (aluminum) as the scanning line material to reduce the resistance value of the scanning line in response to the increase in the screen size and resolution of the liquid crystal panel. Since it is low, a structure in which it is laminated with Cr, Ta, Mo or silicide thereof, which are the above-mentioned refractory metals, is now common. That is, the scanning line 11 is composed of one or more metal layers.

Next, a first silicon nitride (SiNx) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma sieve) device, and the first silicon nitride (SiNx) layer 30 containing almost no impurities is used as a channel of an insulated gate transistor. An amorphous silicon (a-Si) layer 31, a second amorphous silicon layer (n + a-Si) 33 containing phosphorus as an impurity and serving as a source / drain of an insulated gate transistor, and three kinds of thin film layers, For example, the film is sequentially deposited with a film thickness of about 0.3-0.2-0.05 μm. Subsequently, as shown in FIGS. 11B and 12B, for example, a Ti thin film layer 34 having a thickness of about 0.1 μm as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. An AL thin film layer 35 as a low resistance metal layer of about 3 μm and a Ti thin film layer 36 as an intermediate conductive layer of a thickness of about 0.1 μm, that is, a source / drain wiring material are sequentially deposited.

Then, the signal line 12 which is formed by stacking the heat-resistant metal layer 34A, the low-resistance metal layer 35A and the intermediate conductive layer 36A so as to partially overlap the gate electrode 11A by microfabrication technology and also serves as the source electrode of the insulated gate transistor, A drain electrode 21 of an insulated gate transistor comprising a stacked layer of a refractory metal layer 34B, a low resistance metal layer 35B and an intermediate conductive layer 36B is selectively formed so as to partially overlap with the electrode 11A. When forming, the film thickness of the source / drain channel formation region 80B (shaded portion) is 1.5 μm, for example, as shown in FIGS. 11 (c) and 12 (c) by the halftone exposure technique. The photosensitive resin patterns 80A and 80B are formed so that the film thickness of the formation regions 80A (12) and 80A (21) is 3 μm. This is a major feature of the streamlined four-mask process.

Since the active substrate 2 is usually made of a positive photosensitive resin, the photosensitive resin patterns 80A and 80B have the source / drain wiring formation region 80A black, that is, a Cr thin film is formed. The formation region 80B is gray (halftone) and is formed with a line-and-space Cr pattern having a width of, for example, about 0.5 to 1.5 μm so as to reduce light passing through the photomask, and the other regions are white, that is, Cr A photomask from which the thin film has been removed may be used. In the gray area, the line-and-space is not resolved because the resolving power of the exposure machine is insufficient, and about half of the photomask irradiation light from the lamp light source can be transmitted. Photosensitive resin patterns 80A and 80B having a concave cross-sectional shape as shown in FIG. 12C can be obtained according to the residual film characteristics of the resin. The gray region may be formed of a metal layer having a different film thickness or transmittance, for example, a MoSi2 thin film, instead of a slit.

Ti thin film layer 36, AL thin film layer 35, Ti thin film layer 34, and second amorphous silicon layer as shown in FIGS. 11C and 12C using photosensitive resin patterns 80A and 80B as a mask. 33 and the first amorphous silicon layer 31 are sequentially etched to expose the gate insulating layer 30, and then the photosensitive resin patterns 80A and 80B are reduced by 1.5 μm or more by ashing means such as oxygen plasma. The photosensitive resin pattern 80B disappears, the Ti thin film layer 36A (not shown) in the channel formation region is exposed, and the photosensitive resin patterns 80C (12) and 80C (21) are reduced only in the source / drain wiring formation region. ) Can be left.

Therefore, as shown in FIGS. 11D and 12D, the photosensitive resin patterns 80C (12) and 80C (21) whose thickness is reduced are used as a mask, and Ti between the source and drain wirings (channel formation region) is again formed. The thin film layer, the AL thin film layer, the Ti thin film layer, the second amorphous silicon layer 33A, and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is 0.05 to Etch leaving about 0.1 μm. At this time, the source 33S and the drain 33D made of the second amorphous silicon layer are separated. Since the source / drain wirings 12 and 21 are formed by etching the metal layer and then leaving the first amorphous silicon layer 31A about 0.05 to 0.1 .mu.m in length, such a manufacturing method is used. The resulting insulated gate transistor is called channel etch. In the oxygen plasma treatment, the photosensitive resin pattern 80A is converted into a photosensitive resin pattern 80C having a reduced film thickness. Therefore, it is desirable to increase the anisotropy in order to suppress a change in pattern dimension. Specifically, RIE (Reactive Ion) Etching method, ICP (Inductively Coupled Plasma) method having a high density plasma source and TCP (Transfer Coupled Plasma) method oxygen plasma treatment are more desirable.

Further, after removing the photosensitive resin patterns 80C (12) and 80C (21), a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer. As the passivation insulating layer 37, as shown in FIGS. 11 (e) and 12 (e), an area where the electrode terminals of the scanning line 11 and the signal line 12 are formed on the drain electrode 21 and outside the image display section. The openings 62, 63, 64 are respectively formed in the opening 63, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed, and a part 5 of the scanning line is exposed in the opening 63. , 64 is removed to expose part of the drain electrode 21 and part 6 of the signal line. Similarly, an opening 65 is formed on the storage capacitor line 16 to expose a part of the storage capacitor line 16.

Finally, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) or a mixed crystal thereof is formed as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIG. 11 (f) and FIG. 12 (f), the transparent conductive pixel electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by a fine processing technique as shown in FIGS. Thus, the active substrate 2 is completed. As shown in FIGS. 11 (e) and 12 (e), the transparent conductive picture element electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by the microfabrication technique to form the active substrate 2. To be completed. Regarding the configuration of the storage capacitor 15, as shown in FIGS. 11 (e) and 12 (e), the drain electrode 21 and the storage capacitor line 16 include the gate insulating layer 30, the first amorphous silicon layer 31A, and the first storage layer 15A. The example (lower right slanting line part 50) comprised by overlapping two planes through the amorphous silicon layer 33D is illustrated. As for the electrode terminals, transparent conductive electrode terminals 5A and 6A are selectively formed on the passivation insulating layer 37 including the openings 63 and 64.

As described above, when AL is used for the source / drain wirings 12 and 21, the refractory metal layer 34 is necessary to ensure electrical connection with the second amorphous silicon 33, and An intermediate conductive layer 36 is required between the transparent conductive layer and the transparent conductive layer in order to avoid a battery effect in an alkaline solution. As a result, the source / drain wiring must be composed of three layers. It is difficult to avoid the use of a low-resistance metal layer in a large-screen or high-definition liquid crystal panel where the resistance value of the drain wiring becomes severe. Further, when Ti is used for the refractory metal layer 34 and the intermediate conductive layer 36, a dry etching process using a chlorine-based gas is necessary for the etching, and the chlorine-based gas is automatically used for the AL etching. As a result, the burden on the production equipment as well as on the material side increases. When Mo is used for the refractory metal layer 34 and the intermediate conductive layer 36 instead of Ti, a three-layer structure of Mo / AL / Mo can be performed by a single chemical treatment with a phosphoric acid solution to which an appropriate amount of nitric acid is added. It is possible to reduce the investment burden of production equipment, but it is not necessary to explain that simplification of source / drain wiring is effective in reducing production costs.

As described above, in the four-mask process, the contact electrode forming step for the drain electrode 21 and the scanning line 11 is performed at the same time. Therefore, the thicknesses and types of the insulating layers in the openings 62 and 63 corresponding thereto are different. The passivation insulating layer 37 has a lower film forming temperature and inferior film quality as compared with the gate insulating layer 30, and the etching speed with a hydrofluoric acid-based etching solution is several thousand liters / minute and several hundreds liters / minute, respectively. In contrast, the cross-sectional shape of the opening 62 on the drain electrode 21 employs dry etching using a fluorine-based gas for the reason that too much etching occurs at the upper portion and the hole diameter cannot be controlled.

However, even if dry etching is employed, since the opening 62 on the drain electrode 21 is only the passivation insulating layer 37, overetching is unavoidable as compared with the opening 63 on the scanning line 11, depending on the material. In some cases, the drain electrode 21 (intermediate conductive layer 36B) may be reduced in thickness by the etching gas. In removing the photosensitive resin pattern after the etching, the surface of the photosensitive resin pattern is first shaved by about 0.1 to 0.3 μm by oxygen plasma ashing to remove the polymer on the fluorinated surface. In general, chemical treatment using an organic stripping solution, for example, a stripping solution 106 manufactured by Tokyo Ohka Co., Ltd. is performed, but the intermediate conductive layer 36B is reduced in thickness and the underlying aluminum layer 35B is exposed. In this case, it is not rare that AL2O3, which is an insulator, is formed on the surface of the aluminum layer 35B by the oxygen plasma ashing process, and ohmic contact between the drain electrode 36B and the pixel electrode 22 cannot be obtained.

In order to avoid this problem, the thickness of the intermediate conductive layer 36B is set to, for example, 0.2 μm so that the thickness of the intermediate conductive layer 36B may be reduced. Alternatively, when forming the openings 62 to 65, it is possible to avoid the formation of the pixel electrode 22 after removing the aluminum layer 35B and exposing the Ti thin film layer 34B, which is the underlying heat-resistant metal layer. There is also an advantage that the intermediate conductive layer 36 is unnecessary from the beginning.

However, if the in-plane uniformity of the film thickness of these thin films is not good in the former measure, this approach does not necessarily work effectively, and the same is true even when the in-plane uniformity of the etching speed is not good. . The latter measure eliminates the need for the intermediate conductive layer 36B, but the number of steps for removing the aluminum layer 35B increases, and if the cross section control of the opening 62 is insufficient, the pixel electrode 22 may be disconnected. .

In addition, the channel formation process applied in the four-mask process removes the source / drain wiring material between the source / drain wirings 12 and 21 and the semiconductor layer containing impurities at the same time, so that the ON characteristics of the insulated gate transistor are greatly increased. This is a step of determining the length of the channel that is affected (4 to 6 μm in the current mass-produced product). Since the fluctuation of the channel length greatly changes the ON current value of the insulated gate transistor, usually strict manufacturing control is required. However, the channel length, that is, the pattern size of the halftone exposure region, depends on the exposure amount (light source intensity and phosphor mask). Pattern accuracy (especially line & space dimensions), photosensitive resin coating thickness, photosensitive resin phenomenon processing conditions, and the amount of photosensitive resin film reduction in the etching process, etc. Combined with the in-plane uniformity of various quantities, it is not always possible to produce a product with high yield and stability. It requires more stringent manufacturing control than conventional manufacturing control, and it cannot be said that it is at a highly completed level. Is the current situation. In particular, when the channel length is 6 μm or less, the influence of the pattern dimension generated as the film thickness decreases of the photosensitive resin patterns 80A (12) and 80A (21) is large, and this tendency becomes remarkable.

Although it is relatively easy to increase the size of the photomask in advance and avoid the thinning of the pattern size that occurs as the film thickness of the photosensitive resin pattern decreases, the photosensitive resin pattern 80C that is the channel region is relatively easy. Since the gap between (12) and 80C (21) cannot be made thinner than the resolving power of the exposure machine (minimum of about 3 μm), the channel length is eventually twice the amount of film loss in the lateral direction of the photosensitive resin pattern. It is considered that this is one of the reasons that the introduction of the four-mask process is delayed in a production line with an existing glass substrate size of 1 m or more.

The present invention has been made in view of the current situation, and not only does not require strict pattern accuracy management, but also simplifies the configuration of the signal line 12 and promotes the reduction of the manufacturing process by rationalizing the pixel electrode formation process. It is.
JP 2002-206571 A Japanese Patent Application No. 2005-88866

In the opening forming step for connecting the pixel electrode to the drain electrode, the present invention exposes the glass substrate by removing the insulating layer in the pixel electrode formation region, and includes the exposed drain electrode on the glass substrate. The production process can be reduced by forming the pixel electrodes by lift-off. In order to facilitate the formation of the picture element electrode by lift-off, the photosensitive resin pattern whose cross-sectional shape is a reverse taper is used in the step of removing the insulating layer, and the picture element electrode is not disconnected from the drain electrode. In order to obtain a good electrical connection, a step of removing the lower resistance metal layer on the upper part of the drain electrode made of a laminate of the low resistance metal layer and the refractory metal layer and exposing the lower heat resistance metal layer is added. This is an important point of focus of the present invention.

In addition, the side etching using the above photosensitive resin pattern, or the halftone exposure technology is added to the formation of the above photosensitive resin pattern, thereby reducing the photolithography process for selective patterning of the semiconductor layer. In combination with this technology, the process can be reduced with a content different from that disclosed in Patent Document 2, and an active substrate can be manufactured using three photomasks.

In the liquid crystal display device according to claim 1, the insulated gate transistor that is a switching element is a channel etch type,
A scanning line having a part thereof as a gate electrode is formed on one main surface of the first transparent insulating substrate,
A stack of a low-resistance metal layer and a heat-resistant metal layer that can be removed by an etching gas of the gate insulating layer through a gate insulating layer and a first semiconductor layer that does not contain impurities, part of which is a channel Source / drain wiring consisting of
The drain wiring is orthogonal to the scanning line,
A passivation insulating layer for protecting the insulated gate transistor is provided in the uppermost layer,
In the image display unit, a pixel electrode forming region including the end of one drain wiring, a pseudo pixel electrode forming region including the end of the other drain wiring, and a part of the scanning line in the region outside the image displaying unit. electrode terminal formation region of the scanning lines, including, and Oite the electrode terminal formation region of the signal lines including a portion of the signal line, the passivation insulating layer and said first semiconductor layer and said gate insulating layer through openings Of the drain wiring and the first transparent insulating substrate each made of the heat-resistant metal layer, the end of the other drain wiring and the first transparent insulating substrate, and a part of the scanning line. And a part of the signal line made of the refractory metal layer is exposed,
The first semiconductor layer in the channel region between the source / drain wirings is formed to be narrower than the gate electrode,
It is made of the same conductive thin film and includes a pixel electrode in the pixel electrode formation region including the end of the one drain wiring and a pseudo picture in the pseudo pixel electrode formation region including the end of the other drain wiring. An electrode terminal of the scanning line in the electrode terminal forming region of the scanning line including a part of the scanning line, and an electrode terminal of the signal line in the electrode terminal forming region of the signal line including a part of the signal line Is formed.

This configuration ensures electrical connection between part of the drain electrode made of the refractory metal layer and the pixel electrode, part of the signal line also made of the refractory metal layer, and the electrode terminal of the signal line. However, a two-layer structure of a low-resistance metal layer and a heat-resistant metal layer is sufficient, and the signal line structure is simplified. The active substrate is protected by a passivation insulating layer. Further, the first amorphous silicon layer which forms the channel of the insulated gate transistor and does not contain impurities on the gate electrode which is a part of the scanning line is formed to be narrower than the gate electrode. The problem that the OFF current of the insulated gate transistor increases due to the irradiated light is avoided.

In the liquid crystal display device according to claim 2, the insulated gate transistor that is a switching element is a channel etch type,
A scanning line having a gate electrode branched on one main surface of the first transparent insulating substrate is formed;
A stack of a low-resistance metal layer and a heat-resistant metal layer that can be removed by an etching gas of the gate insulating layer through a gate insulating layer and a first semiconductor layer that does not contain impurities, part of which is a channel A source / drain wiring formed so as to partially overlap the gate electrode,
A passivation insulating layer for protecting the insulated gate transistor is provided in the uppermost layer,
In the image display area, the pixel electrode formation area including a part of the drain wiring, in the area outside the image display area, the electrode terminal formation area of the scanning line including a part of the scanning line, and the signal line including a part of the signal line Oite the electrode terminal formation region, the opening of the passivation insulating layer and said first semiconductor layer through the said gate insulating layer is formed, the part of the drain wiring made of each said refractory metal layer a 1 part of the transparent insulating substrate, a part of the scanning line, and a part of the signal line made of the refractory metal layer are exposed;
The Oite the end of the picture element electrode formation region and the continuously gate electrode on bifurcation including regions and the gate electrode, the opening extending through the said a passivation insulating layer first semiconductor layer is formed The gate insulating layer is exposed;
It is made of the same conductive thin film, and includes a pixel electrode on the end portion of the gate electrode and a part of the drain wiring, a pixel electrode on the pixel electrode formation region, a pseudo pixel electrode on the branch portion of the gate electrode, A scanning line electrode terminal is formed in a scanning line electrode terminal formation region including a part of the scanning line, and a signal line electrode terminal is formed in a signal line electrode terminal formation region including a part of the signal line. It is characterized by being.

With this configuration, a part of the pixel electrode is formed including the gate insulating layer on the end portion of the gate electrode, and the gate insulating layer is exposed also in the opening on the branch portion of the gate electrode, and in the opening 2. The first amorphous silicon layer containing no impurities does not exist in the vicinity of the channel region between the source and the drain because the pseudo-pixel electrode that is electrically floating is formed. Similar to the liquid crystal display device, the problem that the OFF current of the insulated gate transistor increases due to the irradiation light from the back light source is avoided.

The liquid crystal display device according to claim 3,
A light shield electrode separated from the branched gate electrode is formed on one main surface of the first transparent insulating substrate,
Oite the upper end of one of the light shielding electrode is continuous with the pixel electrode forming region, and the upper branch of the gate electrode, the region including the end portions of the gate electrode of the other light shielding electrode, the opening passivation insulating layer and extending through the first semiconductor layer is formed, the gate insulating layer is exposed,
It is made of the same conductive thin film, on the end of the one light shield electrode and in the pixel electrode forming region including a part of the drain wiring, and in the opening on the branch of the gate electrode. The first pseudo-pixel electrode, the second pseudo-pixel electrode in the opening including the end of the other light shield electrode and the end of the gate electrode, and an electrode of the scan line including a part of the scan line 3. The liquid crystal according to claim 2, wherein an electrode terminal of the scanning line is formed in the terminal formation region, and an electrode terminal of the signal line is formed in the electrode terminal formation region of the signal line including a part of the signal line. It is a display device.

With this configuration, a part of the picture element electrode is formed including a gate insulating layer on the end of one light shield electrode, and the first pseudo picture element electrode and the first pseudo picture element electrode are formed on the gate insulating layer on the branch part of the gate electrode. The second pseudo picture element electrode is formed on the gate insulating layer in the region including the end of the other light shield electrode and the end of the gate electrode. The first and second pseudo picture element electrodes are both electrically floating, and there is no first amorphous silicon layer containing no impurities in the vicinity of the channel region between the source and drain. 2. The first amorphous silicon layer existing between the electrode and the second pseudo-pixel electrode is light-shielded by the light shield electrode, and the irradiation light from the back surface light source as in the liquid crystal display device according to claim 1. Thus, the problem that the OFF current of the insulated gate transistor increases is avoided.

A fourth aspect of the present invention provides a method for manufacturing the liquid crystal display device according to the first aspect,
Forming a scanning line having a part of a gate electrode on one main surface of the first transparent insulating substrate;
A gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, a heat-resistant metal layer removable with an etching gas between the passivation insulating layer and the gate insulating layer, and a low Sequentially applying a resistive metal layer;
A part of the low-resistance metal layer, the refractory metal layer, the second amorphous silicon layer, and the first amorphous silicon layer is selectively removed, and also serves as a drain wiring and a signal line orthogonal to the scanning line. Forming a source wiring; and
After depositing a passivation insulating layer on the first transparent insulating substrate, in the image display portion, a pixel electrode forming region including an end portion of one drain wiring and a pseudo pixel electrode including an end portion of the other drain wiring In the formation area and the area outside the image display portion, the electrode terminal formation area of the scanning line including a part of the scanning line and the electrode terminal formation area of the signal line including a part of the signal line have openings, and the cross-sectional shape thereof is Forming a reverse-tapered photosensitive resin pattern on the first transparent insulating substrate;
Using the photosensitive resin pattern as a mask, the passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed, and the end of the one drain wiring and the first insulating layer are respectively formed in the opening. Exposing a transparent insulating substrate, an end of the other drain wiring and the first transparent insulating substrate, a part of the scanning line, and a part of the signal line;
Side etching the first amorphous silicon layer;
Removing the low-resistance metal layer exposed in the opening and exposing the end of one drain wiring, the end of the other drain wiring, and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
The photosensitive resin pattern is removed, and a pixel electrode is formed in the pixel electrode formation region including the end portion of the one drain wiring, and a pseudo pixel electrode formation region is formed including the end portion of the other drain wiring. A pixel electrode, an electrode terminal of the scanning line in the electrode terminal formation region of the scanning line including a part of the scanning line, and an electrode of the signal line in the electrode terminal formation region of the signal line including a part of the signal line And a step of forming a terminal.

With this configuration, an active substrate can be manufactured using a scanning line formation process, a source / drain wiring formation process, simultaneous formation of an opening and a pixel electrode, and three photomasks. The step of forming the island of the semiconductor layer is performed by side etching of the first amorphous silicon when the opening is formed.

A fifth aspect of the present invention provides a method for manufacturing the liquid crystal display device according to the second aspect,
Forming a scanning line having a gate electrode branched on one main surface of the first transparent insulating substrate;
A gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, a heat-resistant metal layer removable with an etching gas between the passivation insulating layer and the gate insulating layer, and a low Sequentially applying a resistive metal layer;
A part of the low-resistance metal layer, the refractory metal layer, the second amorphous silicon layer, and the first amorphous silicon layer is selectively removed, and a source (signal line) is overlapped with the gate electrode. ) -Drain wiring forming step;
After depositing a passivation insulating layer on the first transparent insulating substrate, the image display unit includes a pixel electrode formation region including a part of the drain wiring, and a region outside the image display unit includes a part of the scanning line. An electrode terminal forming region of the scanning line and an electrode terminal forming region of the signal line including a part of the signal line, and an area including the end portion of the gate electrode and the gate electrode continuous with the pixel electrode forming region Forming a photosensitive resin pattern on the first transparent insulating substrate, the film thickness of the region including the branched portion is thinner than other regions, and the cross-sectional shape of the region is a reverse taper shape;
Using the photosensitive resin pattern as a mask, the passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed, and a part of the drain wiring and the first transparency are respectively formed in the opening. Exposing the insulating substrate, a part of the scanning line, and a part of the signal line;
Reducing the thickness of the photosensitive resin pattern to expose a passivation insulating layer in a region including an end portion of the gate electrode and a region including a branch portion of the gate electrode;
Using the reduced photosensitive resin pattern as a mask, the passivation insulating layer and the first amorphous silicon layer in the region including the end portion of the gate electrode and the region including the branch portion of the gate electrode are removed. Exposing the gate insulating layer;
Removing the low-resistance metal layer exposed in the opening and exposing a part of the drain wiring and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
The photosensitive resin pattern having a reduced thickness is removed, and a pixel electrode is formed in a pixel electrode formation region including a part of the drain wiring and an end of the gate electrode, and on a branch portion of the gate electrode. The pseudo-pixel electrode, the electrode terminal of the scanning line including a part of the scanning line, the electrode terminal of the scanning line in the electrode terminal forming area of the scanning line, and the signal line of the signal line in the electrode terminal forming area of the signal line including the part of the signal line A step of forming an electrode terminal.

With this configuration, a scanning line forming process, source / drain wiring forming process, and simultaneous formation of an opening and a pixel electrode using a halftone exposure technique, and an active substrate using three photomasks are manufactured. Can do. The step of islanding the semiconductor layer is performed by selectively removing the first amorphous silicon near the channel when the opening is formed.

A sixth aspect of the present invention provides a method for manufacturing the liquid crystal display device according to the third aspect,
A light shield electrode separated from the gate electrode is formed on one main surface of the first transparent insulating substrate,
In the image display area, the pixel electrode forming area including a part of the drain wiring, and in the area outside the image display area, the electrode terminal forming area of the scanning line including a part of the scanning line and the signal line including a part of the signal line. The electrode terminal forming region has an opening, and is continuous with the pixel electrode forming region, on one end of the light shield electrode, on the branch portion of the gate electrode, and on the other end of the light shield electrode and the gate Forming a photosensitive resin pattern on the first transparent insulating substrate, the film thickness on the region including the end of the electrode being thinner than other regions, and the cross-sectional shape of which is a reverse taper shape;
The passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed using the photosensitive resin pattern as a mask, and a part of the drain wiring and the first transparent insulating layer are respectively formed in the opening. Exposing a substrate, a part of a scanning line, and a part of a signal line;
Reduce the film thickness of the photosensitive resin pattern, on the end portion of the one light shield electrode, on the branch portion of the gate electrode, and on the region including the end portion of the other light shield electrode and the end portion of the gate electrode Exposing the passivation insulating layer;
Using the photosensitive resin pattern with the reduced film thickness as a mask, the end of the one light shield electrode, the branch of the gate electrode, the end of the other light shield electrode, and the end of the gate electrode Removing the passivation insulating layer and the first amorphous silicon layer on the containing region to expose the gate insulating layer;
Removing the low-resistance metal layer exposed in the opening and exposing a part of the drain wiring and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
Removing the photosensitive resin pattern having the reduced film thickness, and including a pixel electrode in the pixel electrode formation region on the end of the one light shield electrode and a part of the drain wiring, and the gate electrode A first pseudo-pixel electrode in the opening of the branch portion, a second pseudo-pixel electrode in the opening including the end of the other light shield electrode and the end of the gate electrode, and part of the scanning line Forming a scanning line electrode terminal in a scanning line electrode terminal forming region, and forming a signal line electrode terminal in a signal line electrode terminal forming region including a part of the signal line. And

With this configuration, a scanning line forming process, source / drain wiring forming process, and simultaneous formation of an opening and a pixel electrode using a halftone exposure technique, and an active substrate using three photomasks are manufactured. Can do. The step of island formation of the semiconductor layer is performed by selectively removing the first amorphous silicon near the channel, which is different from the liquid crystal display device according to the second aspect, at the time of forming the opening.

The liquid crystal display device according to claim 7,
It is a vertical alignment type liquid crystal in which the liquid crystal is vertically aligned when no voltage is applied,
A plurality of transparent conductive layers formed on the first transparent insulating substrate, wherein a first alignment control means for regulating a direction in which the liquid crystal is aligned when a voltage is applied to the liquid crystal on the first transparent insulating substrate. A lamination of a passivation insulating layer, a first semiconductor layer, and a gate insulating layer insulating layer located between the strip-shaped pixel electrodes,
2. A second alignment control means for restricting a direction in which the liquid crystal is aligned when a voltage is applied to the liquid crystal on a second transparent insulating substrate or a color filter. 2. A liquid crystal display device according to 2.

With this configuration, the stack of the passivation insulating layer, the first semiconductor layer, and the gate insulating layer insulating layer existing between the strip-like pixel electrodes functions as the alignment control means of the vertical alignment liquid crystal, and the liquid crystal cell is aligned and divided. As a result, a VA (vertical alignment) type liquid crystal display device having a viewing angle superior to that of a TN liquid crystal display device can be obtained.

As described above, the center of the present invention is to form a source / drain wiring composed of a low resistance metal layer and a lamination of a passivation insulating layer and a heat-resistant metal layer that can be removed by an etching gas of the gate insulating layer. After providing the passivation insulating layer, openings are formed in the pixel electrode formation region including a part of the drain electrode, the electrode terminal formation region including a part of the scanning line, and the electrode terminal formation region including a part of the signal line. And a step of forming a photosensitive resin pattern having a cross-sectional shape of an inversely tapered shape on the first transparent insulating substrate, and using the photosensitive resin pattern as a mask, the passivation insulating layer in the opening and the first A step of removing the semiconductor layer and the gate insulating layer, exposing a part of the drain wiring, the first transparent insulating substrate, a part of the scanning line, and a part of the signal line in the opening; Removing the low resistance metal layer exposed in the opening, exposing a part of the drain wiring and the signal line, both of which are made of a refractory metal layer, and the first A step of depositing a conductive thin film layer to be a pixel electrode on the transparent insulating substrate, and removing the photosensitive resin pattern and including a part of the drain wiring in the pixel electrode formation region And forming a scanning line electrode terminal in a scanning line electrode terminal formation region including a part of the scanning line, and forming a signal line electrode terminal in a signal line electrode terminal formation region including a part of the signal line. This method realizes a reduction in the number of steps of processing the opening forming step in the gate insulating layer and the pixel electrode forming step with a single photomask.

In addition, since the source / drain wiring is composed of a stack of heat-resistant metal layers and low-resistance metal layers, not only can the resistance of the signal lines be reduced, but it is also simpler than the conventional three-layer configuration including an intermediate conductive layer. This contributes to further cost reduction.

For the production of the active substrate, the scanning line forming process, the source / drain wiring forming process, and the opening forming process to the gate insulating layer and the pixel electrode forming process are simultaneously formed, and the semiconductor layer is selectively formed. Formation is necessary.

One of the methods for selectively forming a semiconductor layer in the present invention is that an insulated gate transistor is arranged on a scanning line, an opening is formed in a pixel electrode region and a pseudo pixel electrode region parallel to the channel, and a source / drain is formed. The first amorphous silicon layer that does not contain any interstitial impurities is removed by side etching from these openings, and the channel region is formed narrower than the scanning line, resulting in three photomasks. Thus, an active substrate can be manufactured.

Another method for selectively forming a semiconductor layer according to the present invention is to form a photosensitive resin pattern having a cross-sectional shape of an inversely tapered shape. Passivation insulating layers, first semiconductor layers and gates formed in thinner regions than other regions, and using the photosensitive resin pattern as a mask, pixel electrode formation regions, scanning line electrode terminal formation regions, and signal line electrode terminal formation regions After removing the insulating layer, the thickness of the photosensitive resin pattern is reduced to expose a passivation insulating layer in a region where the semiconductor layer needs to be removed, and the photosensitive resin pattern having the reduced thickness is used as a mask. This is done by removing the passivation insulating layer and the first semiconductor layer in the region and exposing the gate insulating layer. Therefore, an active substrate can also be manufactured using three photomasks.

As long as the film quality and thickness do not hinder the lift-off formation of the picture element electrode, restrictions on the conductive thin film for the picture element electrode are relaxed, and the presence or absence of transparency does not matter. However, although not shown, the pixel electrode of the reflection type liquid crystal display device needs to have an uneven surface having a depth of about 0.5 to 1 μm, not a flat base, in order to avoid specular reflection. In many cases, a photosensitive acrylic resin is used to form a base having such an uneven surface, and although there is a cost problem, the photosensitive acrylic resin is used at an appropriate time after the gate insulating layer is deposited. An active substrate is formed by using a single photomask to form an unevenness using a layer, and to perform the step of forming an opening in the gate insulating layer according to the present invention and the step of forming a pixel electrode of either a reflective electrode or a transmissive electrode. The purpose of reducing the process can be achieved even if manufactured.
More rationally, after depositing a transparent conductive layer and a high reflectivity AL thin film layer (Mo thin film layer for suppressing alkali reaction), the transparent conductive layer according to the present invention and (Mo thin film layer) AL thin film layer It is preferable to form a pseudo picture element electrode consisting of a laminate of and to remove the AL thin film layer (Mo thin film layer) in the transparent electrode forming region by a microfabrication technique, but the detailed explanation will be given to another opportunity.

The present invention is effective not only in the transmissive type but also in the reflective type and transflective type liquid crystal display devices. Further, the manufacturing method is the same, but the pattern shape of the transparent conductive pixel electrode is changed. This technique is effective not only for the TN liquid crystal mode but also for the vertical alignment type liquid crystal mode, and is an excellent technology that can simultaneously overcome the two problems of process reduction and viewing angle improvement.

As is apparent from the above description, the requirement of the present invention is to form a source / drain wiring comprising a low resistance metal layer, and a lamination of a heat-resistant metal layer that can be removed by an etching gas of the passivation insulating layer and the gate insulating layer. Then, after providing a passivation insulating layer that protects the insulated gate transistor, an opening that penetrates the passivation insulating layer, the amorphous silicon layer, and the gate insulating layer using a photosensitive resin pattern whose cross-sectional shape is inversely tapered After removing the low-resistance metal layer of the electrode portion exposed in the opening and exposing the heat-resistant metal layer underlying the electrode, the conductive thin film for pixel electrodes is formed using the photosensitive resin pattern as a lift-off material By forming the pixel electrode by layer lift-off, the pixel electrode forming process following the opening forming process and the opening forming process can be performed with a single photomask. A point which enables processing without using techniques, in that it further allowed the fabrication of the active substrate in three photomasks adoption of side etching or half-tone exposure technology Upon selective formation of the semiconductor layer. Therefore, regarding other configurations, it is self-evident that differences in liquid crystal display devices having different materials and film thicknesses, such as scanning lines and gate insulating layers, and manufacturing methods thereof also belong to the scope of the present invention. It has been proved that it is effective not only in a type but also in a reflection type or a transflective type liquid crystal display device. It is also clear that the semiconductor layer of the insulated gate transistor is not limited to an amorphous silicon layer.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a plan view of an active substrate (semiconductor device for display device) according to a first embodiment of the present invention, and FIG. 2 shows AA ′ (insulated gate transistor region) and BB in FIG. Sectional views of manufacturing steps on the lines '(electrode terminal region of scanning line) and CC' (electrode terminal region of signal line), DD '(channel region), and EE' (drain electrode) are shown. . Similarly, FIG. 3 and FIG. 4 show Example 2, FIG. 5 and FIG. 6 show Example 3, and FIG. 7 shows Example 4 showing a plan view of the active substrate and a cross-sectional view of (manufacturing process). In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

In Example 1, first, a metal having high heat resistance such as Cr is used as a first metal layer having a film thickness of about 0.1 to 0.3 μm on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT. The layer is deposited, and the scanning line 11 having a part of the gate electrode as a gate electrode is selectively formed by a fine processing technique. If AL is used to reduce the resistance of the scanning line, it is preferable to sandwich it with a refractory metal layer as described above. Alternatively, similarly to the signal line of the present invention, it is possible to laminate an appropriate refractory metal layer and an AL alloy to which a metal such as Ta, Nd, Hf, or Ni is added in order to improve heat resistance. The reason will be described later.

Next, as in the conventional example, a first SiNx layer 30 that becomes a gate insulating layer is formed on the entire surface of the glass substrate 2 using a PCVD apparatus, and the first amorphous silicon that hardly contains impurities and becomes a channel of an insulated gate transistor. The layer 31, the second amorphous silicon layer 33 containing impurities and serving as the source / drain of the insulated gate transistor, and the three types of thin film layers are, for example, about 0.3-0.2-0.05 μm thick In order to deposit. Further, as shown in FIG. 1A and FIG. 2A, a thin film layer 34 such as MoSi 2 is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT, and a film thickness of 0 The AL thin film layer 35 is sequentially deposited as a low resistance metal layer of about 3 μm. In the present invention, the refractory metal layer 34 needs to be removable with a fluorine-based gas used in the subsequent opening forming step. For example, a refractory metal such as Mo, W, Ta and its alloy, or Cr, Silicides of refractory metals such as Ti, Mo, W, and Ta are selected. Further, Cu may be used as the low resistance metal layer.

Subsequently, in the process of forming the source / drain wiring, as shown in FIGS. 1B and 2B, these thin film layers are sequentially etched using a photosensitive resin pattern by a microfabrication technique, and the refractory metal layer 34A. And a low resistance metal layer 35A and an insulated gate comprising a signal line 12 also serving as a source wiring of an insulated gate transistor and a laminate of a heat resistant metal layer 34B and a low resistance metal layer 35B so as to be orthogonal to the scanning line 11. The drain electrode 21 of the type transistor is selectively formed. Here, the second amorphous silicon layer 33 and the first amorphous silicon layer 31 are successively etched using the photosensitive resin pattern, The first amorphous silicon layer 31 is etched leaving about 0.05 to 0.1 μm. At this time, the source 33A and the drain 33B made of the second amorphous silicon layer are separated, and the first amorphous silicon 31S and 31D underlying the source 33A and the drain 33B are excluded on the glass substrate 2. The first amorphous silicon layer 31A having a reduced thickness is exposed. As shown in FIG. 1B, the drain electrode 21 intersects the scanning line 11 in parallel with the signal line 12 and has a TFT on Gate configuration. Simultaneously with the formation of the source / drain wirings 12 and 21, the storage electrode 72 constituting the storage capacitor 15 is also formed on the preceding scanning line 11.

After the formation of the source / drain wirings 12 and 21, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer to form a passivation insulating layer 37. 1 (c) and FIG. 2 (c), the pixel electrode forming region including the end of one drain electrode 21 and a part of the storage electrode 72 and the other drain electrode 21 are formed by microfabrication technology. The pseudo pixel electrode forming region having a small area including the end portion, and the openings 38, 39, 63 and 63 on the part 5 of the scanning line 11 and the part 6 of the signal line 12 in the region outside the image display part, respectively. 64 and a photosensitive resin pattern 88 having an opening with a cross-sectional shape that is inversely tapered. As the photosensitive resin whose cross-sectional shape of the opening is inversely tapered, for example, a product name TELR-N101PM manufactured by Tokyo Ohka Co., Ltd. may be used. A film thickness of 1 μm or more is sufficient. This product is formed by dividing the conductive thin film layer for the electrode to be deposited into the opening because of the reverse tapered cross-sectional shape in the electrode forming process after forming the organic EL light emitting layer in manufacturing the organic EL display device This is a chemically amplified negative photosensitive resin developed for applications that require a heat treatment (post-exposure-bake) after exposure prior to development processing. Have

Then, using the photosensitive resin pattern 88 as a mask, the passivation insulating layer 37, the first amorphous silicon layer 31A, and the gate insulating layer 30 in the opening are selectively removed to expose the glass substrate 2 and the electrodes described above. Exposed. Usually, dry etching using a fluorine-based gas, for example, CF4, SF6, or a mixed gas thereof is performed to remove the passivation insulating layer 37 and the gate insulating layer 30 made of SiNx. As already described, the refractory metals 34A, 34B, and 34C and the first amorphous silicon layers 31S, 31D, and 31A are also etched with a fluorine-based gas, but the low-resistance metal layers 35A, 35B, and 35C are formed of AL and Cu. Since any of these materials is not etched with a fluorine-based gas, the low-resistance metal layers 35A, 35B (35B1 and 35B2), 35C function as a mask as shown in FIG. As a result of the side etching of the metal layers 34A, 34B (34B1 and 34B2), 34C, the first amorphous silicon layers 31S, 31D, 31B and the gate insulating layer 30A by overetching, the openings 64, 38 are formed. , 39, soot (overhang) is formed around the low resistance metal layers 35A, 35B, 35C exposed.

Further, the etching gas is switched to chlorine gas, and side etching of the refractory metal layers 34A, 34B, 34C and the first amorphous silicon layers 31S, 31D, 31B is performed as shown in FIGS. 1 (d) and 2 (d). I do. In the passivation insulating layer 37A, the gate insulating layer 30A, and the low-resistance metal layer 35, the etching rate by chlorine gas is approximately one digit lower than that of the refractory metal layer and the first amorphous silicon layer, so this side etching is possible. It is. However, when AL is used for the low-resistance metal layer 35, it is necessary to forcibly form aluminum oxide on the surface by oxygen plasma treatment prior to etching with chlorine gas in order to prevent etching of AL with chlorine gas. is there. The amount of side etching is required to be 3 microns or more of mask alignment accuracy so that the first amorphous silicon layer 31C in the channel region between the source / drain wirings 12 and 21 is thinner than the gate electrode 11A. In order for the side etching to proceed effectively, the etching process should preferably use the plasma mode so that the chlorine gas plasma does not have anisotropy. In the RIE mode, processing at a high pressure of 10 Pa or higher is possible. desirable. As a result of side etching of the first amorphous silicon layer 31B, the first amorphous silicon layer 31C in the channel region becomes thinner than the gate electrode 11A in the same manner as in a normal insulated gate transistor, and the irradiation light from the back surface light source. Thus, the problem of increasing the leakage current is avoided.

When copper is selected for the low-resistance metal layer 35, the heat-resistant metal layers 34A, 34B, 34C excluding Mo, W, Ta and the first amorphous silicon layer are etched with an etching solution in which a small amount of nitric acid is mixed with hydrofluoric acid. It is also possible to perform side etching of 31S, 31D, and 31B. However, except for the channel region 31C, the first amorphous silicon layers 31S and 31D are thick, and the second amorphous silicon layers 33A and 33B and the refractory metal layers 34A, 34B and 34C are laminated. Therefore, the amount of side etching is large. Therefore, the low resistance metal layers 35B and 35C, that is, the pattern of the drain electrode 21 and the storage electrode 72 must have a large area exposed in the opening 38. Since the low resistance metal layers 35B and 35C in the opening 38 are removed, the influence on the aperture ratio is small.

Naturally, the overhang formed around the low-resistance metal layers 35A, 35B, and 35C by the side etching of the refractory metal layers 34A, 34B, and 34C and the first amorphous silicon layers 31S, 31D, and 31B is naturally increased. If such an overhang exists, the pixel electrode is disconnected in the subsequent pixel electrode formation process, and the connection between the low resistance metal layer 35A and the signal line electrode terminal, and the low resistance metal layer 35B1. Cannot be connected to the pixel electrode, and the low-resistance metal layer 35B2 cannot be connected to the pseudo-pixel electrode. Furthermore, when AL is selected for the low-resistance metal layers 35A, 35B, and 35C, it is difficult to avoid the problem that ITO and IZO, which are transparent conductive layers, are reduced and lost in resist stripping using an alkaline resist stripping solution. . Therefore, as shown in FIGS. 1E and 2E, the low-resistance metal layers 35A, 35B, and 35C in the openings 64, 38, and 39 are removed to eliminate the overhang, The process of exposing the heat-resistant metal layers 34A, 34B, and 34C, which are the bases of these electrodes, is an important point of the present invention. When removing the low resistance metal layers 35A to 34C, in order to increase the selection ratio with the underlying thermal metal layers 34A to 35C, when AL is selected for the low resistance metal layer 35, a phosphoric acid solution or Cu is selected. It is desirable to use an aqueous solution of ferric chloride (FeCl3) or cupric chloride (CuCl2). Furthermore, in a combination in which AL is selected for the low-resistance metal layer 35 and Mo or W is selected for the refractory metal layer 34, nitric acid must not be added as an additive so that Mo or W does not disappear when removing AL using phosphoric acid, There is also a need to increase the film thickness of Mo or W in response to film reduction. In that respect, the above-mentioned silicide and Ta are easy to use without such restrictions. For example, Mo silicide (MoSi 2) can be etched with a fluorine-based gas dry etch or an etching solution in which a small amount of nitric acid is mixed with hydrofluoric acid, like the amorphous silicon layers 31 and 33. Although it was used as a heat-resistant metal layer in display devices, it is a material that is not well known in the current TFT liquid crystal field.

After exposing part of the refractory metal layer 34A and part 34B of 34B1 and 34B2 in the openings 64, 38, 39 in this way, as shown in FIGS. 1 (f) and 2 (f). In addition, ITO, IZO, or a mixed crystal thereof having a film thickness of about 0.1 μm is deposited on the glass substrate 2 as a transparent conductive layer 91 using a vacuum film forming apparatus such as SPT. In general, in addition to such a thin film thickness of the transparent conductive layer 91, the cross-sectional shape is an inversely tapered shape, so that the transparent conductive layer 91 deposited on the side surface of the photosensitive resin pattern 88 is very few.

Therefore, when the photosensitive resin pattern 88 is removed using a resist stripping solution or a specific organic solvent, melting starts from the side surface of the photosensitive resin pattern 88, and the transparent conductive layer 91 on the photosensitive resin pattern 88 is easily peeled off. Resulting in. This is so-called etch-off. As a result, as shown in FIG. 1 (g) and FIG. 2 (g), the glass in the opening 38, which is the pixel electrode formation region, includes the refractory metal layer 34B1 constituting the end of one drain electrode 21. The substrate 2 includes a picture element electrode 22A and a heat-resistant metal layer 34B2 constituting the end of the other drain electrode 21, and the pseudo picture is formed on the glass substrate 2 in the opening 39 which is a pseudo picture element electrode formation region. The element electrode 22D, the scanning line part 5 and the opening 63 include the scanning line electrode terminal 5A and the signal line refractory metal layer 34A and the opening 64 includes the signal line. The electrode terminal 6A is formed in a self-aligning manner, and the passivation insulating layer 37A on the glass substrate 2 is exposed, and the manufacturing process of the active substrate 2 is completed. If the substrate is heated to improve the film quality when the transparent conductive layer 91 is deposited, if the heating temperature is excessively high, the photosensitive resin pattern 88 is altered in the lift-off process, which makes it difficult to remove the substrate. Is preferably 150 ° C. or lower.

The active substrate 2 and the color filter 9 thus obtained are bonded to form a liquid crystal panel, and Example 1 of the present invention is completed. However, since the pseudo picture element electrode 22D is a picture element electrode of the adjacent upper picture element, it is necessary to cover it with BM to lose the display capability. With respect to the configuration of the storage capacitor 15, as shown in FIG. 1G, the storage electrode 72 formed by stacking the low-resistance metal layer 35C and the refractory metal layer 34C and the scanning line 11 in the previous stage include the gate insulating layer 30A and the first An example (lower right oblique line portion 52) configured by planarly overlapping the amorphous silicon layer 31E and the second amorphous silicon layer 33E (both not shown) is illustrated. . In Example 1, similarly to the conventional example, an opening 66 is formed in the outer peripheral portion of the active substrate 2 to obtain the transparent conductive short-circuit line 40. The transparent conductive electrode terminals 5A and 6A, the short-circuit line 40, By forming the gaps in the form of elongated stripes, the resistance is increased to provide high resistance against static electricity.

When the passivation insulating layer 37, the first amorphous silicon layer 31A, and the gate insulating layer 30 in the opening are completely removed, a part 5 of the scanning line is exposed in the opening 63, but from the viewpoint of heat resistance Since AL is not used alone as a scanning line material, it is usually composed of a laminated layer with a refractory metal layer such as Ti, Cr, etc., so that the scanning line is composed of these refractory metal layers as upper layers and AL as a lower layer. If the size of the opening 63 is smaller than the part 5 of the scanning line, these heat-resistant metal layers are exposed in the opening 63, so that the part 5 of the scanning line is made of AL. It is not removed when the resistance metal layers 35A to 35C are removed. In this case, the size of the part 5 of the scanning line gives a design guideline for determining the size of the electrode terminal of the scanning line. Further, in the scanning line 11 formed of a single layer of aluminum (Al) (Ta) or AL (Nd) having a high heat resistance, for example, containing several percent of Ta, Nd, etc., these AL alloys are removed when the AL layer is removed. In this case, as in the case of the source / drain wirings 12 and 21, if the scanning line 11 is composed of a laminate having an appropriate refractory metal layer as a lower layer and the AL alloy as an upper layer, The electrode terminal of the scanning line is formed to include a part 5 of the scanning line made of the heat-resistant metal layer to ensure electrical contact, and the size of the opening 63 is larger than that of the part 5 of the scanning line. It does not matter if it is large. Thus, since the scanning line 11 may have a two-layer structure like the source / drain wirings 12 and 21, the film forming material is reduced and the film forming apparatus is manufactured as compared with the conventional three-layer electrode line. Since the number of film chambers or film forming apparatuses can be reduced, the production cost is also reduced.

In Example 1, without using the halftone exposure technique in this way, the scanning line forming process, the source / drain wiring forming process, and the simultaneous formation of the opening and the pixel electrode, which are the main objects of the present invention, An active substrate is manufactured using three photomasks, and a step corresponding to the step of forming a semiconductor layer is performed by side etching at the time of opening formation. Therefore, the secondary effect that the dimension management in each patterning process may be a normal level can be obtained. Further, the laminated structure of the scanning lines and the signal lines may be two layers, which contributes to a reduction in cost, but the latter is also a feature that is exhibited in all the embodiments of the present invention.

However, in adopting side etching, there are many restrictions on the low-resistance metal layer 35 and the heat-resistant metal layer 34, and if dry etching is adopted in the side etching, the tendency for the processing time to be long cannot be denied. Therefore, if the opening formation and the island formation process of the semiconductor layer are processed with a single photomask using halftone exposure technology at the time of opening formation, these restrictions can be avoided. 2 will be described.

The second embodiment is the same as the first embodiment up to the step of forming the source / drain wirings 12 and 21 shown in FIGS. 3B and 4B and the subsequent step of depositing the passivation insulating layer 37. Proceed through the manufacturing process. However, here, the gate electrode 11A is branched from the scanning line 11 as in the conventional example.

Subsequently, as shown in FIGS. 3 (c) and 4 (c), a pixel electrode is formed including a part of the drain electrode 21 and a part of the storage electrode 72 by a microfabrication technique using a halftone exposure technique together. A gate adjacent to the pixel electrode formation region and having openings 38, 63 and 64 on the part 5 of the scanning line 11 and the part 6 of the signal line 12 in the region outside the image display part. The film thickness on the region (88B1) including the tip portion of the electrode 11A and the region (88B2) including the branch portion from the scanning line 11 of the gate electrode 11A is, for example, 1 μm, and the film thickness of the other regions is 2 μm. Photosensitive resin patterns 88A and 88B are formed in which the cross-sectional shape of the opening is inversely tapered. Then, using the photosensitive resin patterns 88A and 88B as a mask, the passivation insulating layer 37, the first amorphous silicon layer 31A and the gate insulating layer 30 in the opening are selectively removed to expose the glass substrate 2 and these electrodes. To expose. As a result, the low-resistance metal layers 35A to 35C function as a mask as in the first embodiment, and the lower heat-resistant metal layers 34A to 34C, the first amorphous silicon layers 31S, 31D, and 31B, and the gate insulating layer. As a result of 30A being side-etched by overetching, overhangs are formed around the low-resistance metal layers 35A to 35C exposed in the openings 64 and 39.

Thereafter, when the film thickness of the photosensitive resin patterns 88A and 88B is reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 88B disappears as shown in FIGS. 3 (d) and 4 (d). Then, the passivation insulating layer 37B in the region including the tip of the gate electrode 11A and the passivation insulating layer 37C in the region including the branching portion from the scanning line 11 are exposed, and the photosensitive resin pattern 88A having a reduced thickness is formed to 88C. Converted. Therefore, as shown in FIGS. 3E and 4E, the passivation insulating layer 37B and the first amorphous silicon in the region including the tip of the gate electrode 11A are formed using the photosensitive resin pattern 88C reduced in thickness as a mask. The gate insulating layers 30B and 30C are exposed by selectively removing the layer 31B and the passivation insulating layer 37C and the first amorphous silicon layer 31B in the region including the branch from the scanning line 11. As a result, 31B of the first amorphous silicon layer between the source / drain wirings 12 and 21 is removed to become 31C, and the first amorphous silicon 31C in the channel region is shorter than the gate electrode 11A, so that the back surface The problem that the leakage current increases due to the irradiation light from the light source is avoided.

Then, as in Example 1, the low resistance metal layers 35A to 35C exposed in the openings are removed to eliminate the wrinkles (overhangs), as shown in FIGS. 3 (f) and 4 (f). Thus, the heat-resistant metal layers 34 </ b> A to 34 </ b> C that are the bases of these electrodes are exposed.

After the heat-resistant metal layers 34A, 34B and 34C are thus exposed in the openings 64 and 38, a vacuum film forming apparatus such as SPT is used as shown in FIGS. 3 (g) and 4 (g). On the glass substrate 2, ITO, IZO, or a mixed crystal thereof having a thickness of about 0.1 μm is deposited as the transparent conductive layer 91.

Further, the photosensitive resin pattern 88 is removed using a resist stripping solution or the like, and the transparent conductive layer 91 on the photosensitive resin pattern 88 is etched off. Then, as shown in FIGS. 3 (h) and 4 (h), a pixel electrode is formed including the refractory metal layer 34B which is a part of the drain electrode 21 and the refractory metal layer 34C which is a part of the storage electrode 72. On the glass substrate 2 in the opening 38 which is the region and on the gate insulating layer 30B in the region including the tip of the gate electrode 11A, the region including the branch portion from the scanning line 11 of the gate electrode 11A and the pixel electrode 22A. On the gate insulating layer 30C, the pseudo picture element electrode 22B and the scanning line part 5 are included. In the opening 63, the scanning line electrode terminal 5A and the refractory metal layer 34A which is a part of the signal line are included. Thus, the electrode terminal 6A of the signal line is formed in the opening 64 in a self-aligning manner, and the passivation insulating layer 37A on the glass substrate 2 is exposed to complete the manufacturing process of the active substrate 2.

The active substrate 2 and the color filter 9 thus obtained are bonded to form a liquid crystal panel, and Example 2 of the present invention is completed. The configuration of the storage capacitor 15 is substantially the same as that of the first embodiment as shown in FIG. Similarly to the conventional example, it is possible to form the storage capacitor line 16 simultaneously with the scanning line 11 and obtain the pixel electrode 22A divided into two by the storage capacitor line 16, but the details are omitted. The countermeasure against static electricity is the same as in the first embodiment.

In the second embodiment, a scanning line forming process, source / drain wirings are simultaneously formed, and openings and pixel electrodes are simultaneously formed, which is the main object of the present invention, and an active substrate using three photomasks. The manufacturing cost can be greatly reduced. The step of forming the island of the semiconductor layer is realized by selectively removing the semiconductor layer by applying a halftone exposure technique when forming the opening. However, since the halftone exposure technique is used, the pattern size change is configured by the pseudo pixel electrode 22B and the gate electrode 11A via the gate insulating layer 30B and the pixel electrode 22A and the gate electrode 11A and the gate insulating layer 30C. It causes a change in electrostatic capacity value. The pseudo picture element electrode 22B is electrically floating and has no influence on the display image. However, since the former capacitance value Cgs acts as a parasitic capacitance, it is desirable that the value be small, and the display screen It is desirable that it does not fluctuate. Therefore, in the oxygen plasma treatment as the film reducing means for the photosensitive resin patterns 88A and 88B, it is important to ensure in-plane uniformity in the glass substrate 2.

The third embodiment is a pattern design technique for reducing the capacitance value Cgs formed by the pixel electrode 22A and the gate electrode 11A via the gate insulating layer 30B, and the manufacturing method of the active substrate 2 is the same as that of the second embodiment. It is.

First, as shown in FIG. 5A and FIG. 6A, the difference in pattern design is that a light shield electrode 11B is formed adjacent to the vicinity of the gate electrode 11A and separated in the same direction as the gate electrode 11A. Is Rukoto.

Next, as shown in FIG. 5C and FIG. 6C, the cross-sectional shape of the opening is inversely tapered, and the photosensitive resin patterns 88A and 88B for forming the semiconductor layer and forming the opening are formed. In forming the halftone exposure region having a film thickness of 1 μm on the region (88B1) adjacent to the pixel electrode formation region and including one tip portion far from the gate electrode 11A of the light shield electrode 11B, and the gate electrode 11A In addition to the region (88B2) including the branch portion from the scanning line 11, the other tip portion of the light shield electrode 11B near the gate electrode 11A, the tip portion of the gate electrode 11A, and the region (88B3) including these gaps It is formed in.

Finally, as shown in FIGS. 5 (h) and 6 (h), the picture includes a refractory metal layer 34B which is a part of the drain electrode 21 and a refractory metal layer 34C which is a part of the storage electrode 72. On the glass substrate 2 in the opening 38 which is an element electrode formation region and on the gate insulating layer 30B in the region including one tip of the light shield electrode 11B, the pixel electrode 22A and a branching portion from the scanning line 11 are provided. On the gate insulating layer 30C in the region including the pseudo pixel electrode 22B, the other tip of the light shield electrode 11B, the tip of the gate electrode 11A, and on the gate insulating layer 30D in the region including the gap between them are simulated. The pixel electrode 22C, the scanning line part 5 and the opening 63 include the scanning line electrode terminal 5A and the refractory metal layer 34A which is a part of the signal line, and the opening 64 includes the signal. Forming the electrode terminal 6A of the wire in a self-aligning manner It completes the manufacturing process of the active substrate 2 to expose the passivation insulating layer 37A on the glass substrate 2. The storage capacitor 15 and the countermeasure against static electricity are the same as those in the second embodiment.

According to the configuration of the third embodiment, the picture element electrode 22A is electrostatically coupled to the light shield electrode 11B via the gate insulating layer 30B, and the pseudo picture element electrode 22C is connected to the light shield electrode 11B via the gate insulating layer 30D. And electrostatically coupled to the gate electrode 11A. As a result, the capacitance value Cgs formed by the pixel electrode 22A and the gate electrode 11A is reduced to about 1/3, and the display image quality can be easily maintained. However, since the first amorphous silicon layer 31C on the light shield electrode 11B is added in parallel to the source / drain wirings 12 and 21, a problem of increasing the leakage current of the insulated gate transistor newly arises. However, this is easy to suppress the influence by setting the storage capacitor 15 large, and the aperture ratio is only slightly reduced.

As described above, the active substrate 2 described in the first to third embodiments is a TN type liquid crystal display that adopts a liquid crystal mode in which the transparent conductive pixel electrode 22A and the counter electrode 14 on the color filter 9 are used as electrodes. It was an active substrate used in the apparatus. In the present invention, a liquid crystal display device with a wide viewing angle can be obtained by changing the pattern of the opening (pixel electrode) without changing the manufacturing method of the active substrate 2. explain.

Unlike a TN liquid crystal or an IPS liquid crystal, a vertical alignment liquid crystal that does not require alignment treatment requires a component member as an alignment regulating means on at least one of the two glass plates constituting the liquid crystal cell, preferably both glass substrates. is there. In the initial stage of commercialization of the vertical alignment type liquid crystal panel, a photosensitive resin is used to form a structure having a bowl-shaped cross section called a protrusion having a width of about 10 μm and a height of about 2 to 3 μm on both the active substrate 2 and the color filter 9. However, since the process of forming the protrusions also reflects the manufacturing cost of the liquid crystal panel, technical development is underway so as not to increase the manufacturing process by devising the configuration of the active substrate 2.

As already described, in the method for manufacturing an active substrate according to the present invention, the pixel electrode can be formed in a self-aligned manner in the opening provided in the insulating layer on the active substrate. Therefore, by using the insulating layer adjacent to the pixel electrode as a protrusion, as shown in FIGS. 7A and 7B corresponding to the three-mask process described in the second embodiment. An active substrate 2 for a vertical alignment type liquid crystal panel can be obtained. Here, 72 is a storage electrode formed at the same time as the source / drain wirings 12 and 21, and constitutes the storage capacitor 15 through the storage capacitor line (common electrode) 16 and an insulating layer including the gate insulating layer 30 </ b> A. Also, transparent conductive pixel electrodes 22A-1 to 22A-4 formed in a plurality of strips are interconnected via the storage electrode 72. Of course, it is easy to design an array corresponding to the devices described in the first and third embodiments. In many cases, the transparent conductive material formed on one main surface of the color filter 9 facing the active substrate 2 corresponding to the substantially central portion of the pixel electrodes 22-1 to 22-4 divided into strips. On the counter electrode 14, a protrusion 60 made of a photosensitive resin having a cross-sectional shape is formed. The pixel electrodes 22A-1 and 22A-3 and the pixel electrodes 22A-2 and 22A-4 are substantially orthogonal to each other. As a result, the viewing angle is increased by dividing the direction in which the liquid crystal molecules are inclined by applying a voltage to the liquid crystal cell in four directions. Although the orientation regulating force is reduced, the counter electrode 14 may be partially removed instead of the protrusion 60 to form a slit (cut).

In the configuration corresponding to the process described in the present invention, the gap between the picture element electrode 22A-1 and the picture element electrode 22A-2 is as shown in FIG. 7B and the passivation insulating layer 37A and the first amorphous silicon. This is a bowl-shaped structure formed by stacking 31C and the gate insulating layer 30A. Since the vertically aligned liquid crystal molecules are aligned vertically along the side surface of the projecting bowl-shaped structure, the longer the side surface, that is, the higher the height of the bank-like structure, or the bank-like structure. The gentler the inclination of the object, the stronger the regulatory power of the liquid crystal molecules.

As described above, the first amorphous silicon 31C located between the passivation insulating layer 37A and the gate insulating layer 30A is slightly narrower in pattern width than the gate insulating layer 30A, and the passivation insulating layer 37A is formed in a bowl shape. Therefore, the picture element electrode 22A-1 and the picture element electrode 22A-2 are formed separately on the side surfaces of the passivation insulating layer 37A and the gate insulating layer 30A.
In a vertically aligned liquid crystal panel, if pixel electrodes are formed on the side surfaces of the protrusions, the alignment restriction force of the protrusions is weakened by the local electric field around the pixel electrodes when a voltage is applied, and the response speed of the liquid crystal panel slows down. In the present invention, the transparent conductive layer formed on the side surface of the passivation insulating layer 37A is electrically floating, and a secondary effect of suppressing a decrease in response speed cannot be overlooked.

As described above, the three-mask process according to the present invention not only reduces the manufacturing process and reduces the manufacturing cost, but also has excellent secondary functions such as easy manufacturing management and high response speed. There are many effects, and the production process of the active substrate can be made the same regardless of the difference between the TN type liquid crystal panel and the vertical alignment type liquid crystal panel and the liquid crystal device, so there is no loss of preparation for recombination due to model change, and the mass production scale The larger the production line, the greater the advantages of the present invention.

Plan view of an active substrate according to Embodiment 1 of the present invention. Manufacturing process sectional drawing of the active substrate concerning Example 1 of this invention The top view of the active substrate concerning Example 2 of this invention Manufacturing process sectional drawing of the active substrate concerning Example 2 of this invention The top view of the active substrate concerning Example 3 of this invention Manufacturing process sectional drawing of the active substrate concerning Example 3 of this invention The top view and sectional drawing of the active substrate concerning Example 4 of this invention The perspective view which shows the mounting state of a liquid crystal panel Equivalent circuit diagram of LCD panel Sectional view of a conventional LCD panel Plan view of streamlined active substrate of conventional example Cross-sectional view of the manufacturing process of a streamlined active substrate of the conventional example

Explanation of symbols

1: Liquid crystal panel 2: Active substrate (glass substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: Part of scanning line or electrode terminal 5A: Electrode terminal of transparent conductive scanning line 6: Part of signal line or electrode terminal 6A: Transparent conductive signal line Electrode terminal 9: Color filter (opposing glass substrate)
10: Insulated gate transistor 11: Scanning line 11A: Gate wiring, gate electrode 12: Signal line (source wiring, source electrode)
14: Counter electrode 16: Storage capacitor line, common electrode 17: Liquid crystal 21: Drain electrode (drain wiring, drain electrode)
22, 22A: (transparent conductive) pixel electrode 22B, 22C, 22D: (transparent conductive) pseudo pixel electrode 30: gate insulating layer 31: impurity-free (first) amorphous silicon layer 33: (Second) amorphous silicon layer containing impurities 34: Refractory metal layer (including silicide)
35: Low resistance metal layer (AL thin film layer or Cu thin film layer)
36: Intermediate conductive layer 37: Passivation insulating layer 38: Opening in (pixel electrode forming region) 39: Opening in (pseudo pixel electrode forming region) 50, 52: Storage capacitor forming region 60: (on color filter 9) Projection 62: Opening (on drain electrode) 63: Opening (on part of scanning line or electrode terminal of scanning line) 64: (on part of signal line or electrode of signal line) Opening 65 (on the terminal) 65: Opening (on the counter electrode) 72: Storage electrode 88: Photosensitive resin pattern 88A, 88B having a cross-sectional shape of the opening that is inversely tapered Photosensitive resin pattern with a reverse taper in cross section

Claims (7)

A unit picture having at least a channel-etched insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a pixel electrode connected to the drain wiring on one main surface A liquid crystal is placed between a first transparent insulating substrate (active substrate) in which elements are arranged in a two-dimensional matrix and a second transparent insulating substrate or color filter facing the first transparent insulating substrate. In the filled liquid crystal display device, the configuration of the active substrate is:
A scanning line having a part thereof as a gate electrode is formed on one main surface of the first transparent insulating substrate,
A stack of a low-resistance metal layer and a heat-resistant metal layer that can be removed by an etching gas of the gate insulating layer through a gate insulating layer and a first semiconductor layer that does not contain impurities, part of which is a channel Source / drain wiring consisting of
The drain wiring is orthogonal to the scanning line,
A passivation insulating layer for protecting the insulated gate transistor is provided in the uppermost layer,
In the image display unit, a pixel electrode forming region including the end of one drain wiring, a pseudo pixel electrode forming region including the end of the other drain wiring, and a part of the scanning line in the region outside the image displaying unit. electrode terminal formation region of the scanning lines, including, and Oite the electrode terminal formation region of the signal lines including a portion of the signal line, the passivation insulating layer and said first semiconductor layer and said gate insulating layer through openings Of the drain wiring and the first transparent insulating substrate each made of the heat-resistant metal layer, the end of the other drain wiring and the first transparent insulating substrate, and a part of the scanning line. And a part of the signal line made of the refractory metal layer is exposed,
The first semiconductor layer in the channel region between the source / drain wirings is formed to be narrower than the gate electrode,
It is made of the same conductive thin film and includes a pixel electrode in the pixel electrode formation region including the end of the one drain wiring and a pseudo picture in the pseudo pixel electrode formation region including the end of the other drain wiring. An electrode terminal of the scanning line in the electrode terminal forming region of the scanning line including a part of the scanning line, and an electrode terminal of the signal line in the electrode terminal forming region of the signal line including a part of the signal line A liquid crystal display device, wherein: A unit picture having at least a channel-etched insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a pixel electrode connected to the drain wiring on one main surface A liquid crystal is placed between a first transparent insulating substrate (active substrate) in which elements are arranged in a two-dimensional matrix and a second transparent insulating substrate or color filter facing the first transparent insulating substrate. In the filled liquid crystal display device, the configuration of the active substrate is:
A scanning line having a gate electrode branched on one main surface of the first transparent insulating substrate is formed;
A stack of a low-resistance metal layer and a heat-resistant metal layer that can be removed by an etching gas of the gate insulating layer through a gate insulating layer and a first semiconductor layer that does not contain impurities, part of which is a channel A source / drain wiring formed so as to partially overlap the gate electrode,
A passivation insulating layer for protecting the insulated gate transistor is provided in the uppermost layer,
In the image display area, the pixel electrode formation area including a part of the drain wiring, in the area outside the image display area, the electrode terminal formation area of the scanning line including a part of the scanning line, and the signal line including a part of the signal line Oite the electrode terminal formation region, the opening of the passivation insulating layer and said first semiconductor layer through the said gate insulating layer is formed, the part of the drain wiring made of each said refractory metal layer a 1 part of the transparent insulating substrate, a part of the scanning line, and a part of the signal line made of the refractory metal layer are exposed;
The Oite the end of the picture element electrode formation region and the continuously gate electrode on bifurcation including regions and the gate electrode, the opening extending through the said a passivation insulating layer first semiconductor layer is formed The gate insulating layer is exposed;
It is made of the same conductive thin film, and includes a pixel electrode on the end portion of the gate electrode and a part of the drain wiring, a pixel electrode on the pixel electrode formation region, a pseudo pixel electrode on the branch portion of the gate electrode, A scanning line electrode terminal is formed in a scanning line electrode terminal formation region including a part of the scanning line, and a signal line electrode terminal is formed in a signal line electrode terminal formation region including a part of the signal line. A liquid crystal display device. A light shield electrode separated from the branched gate electrode is formed on one main surface of the first transparent insulating substrate,
Oite the upper end of one of the light shielding electrode is continuous with the pixel electrode forming region, and the upper branch of the gate electrode, the region including the end portions of the gate electrode of the other light shielding electrode, the opening passivation insulating layer and extending through the first semiconductor layer is formed, the gate insulating layer is exposed,
It is made of the same conductive thin film, on the end of the one light shield electrode and in the pixel electrode forming region including a part of the drain wiring, and in the opening on the branch of the gate electrode. The first pseudo-pixel electrode, the second pseudo-pixel electrode in the opening including the end of the other light shield electrode and the end of the gate electrode, and an electrode of the scan line including a part of the scan line 3. The liquid crystal according to claim 2, wherein an electrode terminal of the scanning line is formed in the terminal formation region, and an electrode terminal of the signal line is formed in the electrode terminal formation region of the signal line including a part of the signal line. Display device. In a liquid crystal display device in which liquid crystal is filled between a first transparent insulating substrate (active substrate) and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate, active In making the substrate,
Forming a scanning line having a part of a gate electrode on one main surface of the first transparent insulating substrate;
A gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, a heat-resistant metal layer removable with an etching gas between the passivation insulating layer and the gate insulating layer, and a low Sequentially applying a resistive metal layer;
A part of the low-resistance metal layer, the refractory metal layer, the second amorphous silicon layer, and the first amorphous silicon layer is selectively removed, and also serves as a drain wiring and a signal line orthogonal to the scanning line. Forming a source wiring; and
After depositing a passivation insulating layer on the first transparent insulating substrate, in the image display portion, a pixel electrode forming region including an end portion of one drain wiring and a pseudo pixel electrode including an end portion of the other drain wiring In the formation area and the area outside the image display portion, the electrode terminal formation area of the scanning line including a part of the scanning line and the electrode terminal formation area of the signal line including a part of the signal line have openings, and the cross-sectional shape thereof is Forming a reverse-tapered photosensitive resin pattern on the first transparent insulating substrate;
Using the photosensitive resin pattern as a mask, the passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed, and the end of the one drain wiring and the first insulating layer are respectively formed in the opening. Exposing a transparent insulating substrate, an end of the other drain wiring and the first transparent insulating substrate, a part of the scanning line, and a part of the signal line;
Side etching the first amorphous silicon layer;
Removing the low-resistance metal layer exposed in the opening and exposing the end of one drain wiring, the end of the other drain wiring, and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
The photosensitive resin pattern is removed, and a pixel electrode is formed in the pixel electrode formation region including the end portion of the one drain wiring, and a pseudo pixel electrode formation region is formed including the end portion of the other drain wiring. A pixel electrode, an electrode terminal of the scanning line in the electrode terminal formation region of the scanning line including a part of the scanning line, and an electrode of the signal line in the electrode terminal formation region of the signal line including a part of the signal line A method of manufacturing a liquid crystal display device comprising a step of forming a terminal. In a liquid crystal display device in which liquid crystal is filled between a first transparent insulating substrate (active substrate) and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate, active In making the substrate,
Forming a scanning line having a gate electrode branched on one main surface of the first transparent insulating substrate;
A gate insulating layer, a first amorphous silicon layer containing no impurities, a second amorphous silicon layer containing impurities, a heat-resistant metal layer removable with an etching gas between the passivation insulating layer and the gate insulating layer, and a low Sequentially applying a resistive metal layer;
A part of the low-resistance metal layer, the refractory metal layer, the second amorphous silicon layer, and the first amorphous silicon layer is selectively removed, and a source (signal line) is overlapped with the gate electrode. ) -Drain wiring forming step;
After depositing a passivation insulating layer on the first transparent insulating substrate, the image display unit includes a pixel electrode formation region including a part of the drain wiring, and a region outside the image display unit includes a part of the scanning line. An electrode terminal forming region of the scanning line and an electrode terminal forming region of the signal line including a part of the signal line, and an area including the end portion of the gate electrode and the gate electrode continuous with the pixel electrode forming region Forming a photosensitive resin pattern on the first transparent insulating substrate, the film thickness of the region including the branched portion is thinner than other regions, and the cross-sectional shape of the region is a reverse taper shape;
Using the photosensitive resin pattern as a mask, the passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed, and a part of the drain wiring and the first transparency are respectively formed in the opening. Exposing the insulating substrate, a part of the scanning line, and a part of the signal line;
Reducing the thickness of the photosensitive resin pattern to expose a passivation insulating layer in a region including an end portion of the gate electrode and a region including a branch portion of the gate electrode;
Using the reduced photosensitive resin pattern as a mask, the passivation insulating layer and the first amorphous silicon layer in the region including the end portion of the gate electrode and the region including the branch portion of the gate electrode are removed. Exposing the gate insulating layer;
Removing the low-resistance metal layer exposed in the opening and exposing a part of the drain wiring and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
The photosensitive resin pattern having a reduced thickness is removed, and a pixel electrode is formed in a pixel electrode formation region including a part of the drain wiring and an end of the gate electrode, and on a branch portion of the gate electrode. The pseudo-pixel electrode, the electrode terminal of the scanning line including a part of the scanning line, the electrode terminal of the scanning line in the electrode terminal forming area of the scanning line, and the signal line of the signal line in the electrode terminal forming area of the signal line including the part of the signal line The manufacturing method of the liquid crystal display device which consists of a process of forming an electrode terminal. A light shield electrode separated from the gate electrode is formed on one main surface of the first transparent insulating substrate,
In the image display area, the pixel electrode forming area including a part of the drain wiring, and in the area outside the image display area, the electrode terminal forming area of the scanning line including a part of the scanning line and the signal line including a part of the signal line. The electrode terminal forming region has an opening, and is continuous with the pixel electrode forming region, on one end of the light shield electrode, on the branch portion of the gate electrode, and on the other end of the light shield electrode and the gate Forming a photosensitive resin pattern on the first transparent insulating substrate, the film thickness on the region including the end of the electrode being thinner than other regions, and the cross-sectional shape of which is a reverse taper shape;
The passivation insulating layer, the first amorphous silicon layer, and the gate insulating layer in the opening are removed using the photosensitive resin pattern as a mask, and a part of the drain wiring and the first transparent insulating layer are respectively formed in the opening. Exposing a substrate, a part of a scanning line, and a part of a signal line;
Reduce the film thickness of the photosensitive resin pattern, on the end portion of the one light shield electrode, on the branch portion of the gate electrode, and on the region including the end portion of the other light shield electrode and the end portion of the gate electrode Exposing the passivation insulating layer;
Using the photosensitive resin pattern with the reduced film thickness as a mask, the end of the one light shield electrode, the branch of the gate electrode, the end of the other light shield electrode, and the end of the gate electrode Removing the passivation insulating layer and the first amorphous silicon layer on the containing region to expose the gate insulating layer;
Removing the low-resistance metal layer exposed in the opening and exposing a part of the drain wiring and a part of the signal line, both of which are made of a refractory metal layer;
Depositing a conductive thin film layer on the first transparent insulating substrate;
Removing the photosensitive resin pattern having the reduced film thickness, and including a pixel electrode in the pixel electrode formation region on the end of the one light shield electrode and a part of the drain wiring, and the gate electrode A first pseudo-pixel electrode in the opening of the branch portion, a second pseudo-pixel electrode in the opening including the end of the other light shield electrode and the end of the gate electrode, and part of the scanning line And forming a signal line electrode terminal in the signal line electrode terminal formation region including a part of the signal line. The manufacturing method of the liquid crystal display device of description. It is a vertical alignment type liquid crystal in which the liquid crystal is vertically aligned when no voltage is applied,
A plurality of transparent conductive layers formed on the first transparent insulating substrate, wherein a first alignment control means for regulating a direction in which the liquid crystal is aligned when a voltage is applied to the liquid crystal on the first transparent insulating substrate. A lamination consisting of a passivation insulating layer, a first amorphous silicon layer, and a gate insulating layer located between the strip-shaped pixel electrodes,
2. A second alignment control means for restricting a direction in which the liquid crystal is aligned when a voltage is applied to the liquid crystal on a second transparent insulating substrate or a color filter. 2. A liquid crystal display device according to 2.

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