CN100416389C

CN100416389C - Liquid crystal display and its producing method

Info

Publication number: CN100416389C
Application number: CNB2004100973375A
Authority: CN
Inventors: 川崎清弘
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2004-11-29
Filing date: 2004-11-29
Publication date: 2008-09-03
Anticipated expiration: 2024-11-29
Also published as: CN1782828A

Abstract

A past manufacturing method for cutting down the quantities of manufacturing processes has the technique problems of low manufacturing volume and low production quantity. The present invention solves the technique problems by new techniques, and the new techniques comprise: a islanding procedure of a semiconductor layer and a forming procedure of an opening part of a gate electrode insulating layer are rationalized by introducing a halftoning exposure technique; a forming procedure of a protection layer of an electrode terminal is rationalized by introducing the halftoning exposure technique into an anodisation procedure of source electrode /drain electrode wires, and the new technique belongs to the known technique; a technique which belongs to the known technique rationalizes the formation of pixel electrodes and scan wires, etc. Therefore, the four-path light cover manufacturing scheme and the three-path light cover manufacturing scheme of a TN type liquid crystal display device and an IPS type liquid crystal display device are formed.

Description

Liquid crystal disply device and its preparation method

Technical field that the present invention belongs to

The invention relates to liquid crystal indicator, particularly about active liquid crystal indicator with chromatic image demonstration function.

Prior art

According to the progress of the real packing technique of Micrometer-Nanometer Processing Technology in recent years, liquid crystal material technology and high density etc., on commercial use, provide the liquid crystal indicator of diagonal-size 5～50cm to be used as the display of television image or various images in a large number.In addition, also carry out the colour demonstration by on a slice of the 2 sheet glass substrates that constitute liquid crystal panel, forming the RGB dyed layer easily.Especially, the active liquid crystal panel of built-in on-off element guarantees fewer cross-talk (cross-talk) is provided in each pixel, and answer speed is the image of high-contrast faster.

Though these liquid crystal indicators (liquid crystal panel) generally are the sweep traces by 200～1200, and the establishment of the matrix of 300～1600 signal wire, are also carrying out simultaneously recently and should become more meticulous corresponding to the big picture and the height of the increase of the capacity of display.

Figure 13 is the actual installation state of expression liquid crystal panel, use the sticker connection of electric conductivity drive signal to be supplied on the transparent insulated substrate of a side that is formed on formation liquid crystal panel 1, COG (Chip-On-Glass) mode of the semiconductor integrated circuit wafer 3 of the electrode tip subgroup 5 of the sweep trace on the glass substrate 2 for example, or be used as substrate with for example polyimide resin film, to contain the suitable sticker of electric conductivity medium, to have by gold-plated or plate TCP (Tape-Carrier-Package) film 4 of the Copper Foil terminal (not shown) of solder flux, pressing also is fixed in the actual installation means of TCP mode etc. of the electrode tip subgroup 6 of signal wire, and electric signal is supplied on the image displaying part.At this, for convenience, two mounting meanss are illustrated simultaneously, but in a mode in fact can suitably selecting in the two.

7, the 8th, connected in the omission of liquid crystal panel 1 the distribution road between the

electrode terminal

5,6 of pixel in the image displaying part of middle body and sweep trace and signal wire, might not be constituted with the conductive material identical with electrode tip subgroup 5,6.The 9th, on the subtend face, have the subtend glass substrate or the colored filter of another sheet transparency insulated substrate of common transparent conductivity counter electrode in all liquid crystal cells (Liquid Crystal cell).

Figure 14 is illustrated in to dispose the equivalent circuit diagram that insulated gate transistor is used as the active liquid crystal indicator of on-off element on each pixel, 11 (being 7 among Figure 13) are sweep traces, 12 (being 8 among Figure 13) are signal wires, and 13 is liquid crystal cells, and liquid crystal cells 13 is to be used as capacity cell electrically.The element class that solid line is drawn is to be formed on the side's glass substrate 2 that constitutes liquid crystal panel, and all common counter electrodes 14 in liquid crystal cells 13 that dotted line is drawn are to be formed on the first type surface in opposite directions of the opposing party's glass substrate 9.The OFF resistance of insulated gate transistor 10 or the resistance of liquid crystal cells 13 is when low or when paying attention to the GTG of display image, then must seek some as putting on liquid crystal cells 13 first-class circuit performances side by side and improve means in order to increasing memory capacitance 15 as the time constant of the liquid crystal cells 13 of load.And, the 16th, the common bus of memory capacitance 15.

Figure 15 is the significant points sectional view of the image displaying part of expression liquid crystal indicator, constitute two sheet glass substrates the 2, the 9th of liquid crystal panel 1, separate the gap of several μ m specific ranges by resinousness fiber, pearl or the interval insulant (not shown) that is formed on column spacer on the colored filter 9 etc., encapsulant and/or the joint filling material (both are all not shown) that is constituted with organic property resin seals on peripheral part of glass substrate 9 again, make two glass substrates 2, form an enclosure space between 9, and be equipped with liquid crystal material 17 in this enclosure space.

When colour shows, because of on the enclosure space side of glass substrate, be attached the dyestuff that is called dyed layer 18 or in the pigment any one or contain the organic film of both sides' thickness 1～2 μ m, and be endowed colors displaying function, so this moment, glass substrate 9 claims colored filter (ColorFilter abbreviation CF) again.Then, according to the character of liquid crystal material 17 in two side surfaces of liquid crystal panel 1 arbitrary or two-sided on stick Polarizer 19, liquid crystal panel 1 is brought into play function as photovalve.Now, the liquid crystal material of most of liquid crystal panel on the market is to use the liquid crystal material of TN (TwistNematic) series, and Polarizer 19 needs 2 usually.Though not shown, the permeation type liquid crystal panel configuration has back side light source to be used as light source, by below irradiation white light.

Being connected in liquid crystal 17, being formed on for example thickness on the 2

sheet glass substrates

2,9 and being the polyimide resin film 20 about 0.1 μ m, is with so that the alignment film of liquid crystal alignment on the direction that is determined.The 21st, the drain electrode (distribution) of the drain electrode of connection insulated gate transistor 10 and the pixel electrode 22 of transparent conductivity, many and signal wire (source electrode line) is formed simultaneously.Be semiconductor 23 between signal wire 12 and drain electrode 21, the back is described in detail.Cr thin layer 24 about the borderline thickness 0.1 μ m that is formed on adjacent dyed layer 18 on the colored filter 9 is in order to prevent that exterior light is injected into the light shading member of semiconductor layer 23 and sweep trace 11 and signal wire 12, the technology of being used as so-called black matrix" (Black Matrix, abbreviation BM) and deciding to change.

At this, illustrated about the structure and the manufacture method of the insulated gate transistor of being used as on-off element.Common insulated gate transistor has 2 kinds, introduces wherein a kind of transistor that is called as channel etch type herein.By the introducing of dry etching technology, needed the light shield about 8 roads in the past, be reduced to 5 roads now, help very much reducing of manufacturing cost.

Figure 16 is the planimetric map of expression corresponding to the unit picture element of the active substrate (display device semiconductor device) of 5 road light shield processing procedures, and Figure 17 is A-A ', the B-B ' of expression Figure 16 (e) and the sectional view on the C-C ' line, this manufacture process of following simple declaration.At Figure 16 (c) though in 21 of memory capacitance 16 and drain electrodes across gate insulation layer and overlapping areas 50 (upper left oblique line portion toward the bottom right) is formed with memory capacitance 15, omit this explanation at this.

At first, shown in Figure 16 (a) and Figure 17 (a) like that, glass substrate 2 as the thickness 0.5～1.1mm of the high insulativity substrate of thermotolerance and resistance to chemical reagents and the transparency, for example use SPT (sputter) on a first type surface of the trade name 1737 that healthy and free from worry (Co ning) company produces, to apply the 1st metal level of thickness 0.1～0.3 μ m, and by Micrometer-Nanometer Processing Technology, selectivity forms also sweep trace 11 and the storage capacitance line 16 of double as gate electrode 11A.Though the material of sweep trace is comprehensive consideration resistance to chemical reagents and anti-fluoric acid and electric conductivity and select, and generally speaking, uses the high metal or alloy of thermotolerance such as chromium Cr, tantalum Ta, tungsten (MoW) alloy.

In order to reduce the resistance value of sweep trace corresponding to the big pictureization of liquid crystal panel or high becoming more meticulous, though use Al (aluminium) to be used as the sweep trace material, but the monomer thermotolerance of Al is low, so at present, Cr, Ta, Mo or its silicide that will belong to the thermotolerance metal give laminationization, or imposing anodic oxidation on the Al surface gives oxide layer (Al ₂O ₃) become general technology.Just, sweep trace 11 is made of the metal level more than 1 layer.

Then, make electricity consumption pulp oxygen deposit (PCVD) device mutually on the full surface of glass substrate 2, for example be respectively 0.3-0.2-0.05 μ m thickness, sequential aggradation silicon nitride (SiNx) layer 30 is as gate insulation layer, the 1st amorphous silicon layer 31 of the passage of impure insulated gate transistor hardly, and contains 3 kinds of thin layers such as the 2nd amorphous silicon layer 33 of source/drain of the insulated gate transistor of impurity.Then, shown in Figure 16 (b) and Figure 17 (b), as the island on gate electrode 11A (31A, 32A) the residual semiconductor layer that is constituted by the 1st and the 2nd amorphous silicon layer wideer than the width of gate 11 electrode A, expose gate insulation layer 30.

Then, the vacuum film formation apparatus of use SPT etc., sequential aggradation for example Ti (titanium) thin layer 34 is a heat resistant metal layer about thickness 0.1 μ m, Al thin layer 35 is the low resistance wiring layer about thickness 0.3 μ m, for example Ti thin layer 36 is the intermediate conductive layer about thickness 0.1 μ m, shown in Figure 16 (c) and Figure 17 (c), form by the drain electrode 21 of the insulated gate transistor that lamination constituted of these

thin layers

34A, 35A, 36A and the signal wire 12 of double as source electrode by the Micrometer-Nanometer Processing Technology selectivity.This optionally pattern to form be that photoresist pattern with the formation of the distribution that is used to drain is used as mask, order etching Ti thin layer 36, Al thin layer 35, Ti thin layer the 34, the 2nd amorphous silicon layer 33A and the 1st amorphous silicon layer 31A, the 1st amorphous silicon layer 31A is because of being etched into about remaining 0.05～0.1 μ m, so claimed the passage etching.

Construct in order to make insulated gate transistor not become compensation, source/drain electrodes the 12, the 21st, it is overlapping with gate electrode 11A planarity to form a part (several μ m).Because of should be overlapping is to be used as stray capacitance to bring into play the effect of electric property, so the smaller the better, but the glass substrate temperature during by the expansion coefficient of the precision of the quality of fit of exposure machine and light shield and glass substrate and exposure is determined that the numerical value of practicality is to the maximum about 2 μ m.

Marquis when the wiring resistance of signal wire 12 is unquestioned, not necessarily need be by the low resistance wiring layer 35 that Al constituted, at this moment, if select the heating resisting metal material of Cr, Ti, Ta, Mo etc., then source/

drain distribution

12,21 can be given single-layered, simplify manufacturing process.And, in Japanese kokai publication hei 7-74368 communique, be documented at the transistorized thermotolerance of insulated type.

And; after removing above-mentioned photoresist pattern; use the PCVD device on the full surface of glass substrate 2; the SiNx layer that applies the thickness about 0.3 μ m with the gate insulation layer of being used as transparent insulation course in the same manner is used as protection (passivation) insulation course 37; shown in Figure 16 (d) and Figure 17 (d); remove protection insulation course 37 according to the Micrometer-Nanometer Processing Technology selectivity; and on drain electrode 21, form peristome 62; on the position of the electrode terminal that is formed sweep trace 11 5 in image displaying part zone exceptionally, form peristome 63, on the position of the electrode terminal 6 that is formed with signal wire 12, form peristome 64 and expose the part of drain electrode 21 and sweep trace 11 and signal wire 12.Go up a part that forms peristome 65 and expose storage capacitance line 16 in storage capacitance line 16 (electrode pattern of parallel harness).

Use the vacuum film forming apparatus of SPT etc. to apply thickness 0.1～0.2 μ m left and right sides ITO (Indium-Tin-Oxide at last; indium tin oxide) or IZO is (Indium-Zinc-Oxide; indium-zinc oxide) is used as transparency conducting layer; shown in Figure 16 (e) and Figure 17 (e); on protection insulation course 37, comprise peristome 62 ground by Micrometer-Nanometer Processing Technology and optionally form pixel electrode 22, and finish initiatively substrate 2.Even the part of the sweep trace that exposes 11 in the peristome 63 is used as electrode terminal 5; and also the part of the signal wire that exposes 12 in the peristome 64 can be used as electrode terminal 6; as shown in the figure; also can on protection insulation course 37, comprise

peristome

63,64 ground and optionally form electrode terminal 5A, the 6A that constitutes by ITO, but the general short-circuit line 40 that is connected the transparent conductivity between

electrode terminal

5A, 6A that also forms simultaneously.Its reason is, though not shown, make to form elongated strip between

electrode terminal

5A, 6A and the short-circuit line 40 and cause high resistanceization and can be used as the high resistance that the static countermeasure is used.Equally, form the electrode terminal that leads to storage capacitance line 16 that comprises peristome 65.

Invent problem to be solved

Like this in 5 road light shield operations, form operation because of implementing contacting of drain electrode 21 and sweep trace 11 simultaneously, so the thickness of the insulation course in corresponding these the

peristome

62,63 is then different with kind.Protection insulation course 37 is compared with gate insulation layer 30, and the system film temperature is low, membranous relatively poor, and the Wet-type etching that carries out for the etching solution by fluoric acid series is because of etching speed respectively is number

/ minute, the number

/ minute, differing 1 order of magnitude, the section shape of the peristome 62 on the drain electrode 21 is owing to produce over etching and the cause in uncontrollable aperture on top, and changes the dry-etching of adopting the gas that uses fluorine series.

Even employing dry-etching; peristome 62 on the drain electrode 21 because of only for the protection insulation course 37, so, compare with the peristome 63 on the sweep trace 11; can't avoid over etching, exist different and situation that the etched gas of thickness generation intermediate conductive layer 36A is cut down along with material.In addition, removing of photoresist pattern after finishing for etching, at first in order to remove the polymkeric substance on the surface of being fluoridized, with the oxygen plasma ashing, the surface of photoresist pattern is cut down about 0.1～0.3 μ m, then, to use organic stripper, for example the Tokyo soup that should change stripper 106 grades of made is treated to the general practice, but when exposing the state of aluminium lamination 35A of substrate when cutting down intermediate conductive layer 36A, on the surface of aluminium lamination 35A, form the Al that belongs to insulator with the oxygen plasma ashing treatment ₂O ₃And and pixel electrode 22 between just can not get Ohmic contact.At this, even it is also no problem to cut down the thickness of intermediate conductive layer 36A, for example thickness is set for 0.2 μ m, can address this problem.Perhaps when forming opening portion 62～65, also can adopt and remove aluminium lamination 35A and expose the eluding game that forms pixel electrode 22 after the thin layer 34A of heat resistant metal layer of substrate again, at this moment, the advantage that does not need intermediate conductive layer 36A is from the beginning arranged.

But in the countermeasure in front, if when the inner evenness of the thickness of these films is undesirable, useful effect is then not necessarily brought into play in this cooperations, and in addition, the inner evenness of etching speed is not as if well identical yet.In the countermeasure of back, though do not need intermediate conductive layer 36A, increase the operation remove aluminium lamination 35A, control when insufficient when the section of peristome 62 in addition, then have the possibility that pixel electrode 22 breaks takes place.

In addition, in the insulated gate transistor of channel etch type, if the 1st amorphous silicon layer 31 free from foreign meter of passage area is not when applying thicker (being generally in the channel etch type more than the 0.2 μ m), then influence the inner evenness of glass substrate greatly, it is inconsistent often to become the inconsistent especially OFF of electric crystal characteristic electric current.This situation influences the running rate and the particle situation occurred of PVCD device greatly, also is very important item from the viewpoint of production cost.

Then, introduce 4 road light shield processing procedures of an example of improving above-mentioned 5 road light shield processing procedures.4 road light shield processing procedures are according to introducing halftone exposure technology, reduce the lithography operation, and Figure 18 is the planimetric map corresponding to the unit picture element of the active substrate of 4 road light shield processing procedures, and Figure 19 is A-A ', the B-B ' of expression Figure 18 (e) and the sectional view on the C-C ' line.

At first, coexist mutually on the first type surface of glass substrate 2 with 5 road light shield processing procedures, the vacuum film forming apparatus of use SPT etc., apply the 1st metal level about thickness 0.1～0.3 μ m, and shown in Figure 18 (a) and Figure 19 (a), form also sweep trace 11 and the storage capacitance line 16 of double as gate electrode 11A by the Micrometer-Nanometer Processing Technology selectivity.

Then, use the PCVD device on all surfaces of glass substrate 2 for example respectively with the thickness about 0.3～0.2～0.05 μ m, sequential aggradation silicon nitride (SiNx) layer 30 is as gate insulation layer, the 1st amorphous silicon layer 31 of the passage of impure insulated gate transistor hardly, and contains 3 kinds of thin layers such as the 2nd amorphous silicon layer 33 of source/drain of the insulated gate transistor of impurity.Then, for example Ti thin layer 34 about the vacuum film forming apparatus sequential applications thickness 0.1 μ m of use SPT etc. as heat resistant metal layer, Al thin layer 36 about thickness 0.3 μ m as the low resistance wiring layer, it is the source/drain wiring material, though form by these thin layers 34A by the Micrometer-Nanometer Processing Technology selectivity, 35A, the drain electrode 21 of the insulated gate transistor that lamination constituted of 36A and the signal wire 12 of double as source electrode, but form for this selectivity pattern, by the halftone exposure technology shown in Figure 18 (b) and Figure 19 (b), there is the passage of the source/drain interpolar that for example forms thickness 1.5 μ m to form regional 80C (oblique line portion), forms and form regional 80A than source/drain distribution, the point of photoresist pattern 80A～80C that the thickness 3 μ m of 80B are thinner is a significant feature.

So photoresist pattern 80A～80C is because of being to use the photoresist of common eurymeric in the making base plate for liquid crystal display device, so it is black that the source/drain distribution forms regional 80A, 80B, promptly be to form the Cr film, passage area 80C is a grey, for example form the Cr pattern that adds null width (line and space) about width 0.5～1 μ m, other zones are white, promptly are if use the light shield that is removed the Cr film to get final product.Gray area is because of the resolving power deficiency of exposure machine, so can't resolve trip and null, and seen through because can make from about half of the light shield irradiates light of lamp source, so, can obtain the photoresist pattern 80A～80C of the section shape that has shown in Figure 19 (b) in response to the residual membrane property of normal Photosensitive resin.

Above-mentioned photoresist pattern 80A～80C is used as mask, shown in Figure 19 (b), order etching Ti thin layer 36, Al thin layer 35, Ti thin layer the 34, the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 and after exposing gate insulation layer 30, shown in Figure 18 (c) and Figure 19 (c), make the thickness of photoresist case 80A～80C according to the ashing means of oxygen plasma etc., for example more than 3 μ m reduce by 1.5 μ m and become 81A, 81B the time, photoresist pattern 80C then disappears and exposes passage area.At this, be used as masking layer with

photoresist pattern

81A, 81B behind the reduction film, by Ti thin layer 36A, Al thin layer 35A, Ti thin layer 34A, the 2nd amorphous silicon layer 33A and the 1st amorphous silicon layer 31A of etching source/drain wiring closet (passage forms the zone), the 1st amorphous silicon layer 31A is about etch residue 0.05～0.1 μ m once more.And, in above-mentioned oxygen plasma is handled, because of suppressing the variation of pattern dimension, so preferably strengthen anisotropy, back narration reason wherein.

And; remove after above-mentioned photoresist pattern 81A, the 81B; identical with 5 road light shield processing procedures; shown in Figure 18 (d) and Figure 19 (d); the SiNx layer that applies 0.3 μ m left and right sides thickness on all surfaces of glass substrate 2 is used as transparent insulation course; and be used as protection insulation course 37 with this, on the drain electrode 21 and be formed with on the zone of

electrode terminal

5,6 of sweep trace 11 and signal wire 12 and respectively be formed with

opening portion

62,63,64.

At last; use SPT equal vacuum film forming apparatus; apply ITO for example or IZO and form transparency conducting layer about thickness 0.1～0.2 μ m; shown in Figure 18 (e) and Figure 19 (e); have the pixel electrode 22 that optionally forms electrically conducting transparent on the protection insulation course 37 of opening portion 62 by Micrometer-Nanometer Processing Technology, and finishing initiatively substrate 2.About electrode terminal, this be included in the

opening portion

63,64 that optionally forms on the protection insulation course 37 by

electrode terminal

5A, 6A that ITO constituted.

Summary of the invention

(inventing problem to be solved)

So, by using the halftone exposure technology, can simplify 5 road light shield processing procedures is 4 road light shields, and obtains and 5 road light shield processing procedures product much at one.But in 4 road light shield processing procedures, the passage that is suitable for forms operation and removes the source/drain wiring material and the semiconductor layer of 12,21 of source/drain distributions because of selectivity, is the operation of the passage length (present volume production product are 4～6 μ m) of the ON characteristic that decision can left and right sides insulated gate transistor.The length change of this passage length significantly changes because of the ON current value that makes insulated gate transistor, so strict manufacturing management usually.

As previously mentioned, the long pattern dimension in halftone exposure zone just of passage is to be subjected to exposure (intensity of light source and light shield precision, especially row and null size), the multiple parameters of the coating thickness of photoresist, the development treatment of photoresist and the film reduction of the photoresist in this etching work procedure etc. about, in addition, the inner evenness of adding this tittle is also identical, not necessarily can reach the high stable production of turnout, need be than stricter in the past manufacturing management, with present situation, cannot say so has reached the level of high completeness.Especially, passage length is 6 μ m when following, and this tendency is more for significantly.

The present invention creates in view of present situation, and the undesirable condition when not only avoiding common formation contact in 5 road light shield processing procedures or 4 road light shield processing procedures in the past adopts the big halftone exposure technology of error permission and realizes deleting manufacturing process.In addition, in order to realize the low price of liquid crystal panel, and, obviously pursue as can be known and delete that more worker ordinal numbers are necessary, because of helping to simplify the technology of main manufacturing process or cost degradation, thereby more improve value of the present invention corresponding to the increase of demand.

(solving the means of problem)

In the present invention, at first form operation, realize deleting of manufacturing process with island chemical industry preface and the contacting of gate insulation layer that the halftone exposure technology is applicable to the semiconductor layer that carries out the pattern accuracy control easily.Then; for the path protection layer is given on insulated gate transistor; merged the technology that passing through of Japanese kokai publication hei 4-302438 number of prior art the disclosing semiconductor layer that anodic oxidation will contain impurity is transformed into silicon oxide layer; protect only source/drain distribution with oxide effectively with the confession that the Japanese kokai publication hei 2-216129 communique of prior art discloses; on surface, form the anodizing technology of insulation course, realize the rationalization and the low temperatureization of processing procedure by the source/drain distribution that aluminium constituted.And, make the formation operation rationalization technology of the pixel electrode that is disclosed in the flat 5-268726 communique of Japanese Patent Application of prior art be suitable for the present invention and adopted.In addition in order to delete operation, also be suitable for the halftone exposure technology and make the protective seam of electrode terminal form operation and rationalized in the formation of the anodic oxide coating of source/drain distribution.

Insulation gate transistor according to an aspect of the present invention is the insulated gate transistor of a kind of bottom gate type; it is characterized by: be formed with the gate electrode that is constituted by the 1st metal level more than 1 layer on the insulated substrate; between on the gate electrode, form island and the 1st semiconductor layer free from foreign meter across the gate insulation layer more than 1 layer; it is overlapping and will become a pair of the 2nd semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on above-mentioned the 1st semiconductor layer; be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than 1 layer can anodised metal level constitutes the source/drain distribution; and except that the electric property join domain of source electrode distribution; be formed with anodic oxide coating on the source/drain distribution He on the passage; anodic oxide coating is because of performance protective seam function; so need not give the protection insulation course of SiNx etc., relevant liquid crystal indicator is the 3rd of claims; the 4th; the 6th and the 2nd; the 3rd; the 5th; clearly record is arranged among the 6th the embodiment.

Liquid crystal indicator according to an aspect of the present invention, it is to belong to the liquid crystal filling: insulated gate transistor on a first type surface, having at least, the sweep trace of the gate electrode of the above-mentioned insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become the 1st transparent insulated substrate of the matrix of two-dimentional (Quadratic Finite Element) by assortment with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc., and the liquid crystal indicator that is constituted between the 2nd transparent insulativity substrate relative with the above-mentioned the 1st transparent insulated substrate subtend or the color filter, it is characterized by:

At least on a first type surface of the 1st transparent insulated substrate, be formed with by the sweep trace that lamination constituted of transparency conducting layer and metal level and the pixel electrode of transparent conductivity;

Form island and the 1st semiconductor layer free from foreign meter across electricity slurry protective seam and gate insulation layer between on the gate electrode;

It is overlapping and will become a pair of the 2nd semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on above-mentioned the 1st semiconductor layer;

On slurry protective seam of the electricity on the pixel electrodes and gate insulation layer, be formed with peristome;

Be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode distribution (signal wire) and similarly be formed with the drain electrode distribution on above-mentioned the 2nd semiconductor layer and on the gate insulation layer and on an one of the pixel electrode in the above-mentioned opening portion;

The protection insulation course that on pixel electrodes, has opening portion, and described protection insulation course is formed on the 1st transparent insulated substrate.

According to this formation, the lithography process number that then uses 1 road light shield to handle sweep trace and pixel electrode is deleted, in addition, the opening portion that also adds the island chemical industry preface of using 1 road light shield to handle semiconductor layer and gate insulation layer forms the photography etching work procedure number of operation and is deleted, can use 4 road light shields to make the liquid crystal indicator of TN types.In addition, because of the thickness of the protection insulation course on the electrode terminal of sweep trace and signal wire is identical, so the undesirable condition relevant with forming contact do not take place.

Liquid crystal indicator according to an aspect of the present invention, be to belong to the liquid crystal filling in having at least on the first type surface: the signal wire of the sweep trace of the gate electrode of insulated gate transistor, the above-mentioned insulated gate transistor of double as and also double as source electrode distribution and the unit picture element of pixel electrode etc. on being connected to the drain electrode distribution are become the 1st transparent insulated substrate of two-dimentional matrix by assortment, and and the 2nd transparent insulativity substrate of the above-mentioned the 1st transparent insulated substrate subtend or color filter between and the liquid crystal indicator that constituted it is characterized by:

At least on a first type surface of the 1st transparent insulated substrate, be formed with by the sweep trace that metal level constituted more than 1 layer;

Between on the gate electrode, form island and the 1st semiconductor layer free from foreign meter across the gate insulation layer more than 1 layer;

It is overlapping and will become the 2nd semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on above-mentioned the 1st semiconductor layer;

Be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than 1 layer can anodised metal level constitutes source electrode (signal wire)/drain electrode distribution;

On the above-mentioned drain electrode distribution and on the gate insulation layer,, on signal wire, be formed with the electrode terminal of transparent conductivity in the pixel electrode of transparent conductivity and the zone outside the image displaying part;

Except that with above-mentioned drain electrode distribution on the pixel electrode overlapping areas and the electrode terminal zone of signal wire, on the surface of source/drain distribution, be formed with anodic oxide coating;

On the 1st semiconductor layer of above-mentioned source/drain wiring closet, be formed with silicon oxide layer.

Deleted according to the lithography process number that this formation uses 1 road light shield to handle sweep trace and pixel electrode; in addition; also add the formation of using 1 road light shield processed pixels electrode and protect the lithography process number that forms to be deleted, can use 4 road light shields to make the liquid crystal indicator of TN types.Formation contains the silicon oxide layer of impurity and protects passage on the passage of source/drain interpolar, on the surface of signal wire and drain electrode distribution, forms the tantalum pentoxide (Ta of the anodic oxide coating that belongs to insulativity simultaneously ₂O ₅) or aluminium oxide (Al ₂O ₃) and give the protection function.Therefore need not the protection insulation course is coated on all surfaces of glass substrate, the thermotolerance of insulated gate transistor then can not have problems.In addition, the insulation course of protection passage is because of being that to be transformed into silicon oxide layer with the amorphous silicon layer that anodic oxidation contains impurity obtained, so the uncrystalline layer free from foreign meter that does not need to become channel layer is made into thick film, and the liquid crystal indicator of realization TN type.

Liquid crystal indicator according to an aspect of the present invention is characterized by:

At least on a first type surface of the 1st transparent insulated substrate, be formed with in the same manner by the sweep trace that lamination constituted of transparency conducting layer and metal level and the pixel electrode of transparent conductivity;

On slurry protective seam of the electricity on the pixel electrodes and gate insulation layer, be formed with opening portion;

Be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than 1 layer can anodised metal level constitutes source electrode distribution (signal wire) and similarly be formed with the drain electrode distribution on above-mentioned the 2nd semiconductor layer and on the gate insulation layer and on an one of the pixel electrode in the above-mentioned peristome;

Except that the electrode terminal zone of above-mentioned signal wire, be formed with anodic oxide coating on the surface of source/drain distribution;

According to this formation; the photoetch process number that uses 1 road light shield to handle sweep trace and pixel electrode is deleted; the photoetch process number that forms operation with the peristome that uses 1 road light shield to handle the island chemical industry preface of semiconductor layer and gate insulation layer is deleted; with the formation of using 1 road light shield processed pixels electrode with protect film formed photoetch process number to be deleted, can make the liquid crystal indicator of TN types by 3 road light shields.

Liquid crystal image display device according to an aspect of the present invention is to belong to the liquid crystal filling in having at least on the first type surface: the signal wire of the sweep trace of the gate electrode of insulated gate transistor, the above-mentioned insulated gate transistor of double as and also double as source electrode distribution and the unit picture element of pixel electrode on being connected to the drain electrode distribution are become the 1st transparent insulated substrate of two-dimentional matrix etc. by assortment, and and the 2nd transparent insulativity substrate of the above-mentioned the 1st transparent insulated substrate subtend or color filter between and the liquid crystal indicator that constituted it is characterized by:

Be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than 1 layer can anodised metal level constitutes source electrode distribution (signal wire)/drain electrode distribution (pixel electrode), with on gate insulation layer, be formed with a part that contains the sweep trace in the above-mentioned opening portion, by the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

On the electrode terminal of above-mentioned sweep trace and signal wire, on all surfaces of the 1st transparent insulated substrate, be formed with the protection insulation course.

Constitute according to this, the peristome that uses 1 road light shield to handle the island chemical industry preface of semiconductor layer and gate insulation layer forms the photoetch process number of operation and is deleted, can use 4 road light shields to obtain the liquid crystal indicator of IPS type.In addition, because of the thickness of the protection insulation course on the electrode terminal of sweep trace and signal wire is identical, so the undesirable condition relevant with forming contact do not take place.

Liquid crystal image display device according to an aspect of the present invention is characterized by:

At least on a first type surface of the 1st transparent insulated substrate, be formed with in the same manner by the sweep trace that metal level constituted more than 1 layer;

It is overlapping and will become the 2nd semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on above-mentioned the 1st semiconductor layer, removes zone beyond image displaying part and is formed on gate insulation layer in the opening portion on the sweep trace;

Be formed with on above-mentioned the 2nd semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than 1 layer can anodised metal level constitutes source electrode distribution (signal wire)/drain electrode distribution (pixel electrode), with on gate insulation layer, be formed with a part that contains the sweep trace in the above-mentioned peristome, by the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Except that the electrode terminal zone of above-mentioned signal wire, on the surface of source/drain distribution, be formed with anodic oxide coating;

According to this formation; use the formation of 1 road light shield processing source/drain distribution and the photoetch process number of protective seam formation to be deleted; on the passage of source/drain interpolar, form the silicon oxide layer that contains impurity and protect passage, on the surface of signal wire and drain electrode distribution, be formed with the tantalum pentoxide (Ta of the anodic oxide coating that belongs to insulativity simultaneously ₂O ₅) or aluminium oxide (Al ₂O ₃) and give the protective seam function.Therefore, need not apply the protection insulation course on the full surface of glass substrate, the thermotolerance of insulated gate transistor can not become problem.In addition; because of the insulation course of protection passage is that to be transformed into silicon oxide layer by the amorphous silicon layer that anodic oxidation contains impurity obtained; thereby the uncrystalline layer free from foreign meter that does not need to become channel layer is made into thick film, the liquid crystal indicator of realization IPS type.

The manufacture method of liquid crystal indicator according to an aspect of the present invention, it is to belong to the liquid crystal filling: insulated gate transistor on a first type surface, having at least, the sweep trace of the gate electrode of the above-mentioned insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become the 1st transparent insulated substrate of two-dimentional matrix by assortment with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc., and and the 2nd transparent insulativity substrate of the above-mentioned the 1st transparent insulated substrate subtend or color filter between and the manufacture method of the liquid crystal indicator that constituted it is characterized by: have

At least on a first type surface of the 1st transparent insulated substrate, form the sweep trace that is constituted by transparency conducting layer and the 1st metal level and intend the seemingly operation of pixel electrode;

Sequential applications electricity slurry protective seam, gate insulation layer, the 1st amorphous silicon layer free from foreign meter and contain the operation of the 2nd amorphous silicon layer of impurity;

Form the zone and intend at the electrode terminal of sweep trace, form the operation of the thicker photoresist pattern of other regional thickness of Film Thickness Ratio of having on opening portion and the gate electrode like on the pixel electrode;

Remove the 2nd amorphous silicon layer, the 1st amorphous silicon layer, gate insulation layer, electricity slurry protective seam and the 1st metal level in the above-mentioned opening portion, and expose the sweep trace part of transparent conductivity and the operation of pixel electrode;

Reduce the thickness of above-mentioned photoresist pattern and expose the operation of the 2nd amorphous silicon layer;

Island ground forms than wideer the 2nd amorphous silicon layer of gate electrode width and the operation of the 1st amorphous silicon layer on gate electrode;

After applying the 2nd metal level more than 1 layer, on the gate insulation layer and on the 2nd amorphous silicon layer, comprise source electrode (signal wire)/drain electrode distribution and above-mentioned opening portion and by the operation of the electrode terminal of the signal wire that a part was constituted of the electrode terminal of sweep trace and signal wire to be formed with gate electrode with overlapping;

Remove the operation of the 2nd amorphous silicon layer of above-mentioned source/drain wiring closet;

On the full surface of above-mentioned the 1st transparent insulated substrate, form the operation of protection insulation course; And

The operation of optionally removing the protection insulation course forming opening portion on the above-mentioned electrode terminal and on the protection insulation course on the pixel electrode.

According to this formation, deleting of the photoetch process number of realization use 1 road light shield processed pixels electrode and sweep trace, form the deleting of photoetch process number of operation with the opening portion that uses 1 road light shield to handle the island chemical industry preface of semiconductor layer and gate insulation layer, can be by the liquid crystal indicator of 4 road light shield manufacture TN types.Then, because of the thickness of the protection insulation course on the electrode terminal of sweep trace and signal wire is identical, so the undesirable condition relevant with forming contact do not take place.

The manufacture method of liquid crystal indicator according to an aspect of the present invention is characterized by: have

At least on a first type surface of the 1st transparent insulated substrate, form operation by the sweep trace that metal level constituted more than 1 layer;

The gate insulation layer of sequential applications more than 1 layer and the 1st amorphous silicon layer and the operation that contains the 2nd amorphous silicon layer of impurity free from foreign meter;

Electrode terminal at sweep trace forms on the zone, forms the operation of the thicker photoresist pattern of other the regional thickness of Film Thickness Ratio have on opening portion and the gate electrode;

Remove the operation of the 2nd interior amorphous silicon layer of above-mentioned opening portion, the 1st amorphous silicon layer, gate insulation layer;

On the gate insulation layer and on the 2nd amorphous silicon layer, make a part and gate electrode form overlappingly by more than 1 layer can source electrode (signal wire)/drain electrode distribution that anodised metal level constituted operation;

On the gate insulation layer and on the part of above-mentioned drain electrode distribution,, on signal wire, form the operation of the electrode terminal of transparent conductivity in the pixel electrode of transparent conductivity and the zone outside the image displaying part; And

The photoresist pattern that is used in the selectivity pattern of pixel electrodes and electrode terminal is used as mask; the electrode terminal of protection pixel electrode and signal wire, the operation of the amorphous silicon layer of anodic oxidation source/drain distribution and source/drain wiring closet simultaneously.

Constitute according to this, the island chemical industry preface that realizes using 1 road light shield to handle semiconductor layer and the opening portion of gate insulation layer form the deleting of photoetch process number of operation.In addition; for the formation of source/drain distribution and the anodic oxidation of passage and source/drain distribution, can use 1 road light shield to handle the electrode terminal of guard signal line; cause can stop the increase of photoetch process number, thus available 4 road light shield manufacture TN type liquid crystal indicators.

Remove the 2nd amorphous silicon layer, the 1st amorphous silicon layer, gate insulation layer, electricity slurry protective seam and metal level in the above-mentioned opening portion, and expose the sweep trace part of transparent conductivity and the operation of pixel electrode;

Apply more than 1 layer can anodised metal level after, it is overlapping with gate electrode to form a part, and corresponding to the thicker source electrode (signal wire) in other zones of the Film Thickness Ratio on the electrode terminal of sweep trace and signal wire/drain electrode distribution and contain above-mentioned transparent conductivity sweep trace a part and by the operation of the photoresist pattern of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Above-mentioned photoresist pattern is used as mask, and selectivity is removed can anodised metal level and form the operation of the electrode terminal of the electrode terminal of source/drain distribution and sweep trace and signal wire;

Reduce the thickness of above-mentioned photoresist pattern and expose the operation of source/drain distribution; And

Protect above-mentioned electrode terminal, simultaneously the operation of the amorphous silicon layer of anodic oxidation source/drain distribution and source/drain wiring closet.

Follow according to this formation; realize using 1 road light shield to handle the operation of sweep trace and pixel electrode; the photoetch process number that forms operation with the opening portion that uses 1 road light shield to handle semi-conductive island chemical industry preface and gate insulation layer is deleted; in addition; formation for the source/drain distribution; anodic oxidation with passage and source/drain distribution; can use 1 road light shield to handle the electrode terminal of guard signal line; because of can stoping the increase of photoetch process number, so can be with 3 road light shield manufacture TN type liquid crystal indicators.

At least on a first type surface of the 1st transparent insulated substrate, form by the sweep trace that metal level constituted more than 1 layer and the operation of counter electrode;

Remove the operation of the 2nd interior amorphous silicon layer of above-mentioned peristome, the 1st amorphous silicon layer, gate insulation layer;

On gate insulation layer, a part can be formed overlappingly with gate electrode contain the 2nd amorphous silicon layer and by the source electrode that the 2nd metal level constituted (signal wire) more than 1 layer/drain electrode distribution (pixel electrode) with contain above-mentioned opening portion and by the operation of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Remove the operation of the 2nd amorphous silicon layer of above-mentioned source/drain wiring closet; And

Except that the electrode terminal of above-mentioned sweep trace and signal wire, on the full surface of the 1st transparent insulated substrate, form the operation of protection insulation course.

Follow according to this formation, can use 1 road light shield to handle the island chemical industry preface of semiconductor layer and the opening portion of gate insulation layer forms operation, realize deleting the photoetch process number, can be with the liquid crystal indicator of 4 road light shield manufacture IPS types.In addition, less compared with the 4 road light shield processing procedure variation points that in the past quilt rationalizes, import volume production factory easily.

Island ground forms the operation of exposing gate insulation layer than wideer the 2nd amorphous silicon layer of gate electrode width and the 1st amorphous silicon layer on gate electrode;

Electrode terminal at sweep trace forms on the zone, forms the operation that has opening portion and remove the gate insulation layer in the above-mentioned opening portion;

Apply more than 1 layer can anodised metal level after, it is overlapping with gate electrode to form a part, and corresponding to the thicker source electrode (signal wire) in other zones of the Film Thickness Ratio on the electrode terminal of sweep trace and signal wire/drain electrode distribution (pixel electrode) with contain above-mentioned opening portion and by the operation of the photoresist pattern of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Above-mentioned photoresist pattern is used as mask, and selectivity is removed can anodised metal level and form the operation of the electrode terminal of the electrode terminal of source/drain distribution and sweep trace and signal wire; Reduce the thickness of above-mentioned photoresist pattern and expose the operation of source/drain distribution; And one side is protected above-mentioned electrode terminal, the operation of the amorphous silicon layer of one side anodic oxidation source/drain distribution and source/drain wiring closet.

Follow according to this formation, form the silicon oxide layer that contains impurity and protect passage on the passage of source/drain interpolar, the while is formed with the anodic oxide coating of insulativity and gives the protection function on the surface of signal wire and drain electrode distribution.Therefore, need not apply the protection insulation course on the full surface of glass substrate, the thermotolerance of insulated gate transistor can not become problem.In addition; can use 1 road light shield to handle the operation that forms the source/drain distribution; and the electrode terminal of the guard signal line operation of anodic oxidation source/drain distribution simultaneously, realize deleting the photoetch process number, can be with the liquid crystal indicator of 4 road light shield manufacture IPS types.

The manufacture method of liquid crystal indicator according to an aspect of the present invention comprises:

Reduce the thickness of above-mentioned photoresist pattern and expose the operation of source/drain distribution; And one side is protected above-mentioned electrode terminal, the operation of the amorphous silicon layer of while anodic oxidation source/drain distribution and source/drain wiring closet.

According to this formation; the opening portion that uses 1 road light shield to handle the island chemical industry preface of semiconductor layer and gate insulation layer forms the photoetch process number of operation and is deleted; add and to use 1 road light shield to handle the operation that forms the source/drain distribution; also deleted with the photoetch process number of the operation of the electrode terminal of guard signal line anodic oxidation simultaneously source/drain distribution, can be with the liquid crystal indicator of 3 road light shield manufacture IPS types.

Embodiment

According to Fig. 1～Figure 12 embodiments of the invention are described.Fig. 1 is the planimetric map of the related semiconductor device that is used for display device of expression the 1st embodiment of the present invention (initiatively substrate), and Fig. 2 is on the A-A ' line of presentation graphs 1 (f) and on the B-B ' line and the sectional view of the manufacturing process on the C-C ' line.Similarly the 2nd embodiment is with Fig. 3 and Fig. 4, and the 3rd embodiment is with Fig. 5 and Fig. 6, and the 4th embodiment is with Fig. 7 and Fig. 8, and the 5th embodiment is with Fig. 9 and Figure 10, and the 6th embodiment represents the initiatively planimetric map and the manufacturing procedure picture of substrate respectively with Figure 11 and Figure 12.And, at first precedent same area, give same-sign and detailed.

The 1st embodiment

In the 1st embodiment, at first, use SPT equal vacuum film forming apparatus for example on a first type surface of glass substrate 2, to apply ITO as the transparency conducting layer 91 of thickness 0.1～0.2 μ m, for example Cr, Ta, MoW alloy etc. are used as the 1st metal level 92 of thickness 0.1～0.3 μ m, shown in Fig. 1 (a) and Fig. 2 (a), by the sweep trace 11 of Micrometer-Nanometer Processing Technology selectivity formation by the double as gate electrode 11A that lamination constituted of transparency conducting layer 91A and the 1st metal level 92A; By the plan that lamination constituted of transparency conducting layer 91B and the 1st metal level 92B like pixel electrode 93; With by the plan that lamination constituted of transparency conducting layer 91C and the 1st metal level 92C like short-circuit line 94.Between across gate insulation layer the dielectric voltage withstand of signal wire is promoted, though in order to promote these electrodes of turnout preferably carry out section shape with dry-etching inclination control, but in the dry etching technology of ITO when the etching gas of having developed is hydrogen iodide or hydrogen bromide, because of the resultant of reaction accumulating amount of gas exhaust system big, so far be not practical as yet, therefore (argon, sputter-etch argon) gets final product for example should the surface to adopt Ar.

Then, on the full surface of glass substrate 2, apply for example TaOx or the SiO that will become electricity slurry protective seam with the thickness about 0.1 μ m ₂Deng transparent insulating layer 71.This electricity slurry protective seam 71 is when the SiNx of the gate insulation layer of passing through subsequent P CVD device forms; to be exposed to sweep trace 11 or to intend preventing the membranous change of SiNx and required in order to reduce, in detail with reference to first precedent Japanese kokai publication sho 59-9962 communique like transparency conducting layer 91A, the 91B of the end, limit of pixel electrode 93.

After the coating of electricity slurry protective seam 71 is identical with the 1st embodiment; use the PCVD device; with for example thickness sequential applications about 0.2-0.1-0.05 μ m will become gate insulation layer 1SiNx layer 30, will become the 1st amorphous silicon layer 31 of the passage of impure hardly insulated gate transistor, and will become the 3 kind thin layers of the 2nd amorphous silicon layer 33 of the source/drain of the insulated gate transistor that contains impurity.At this, because of gate insulation layer is that lamination by electricity slurry protective seam and 1SiNx layer is constituted, so that the preferred the 1st SiNx layer forms is thinner than first precedent.

Then, except the plan that is formed on image displaying part zone exceptionally like on the short-circuit line 94, form at the electrode terminal of sweep trace 11 and to have opening portion 63A on the zone, with intending having opening portion 74 like on the pixel electrode 93, the formation zone of while insulated gate transistor, promptly the thickness of the regional 84A on the gate electrode 11A is to form for example 2 μ m and photoresist pattern 84A, the 84B thicker than the thickness 1 μ m of other regional 84B by the halftone exposure technology.Then; shown in Fig. 1 (b) and Fig. 2 (b); comprise the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 and gate insulation layer 30 and the electricity slurry protective seam 71 photoresist pattern 84A, 84B being used as mask and exposing; order etching the 1st metal level 92; and the electrode terminal that a part of exposing sweep trace 11 is used as sweep trace forms regional 5A; similarly expose the transparency conducting layer of intending like short-circuit line 94 and be used as short-circuit line 91C (40), expose the transparency conducting layer 91B that intends like pixel electrode 93 and be used as pixel electrode 22.The electrode terminal maximum of sweep trace 11 reaches and drives with about half of the electrode separation of LSI, because of having the above size of 20 μ m usually, so as easy as rolling off a log making also has manageable this to finish the precision of size in order to form the light shield of opening portion 63A (white region).

Then, when the ashing means by oxygen plasma etc. reduce above-mentioned photoresist pattern 84A, 84B thickness more than the 1 μ m, then shown in Fig. 1 (c) and Fig. 2 (c), photoresist pattern 84B disappears, expose the 2nd amorphous silicon layer 33, the while is selectivity formation photoresist pattern 84C on gate electrode 11A only.Photoresist pattern 84C, just the pattern wide cut of island semiconductor layer is because be the size that the mask quality of fit is added the source/drain wiring closet, so when the source/drain wiring closet is made as 4～6 μ m, quality of fit is made as ± during 3 μ m, then become 10～12 μ m, not strict with dimensional accuracy.But, when photoresistance pattern 84A is converted into 84C, if the photoresistance pattern reduces the thickness of 1 μ m to same sex ground, size then not only reduces by 2 μ m, mask quality of fit when follow-up source/drain distribution forms also dwindles 1 μ m and becomes ± 2 μ m, and is more serious than the former influence for the influence of the latter on the processing procedure.Therefore, in above-mentioned oxygen plasma is handled,, serve as preferred to strengthen anisotropy for the variation that suppresses pattern dimension.Particularly, RIE (Reactive Ion Etching) mode, have ICP (the Inductive Coupled Plasama) mode in high-density electric slurry source or the oxygen plasma of TCP (Transfer Coupled Plasama) mode in addition and be treated to the best.Then, shown in Fig. 1 (d) and Fig. 2 (d), photoresist pattern 84C is used as mask optionally becomes wideer and, expose gate insulation layer 30A with the 2nd amorphous silicon layer 33B and the 1st amorphous silicon layer 31B are residual as island 31A, 33A than the width of gate 11 electrodes.Island semiconductor layer 31A, 33A, just the big or small minimum of photoresist pattern 84C (black region) also has 10 μ m, not only make the light shield of the zone beyond white portion and the black region being used as the halftone exposure zone easily, even the dimensional accuracy of island semiconductor layer 31A, 33A change, because of the almost electrical specification change of naked gate type transistor, should carry out the processing procedure management easily so can understand it.

At this moment, the electrode terminal by transparency conducting layer constituted on the glass substrate 2 forms regional 5A, short-term road 91C and pixel electrode 22 is exposed to the open air in etching gas though be exposed to, but the fluorine serial gas that belongs to the etching gas of

amorphous silicon layer

33B, 31B, can not produce the thickness that for example makes these transparency conducting layers reduces, or make resistance change, or make undesirable conditions such as transparency change, comparatively suitable.

After removing above-mentioned photoresist pattern 84C, use for example heating resisting metal thin layer 34 of Ti, Ta etc. the heat resistant metal layer about as thickness 0.1 μ m of SPT equal vacuum film forming apparatus sequential applications, apply the low resistance wiring layer of Al thin layer 35 about then as thickness 0.3 μ m.Then, shown in Fig. 1 (e) and Fig. 2 (e), though by these thin layers of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern order etching, selectivity forms the part comprise pixel electrode 22 and the drain electrode 21 of the insulated gate transistor that is made of 2 layer laminate 34A, 35A and the signal wire 12 of double as source electrode distribution, but it is identical with first precedent at this, order etching the 2nd amorphous silicon layer 33A and the 1st amorphous silicon layer 31A, and the 1st amorphous silicon layer 31A is about residual 0.05～0.1 μ m and etched.And, form source/drain distribution 12,21 o'clock, also form in image displaying part zone exceptionally simultaneously the sweep trace 11 that comprises opening portion 63A a part sweep trace electrode terminal 5 and by the electrode terminal that a part constituted 6 of signal wire 12.And,, if when the restriction of resistance value is not strict, then can be reduced to the individual layer of Ta, Cr, Mo etc. as the formation of source/drain distribution 12,21 at this.

After source/

drain distribution

12,21 forms; identical with 5 road light shield processing procedures in the past; be used as transparent insulation course and be made as protection insulation course 37 at the 2SiNx layer that applies the thickness about 0.3 μ m on the full surface of glass substrate 2; shown in Fig. 1 (f) and Fig. 2 (f); on the

electrode terminal

5,6 of pixel electrode 22 and sweep trace 11 and signal wire 12, optionally respectively form opening

portion

38,63,64, expose the major part of pixel electrode 22 and

electrode terminal

5,6.

Fit the active substrate 2 so obtain and colored filter and make liquid crystal panelization, finish the 1st embodiment of the present invention.Formation about memory capacitance 15; though having between formation across electricity slurry protective seam 71 and gate insulation layer 30A planarity lamination, illustration includes pixel electrode 22 and the example (upper left oblique line portion 52) of the sweep trace 11 of the storage electrode 73 that is formed simultaneously with drain electrode distribution 21 and leading portion toward the bottom right; but the formation of memory capacitance 15 is as limit, also can be and the storage capacitance line that is formed simultaneously of sweep trace and pixel electrode between be situated between and have the structure of the insulation course that comprises gate insulation layer.In addition, though other structure also can, omit detailed explanation.

The 2nd embodiment

The 2nd embodiment is and routine the 1st metal level that at first uses in the same manner about SPT equal vacuum device coating thickness 0.1～0.3 μ m of going ahead of the rest, shown in Fig. 3 (a) and Fig. 4 (a), form also sweep trace 11 and the common electric capacity line 16 of double as gate electrode 11A by the Micrometer-Nanometer Processing Technology selectivity.When considering that the Al monomer lacks thermotolerance, in order to make the sweep trace low resistanceization, can select the lamination of the individual layer formation of Al (Zr, Ta) alloy etc. or Al/Ta, Ta/Al/Ta, Al/Ti, Ti/Al/Ti, Al/Al (Ta, Zr) alloy etc. to constitute as the formation of sweep trace, but in the present invention, the sweep trace material is almost unrestricted.Wherein, Al (Ta, Zr) is the high Al alloy of thermotolerance that following Ta of number % or Zr etc. are added in representative.

Then, use the PCVD device on the full surface of glass substrate 2 for example with the thickness sequential applications about 0.3-0.1-0.05 μ m will become gate insulation layer 1SiNx layer 30, will become the 1st amorphous silicon layer 31 of the passage of impure hardly insulated gate transistor, and will become the 3 kind thin layers of the 2nd amorphous silicon layer 33 of the source/drain of the insulated gate transistor that contains impurity.So that the 1st amorphous silicon layer 31 is compared with the past, can apply thinlyyer, this point also is a speciality of the present invention, its reason is narrated in the back.Then, shown in Fig. 3 (b) and Fig. 4 (b), electrode terminal at sweep trace 11 forms on the zone, has opening portion 63A (form have opening portion 65A on the zone with electrode terminal) at common electric capacity line 16, form the formation zone of insulated gate transistor simultaneously according to the halftone exposure technology, just the thickness of the regional 82A on the gate electrode 11A for example is 2 μ m, with the photoresist pattern 82A thicker than the thickness 1 μ m of other regional 82B, 82B is with photoresist pattern 82A, 82B is used as mask and selectivity is removed the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 and the gate insulation layer 30 in the opening portion 63A (with peristome 65A) and expose sweep trace 11 part 72 of (line 16 is held in energising together).

Then, when the ashing means by oxygen plasma etc. are deleted above-mentioned photoresist pattern 82A, 82B thickness more than the 1 μ m, then shown in Fig. 3 (c) and Fig. 4 (c), photoresist pattern 82B disappears, expose the 2nd amorphous silicon layer 33, the while is selectivity formation photoresist pattern 82C on gate electrode 11A only.At this, shown in Fig. 1 (d) and Fig. 2 (d), photoresist pattern 82C is used as the mask selectivity becomes wideer and be used as island 31A, 33A with the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 are residual than the width of gate 11 electrode A, expose gate insulation layer 30.At this moment, though should be noted that a part 72 that is exposed to the sweep trace 11 in the opening portion 63A is because of being exposed to etching gas or etching agent, so produce the film of sweep trace 11 deletes along with the material of sweep trace 11, even but the situation that has the Al alloy to expose, if the orlop of drain electrode distribution material selects Ti then to avoid the influence of oxidation easily.In addition as described in the example of front, also can adopt and earlier sweep trace 11 is used as for example lamination of Al/Ti/Al,, also can remove Al and method for making that the Ti of lower floor is exposed even the Ti on upper strata disappears.

Remove after the above-mentioned photosensitive resin 82C, use SPT equal vacuum film forming apparatus, the heating resisting metal thin layer 34 of sequential applications Ti, Ta etc. about as thickness 0.1 μ m can anodised heat resistant metal layer, Al thin layer 35 about as thickness 0.3 μ m equally can anodised low resistance wiring layer, about also having heating resisting metal thin layer 36 such as Ta as thickness 0.1 μ m equally can anodised intermediate conductive layer.Then, by the source/drain distribution material that film constituted of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern order etching by these 3 kinds, shown in Fig. 3 (e) and Fig. 4 (e), selectivity forms by the drain electrode (distribution) 21 of the insulated gate transistor that lamination constituted of 34A, 35A, 36A and the also signal wire 12 of double as source electrode (distribution).Selectivity pattern for source/drain distribution 12,21 forms, and as before, does not need etching to contain the 2nd amorphous silicon layer 33A of impurity and the 1st amorphous silicon layer 31A free from foreign meter.And, generally also formed simultaneously in 12,21 o'clock and comprise opening portion 63A forming the source/drain distribution at the electrode terminal 5 of the sweep trace of interior sweep trace 11 parts 72 with by the electrode terminal that a part constituted 6 of signal wire.Formation as the source/drain distribution, when if the restriction of resistance value is not strict, can be simplified then that be made as can anodised Ta individual layer, in addition, the Al alloy that is added with Nd descends because of the chemical current potential, chemical corrosion reaction in the aqueous slkali of imaging liquid or photoresistance stripper etc. and ITO is suppressed, so do not need intermediate conductive layer 36A this moment, the stromatolithic structure of source/drain distribution 12,21 can be made as 2 layers of structure (34A, 35A), the formation of source/drain distribution 12,21 can be simplified.

After forming 12,21 formation of source/drain distribution, use SPT equal vacuum film forming apparatus on the full surface of glass substrate 2, for example apply ITO and be used as transparency conducting layer about thickness 0.1～0.2 μ m, shown in Fig. 3 (f) and Fig. 4 (f), by the Micrometer-Nanometer Processing Technology of usability photosensitiveness resin pattern 83, selectivity forms the pixel electrode 22 of the part of the intermediate conductive layer 36A that comprises drain electrode 21 on gate insulation layer 30.At this moment, also be made as electrode terminal 5A, the 6A of transparent conductivity forming transparency conducting layer on the electrode terminal 5 of sweep trace and on the electrode terminal 6 of signal wire.At this, with the in advance routine identical short-circuit line 40 that transparent conductivity is set, form elongated strip between

electrode terminal

5A, 6A and the short-circuit line 40 by making, then easy high resistance changes into and is the high resistance to antistatic usefulness.

Then, above-mentioned photoresist pattern 83 is used as mask, also anodic oxidation source/

drain distribution

12,21 in the time of irradiates light, and on this surface, form oxide layer, the 2nd amorphous silicon layer 33A that contains impurity that anodic oxidation is simultaneously exposed between source/

drain distribution

12,21, with the part of the 1st amorphous silicon layer 31A free from foreign meter, shown in Fig. 3 (g) and Fig. 4 (g), form the silicon oxide layer (SiO that contains impurity that belongs to insulation course ₂) 66 and silicon oxide layer (not shown) free from foreign meter.

Exposing on source/

drain distribution

12,21 has Ta, exposes the lamination that Ta, Al, Ti are arranged in addition on the side, and going bad by anodic oxidation Ti becomes to belong to semi-conductive titanium dioxide (TiO ₂) 68, the aluminium (Al that Al goes bad and becomes to belong to insulation course ₂O ₃) 69, the Ta tantalum pentoxide (Ta that goes bad and become to belong to insulation course then ₂O ₅) 70.Though titanium oxide layer 68 is not an insulation course, thickness as thin as a wafer, and it is also little to expose area, so for being can not throw into question in the protection, heating resisting metal thin layer 34A also is preferably Ta.But Ta is different with Ti, must be noted that the surface oxide layer at the bottom of its absorption base and is short of the characteristic of the function that becomes Ohmic contact easily.

Interchannel the 2nd crystalloid silicon layer 33A that contains impurity causes the leakage current that increases insulated gate transistor when in the complete on-insulated stratification of thickness direction.At this, implement anodic oxidation in the time of irradiates light, be very important main points for the anodic oxidation operation, in the example announcement is being arranged also in advance.Particularly, if the great light of irradiation about 1 myriametre candle light, if the leakage current of insulated gate transistor then calculates from the channel part of 12,21 of source/drain distributions and the area of drain electrode 21 when surpassing μ, is 10m/cm ²About anodic oxidation can be for obtaining good membranous current density.

In addition, utilize anodic oxidation to contain the 2nd amorphous silicon layer 33A of impurity, and voltage is set the formation voltage 100V of the silicon oxide layer 66 that becomes to belong to insulation course than enough going bad for and is also exceeded about 10V, to be contacted with contain set response voltage the part of the 1st amorphous silicon layer 31A free from foreign meter of the silicon oxide layer 66 of the formed impurity of high voltage (

About) till, making and go bad into silicon oxide layer (not shown) free from foreign meter, the electrical purity raising by this passage can make electrically separating fully of 12,21 of source/drain distributions.Just, the OFF electric current of insulated gate transistor fully reduces, and can obtain high ON/OFF ratio.

Thickness by each oxide layer of the formed tantalum pentoxide 70 of anodic oxidation, aluminium 69, titanium dioxide 68 is just enough with the protective seam of being used as distribution about 0.1～0.2 μ m, makes the treating fluid of spent glycol etc., applies voltage and surpasses 100V equally.The item that should be careful for the anodic oxidation of source/

drain distribution

12,21, though it is not shown, but all signal wires 12 are parallel connection or series connection electrically, certainly must remove parallel-series in certain of manufacturing process afterwards, otherwise not only to the electric checking of active substrate 2, even also can cause obstacle for the actual act of liquid crystal indicator.As the releasing means, can be by the evapotranspiring of irradiating laser light, or the simple and easy means such as mechanicalness excision by scraping blade, in this detailed.

Covering pixel electrode 22 with photoresist pattern 83, is because not only do not need anodic oxidation pixel electrode 22, does not need also to guarantee that the above kinetic current that flows in drain electrode 21 via insulation gate transistor of aequum gets final product.

At last, remove above-mentioned photoresist pattern 83, shown in Fig. 3 (h) and Fig. 4 (h), finish initiatively substrate 2 (semiconductor device that is used for display device).Fit the active substrate 2 of gained like this and colored filter and make liquid crystal panelization are finished the 1st embodiment of the present invention.Formation about memory capacitance 15, though as Fig. 3 (h) exemplary illustrate configuration example (upper left oblique line portion 51 toward the bottom right) across overlapping storage capacitance line 16 of gate insulation layer 30 planarityes and pixel electrode 22 arranged between formation, but the formation of memory capacitance 15 is not limited to this, and the formation have the insulation course that comprises gate insulation layer 30 of being situated between between the sweep trace 11 of pixel electrode 22 and epimere is also passable.In addition, other formation also can, but omit detailed explanation.

Though be among the 2nd embodiment for island chemical industry preface as semiconductor layer, with in order to form sweep trace contact remove the low layer of pattern precision that electrode terminal forms the operation of the gate insulation layer on the zone, be suitable for the halftone exposure technology and carry out deleting of photoetch operation, with 4 road light shield manufactures active substrates, but as adopting among the 1st embodiment, cause is by the attached technology that gives the formation of identical light shield processed pixels electrode and sweep trace, then more can promote operation to delete and with 3 road light shield manufactures substrates initiatively, thereby with the 3rd embodiment explanation.

The 3rd embodiment

The 3rd embodiment is shown in Fig. 5 (d) and Fig. 6 (d), to semi-conductive island chemical industry preface with contact operation till be to carry out with the processing procedure identical with the 1st embodiment.Utilize the halftone exposure technology to form then, after removing the above-mentioned photoresist pattern 84C that is cut down thickness, use SPT equal vacuum film forming apparatus, sequential applications for example heating resisting metal such as Ti, Ta thin layer 34 about as thickness 0.1 μ m can anodised heat resistant metal layer, Al thin layer 35 about as thickness 0.3 μ m equally can anodised low resistance wiring layer.Then shown in Fig. 5 (e) and Fig. 6 (e), by the etching of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 85A～85D order by source/drain wiring material that these films constituted, and selectivity form comprise opening portion 74 the part of interior pixel electrode 22 by the drain electrode 21 of the insulated gate transistor that lamination constituted of 34A and 35A and the equally also signal wire 12 of double as source electrode.Though when source/drain distribution 12,21 forms, also form simultaneously and comprise the electrode terminal 5 that the electrode terminal that is made of transparency conducting layer forms the sweep trace of regional 5A, with the electrode terminal that a part constituted 6 by signal wire, but be 3 μ m by the formation in advance of halftone exposure technology corresponding to the thickness (black region) of regional 85A, the 85B of electrode terminal 5,6 this moment, with than the thicker photoresist pattern 85A～85D of thickness 1.5 μ m of regional 85C, 85D (middle tone zone) corresponding to drain electrode distribution 12,21, be key character of the present invention.Though the minimum dimension corresponding to regional 85A, the 85B of electrode terminal 5,6 has tens of μ m big, size is finished in also as easy as rolling off a log management for light shield manufacture, but because of the minimum dimension corresponding to regional 85C, the 85D of source/drain distribution 12,21 is that the dimension precision requirement of 4～8 μ m is than higher, so be to need the tiny thin patterns of seam for half-tone regions.But, in the present invention, source/drain distribution 12,21 is because of forming with 1 exposure-processed and 1 etch processes, so compared with halftone exposure technology in the past, with compare with 2 formed occasions of etch processes with 1 exposure-processed, the no matter size of source/drain distribution 12,21 management, still between the source/drain distribution 12,21, just the long size of passage is managed all than the manageable pattern precision of halftone exposure technology in the past.

After source/

drain distribution

12,21 forms, when ashing means by oxygen plasma etc., when above-mentioned photoresist pattern 85A～85D is reduced thickness more than the 1.5 μ m,

photoresist pattern

85C, 85D then disappear and expose source/

drain distribution

12,21, simultaneously can be only on

electrode terminal

5,6, selectivity forms photoresist pattern 85E, 85F.Also can understand easily from the size of

electrode terminal

5,6, the situation that influences pattern dimension here by the oxygen plasma processing hardly also is a feature of the present invention.At this, shown in Fig. 5 (f) and Fig. 6 (f),

photoresist pattern

85E, 85F are used as mask, with the 2nd embodiment in the same manner, irradiates light, anodic oxidation source/

drain distribution

12,21 and

form oxide layer

68,69 simultaneously, the part of the 2nd amorphous silicon layer 33A that anodic oxidation is simultaneously exposed between source/

drain distribution

12,21 and the 1st amorphous silicon layer 31A of adjacency, and form the silicon oxide layer (not shown) that belongs to the silicon oxide layer that contains impurity 66 of insulation course and do not contain impurity.

After anodic oxidation is finished, remove photoresist pattern 85E, 85F, shown in Fig. 5 (g) and Fig. 6 (g), have anodic oxide coating in this side, expose the electrode terminal 5,6 that constitutes by low resistance metal layer.But for to antistatic, electrode terminal forms regional 5A and is connected for example short-circuit line 91C, and as shown, if not electrode terminal 6 comprises short-circuit line 91C and is formed, does not then form anodic oxide coating on the side of electrode terminal 5.And, with source/drain distribution 12-, 21 formation, the undemanding words of the restriction of resistance value, then can be simplified can be made as can anodised Ta individual layer.Fit the active substrate 2 of gained like this and colored filter and make liquid crystal panelization are finished the 2nd embodiment of the present invention.Formation about memory capacitance 15; though as Fig. 5 (g) illustrate for example between formation across the lamination of electricity slurry protective seam 71A and gate insulation layer 30A and the overlapping part that includes pixel electrode 22 of planarity simultaneously and source/drain distribution 12; 21 storage electrodes that form 73 and the configuration example that is formed on the raised areas of leading portion sweep trace 11 (upper left oblique line portion 52) toward the bottom right; but the formation of memory capacitance 15 is not limited to this; identical with the 2nd embodiment, pixel electrode 22 and and the common electric capacity line 16 that forms simultaneously of sweep trace 11 between the formation that has the insulation course that comprises gate insulation layer 30A that is situated between also be fine.In addition, other formation also can, but omit detailed explanation.

Among the 3rd embodiment, because of so when the anodic oxidation of source/drain 12,21 and the 2nd amorphous silicon layer 33A, the pixel electrode 22 that is electrically connected drain electrode 21 also exposes, thus pixel electrode 22 simultaneously also by anodic oxidation, this point then has very big-difference with the 1st embodiment.Therefore, membranous difference along with the transparency conducting layer that constitutes pixel electrode 22 is also arranged, the situation that increases resistance value by anodic oxidation also can take place, at this moment, though must suitably change the film forming condition of transparency conducting layer, prepare the membranous of hypoxgia in advance, but can not reduce the situation of the transparency of transparency conducting layer in anodic oxidation.In addition, though the electric current in order to anodic oxidation drain electrode 21 and pixel electrode 22 also is supplied to by the passage of insulated gate transistor, but because the area of pixel electrode 22 is big, so need bigger oxidation current or oxidation for a long time, even light can not cause obstacle to the resistance of channel part yet outside irradiation was many strong, for form on the drain electrode 21 and on the storage electrode 73 with signal wire 12 on the anodic oxide coating of equal membranous and thickness, be not enough only with the prolongation oxidization time.But, even the anodic oxide coating that is formed on the drain electrode 21 is more or less incomplete, many trustworthinesses that can obtain that nothing serious in practicality.Be essentially interchange because be applied in the drive signal of liquid crystal cells, in order to make between counter electrode 14 and pixel electrode 22 (drain electrode 21), can reduce the DC voltage composition, the voltage of counter electrode 14 is adjusted (reducing the adjustment of flicker) when image is checked, therefore, no flip-flop is flowed and form insulation course and get final product.

Though liquid crystal indicator discussed above is to use the liquid crystal cells of TN type, but the liquid crystal indicator of the transverse electric field of IPS (In-Plain-Swticing) mode control to(for) a pair of counter electrode that forms to be separated by predetermined distance and pixel electrode with pixel electrode, the operation that the present invention suggested plans is deleted also effective, with afterwards embodiment explanation.

The 4th embodiment

The 4th embodiment at first uses SPT equal vacuum film forming apparatus on a first type surface of glass substrate 2, apply the 1st metal level about thickness 0.1～0.3 μ m, shown in Fig. 7 (a) and Fig. 8 (a), form also sweep trace 11 and the common electric capacity line 16 of double as gate electrode 11A by the Micrometer-Nanometer Processing Technology selectivity.

Then, use the PCVD device on the full surface of glass substrate 2 for example with the thickness sequential applications about 0.3-0.2-0.05 μ m will become gate insulation layer 1SiNx layer 30, will become the 1st amorphous silicon layer 31 of the passage of impure hardly insulated gate transistor, and will become the 3 kind thin layers of the 2nd amorphous silicon layer 33 of the source/drain of the insulated gate transistor that contains impurity.

Then, electrode terminal at sweep trace 11 forms on the zone, by the halftone exposure technology, formation has the opening portion 63A formation zone of insulated gate transistor simultaneously, that is the thickness of the regional 82A on the gate electrode 11A is for example 2 μ m, with the thicker photoresist pattern 82A of thickness than the 1 μ m of other regional 82B, 82B, shown in Fig. 7 (b) and Fig. 8 (b), with

photoresist pattern

82A, 82B is used as mask and selectivity is removed the 2nd amorphous silicon layer 33 in the peristome 63A and the 1st amorphous silicon layer 31 and gate insulation layer 30 and expose the part 72 of sweep trace 11.

Then, when the ashing means by oxygen plasma etc. are cut down above-mentioned

photoresist pattern

82A, 82B thickness more than the 1 μ m, then shown in Fig. 7 (c) and Fig. 8 (c), photoresist pattern 82B disappears, expose the 2nd amorphous silicon layer 33, the while is selectivity formation photoresist pattern 82C on gate electrode 11A only.At this, shown in Fig. 7 (d) and Fig. 8 (d), photoresist pattern 82C is used as mask optionally becomes wideer and form

island

31A, 33A with the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 are residual than the width of gate 11 electrode A, expose gate insulation layer 30.

Remove after the above-mentioned photosensitive resin 82C, use SPT equal vacuum film forming apparatus, sequential applications is the heat resistant metal layer of heating resisting metal such as Ti, Ta thin layer 34 about as thickness 0.1 μ m for example, the low resistance wiring layer of Al thin layer 35 about as thickness 0.3 μ m.Then, though shown in Fig. 7 (e) and Fig. 8 (e), by the etching of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern order by source/drain distribution material that these films constituted, selectivity forms by the drain electrode (distribution) 21 of the insulated gate transistor that becomes pixel electrode that lamination constituted of 34A, 35A and the also signal wire 12 of double as source electrode (distribution), but, identical at this with the example of going ahead of the rest, order etching the 2nd amorphous silicon layer 33A and the 1st amorphous silicon layer 31A, the 1st amorphous silicon layer 31A are etched into remaining 0.05～0.1 μ m degree.And, generally also formed simultaneously in 12,21 o'clock and comprise opening portion 63A forming the source/drain distribution at the electrode terminal 5 of the sweep trace of interior sweep trace 11 parts with by the electrode terminal that a part constituted 6 of signal wire 12.And, in the formation of this source/drain distribution 12,21 if the restriction of resistance value and undemanding words, then can be simplified be made as can anodised Ta, Cr, the individual layer of Mo etc.

After source/

drain distribution

12,21 forms; identical with five road light shield processing procedures in the past; the 2SiNx layer that applies 0.3 μ m left and right sides thickness on the full surface of glass substrate 2 is used as the protection insulation course; shown in Fig. 7 (f) and Fig. 8 (f); on the

electrode terminal

5,6 of sweep trace 11 and signal wire 12, optionally form opening

portion

63,64 and expose the major part of

electrode terminal

5,6, finish initiatively substrate 2.

Fit the active substrate 2 so obtain and colored filter and make liquid crystal panelization, finish the 4th embodiment of the present invention.The liquid crystal indicator of IPS type does not need the pixel electrode 22 of transparent conductivity by above explanation obviously as can be known on active substrate 2, therefore, do not need the intermediate conductive layer on the source/drain distribution yet.Formation about memory capacitance 15, though the example (upper left oblique line portion 52 toward the bottom right) that counter electrode (storage capacitance line) 16 and pixel electrode (drain electrode) 21 is situated between and has gate insulation layer 30 and constitute is shown for example in Fig. 7 (f), but the formation of memory capacitance 15 is not limited to this, has the insulation course that contains gate insulation layer 30 and also is fine even be situated between between the sweep trace 11 of pixel electrode 21 and leading portion.And, in Fig. 7 (f), though with the high resistance member, the for example insulated gate transistor of OFF state or elongated electric conductivity circuit, static gas scheme between the electrode terminal 5 of connection sweep trace and the electrode terminal 6 of signal wire is also not shown, but because of the operation of a part 72 that opening portion 63A is set and exposes sweep trace 11 is arranged, so easily to antistatic.

Among the 4th embodiment because of protective seam to active substrate 2; the nitrided silicon layer (SiNx) that employing is produced with the identical use of the example PCVD device of going ahead of the rest; so in existing volume production workshop; there is the processing procedure variation point less; the easy advantage that imports; at this also identical operation and the cost degradation that can further delete by the anodised resist technology of source/drain, by the 5th and the 6th embodiment explanation with the 3rd embodiment.

The 5th embodiment

The 5th embodiment also is to use SPT equal vacuum film forming apparatus earlier on a first type surface of glass substrate 2, apply the 1st metal level about thickness 0.1～0.3 μ m, shown in Fig. 9 (a) and Figure 10 (a), form also sweep trace 11 and the counter electrode 16 of double as gate electrode 11A by the Micrometer-Nanometer Processing Technology selectivity.

Then, use the PCVD device on the full surface of glass substrate 2, for example with the thickness about 0.3-0.1-0.05 μ m, sequential applications will become gate insulation layer the 1st SiNx layer 30, will become the 1st amorphous silicon layer 31 of the passage of impure hardly insulated gate transistor, and will become the 3 kind thin layers of the 2nd amorphous silicon layer 33 of the source/drain of the insulated gate transistor that contains impurity.

Then, shown in Fig. 9 (b) and Figure 10 (b), remove the 2nd amorphous silicon layer 33 and the 1st amorphous silicon layer 31 by the Micrometer-Nanometer Processing Technology selectivity, and formation is exposed gate insulation layer 30 than wideer island semiconductor layer 31A, the 33A of the width of gate 11 electrode A on gate electrode 11A.

Then, shown in Fig. 9 (c) and Figure 10 (c), form at the electrode terminal of sweep trace 11 by Micrometer-Nanometer Processing Technology and to form opening portion 63A on the zone, selectivity is removed the gate insulation layer 30 in the peristome 63A and is exposed the part 72 of sweep trace 11.

And, use SPT equal vacuum film forming apparatus, heating resisting metal such as sequential applications Ti, Ta thin layer 34 about as thickness 0.1 μ m can anodised heat resistant metal layer, Al thin layer 35 about as thickness 0.3 μ m equally can anodised low resistance wiring layer.Then, shown in Fig. 9 (d) and Figure 10 (d), by the etching of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 85A～85D order by source/drain wiring material that these films constituted, selectivity forms by the drain electrode 21 of the insulated gate transistor that will become pixel electrode that lamination constituted of 34A and 35A and the also signal wire 12 of double as source electrode 11A.Forming source/drain distribution 12,21 o'clock, though also form simultaneously and comprise the part 72 of opening portion 63A at interior sweep trace 11, by the electrode terminal 5 of sweep trace and the electrode terminal that a part constituted 6 of signal wire, but this moment, identical with the 3rd embodiment, according to the halftone exposure technology, the thickness (black region) of regional 85A, the 85B of the electrode terminal 5,6 that forms is for example 3 μ m, and ratio is corresponding to the thicker photoresist pattern 85A～85D of thickness 1.5 μ m of regional 85C, the 85D (middle tone zone) of drain electrode distribution 12,21.

After source/

drain distribution

12,21 forms, when ashing means by oxygen plasma etc., when above-mentioned photoresist pattern 85A～85D is cut down thickness more than the 1.5 μ m,

photoresist pattern

85C, 85D then disappear and expose source/

drain distribution

12,21, simultaneously can be only on the electrode terminal 5 and on the electrode terminal 6, selectivity forms photoresist pattern 85E, 85F.At this, shown in Fig. 9 (e) and Figure 10 (e),

photoresist pattern

85E, 85F are used as mask, an irradiates light, one side anodic oxidation source/

drain distribution

12,21 and form

anodic oxide coating

68,69 on described surface, the 2nd an amorphous silicon layer 33A that anodic oxidation is simultaneously exposed between source/

drain distribution

12,21 and the part of the 1st amorphous silicon layer 31A, and form the silicon oxide layer (not shown) that belongs to the silicon oxide layer that contains impurity 66 of insulation course and do not contain impurity.

After anodic oxidation is finished, when removing

photoresist pattern

85E, 85F, then shown in Fig. 9 (f) and Figure 10 (f), expose the electrode terminal 5 and the electrode terminal 6 that are constituted by the low resistance thin film layer.But, though on the side of the electrode terminal 6 of signal wire 12 with the signal wire 12 identical

anodic oxide coatings

69,68 that are formed with,, be careful on the side of the electrode terminal 5 of sweep trace and do not form anodic oxide coating.This is independently to give anodised cause for the electrode terminal 5 that makes sweep trace, as described in the 2nd embodiment, for to antistatic, when giving anodic oxidation, on the side of the electrode terminal 5 of sweep trace, also only form the segment anode oxide layer when the electrode terminal 6 of electrode terminal 5 that connects sweep trace with the resistive member and signal wire.With the resistive member, because IPS type liquid crystal indicator does not need transparency conducting layer, so need any one in sweep trace material, signal line material and the semiconductor layer, but because have in order to be connected in the opening portion 63A of sweep trace 11, so also unrestricted for which is selected, detailed.

Fit the active substrate 2 so obtain and colored filter and give liquid crystal panelization, finish the 4th embodiment of the present invention.About the formation of memory capacitance 15, show the example that counter electrode (storage capacitance line) 16 and pixel electrode (drain electrode) 21 is situated between and has gate insulation layer 30 and constitute in Fig. 9 (f) example of passing the imperial examinations at the provincial level.

Rationalization except the formation opening portion of the island chemical industry preface of the semiconductor layer that adopted among the 4th embodiment and gate insulation layer; also can adopt the embodiment of rationalization of the formation protection insulation course of the source/drain distribution among the 5th embodiment simultaneously, this is used as the 6th embodiment be illustrated.

The 6th embodiment

The 6th embodiment shown in Figure 11 (d) and Figure 12 (d), at the island chemical industry preface of semiconductor layer with form the operation that contacts till the operation, carry out with almost identical processing procedure with the 4th embodiment.Then, formation operation for the source/drain distribution, then use SPT equal vacuum film forming apparatus, sequential applications for example heating resisting metal such as Ti, Ta thin layer 34 about as thickness 0.1 μ m can anodised heat resistant metal layer, Al thin layer 35 about as thickness 0.3 μ m equally can anodised low resistance wiring layer.Then shown in Figure 11 (e) and Figure 12 (e), by the etching of Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 85A～85D order by source/drain wiring material that these films constituted, and the lamination that optionally forms by 34A and 35A is constituted, to become the drain electrode 21 of the insulated gate transistor of pixel electrode, the equally also signal wire 12 of double as source electrode, forming source/drain distribution 12,21 o'clock, also formation comprises the part of opening portion 63A at interior sweep trace 11 simultaneously, by the electrode terminal 5 of sweep trace and the electrode terminal that a part constituted 6 of signal wire.This moment is identical with the 5th embodiment, the thickness that forms on the electrode terminal 5,6 by the halftone exposure technology for example is regional 85A, the 85B of 3 μ m, and ratio is corresponding to the thicker photoresist pattern 85A～85D of thickness 1.5 μ m of regional 85C, the 85D of drain electrode distribution 12,21.

After source/

drain distribution

12,21 forms, ashing means by oxygen plasma etc., when above-mentioned photoresist pattern 85A～85D is cut down thickness more than the 1.5 μ m,

photoresist pattern

85C, 85D then disappear and expose source/

drain distribution

12,21, simultaneously can be only on the electrode terminal 5 and on the electrode terminal 6, selectivity forms photoresist pattern 85E, 85F.At this, shown in Figure 11 (f) and Figure 12 (f),

photoresist pattern

85E, 85F are used as mask, anodic oxidation source/

drain distribution

12,21 in the time of irradiates light and

form oxide layer

68,69, the 2nd an amorphous silicon layer 33A that anodic oxidation is simultaneously exposed between source/

drain distribution

After anodic oxidation is finished, when removing

photoresist pattern

85E, 85F, then shown in Figure 11 (g) and Figure 12 (g), expose the electrode terminal 5 and the electrode terminal 6 that are constituted by the low resistance thin film layer.Fit the active substrate 2 so obtain and colored filter and make liquid crystal panelization, finish the 5th embodiment of the present invention.About the formation of memory capacitance 15, between showing between counter electrode (storage capacitance line) 16 and the pixel electrode (drain electrode) 21 for example, Figure 11 (g) is separated with the formation example of gate insulation layer 30.

Though employed light shield respectively is 4 roads, 3 roads in the 5th embodiment and the 6th embodiment, the liquid crystal indicator that is obtained is indifference almost.Described difference also only is exposed to the film that the electrode terminal that is formed on sweep trace forms the part of the sweep trace in the opening portion on the zone and is deleted or envenomation.That is to say that the 6th embodiment can more advance one deck and reduce operation.

The invention effect

As mentioned above, the part of the liquid crystal display that the present invention puts down in writing, because of the while anodic oxidation by can The source/drain distribution that anodised source/drain wiring material consists of and insulated-gate type crystal The channel surface of pipe, and form protective layer (passivation layer), thus extra heating process, non-Crystal silicon does not need excessive heat resistance as the insulated gate transistor of semiconductor layer. In other words, with shape Become the protection effect then to be attached with and do not produce the effect that electric property worsens. In addition, for source/drain The anodic oxidation of distribution, by importing the halftone exposure technology, then alternative is protected scan line or letter The electrode terminal of number line is obtained and can be stoped the effect that increases the photoetch process number.

And because contain the amorphous silicon layer of impurity with anodic oxidation, making to become the insulated-gate type crystal 1 couple of the source/drain of pipe is contained the electrochemistry that the insulated separation of the amorphous silicon layer of impurity is gone bad Method, thus can be as not in the past, can cause because of the damage the during etching of passage semiconductor layer The possibility that the electric characteristics of insulated gate transistor worsens, in addition, because can becoming passage not Impure amorphous silicon layer reduces to optimal thickness and is filmed, so relevant PCVD device Running rate and particle situation occurred also be significantly improved.

In addition, can process semiconductor layer by importing the halftone exposure technology with identical light shield The opening portion of island chemical industry order and gate insulation layer forms operation, can reduce operation, intends by importing Like pixel electrode, use identical light shield to form simultaneously the rationalization of pixel electrode and scan line etc., lead to Cross and delete operation and rationalize 5 roads then the photoetch process number can be deleted into than in the past lower, make Make liquid crystal indicator with 4 roads or 3 road light shields, even from the cost viewpoint of liquid crystal indicator It also is important feature. And the pattern precision of these operations is not such height, so yet Can very big impact not arranged to output or quality, carry out easily production management.

And, in the liquid crystal indicator of the IPS type of the 5th and the 6th embodiment, result from subtend Electric field between electrode and the pixel electrode, because being applied in gate insulation layer and anodic oxide coating, so The protection insulating barrier of the poor quality as existing in the past that is not situated between also has to be not easy to produce to show that burning of image is residual The advantage of shadow phenomenon. This be because the drain electrode distribution (pixel electrode) anodic oxide coating because not being used as Insulating barrier but bring into play function as resistive formation is not so produce stored charge.

And, main points of the present invention by above-mentioned explanation obviously as can be known, at the insulated gate of channel etch type In the transistor npn npn, use can anodised source/drain wiring material, with the amorphous that contains impurity Side by side also to the oxidation of source/drain jumper list surface anode, wherein any one all makes insulating barrier to silicon layer The point of changing, about formation in addition, the material of pixel electrode, gate insulation layer etc. or thickness etc. For different liquid crystal indicators or the difference of this manufacture method also belongs to category of the present invention, even Be reflection-type liquid-crystal display device, application of the present invention can not change yet, in addition, and the insulated-gate type crystalline substance The semiconductor layer of body pipe also is not limited to non-crystalline silicon.

The accompanying drawing simple declaration

Fig. 1 is the planimetric map of the related semiconductor device that is used for display device of the 1st embodiment of the present invention;

Fig. 2 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 1st embodiment of the present invention;

Fig. 3 is the planimetric map of the related semiconductor device that is used for display device of the 2nd embodiment of the present invention;

Fig. 4 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 2nd embodiment of the present invention;

Fig. 5 is the planimetric map of the related semiconductor device that is used for display device of the 3rd embodiment of the present invention;

Fig. 6 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 3rd embodiment of the present invention;

Fig. 7 is the planimetric map of the related semiconductor device that is used for display device of the 4th embodiment of the present invention;

Fig. 8 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 4th embodiment of the present invention;

Fig. 9 is the planimetric map of the related semiconductor device that is used for display device of the 5th embodiment of the present invention;

Figure 10 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 5th embodiment of the present invention;

Figure 11 is the planimetric map of the related semiconductor device that is used for display device of the 6th embodiment of the present invention;

Figure 12 is manufacturing process's sectional view of the related semiconductor device that is used for display device of the 6th embodiment of the present invention;

Figure 13 is the installment state of expression liquid crystal panel;

Figure 14 is the equivalent circuit diagram of liquid crystal panel;

Figure 15 is the sectional view of available liquid crystal panel;

Figure 16 is the planimetric map of the active substrate of example in advance;

Figure 17 is manufacturing process's sectional view of the active substrate of example in advance;

The planimetric map of the active substrate that Figure 18 is rationalized;

Manufacturing process's sectional view of the active substrate that Figure 19 is rationalized.

Symbol description

1: liquid crystal panel

2: active substrate (glass substrate)

3: semiconductor integrated circuit wafer

The 4:TCP film

5,6: electrode terminal

9: colored filter (glass substrate in opposite directions)

10: insulated gate transistor

11: sweep trace (gate distribution, gate electrode)

12: signal wire (source electrode distribution, source electrode)

16: common electric capacity line (being counter electrode in the IPS type)

17: liquid crystal

19: Polarizer

20: alignment film

21: drain electrode (the drain electrode distribution is pixel electrode in the IPS type)

The 22:(transparent conductivity) pixel electrode

30: gate insulation layer

31: (the 1st) amorphous silicon layer free from foreign meter

33: (the 2nd) amorphous silicon layer that contains impurity

31A, 33A: island semiconductor layer

31B, 33B: amorphous silicon layer

34:(can be anodised) heat resistant metal layer

35:(can be anodised) low resistance metal layer (Al)

36:(can be anodised) intermediate conductive layer

37: the protection insulation course

63: peristome

71: electricity slurry protective seam

74: peristome

84: the photoresist pattern

91: transparency conducting layer

92: the 1 metal levels

93: pixel electrode

94: short-circuit line

Claims

1. the insulated gate transistor of a bottom gate type is characterized by:

Be formed with on the insulated substrate by the gate electrode that the first metal layer constituted more than one deck, gate insulation layer between on the gate electrode more than one deck and form island and first semiconductor layer free from foreign meter, it is overlapping and will become second semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on described first semiconductor layer, form on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes the source/drain distribution, and except that the electric property join domain of source electrode distribution, at source electrode, be formed with anodic oxide coating on the drain electrode distribution with on the passage.

2. liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the liquid crystal indicator that constitutes with the first transparent insulated substrate, wherein have at least on the first type surface of the described first transparent insulated substrate: the signal wire of the sweep trace of the gate electrode of insulated gate transistor, the described insulated gate transistor of double as and also double as source electrode distribution is become two-dimentional matrix with the unit picture element of pixel electrode etc. on being connected to the drain electrode distribution by assortment, it is characterized in that:

At least on a first type surface of the first transparent insulated substrate, be formed with by the sweep trace that lamination constituted of transparency conducting layer and metal level and the pixel electrode of transparent conductivity;

Form island and first semiconductor layer free from foreign meter across electricity slurry protective seam and gate insulation layer between on the gate electrode;

It is overlapping and will become second semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on described first semiconductor layer;

On slurry protective seam of the electricity on the described pixel electrode and gate insulation layer, be formed with opening portion;

Be formed with on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode distribution (signal wire) and on described second semiconductor layer and on the gate insulation layer and on the part of the pixel electrode in the described opening portion, similarly be formed with the drain electrode distribution; And

The protection insulation course that on described pixel electrode, has opening portion, and described protection insulation course is to be formed on the first transparent insulated substrate.

3. liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the liquid crystal indicator that constitutes with the first transparent insulated substrate, wherein have at least on the first type surface of the described first transparent insulated substrate: the signal wire of the sweep trace of the gate electrode of insulated gate transistor, the described insulated gate transistor of double as and also double as source electrode distribution is become two-dimentional matrix with the unit picture element of pixel electrode etc. on being connected to the drain electrode distribution by assortment, it is characterized in that:

At least on a first type surface of the first transparent insulated substrate, be formed with by the sweep trace that metal level constituted more than one deck;

Gate insulation layer between on the gate electrode more than one deck and form island and first semiconductor layer free from foreign meter;

It is overlapping and will become second semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part layer by layer at described first semiconductor;

Be formed with on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode (signal wire)/drain electrode distribution;

On the described drain electrode distribution and on the gate insulation layer,, on signal wire, be formed with the electrode terminal of transparent conductivity in the pixel electrode of transparent conductivity and the zone outside the image displaying part;

Except that with described drain electrode distribution on the pixel electrode overlapping areas and the electrode terminal zone of signal wire, on the surface of source/drain distribution, be formed with anodic oxide coating; And

On first semiconductor layer of described source/drain wiring closet, be formed with silicon oxide layer.

4. liquid crystal indicator, be with the liquid crystal filling in the first transparent insulated substrate and and the second transparent insulativity substrate of the described first transparent insulated substrate subtend or color filter between and the liquid crystal indicator that constitutes, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized by:

Be formed with on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode distribution (signal wire) and on described second semiconductor layer and on the gate insulation layer and on the part of the pixel electrode in the described opening portion, similarly be formed with the drain electrode distribution;

Except that the electrode terminal zone of described signal wire, be formed with anodic oxide coating on the surface of source/drain distribution; And

5. liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the liquid crystal indicator that constitutes with the described first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that:

Be formed with on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode distribution (signal wire)/drain electrode distribution (pixel electrode), with a part that on gate insulation layer, is formed with the sweep trace that contains described opening portion, by the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire; And

On the electrode terminal of described sweep trace and signal wire, on the full surface of the first transparent insulated substrate, be formed with the protection insulation course.

6. liquid crystal indicator, be to belong to the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the liquid crystal indicator that constitutes with the first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that:

It is overlapping and will become second semiconductor layer that contains impurity of the source/drain of insulated gate transistor with gate electrode to be formed with a part on described first semiconductor layer, removes zone beyond image displaying part and is formed on gate insulation layer in the opening portion on the sweep trace;

Be formed with on described second semiconductor layer and on the gate insulation layer contain heat resistant metal layer and by more than one deck can anodised metal level constitutes source electrode distribution (signal wire)/drain electrode distribution (pixel electrode), with a part that on gate insulation layer, is formed with the sweep trace that contains described opening portion, by the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Except that the electrode terminal zone of described signal wire, on the surface of source/drain distribution, be formed with anodic oxide coating; And

7. the manufacture method of a liquid crystal indicator, be to belong to the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with this first transparent insulated substrate, wherein on a described first type surface, have at least: insulated gate transistor at the first transparent insulated substrate, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that having

On a first type surface of the first transparent insulated substrate, form by sweep trace that transparency conducting layer and the first metal layer constituted and the operation of intending like pixel electrode;

Sequential applications electricity slurry protective seam, gate insulation layer, first amorphous silicon layer free from foreign meter and contain the operation of second amorphous silicon layer of impurity;

Remove second amorphous silicon layer, first amorphous silicon layer, gate insulation layer, electricity slurry protective seam and the first metal layer in the described opening portion, and expose the sweep trace part of transparent conductivity and the operation of pixel electrode;

Reduce the thickness of described photoresist pattern and expose the operation of second amorphous silicon layer;

Island ground forms than wideer second amorphous silicon layer of gate electrode width and the operation of first amorphous silicon layer on gate electrode;

After applying the second above metal level of one deck, on the gate insulation layer and on second amorphous silicon layer, comprise source electrode (signal wire)/drain electrode distribution and described opening portion and by the operation of the electrode terminal of the signal wire that a part was constituted of the electrode terminal of sweep trace and signal wire to be formed with gate electrode with overlapping;

Remove the operation of second amorphous silicon layer of described source/drain wiring closet;

On the full surface of the described first transparent insulated substrate, form the operation of protection insulation course; And

The operation of optionally removing the protection insulation course forming opening portion on the described electrode terminal and on the protection insulation course on the pixel electrode.

8. the manufacture method of a liquid crystal indicator, be to belong to the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with this first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that comprising

At least on a first type surface of the first transparent insulated substrate, form the operation of the sweep trace that constitutes by the metal level more than one deck;

Gate insulation layer that sequential applications one deck is above and first amorphous silicon layer free from foreign meter and the operation that contains second amorphous silicon layer of impurity;

Remove the operation of the second interior amorphous silicon layer of described opening portion, first amorphous silicon layer, gate insulation layer;

On the gate insulation layer and on second amorphous silicon layer, make a part and gate electrode form overlappingly by more than one deck can source electrode (signal wire)/drain electrode distribution that anodised metal level constituted operation;

On the gate insulation layer and on the part of described drain electrode distribution,, on signal wire, form the operation of the electrode terminal of transparent conductivity in the pixel electrode of transparent conductivity and the zone outside the image displaying part; And

The photoresist pattern that will be used for the selectivity pattern of described pixel electrode and electrode terminal is used as mask, the electrode terminal of protection pixel electrode and signal wire, the operation of the amorphous silicon layer of anodic oxidation source/drain distribution and source/drain wiring closet simultaneously.

9. the manufacture method of a liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with the described first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that comprising

At least on a first type surface of the first transparent insulated substrate, form the sweep trace that constitutes by transparency conducting layer and the first metal layer and intend the seemingly operation of pixel electrode;

Remove second amorphous silicon layer, first amorphous silicon layer, gate insulation layer, electricity slurry protective seam and metal level in the described opening portion, and expose the sweep trace part of transparent conductivity and the operation of pixel electrode;

Apply one deck above can anodised metal level after, it is overlapping with gate electrode to form a part, and corresponding to the thicker source electrode (signal wire) in other zones of the Film Thickness Ratio on the electrode terminal of sweep trace and signal wire/drain electrode distribution and contain described transparent conductivity sweep trace a part and by the operation of the photoresist pattern of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Described photoresist pattern is used as mask, and selectivity is removed can anodised metal level and form the operation of the electrode terminal of the electrode terminal of source/drain distribution and sweep trace and signal wire;

Reduce the thickness of described photoresist pattern and expose the operation of source/drain distribution; And

Protect described electrode terminal, simultaneously the operation of the amorphous silicon layer of anodic oxidation source/drain distribution and source/drain wiring closet.

10. the manufacture method of a liquid crystal indicator, be to belong to the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with the described first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that comprising

At least on a first type surface of the first transparent insulated substrate, form by the sweep trace that metal level constituted more than one deck and the operation of counter electrode;

On gate insulation layer, a part and gate electrode are formed overlappingly contain second amorphous silicon layer and by the source electrode that second metal level constituted (signal wire) more than one deck/drain electrode distribution (pixel electrode) with contain described opening portion and by the operation of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

Remove the operation of second amorphous silicon layer of described source/drain wiring closet; And

Except that the electrode terminal of described sweep trace and signal wire, on the full surface of the first transparent insulated substrate, form the operation of protection insulation course.

11. the manufacture method of a liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with the described first transparent insulated substrate, wherein, on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that comprising

At least on a first type surface of the first transparent insulated substrate, form the sweep trace that constitutes by the metal level more than one deck and the operation of counter electrode;

Island ground forms the operation of exposing gate insulation layer than wideer second amorphous silicon layer of gate electrode width and first amorphous silicon layer on gate electrode;

Electrode terminal at sweep trace forms on the zone, forms the operation that has opening portion and remove the gate insulation layer in the described opening portion;

Apply one deck above can anodised metal level after, it is overlapping with gate electrode to form a part, and corresponding to the thicker source electrode (signal wire) in other zones of the Film Thickness Ratio on the electrode terminal of sweep trace and signal wire/drain electrode distribution (pixel electrode) with contain described opening portion and by the operation of the photoresist pattern of the electrode terminal of the signal wire that a part constituted of the electrode terminal of sweep trace and signal wire;

One side is protected described electrode terminal, the operation of the amorphous silicon layer of one side anodic oxidation source/drain distribution and source/drain wiring closet.

12. the manufacture method of a liquid crystal indicator, be with the liquid crystal filling between the first transparent insulated substrate and second transparent insulativity substrate relative or color filter and the manufacture method of the liquid crystal indicator that constitutes with the described first transparent insulated substrate, wherein on a first type surface of the described first transparent insulated substrate, have at least: insulated gate transistor, the sweep trace of the gate electrode of the described insulated gate transistor of double as and the also signal wire of double as source electrode distribution, is become two-dimentional matrix with the unit picture element that is connected to the pixel electrode of drain electrode on the distribution etc. by assortment, it is characterized in that comprising