CN100545726C - Liquid crystal disply device and its preparation method - Google Patents
Liquid crystal disply device and its preparation method Download PDFInfo
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- CN100545726C CN100545726C CNB2007101626506A CN200710162650A CN100545726C CN 100545726 C CN100545726 C CN 100545726C CN B2007101626506 A CNB2007101626506 A CN B2007101626506A CN 200710162650 A CN200710162650 A CN 200710162650A CN 100545726 C CN100545726 C CN 100545726C
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Abstract
The present invention provides a kind of Liquid crystal disply device and its preparation method, and its problem is in the manufacture method that reduces conventional worker ordinal number, when passage length shortens, makes surplus (margin) and diminishes and the yield rate reduction.Solution of the present invention possesses: by introducing shadow tone (halftone) exposure technique, and the innovative techniques that the formation operation of the formation operation of sweep trace and etch stop layer is rationalized; Introduce the halftone exposure technology with passing through in the source electrode of known technology, the anodic oxidation operation of drain electrode wiring, form the innovative techniques that operation is rationalized with protective seam with electrode terminal; Form the technical combinations of the rationalization technology of pixel electrode and sweep trace simultaneously with utilization and known technology, with the four road mask plate technologies of constructing TN type liquid crystal indicator and IPS type liquid crystal indicator, the invention of three road mask plate technologies.
Description
The application is on November 29th, 2004 for the applying date, and application number is 200410098206.9, and denomination of invention is divided an application for the Chinese invention patent application of " Liquid crystal disply device and its preparation method ".
Technical field
The invention relates to liquid crystal indicator, especially about the liquid crystal indicator of active (active) type with coloured image Presentation Function.
Background technology
In recent years, along with development of technology such as Micrometer-Nanometer Processing Technology, liquid crystal material technology and high-density installation technology, the television image of the liquid crystal indicator at 5 to 50cm diagonal angles or various image display are provided under commercial basis (base) in a large number.And, by on one side of the two sheet glass substrates that constitute liquid crystal panel, be pre-formed the dyed layer of RGB, also realize colored the demonstration than being easier to.Especially be provided with in each pixel in so-called active formula (active) liquid crystal panel of on-off element, crosstalking between signal, (cross-talk) is less, response speed is also very fast, the image that can guarantee to obtain to have high correlative value.
Generally, these liquid crystal indicators (liquid crystal panel) are to have 200 to 1200 sweep traces, and the matrix of 300 to 1600 left and right sides signal wires constitutes, and recently, the big pictureization and the height that carry out corresponding capacity of display increase just simultaneously become more meticulous.
Figure 23 illustrates the installment state of display panels, utilizes seating meanses such as COG (Chip-On-Glass) mode or TCP (Tape-Carrier-Package) mode, and electric signal is provided to image displaying part.This COG mode, be to use the electric conductivity sticker, connection is in order to being provided to drive signal the semiconductor integrated circuit chip 3 of scan-line electrode terminal group 5, and this scan-line electrode terminal group 5 is formed on and constitutes liquid crystal panel 1 transparent insulated substrate on one side for example on the glass substrate 2.This TCP mode is to be substrate with the polyimide based resin film, utilizes the suitable sticker that contains the electric conductivity media, will have the TCP film 4 of gold or plating scolding tin Copper Foil terminal, is crimped on the electrode tip subgroup 6 of signal wire and fixes.Herein, for the aspect explanation, illustrate two kinds of mounting meanss simultaneously, and in fact suitably select any one mode to get final product.
The wiring topology that is used for connecting 5,6 of the electrode terminals of the pixel of the image displaying part that is positioned at liquid crystal panel 1 substantial middle part and sweep trace and signal wire is 7,8, not necessarily will use the conductive material identical with electrode tip subgroup 5,6 to constitute.The 9th, on opposite face, have the relative glass substrate or the colored filter of another sheet transparency insulated substrate of the common transparent conductivity counter electrode of all liquid crystal structure cells.
Figure 24 is that expression is disposed at the equivalent circuit diagram of each pixel as the active formula liquid crystal indicator of on-off element with insulated gate electrode transistor npn npn 10,11 (Figure 23 is 7) are that sweep trace, 12 (Figure 23 is 8) is a signal wire, the 13rd, the liquid crystal structure cell, and liquid crystal structure cell 13 is to handle as capacity cell.The element that solid line is described is formed on a slice glass substrate 2 that constitutes liquid crystal panel, and what dotted line was described is formed on the relative interarea of another sheet glass substrate 9 with common 14 of the counter electrodes of all liquid crystal structure cells 12.When the resistance of the OFF of insulated gate electrode transistor npn npn 10 resistance or liquid crystal structure cell 13 is low or when paying attention to the GTG of display image, can manage to increase the circuit setting, it is in parallel and set up to be about to additional storage electric capacity 15 and liquid crystal structure cell 13, and this additional storage electric capacity 15 can increase the time constant as the liquid crystal structure cell 13 of load.In addition, the 16th, the common bus of storage capacitors 15.
Figure 25 is the main position sectional view of the image displaying part of liquid crystal indicator, constitute two sheet glass substrates 2,9 of liquid crystal panel 1, be by resinousness fiber, particle or be formed at pillar-shaped distance piece material (not shown) uniformly-spaced on the colored filter 9, form across counting the specific interval about μ m, and, its gap (gap) is in the peripheral part of glass substrate 9, the confined space of encapsulant that formation is constituted by organic property resin and/or joint filling material (any all be not illustrated) sealing, and in this confined space filling liquid crystal 17.
Because when realizing colored the demonstration, it is confined space side at glass substrate 9, be capped the organic film about any one or boths' of the containing dyestuff or pigment that are called dyed layer 18 thickness 1 to 2 μ m, to give the function that color shows, so this moment, glass substrate 9 can be described as colored filter (Color Filter abbreviates CF as) again.And, the character of pressing liquid crystal material 17, and on glass substrate 9 or glass substrate 2 below any one or both sides on paste Polarizer 19, make liquid crystal panel 1 have the function of electrooptic element.At present, most of liquid crystal panel of Xiao Shouing all is the structure that uses TN (twist nematic) on liquid crystal material on the market, therefore generally needs two Polarizers.Though not expression among the figure, at the permeation type liquid crystal panel, be to dispose back side light source as light source, by below irradiation white light.
Contacting with liquid crystal 17 and be formed on polyimide based resin film 20 about for example thickness 0.1 μ m on the two sheet glass substrates 2,9, is to be used for making the alignment film of liquid crystal alignment in specific direction.The 21st, be used for connecting the drain electrode of insulated gate electrode transistor npn npn 10 and the drain electrode (wiring) of transparent conductivity pixel electrode 22, most and signal wire (source electrode line) 12 forms simultaneously.Between signal wire 12 and drain electrode 21 is semiconductor layer 23, and can describe in detail after this semiconductor layer 23.On colored filter 9, be formed at the Cr thin layer 24 about the thickness 0.1 μ m that dyed layer 18 has a common boundary, be to be used for preventing the light shielding portion bulk-breaking of incidence of external light to semiconductor layer 23 and sweep trace 11 and signal wire 12, black matrix" (Black Matrix is called for short BM) technology commonly used that Here it is.
At this, illustrate about structure and manufacture method as the insulated gate electrode transistor npn npn of on-off element.Insulated gate electrode transistor npn npn at present commonly used has two kinds, is introduced as knowing example with a kind of insulated gate electrode transistor npn npn that is called channel etch type wherein.By introducing dry etch technique, needed to use the mask plate about eight roads originally, be reduced to five roads at present, this reduction for technology cost (process cost) has sizable benefiting.Figure 26 is the unit picture element planimetric map that constitutes the active formula substrate (semiconductor device that is used for display device) of the liquid crystal panel of knowing.Represent A-A ', the B-B ' of Figure 27 (e) and the sectional view of C-C ' line, its manufacturing process of following simple declaration at Figure 26.
At first, shown in Figure 26 (a) and Figure 27 (a), glass substrate 2 about thickness 0.5 to 1.1 μ m, for example on the interarea of the commodity by name 1737 of Corning Incorporated's manufacturing, use SPT (sputter) equal vacuum film forming apparatus, cover the first metal layer about thickness 0.1 to 0.3 μ m, as thermotolerance, resistance to chemical reagents and the high insulativity substrate of the transparency, and utilize Micrometer-Nanometer Processing Technology, optionally form sweep trace 11 and the capacitor storage beam 16 of double as gate electrode 11A.With regard to the sweep trace material, take all factors into consideration thermotolerance, resistance to chemical reagents, hydrofluoric acid resistance and electric conductivity after, general select to use the high metal or alloy of thermotolerance such as Cr, Ta, MoW alloy.
For big pictureization and the height that adapts to liquid crystal panel becomes more meticulous, reduce the resistance value of sweep trace, using Al (aluminium) is rational as the material of sweep trace, but because the monomer thermotolerance of Al is low, so the technology that adopts is the silicide of the above-mentioned heating resisting metal Cr of lamination, Ta, Mo or these metals at present, perhaps, on the Al surface, utilize anodic oxidation additional oxide layer (Al
2O
3).That is to say that sweep trace 11 is made of the metal level more than one deck.
And, on whole of glass substrate 2, use PCVD (PCVD) device, for example, cover three kinds of thin layers in regular turn: as a SiNx (silicon nitride) layer 30 of gate insulator respectively with the thickness about 0.3 μ m, 0.05 μ m, 0.1 μ m; With first amorphous silicon (a-Si) layer 31 as impure insulated gate electrode transistor npn npn passage hardly; With the 2nd SiNx layer 32 as the insulation course of protecting passage; and shown in Figure 26 (b) and Figure 27 (b), utilize Micrometer-Nanometer Processing Technology, the 2nd SiNx layer 32 on the optionally residual gate electrode 11A; make its width thinner and form 32D, expose first amorphous silicon layer 31 than gate electrode 11A.
Then, the same PCVD device that uses, with for example thickness about 0.05 μ m, be capped second amorphous silicon layer 33 of impure for example phosphorus at whole face after, shown in Figure 26 (c) and Figure 27 (c), use SPT equal vacuum film forming apparatus, cover in regular turn: for example Ti about thickness 0.1 μ m, Cr, thin layers such as Mo 34 are as heat resistant metal layer, for example Al thin layer 35 about thickness 0.3 μ m is as the low resistance wiring layer, for example Ti thin layer 36 about thickness 0.1 μ m is as intermediate conductive layer, and, utilize Micrometer-Nanometer Processing Technology, optionally form: by as source electrode, three kinds of film 34A of this of drain electrode wiring material, 35A, the drain electrode 21 of the insulated gate electrode transistor npn npn that lamination constituted of 36A, signal wire 12 with the double as source electrode.The generation type of this selectivity pattern, be when forming with source electrode, drain electrode wiring employed photoresist pattern as mask, in regular turn behind etching Ti thin layer 36, Al thin layer 35, the Ti thin layer 34, remove second amorphous silicon layer 33 of 12,21 of source electrodes, drain electrode, and expose the 2nd SiNx layer 32D, also remove first amorphous silicon layer 31 simultaneously, and expose gate insulator 30 in other zone.As mentioned above because have the 2nd SiNx layer 32D as the path protection layer, so the etching meeting of second amorphous silicon layer 33 finish automatically, so this manufacture method promptly is called the etch-stop method.
Can not form the mode that biasing is constructed with the insulated gate electrode transistor npn npn, it is overlapping to make source electrode, drain electrode 12,21 and etch stop layer 32D be part (number μ m) in the plane.Because the effect that this lap has stray capacitance electrically, so it is the smaller the better, but because be that glass substrate temperature during by the expansion coefficient of the precision of the alignment precision of exposure machine, mask plate and glass substrate and exposure is determined, so the numerical value of reality is at most about 2 μ m.
Then, after removing above-mentioned photoresist pattern, with gate insulator similarly, use the PCVD device, on whole of glass substrate 2, be capped SiNx layer about thickness 0.3 μ m as transparent insulation course, and form passivation insulation 37, then, shown in Figure 26 (d) and Figure 27 (d), utilize Micrometer-Nanometer Processing Technology, optionally remove passivation insulation 37, form: opening portion 62 is positioned on the drain electrode 21; Be positioned at the zone beyond the image displaying part with opening portion 63 and be formed with on the position of electrode terminal 5 of sweep trace 11; Be positioned at the position of the electrode terminal 6 that is formed with signal wire 12 with opening portion 64, and expose drain electrode 21 and sweep trace 11 and segment signal line 12.Go up formation opening portion 65 in capacitor storage beam 16 (the parallel pattern electrode of tying up bundle), and exposed portions serve capacitor storage beam 16.
At last, use SPT equal vacuum film forming apparatus, cover for example ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), shown in Figure 26 (e) and Figure 27 (e), utilize Micrometer-Nanometer Processing Technology, contain opening portion 62 ground and on passivation insulation 37, optionally form pixel electrode 22, and finish active formula substrate 2.Also the part of scanning line of exposing in the opening portion 63 11 can be made as electrode terminal 5, the segment signal line 12 that exposes in the opening portion 64 is made as electrode terminal 6, also can be as shown in the figure, contain opening portion 63,64 ground on passivation insulation 37, optionally form the electrode terminal 5A, the 6A that constitute by ITO, generally, the transparent conductivity short-circuit line 40 between connection electrode terminal 5A, 6A also can form simultaneously.Though not shown herein, yet, why so be because electrode terminal 5A, 6A and 40 of short-circuit lines are formed elongated line (stripe) shape, can high resistanceization and be formed for the high resistance that electrostatic prevention is used.Similarly, can contain the electrode terminal that opening portion 65 ground form capacitor storage beam 16.
When the cloth line resistance of signal wire 12 can not throw into question, just not necessarily to use the low resistance wiring layer 35 that constitutes by Al, at this moment, if select heating resisting metal materials such as Cr, Ta, Mo, can be with source electrode, drain electrode wiring 12,21 single-layered, simplification.By this formation, source electrode, drain electrode wiring use heat resistant metal layer, and it is very important guaranteeing to electrically connect with second amorphous silicon layer, in addition, about the thermotolerance of insulated gate electrode transistor npn npn, then write up is in the Japanese kokai publication hei 7-74368 of well-known examples communique.In addition, among Figure 26 (c), capacitor storage beam 16 and drain electrode 21, sandwich gate insulator 30 are plane overlapping areas 50 (bottom right oblique line part), are formed with storage capacitors 15, still, omit its detailed explanation at this.
The rationalization of the island chemical industry preface that above-mentioned five road mask plate technologies are semiconductor layers contacts the result that the operation minimizing is once obtained with forming, and omits its detailed reason of explanation herein.Originally, need to use about seven to eight road mask plates, and can be reduced to five roads at present by introducing dry etch technique, this reduction for the technology cost has sizable benefiting.In order to reduce the production cost of liquid crystal indicator, effective and efficient manner is the technology cost that reduces in the production process of active formula substrate, also has, and reduces the part part cost in panel assembling procedure and the module installation procedure, and this is well-known development goal.In addition, in order to reduce the technology cost, the process number that for example has the technology of making to tail off reduces, inexpensive process is developed or the modes such as displacement of technology, exemplifies the four road mask plate technologies that make active formula substrate with four road mask plates herein, and the minimizing of operation is described.Four road mask plate technologies are by introducing the halftone exposure technology, reduce the photo etching operation, Figure 28 is the unit picture element planimetric map corresponding to the active formula substrate of four road mask plate technologies, represents A-A ', the B-B ' of Figure 29 (e) and the sectional view of C-C ' line at Figure 28.As mentioned above, the normal at present insulated type transistor that uses has two kinds, and in this employing is the insulated gate electrode transistor npn npn of channel etch type.
At first, with five road mask plate technologies similarly, on an interarea of glass substrate 2, use SPT equal vacuum film forming apparatus, be capped the first metal layer about thickness 0.1 to 0.3 μ m, then, shown in Figure 28 (a) and Figure 29 (a), utilize Micrometer-Nanometer Processing Technology, optionally form sweep trace 11 and the capacitor storage beam 16 of double as gate electrode 11A.
Secondly, on whole of glass substrate 2, use PCVD (PCVD) device, for example, cover three kinds of thin layers in regular turn: as the SiNx layer 30 of gate insulator, as first amorphous silicon layer 31 of impure insulated gate electrode transistor npn npn passage hardly, as the source electrode of impure insulated gate electrode transistor npn npn, second amorphous silicon layer 33 of drain electrode respectively with the thickness about 0.3 μ m, 0.2 μ m, 0.05 μ m.Then, use SPT equal vacuum film forming apparatus, be capped in regular turn: for example Ti thin layer 34 about thickness 0.1 μ m is as heat resistant metal layer; With Al thin layer 35 about thickness 0.3 μ m as the low resistance wiring layer; With for example Ti thin layer 36 about thickness 0.1 μ m as intermediate conductive layer, that is to say, be capped source electrode, drain electrode wiring material in regular turn.Utilize Micrometer-Nanometer Processing Technology, optionally form the drain electrode 21 of insulated gate electrode transistor npn npn and the signal wire 12 of double as source electrode, and be somebody's turn to do when selecting pattern to form, maximum feature is shown in Figure 28 (b) and Figure 29 (b), being formed on the thickness that the passage between source electrode, drain electrode forms regional 80B (oblique line part) for example is 1.5 μ m, forms thinner photoresist pattern 80A, the 80B of thickness 3 μ m of regional 80A (12), 80A (21) than source electrode, drain electrode wiring.
Because this photoresist pattern 80A, 80B generally use the positivity photoresist in the making of the substrate that is used for liquid crystal indicator, be black so source electrode, drain electrode wiring form regional 80A, promptly form the Cr film; Passage area 80B is a grey, promptly forms for example Cr pattern of the line/spacing about width 0.5 to 1 μ m (line and space); Other zone is a white, even get final product with the mask plate of removing the Cr film.Because gray area, the lack of resolution of exposure machine, so line/spacing (line and space) can't be resolved, mask plate irradiates light from light source is seen through about half, therefore according to the residual membrane property of positive photosensitive resin, can obtain to have photoresist pattern 80A, the 80B of the section shape shown in Figure 29 (b).
With above-mentioned photoresist pattern 80A, 80B is as mask, etching in regular turn shown in Figure 29 (b): Ti thin layer 36, Al thin layer 35, Ti thin layer 34, second amorphous silicon layer 33 and first amorphous silicon layer 31, and after exposing gate insulator 30, shown in Figure 28 (c) and Figure 29 (c), utilize ashing means such as oxygen plasma, make photoresist pattern 80A, the thickness of 80B, for example reduce from 3 μ m and reduce by 1.5 μ m when above, photoresist pattern 80B disappears, and expose passage area, simultaneously only can be at source electrode, drain electrode wiring forms the zone and goes up residual 80C (12), 80C (21).At this, the photoresist pattern 80C (12), the 80C (21) that reduce with thickness are as mask, the Ti thin layer of (passage forms the zone), Al thin layer, Ti thin layer, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A between etching source electrode, drain electrode wiring in regular turn make about residual about 0.05 to the 0.1 μ m of the first amorphous silicon layer 31A again.In addition, pattern dimension changes when suppressing above-mentioned oxygen plasma treatment, so be good to strengthen anisotropy, its reason describes in detail in the back.
Then, remove above-mentioned photoresist pattern 80C (12), behind the 80C (21), with five road mask plate technologies similarly, shown in Figure 28 (d) and Figure 29 (d), on 2 whole of glass substrates, the SiNx layer that is capped 0.3 μ m left and right sides thickness is as transparent insulation course, and formation passivation insulation 37, on the zone of the electrode terminal that forms drain electrode 21 and sweep trace 11 and signal wire 12, form opening portion 62 respectively, 63,64, then, remove passivation insulation 37 and gate insulator 30 in the opening portion 63, and exposed portions serve sweep trace 11 is removed opening portion 62 simultaneously, passivation insulation 37 in 64, and exposed portions serve drain electrode 21 and segment signal line.
At last, use SPT equal vacuum film forming apparatus, be capped for example ITO or IZO, as the transparency conducting layer about thickness 0.1 to 0.2 μ m, shown in Figure 28 (e) and Figure 29 (e), utilize Micrometer-Nanometer Processing Technology, on passivation insulation 37, contain opening portion 62 ground selectivity and form transparent conductivity pixel electrode 22, and finish active formula substrate 2.About electrode terminal, be on passivation insulation 37 at this, contain opening portion 63,64 and optionally form transparent conductivity electrode terminal 5A, the 6A that constitutes by ITO.
Summary of the invention
Invent problem to be solved
By this formation, because in five road mask plate technologies and four road mask plate technologies, contact operation for the formation of drain electrode 21 and sweep trace 11 and finish simultaneously, so be different with thickness of insulating layer and kind in these corresponding opening parts 62,63.Passivation insulation 37 is compared with gate insulator 30, and the system film temperature is lower and membranous relatively poor, and utilizing hydrofluorite is etching solution when carrying out etching, and both etching speeds are respectively several
Divide, count
Divide, differ an order of magnitude, and, because the section shape of the opening portion 62 on the drain electrode 21 over etching takes place and the reason in uncontrollable aperture on top, be the dry etching (dry-etch) of gas so adopt the use fluorine.
Even when adopting dry etching, because the opening portion 62 on the drain electrode 21 only is a passivation insulation 37, so compare with the opening portion 63 on the sweep trace 11, can't avoid over etching, and, have the situation that intermediate conductive layer 36A causes thickness to reduce because of etching gas sometimes according to the difference of material.And, generally speaking, after etching finishes, in the time of removing the photoresist pattern, at first in order to remove the polymkeric substance of fluorinated surface, so utilize the oxygen plasma ashing,, reduce about 0.1 to 0.3 μ m with the surface of photoresist pattern, then, re-use organic stripper, for example the stripper 106 of chemical industry Zhu Shi commercial firm system is answered in Tokyo, carries out soup and handles.And the thickness of working as middle conductive layer 36A reduces, and when being the state that exposes substrate aluminium lamination 35A, utilizes the oxygen plasma ashing treatment, forms the Al as insulator on the surface of aluminium lamination 35A
2O
3, make itself and 22 of pixel electrodes can't obtain Ohmic contact.At this, also thickness can be made as for example 0.2 μ m, intermediate conductive layer 36A thickness is reduced, can avoid this problem to take place.Perhaps, when opening portion 62 to 65 forms, remove aluminium lamination 35A, expose Ti thin layer 34A as the substrate heat resistant metal layer after, forming pixel electrode 22 more also is to solve countermeasure, and has this moment from promptly not needing at first the advantage of intermediate conductive layer 36A.
Yet with the former countermeasure, when the inner evenness of the thickness of these films was undesirable, this cooperation not necessarily can play a role effectively, in addition, when the inner evenness of etching speed is undesirable, also was same situation fully.Though the latter's countermeasure can not need intermediate conductive layer 36A,, can increase the removal operation of aluminium lamination 35A, in addition, control when inadequate when the section of opening portion 62, probably have the possible type that fracture takes place pixel electrode 22.
Add, in the insulated gate electrode transistor npn npn of channel etch type, first amorphous silicon layer 31 free from foreign meter of passage area, when not being capped thicker thickness (being generally more than the 0.2 μ m) in advance, can produce very big influence to the homogeneity in the face of glass substrate, inconsistent phenomenon takes place in transistor characteristic particularly OFF electric current easily.The influence that this point is subjected to the running rate of PCVD and particle situation occurred is very big, from the production cost viewpoint, also is very important item.
And, form operation owing to be applicable to the passage of four road mask plate technologies, be source electrode, drain electrode wiring material and the impure semiconductor layer of optionally removing 12,21 of source electrodes, drain electrode wiring, so be with the operation that decides the passage length (present volume production product are 4 to 6 μ m) that influences the ON of insulated gate electrode transistor npn npn characteristic largely.Because the change of this passage length can make the ON current value of insulated gate electrode transistor npn npn produce big variation, so generally all can require rigorous manufacturing management.Yet, present situation is a passage length, the pattern dimension in halftone exposure zone just, the amount of being exposed (the pattern precision of the intensity of light source and mask plate, especially line/spacing dimension), the coating thickness of photoresist, the development treatment of photoresist, and the influence of all multiparameters such as photoresist thickness reduction of this etching work procedure, add the inner evenness of above-mentioned this tittle, so not necessarily can under yield rate height and stable status, produce, stricter manufacturing management must be arranged, therefore the not talkative completeness that has reached high level.Particularly passage length is 6 μ m when following, and along with the minimizing of photoresistance pattern thickness, the far-reaching tendency that pattern dimension is produced is more obvious.
The present invention invents in view of relevant present situation, its purpose not only is to avoid five road mask plate technologies or four road mask plate technologies in the past, forming the unfavorable condition that produces when contacting jointly, make the bigger halftone exposure technology of surplus (margin) by adopting, realize the minimizing of manufacturing process.In addition, realize the low price of liquid crystal panel, worker ordinal number still less must be painstakingly pursued in the increase of adaption demand, and the simplification by being additional to other main manufacturing process or the technology of cost degradation can improve value of the present invention more.
In order to solve the means of problem
Among the present invention, at first adopt, be useful in the formation operation of the etch stop layer that the pattern accuracy control carries out easily and the formation operation of sweep trace, to realize the minimizing of manufacturing process the halftone exposure technology.Secondly, with the passivation effectively of source electrode, drain electrode wiring, merge that to know Technology in Japan Te Kaipingdi 2-21612 communique disclosed for only, by the source electrode that aluminium constituted, the surface of drain electrode wiring, form the anodizing technology of insulation course, to realize the rationalization and the low temperatureization of operation.And Technology in Japan Te Kaipingdi 5-268726 communique is disclosed knowing, and the formation that pixel electrode is formed the operation rationalization is applicable to the present invention.And in order further to reduce operation, the anodic oxide coating of source electrode, drain electrode wiring forms the halftone exposure technology that also is suitable for, and forms operation with the protective seam with electrode terminal and rationalizes.
According to a first aspect of the invention, a kind of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate; it is characterized by: on an interarea of the first transparent insulated substrate, form at least and constituted by the first metal layer more than one deck; and its side has the sweep trace of insulation course; gate insulator more than formation one deck on the gate electrode and first semiconductor layer free from foreign meter; on above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode; on the part of above-mentioned protection insulation course; on first semiconductor layer and on the first transparent insulated substrate; formation is by the source wiring that lamination constituted (signal wire) of second impure semiconductor layer and second metal level more than one deck; drain electrode wiring; on the first transparent insulated substrate, be formed on the above-mentioned drain electrode wiring and the electrode terminal of sweep trace and signal wire forms the transparent resin layer that has opening portion on the zone; the electrode terminal of removing above-mentioned sweep trace forms the gate insulator on the zone; the electric conductivity pixel electrode that comprises above-mentioned opening portion; with comprise on the sweep trace with signal wire on the electric conductivity counter electrode, be formed on the above-mentioned transparent resin layer.
By this formation, owing on active formula substrate, form thicker transparent resin layer, to give deactivation function, so not only do not need passivation insulation is covered on whole of glass substrate, and the heat resistant type of insulated gate electrode transistor npn npn can not have problems, also pixel electrode and counter electrode can be configured on the transparent resin layer, the orientation that aperture opening ratio is high is handled and also is easy to reach, and can obtain the high IPS type liquid crystal indicator of image quality.
According to a second aspect of the invention, a kind of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate; it is characterized by: on an interarea of the first transparent insulated substrate, form at least and constituted by the first metal layer more than one deck; and its side has the sweep trace and the counter electrode of insulation course; at the gate insulator that is formed with on the counter electrode more than one deck; with be formed with gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode; on above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode; zone beyond image displaying part; gate insulator on sweep trace forms opening portion; on the part of above-mentioned protection insulation course part; on first semiconductor layer and on the first transparent insulated substrate; be formed with the source wiring that lamination constituted (signal wire) by second impure semiconductor layer and second metal level more than one deck; drain electrode wiring (pixel electrode); the electrode terminal of the sweep trace that is constituted with first semiconductor layer that comprises above-mentioned opening portion periphery and second semiconductor layer and by second metal level; with the electrode terminal by the signal wire that segment signal line constituted in image displaying part zone in addition; on the electrode terminal of above-mentioned signal wire, on signal wire, form the photonasty organic insulator.
By this formation, on the passage between source electrode, drain electrode, form the protection insulation course, with the protection passage, form the photonasty organic insulator on the surface of signal wire simultaneously, to give deactivation function, on counter electrode, form gate insulator.And, can obtain having the IPS type liquid crystal indicator of the metallic electrode terminal identical with signal wire.
According to a third aspect of the invention we, a kind of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by: on an interarea of the first transparent insulated substrate, form at least and constituted by the first metal layer more than one deck, and its side has the sweep trace and the counter electrode of insulation course, at the gate insulator that forms on the counter electrode more than one deck; With forming gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode, on above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode, zone beyond image displaying part, gate insulator on sweep trace forms opening portion, on the part of above-mentioned protection insulation course, on first semiconductor layer and on the first transparent insulated substrate, form: by the second impure semiconductor layer and more than one deck can anodised metal level the source wiring that lamination constituted (signal wire), drain electrode wiring (pixel electrode); With first semiconductor layer that comprises above-mentioned opening portion periphery and second semiconductor layer and by electrode terminal that can the sweep trace that anodised metal level constituted; Form electrode terminal with zone beyond the image displaying part by the signal wire that a part constituted of signal wire, on the electrode terminal of above-mentioned signal wire, form anodic oxide coating on the surface of source electrode, drain electrode wiring.
By this formation, on the passage between source electrode, drain electrode, form the protection insulation course, with the protection passage, form the tantalum pentoxide (Ta of the anodic oxide coating that belongs to insulativity simultaneously on the surface of signal wire and drain electrode wiring
2O
5) or aluminium oxide (Al
2O
3), to give deactivation function, on counter electrode, form gate insulator.And, can obtain having the IPS type liquid crystal indicator of the metallic electrode terminal identical with signal wire.
According to a forth aspect of the invention, a kind of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by: on an interarea of the first transparent insulated substrate, form at least and constituted by the first metal layer more than one deck, and its side has the sweep trace and the counter electrode of insulation course, at the gate insulator that forms on the counter electrode more than one deck; With forming gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode; on above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode; on the part of above-mentioned protection insulation course; on first semiconductor layer and on the first transparent insulated substrate; formation is by the source wiring that lamination constituted (signal wire) of second impure semiconductor layer and second metal level more than one deck; drain electrode wiring (pixel electrode); zone beyond image displaying part; the electrode terminal that is formed on sweep trace on the first transparent insulated substrate form on the zone with electrode terminal by the signal wire that segment signal line constituted on have the transparent insulating layer of opening portion, in above-mentioned opening portion, expose as the part of scanning line of the electrode terminal of sweep trace and the electrode terminal of signal wire.
By this formation, on active formula substrate, provide the passivation insulation that constitutes by transparent insulating layer, if use thicker transparent resin at transparent insulating layer, being easy to orientation handles, not only can obtain the higher IPS type liquid crystal indicator of image quality, can also handle the few process number of opening portion formation operation Minus of the opening portion formation operation and the passivation insulation on the drain electrode of the gate insulator on the sweep trace with same mask plate Come, can only use three road mask plates to make liquid crystal indicators.
According to a fifth aspect of the invention, a kind of manufacture method of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by and have: on an interarea of the first transparent insulated substrate, be capped in regular turn at least: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above; Corresponding to sweep trace, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone; With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer; Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course; On gate electrode, stay width exposes first amorphous silicon layer than the also thin protection insulation course of gate electrode operation; After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace; Be capped the operation of the second impure amorphous silicon layer comprehensively; With part and the overlapping mode of above-mentioned protection insulation course, form by second amorphous silicon layer and the source electrode that lamination constituted (signal wire) of second metal level more than one deck, the operation of drain electrode wiring; With will form on the zone at the electrode terminal of the sweep trace in the zone on the drain electrode wiring, beyond the image displaying part and on the electrode terminal by the signal wire that segment signal line constituted, the transparent resin layer that has opening portion respectively is formed on the operation on the above-mentioned first transparent insulated substrate; The electrode terminal of removing above-mentioned sweep trace forms gate insulator on the zone and the operation of exposed portions serve sweep trace; And will comprise the opening portion on the above-mentioned drain electrode wiring electric conductivity pixel electrode and comprise on the sweep trace with signal wire on the counter electrode of electric conductivity, be formed on the operation on the above-mentioned transparent resin layer.
By this formation, can use one mask plate to handle the formation operation of sweep trace and the formation operation of etch stop layer, to realize the minimizing of lithography process number.And, and know example similarly, the opening portion of passivation insulation is formed the operation that is connected to form that the operation double as connects sweep trace, manufacturing process also reduces, and therefore can use four road mask plates to make IPS type liquid crystal indicator.
According to a sixth aspect of the invention, a kind of manufacture method of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in aforementioned dielectric grid type transistor drain pixel electrode, and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by and have: on an interarea of the first transparent insulated substrate, be capped in regular turn at least: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above; Corresponding to sweep trace and counter electrode, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone; With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer; Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course; On gate electrode, stay the width protection insulation course also thinner, and expose the operation of first amorphous silicon layer than gate electrode; After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace and counter electrode; Be capped the operation of the second impure amorphous silicon layer comprehensively; Zone beyond the image displaying part forms the zone at the electrode terminal of sweep trace and forms opening portion, second amorphous silicon layer, first amorphous silicon layer and gate insulator in the above-mentioned opening portion of selective removal, and the operation of exposed portions serve sweep trace; After being capped the second above metal level of one deck, formation corresponding to the overlapping source wiring (signal wire) of part and above-mentioned protection insulation course, drain electrode wiring (pixel electrode), comprise electrode terminal, the zone beyond image displaying part that above-mentioned opening portion forms sweep trace and form electrode terminal by the signal wire that segment signal line constituted, form the operation of the also thick photonasty organic insulation layer pattern in other zone of Film Thickness Ratio on the signal wire; With above-mentioned photonasty organic insulation layer pattern as mask, selective removal second metal level, second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reach the thickness that reduces above-mentioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
By this formation, can use one mask plate to handle the formation operation of etch stop layer and the formation operation of sweep trace, to realize the minimizing of lithography process number.And, when source electrode, drain electrode wiring formation, use the halftone exposure technology, optionally residual photonasty organic insulator on signal wire only, in this way, also can reduce manufacturing process unnecessary when forming passivation insulation, the result can use three road mask plates to make TN type liquid crystal indicator.
According to a seventh aspect of the invention, a kind of manufacture method of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by and have: on an interarea of the first transparent insulated substrate, be capped in regular turn at least: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above; Corresponding to sweep trace and counter electrode, and form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone; With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer; Reduce the thickness of the photoresist pattern that has reduced above-mentioned thickness, and expose the operation of protecting insulation course; On gate electrode, stay the width protection insulation course also thinner, and expose the operation of first amorphous silicon layer than gate electrode; After above-mentioned photoresist pattern is removed, form the operation of insulation course in the side of sweep trace and counter electrode; Be capped the operation of the second impure amorphous silicon layer comprehensively; Zone beyond the image displaying part forms the zone at the electrode terminal of sweep trace and forms opening portion, second amorphous silicon layer, first amorphous silicon layer and gate insulator in the selective removal opening portion, and the operation of exposed portions serve sweep trace; Be capped one deck above can anodised metal level after, form counterpart and above-mentioned protection insulation course overlapping source wiring (signal wire), drain electrode wiring (pixel electrode), comprise above-mentioned opening portion form the electrode terminal of sweep trace, in image displaying part zone exceptionally corresponding to electrode terminal by the signal wire that segment signal line constituted, form the operation of other the regional also thick photoresist pattern of Film Thickness Ratio on the electrode terminal of sweep trace and signal wire; As mask, selective removal can anodised metal level, second amorphous silicon layer and first amorphous silicon layer with above-mentioned photoresist pattern, and forms the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of above-mentioned photoresist pattern, and expose the operation of source electrode, drain electrode wiring; And the above-mentioned electrode terminal of protection, the operation of the source electrode of anodic oxidation simultaneously, drain electrode wiring.
By this formation, can use one mask plate to handle the formation operation of etch stop layer and the formation operation of sweep trace, to realize the minimizing of lithography process number.And; on the passage between source electrode, drain electrode; can form the protection insulation course with the protection passage; during source electrode, drain electrode wiring formation simultaneously, use the halftone exposure technology, on source electrode, drain electrode wiring, optionally form anodic oxide coating; in this way; also can reduce manufacturing process unnecessary when forming passivation insulation, the result can use three road mask plates to make TN type liquid crystal indicator.
According to an eighth aspect of the invention, a kind of manufacture method of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by and have: on an interarea of the first transparent insulated substrate, be capped in regular turn at least: gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course that the first metal layer that one deck is above and one deck are above; Corresponding to sweep trace and counter electrode, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone; With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer; Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course; On gate electrode, stay the also thin protection insulation course of width gate electrode, and expose the operation of first amorphous silicon layer; After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace and counter electrode; Be capped the operation of the second impure amorphous silicon layer comprehensively; With part and the overlapping mode of above-mentioned protection insulation course, form by the source wiring that lamination constituted (signal wire) of second amorphous silicon layer and second metal level more than one deck, the operation of drain electrode wiring (pixel electrode); Zone beyond image displaying part forms the operation that has the transparent insulating layer of opening portion on the electrode terminal that reaches on the zone by the signal wire that segment signal line constituted at the electrode terminal that is formed on sweep trace on the first transparent insulated substrate; And remove electrode terminal at above-mentioned sweep trace and form gate insulator on the zone, and the operation of exposed portions serve sweep trace.
By this formation, use mask plate one, handle the formation operation of etch stop layer and the formation operation of sweep trace, to realize the minimizing of lithography process number.And, and know example similarly, the opening of passivation insulation is formed operation, double as connects the operation that is connected to form of sweep trace, and manufacturing process also can reduce, and therefore uses three road mask plates just can make IPS type liquid crystal indicator.
According to a ninth aspect of the invention, a kind of manufacture method of liquid crystal indicator is provided, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in aforementioned dielectric grid type transistor drain pixel electrode, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative or the colored filter with the aforementioned first transparent insulated substrate, it is characterized by and have: on an interarea of the first transparent insulated substrate, be capped in regular turn at least: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above; Corresponding to sweep trace and counter electrode, the operation of the photoresist pattern that be formed on the gate electrode, on the intersection region of sweep trace and signal wire, on the intersection region of counter electrode and signal wire and other zone of Film Thickness Ratio on the intersection region of counter electrode and pixel electrode is also thick; With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer; Form the operation of insulation course in the side of sweep trace and counter electrode; Reduce the thickness of above-mentioned photoresist pattern and expose the protection insulation course, remove on the sweep trace with counter electrode on protection insulation course, first amorphous silicon layer, gate insulator, and expose the operation of sweep trace and counter electrode; Further minimizing has reduced the thickness of the above-mentioned photoresist pattern of thickness, stays the width protection insulation course also thinner than gate electrode on gate electrode, and exposes the operation of first amorphous silicon layer; Be capped the operation of the second impure amorphous silicon layer comprehensively; Be capped one deck above can anodised metal level after, form the overlapping source wiring (signal wire) of part and above-mentioned protection insulation course, drain electrode wiring (pixel electrode), the zone beyond image displaying part comprise part of scanning line form the electrode terminal of sweep trace, corresponding to electrode terminal by the signal wire that segment signal line constituted, form the operation of the also thick photoresist pattern in other zone of Film Thickness Ratio on the above-mentioned electrode terminal; As mask, selective removal can anodised metal level, second amorphous silicon layer and first amorphous silicon layer with above-mentioned photoresist pattern, and forms the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of above-mentioned photoresist pattern and expose the operation of source electrode, drain electrode wiring; And the above-mentioned electrode terminal of protection, the operation of the source electrode of anodic oxidation simultaneously, drain electrode wiring and counter electrode.
By this formation, use mask plate one, the minimizing of lithography process number of handling the formation operation of the formation operation of etch stop layer and sweep trace and exposing the operation of sweep trace is achieved.In addition; on the passage between source electrode, drain electrode; can form the protection insulation course with the protection passage, during source electrode, drain electrode wiring formation simultaneously, use the halftone exposure technology; on source electrode, drain electrode wiring, optionally form anodic oxide coating; in this way, also can reduce manufacturing process unnecessary when forming passivation insulation, the result; use the twice mask plate, can make IPS type liquid crystal indicator.
Preferably, the insulation course that is formed at the sweep trace side is an organic insulator, and forms by electroplating (elechoplahing).
By constituting, no matter what the material or the formation of sweep trace be, can form organic insulator in the side of sweep trace by electrochemical plating, and can use the halftone exposure technology, with one mask plate, handle sweep trace continuously and form operation and etch stop layer formation operation.
Preferably, the first metal layer is by can being constituted by anodised metal level, and the insulation course that is formed at the sweep trace side forms by anodic oxidation.
By this formation, can form anodic oxide coating in the side of sweep trace by anodic oxidation, and can use the halftone exposure technology, with one mask plate, handle sweep trace continuously and form operation and etch stop layer formation operation.
Description of drawings
Fig. 1 is the planimetric map about the semiconductor device that is used for display device of first embodiment of the invention;
Fig. 2 is the manufacturing process's sectional view about the semiconductor device that is used for display device of first embodiment of the invention;
Fig. 3 is the planimetric map about the semiconductor device that is used for display device of second embodiment of the invention;
Fig. 4 is the manufacturing process's sectional view about the semiconductor device that is used for display device of second embodiment of the invention;
Fig. 5 is the planimetric map about the semiconductor device that is used for display device of third embodiment of the invention;
Fig. 6 is the manufacturing process's sectional view about the semiconductor device that is used for display device of third embodiment of the invention;
Fig. 7 is the planimetric map about the semiconductor device that is used for display device of fourth embodiment of the invention;
Fig. 8 is the manufacturing process's sectional view about the semiconductor device that is used for display device of fourth embodiment of the invention;
Fig. 9 is the planimetric map about the semiconductor device that is used for display device of fifth embodiment of the invention;
Figure 10 is the manufacturing process's sectional view about the semiconductor device that is used for display device of fifth embodiment of the invention;
Figure 11 is the planimetric map about the semiconductor device that is used for display device of sixth embodiment of the invention;
Figure 12 is the manufacturing process's sectional view about the semiconductor device that is used for display device of sixth embodiment of the invention;
Figure 13 is the planimetric map about the semiconductor device that is used for display device of seventh embodiment of the invention;
Figure 14 is the manufacturing process's sectional view about the semiconductor device that is used for display device of seventh embodiment of the invention;
Figure 15 is the planimetric map about the semiconductor device that is used for display device of eighth embodiment of the invention;
Figure 16 is the manufacturing process's sectional view about the semiconductor device that is used for display device of eighth embodiment of the invention;
Figure 17 is the planimetric map about the semiconductor device that is used for display device of ninth embodiment of the invention;
Figure 18 is the manufacturing process's sectional view about the semiconductor device that is used for display device of ninth embodiment of the invention;
Figure 19 is the planimetric map about the semiconductor device that is used for display device of tenth embodiment of the invention;
Figure 20 is the manufacturing process's sectional view about the semiconductor device that is used for display device of tenth embodiment of the invention;
Figure 21 is the arrangement plan about the connection pattern that supplies insulation course formation of the present invention first to the 9th embodiment;
Figure 22 is the arrangement plan about the connection pattern of tenth embodiment of the invention insulation course;
Figure 23 is the stereographic map of the installment state of expression liquid crystal panel;
Figure 24 is the equivalent circuit diagram of liquid crystal panel;
Figure 25 is the sectional view of conventional liquid crystal panel;
Figure 26 is the planimetric map of the active formula substrate of conventional example;
Figure 27 is manufacturing process's sectional view of the active formula substrate of conventional example;
Figure 28 is the planimetric map of the active formula substrate of rationalization;
Figure 29 is manufacturing process's sectional view of the active formula substrate of rationalization.
Embodiment
Inventive embodiments
According to Fig. 1 to Figure 22 embodiments of the invention are described.Fig. 1 represents the planimetric map of the semiconductor device that is used for display device (active formula substrate) of relevant first embodiment of the invention, on the A-A ' line of Fig. 2 presentation graphs 1 and on B-B ' line and the sectional view of the manufacturing process on C-C ' line.Same, second embodiment is with Fig. 3 and Fig. 4, the 3rd embodiment is with Fig. 5 and Fig. 6, and the 4th embodiment is with Fig. 7 and Fig. 8, and the 5th embodiment is with Fig. 9 and Figure 10, the 6th embodiment is with Figure 11 and Figure 12, the 7th embodiment is with Figure 13 and Figure 14, and the 8th embodiment is with Figure 15 and Figure 16, and the 9th embodiment is with Figure 17 and Figure 18, the tenth embodiment is with Figure 19 and Figure 20, represents the planimetric map of active formula substrate and the sectional view of manufacturing process respectively.In addition, with the same position of conventional example, then attached with identical symbol to omit detailed explanation.
First embodiment
First embodiment is same with conventional example, at first, on an interarea of glass substrate 2, use SPT equal vacuum film forming apparatus, the alloy or the silicide of for example Cr, the Ta about covering thickness 0.1 to 0.3 μ m, Mo etc. or these metals are as the first metal layer.Explanation by the back is learnt, when the present invention selects the organic insulator conduct to be formed on the insulation course of gate insulator side, the sweep trace material almost without limits, yet, when selecting the anodic oxide coating conduct to be formed on the insulation course of gate insulator side, then this anodic oxide coating must have insulativity, this moment is if consider that the resistance of Ta monomer is higher, lack stable on heating words with the Al monomer, in order to realize the low resistanceization of sweep trace, the formation of sweep trace can be selected Al (Zr, Ta, Nd) individual layer such as alloy constitutes, or Al/Ta, Ta/Al/Ta, Al/AL (Ta, Zr, Nd) lamination of alloy etc. constitutes.In addition, Al (Ta, Zr, Nd) meaning is added the high Al alloys of thermotolerance such as number % following Ta, Zr or Nd.
Secondly; use the PCVD device; on whole of glass substrate 2; for example respectively with 0.3 μ m; 0.05 μ m; 0.1 the thickness about μ m; cover in regular turn: as a SiNx layer 30 of gate insulator; first amorphous silicon layer 31 under the passage of impure hardly insulated gate electrode transistor npn npn; and three kinds of thin layers such as the 2nd SiNx layer 32 that become insulation course that are used for protecting passage; then; shown in Fig. 1 (a) and Fig. 2 (a); utilize the halftone exposure technology; forming the protection insulation course, to form the zone be that the thickness of the regional 81A on the gate electrode 11A for example is that the ratio of 2 μ m is corresponding to the thicker photoresist pattern 81A of the 1 μ m of the thickness on the regional 81B of sweep trace 11 and capacitor storage beam 16; 81B; with photoresist pattern 81A; 81B is as mask; optionally remove path protection layer 32; first amorphous silicon layer 31; gate insulator 30 and the first metal layer, and expose glass substrate 2.Because the wire spoke of sweep trace 11 is wide, by the relation of resistance value, even if the narrowest generally also have the above size of 10 μ m, the mask plate of 81B (middle tone zone) is made or the accuracy control of its processing dimension can easily carry out so be used for forming.
Then; utilize ashing means such as oxygen plasma; make the thickness of above-mentioned photoresist pattern 81A, 81B reduce by 1 μ m when above; photoresist pattern 81B disappears; and expose the 2nd SiNx layer 32A, 32B (figure expression); can only form on the zone simultaneously, optionally form photoresist pattern 81C at the protection insulation course.Because photoresist pattern 81C (black region); it is the pattern width of path protection layer; be that size between source electrode, drain electrode wiring adds the mask plate alignment precision; so be made as 4 to 6 μ m between source electrode, drain electrode wiring; alignment precision is made as ± during 3 μ m; minimum also has 10 to 12 μ m, and dimension precision requirement is not strict.Yet, when photoresistance pattern 81A is converted into 81C, when the thickness isotropy of photoresistance pattern reduces by 1 μ m, size not only can reduce by 2 μ m, and when follow-up source electrode, drain electrode wiring formation, the mask plate alignment precision can dwindle 1 μ m, and form ± 2 μ m, the latter's requirement is than the former strictness on technology.Therefore, during above-mentioned oxygen plasma is handled, in the time of suppressing the variation of pattern dimension, be good to strengthen anisotropy.Particularly, the oxygen plasma treatment with RIE (Reactive Ion Etching) mode, ICP (the Inductive Coupled Plasama) mode with high-density plasma source or TCP (Transfer CoupledPlasama) mode is good.Perhaps, ideal situation is, the change in size amount of estimation photoresistance pattern designs the pattern dimension of photoresistance pattern 81A bigger in advance, or so that exposure, the development conditions that the pattern dimension of photoresistance pattern 81A increases seek technology in response to etc. disposal.And; shown in Fig. 1 (b) and Fig. 2 (b); with photoresist pattern 81C as mask; with the 2nd SiNx layer 32A; with the width mode selectivity in addition etching also thinner than gate electrode 11A; form the 2nd SiNx layer 32D (etch stop layer, path protection layer, protection insulation course), expose the first amorphous silicon layer 31A on the sweep trace 11 and the first amorphous silicon layer 31B on the capacitor storage beam 16 simultaneously.The protection insulation course forms the zone; it is the size of photoresist pattern 81C (black region); minimum dimension has the size of 10 μ m at least; not only the zone beyond white region and the black region makes as the mask plate in halftone exposure zone and is easy to; with the insulated gate transistor of channel etch type relatively the time; the ON electric current of insulated gate electrode transistor npn npn is that the size by path protection insulation course 32D decides; rather than decided by the size of 12,21 of source electrodes, drain electrode wiring, so process management is more easy.Particularly, for example to make the size between source electrode, drain electrode wiring become 5 ± 1 μ m in channel etch type, the size of the protection insulation course of etch-stop type becomes the mode of 10 ± 1 μ m, and under identical exposure, development conditions, the variation of ON electric current approximately reduces by half.
After removing photoresist pattern 81C, shown in Fig. 1 (c) and Fig. 2 (c), form insulation course 76 in the side of gate electrode 11A.Therefore, as shown in figure 21, must have that (capacitor storage beam 16 too with sweep trace 11, then omit diagram herein) wiring 77 of binding side by side with electroplate or be used to provide during anodic oxidation current potential at the outer peripheral portion of glass substrate 2 be connected pattern 78, and, the system diaphragm area 79 of the amorphous silicon layer 31 that use makes with plasma CVD and the suitable mask means of silicon nitride layer 30,32 is limited to the inside that connects pattern 78, must expose at least to connect pattern 78.Connecting on the pattern 78, use connection means such as crocodile clip, give+(just) current potential, make glass substrate 2 soak in the reactant liquor that with ethylene glycol is Main Ingredients and Appearance when carrying out anodic oxidation, if sweep trace 11 is the words of alloy for Al, then response voltage 200V for example forms the aluminium oxide (Al with 0.3 μ m thickness
2O
3).During plating, shown in monthly magazine " Process Technology of Polymer " in November, 2002 document, contain the polyimide electroplate liquid of five carboxyls,, form polyimide resin bed with 0.3 μ m thickness with plating (electroplating) voltage of counting V.And, by forming insulation course 76, the pin hole that is created in the gate insulator 30A on the sweep trace 11 belongs to the aluminium oxide of insulation course or the cause that the polyimide resin is imbedded, so the spinoff that also has the layer short circuit between source electrode described later, the drain electrode wiring 12,21 to be suppressed.
Then, use the PCVD device, on whole of glass substrate 2, with for example thickness about 0.05 μ m, after being capped second amorphous silicon layer 33 of impure for example phosphorus, shown in Fig. 1 (d) and Fig. 2 (d), zone beyond image displaying part utilizes Micrometer-Nanometer Processing Technology, on sweep trace 11, form opening portion 63A, with forming opening portion 65A on the capacitor storage beam 16 or on the electrode terminal at the arranged side by side electrode of binding capacitor storage beam 16, optionally remove first amorphous silicon layer 33 in the opening portion 63A, the first amorphous silicon layer 31A and gate insulator 30A, and optionally remove part of scanning line 73, second amorphous silicon layer 33 in the opening portion 65A, the first amorphous silicon layer 31B and gate insulator 30B, exposed portions serve capacitor storage beam 16.
Then, in the formation operation of source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is as implementing anodised heat resistant metal layer; Can carry out anodised low resistance wiring layer equally with for example Al thin layer 35 conducts about thickness 0.3 μ m; Can implement anodised intermediate conductive layer equally with heating resisting metal thin layers such as for example Ta 36 conducts about thickness 0.1 μ m.Then, utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern, the source electrode that etching in regular turn is made of this three-layer thin-film, drain electrode wiring material and second amorphous silicon layer 33 and the first amorphous silicon layer 31A, 31B, and expose gate insulator 30A, 30B, and shown in Fig. 1 (e) and Fig. 2 (e), optionally form by the drain electrode 21 of the insulated gate electrode transistor npn npn that lamination constituted of 34A, 35A, 36A and the signal wire 12 of double as source electrode.In order not make source electrode, drain electrode wiring 12,21 setover and can't work, must form with path protection layer 32D certainly and overlap.And, generally for fear of the spinoff of following galvanic action to produce, when source electrode, drain electrode wiring 12,21 form, also comprise the electrode terminal 5 that part of scanning line 73 ground form sweep trace simultaneously, but because electrode terminal 5 is dispensable, so also can directly form transparent conductivity electrode terminal 5A in subsequent handling.With regard to the formation of source electrode, drain electrode wiring 12,21, when the restriction of resistance value is loose, it is rational simplifying and forming the Ta individual layer, in addition, add in the Al alloy of Nd, chemical potential reduces, the chemical corrosion reaction that produces with ITO in alkaline solution can be suppressed, so do not need intermediate conductive layer 36 this moment, the stromatolithic structure of source electrode, drain electrode wiring 12,21 can be formed two-layer formation, and the formation of source electrode, drain electrode wiring 12,21 can obtain some simplification.This part adopts IZO to replace ITO also is same situation.
After source electrode, drain electrode wiring 12,21 form, use SPT equal vacuum film forming apparatus, on whole of glass substrate 2, for example cover the ITO about thickness 0.1 to 0.2 μ m as transparency conducting layer, and shown in Fig. 1 (f) and Fig. 2 (f), utilize Micrometer-Nanometer Processing Technology, comprise the part intermediate conductive layer 36A of drain electrode 21, on glass substrate 2, optionally form pixel electrode 22.At this moment, the zone outside the pixel display part on the electrode terminal 5 of sweep trace and on the electrode terminal 6 of segment signal line, also forms the electrically conducting transparent layer pattern, and as electrode terminal 5A, the 6A of transparent conductivity.As mentioned above, do not form electrode terminal 5, be fine yet and comprise the direct electrode terminal 5A that forms in opening portion 63A ground at this moment.And, same at this and conventional example, by transparent conductivity short-circuit line 40 is set, electrode terminal 5A, 6A and 40 of short-circuit lines are formed elongated wire, carry out high resistanceization and form the high resistance that the static countermeasure is used.
And shown in Fig. 1 (g) and Fig. 2 (g), the photoresist pattern 83A that forms pattern with the selectivity that is used in pixel electrode 22 is as mask, and irradiates light source electrode, drain electrode wiring 12,21 simultaneously carries out anodic oxidation, to form oxide layer on its surface.At this moment, electrode terminal 5A, 6A protect with photoresist pattern 83B, 83C.At source electrode, expose Ta above the drain electrode wiring 12,21, and expose Ta, Al in the side, the lamination of Ti and the second amorphous silicon layer 33A, and utilize anodic oxidation to make the second amorphous silicon layer 33A go bad into impure silicon oxide layer (SiO respectively
2) 66, Ti goes bad into semi-conductive titanium dioxide (TiO
2) 68, Al goes bad and becomes aluminium oxide (AL as insulation course
2O
3) 69, and Ta goes bad and becomes tantalum pentoxide (Ta as insulation course
2O
5) 70.Titanium oxide layer 68 is not an insulation course, thickness as thin as a wafer, therefore the area that exposes is also very little, can not constitute problem in passivation, and heating resisting metal thin layer 34A preferably selects Ta.But should be noted that Ta is different with Ti, the surface oxide layer at the bottom of its shortcoming absorption base makes the more easy functional characteristic of Ohmic contact.
In order on drain electrode wiring 21, to form good membranous anodic oxide coating, thus irradiates light to implement anodic oxidation simultaneously be the very important point on the anodic oxidation operation, this has been disclosed in the existing example.Particularly, if the light of the intensity abundance about irradiation one myriametre candle light (lux), the leakage current of insulated gate electrode transistor npn npn surpasses μ A, by the area calculating of drain electrode 21, with 10mA/cm
2About anodic oxidation, can obtain being used for obtaining good membranous current density.And, even anodic oxide coating is membranous insufficient on the drain electrode wiring 21, the reason that generally can obtain abundant reliability is, the drive signal that puts on the liquid crystal structure cell exchanges basically, so that the mode that the DC voltage composition tails off between counter electrode 14 and pixel electrode 22 (drain electrode 21), when checking, image adjusts the voltage (adjustment that flicker reduces) of counter electrode 14, the DC voltage composition tails off, so on the basic principle, as long as form insulation course in advance, flip-flop is flowed get final product.
The thickness of each oxide layer of the tantalum pentoxide 70 that forms with anodic oxidation, aluminium oxide 69, titanium dioxide 68, silicon oxide layer 66, form the passivation that has been enough to about 0.1 to 0.2 μ m as wiring, make the reactant liquor of spent glycol etc., apply voltage and surpass 100V equally and realize.The item that should be careful during the anodic oxidation of source electrode, drain electrode wiring 12,21 is, though not shown but all signal wires 12 must form electrically in parallel or series connection, in follow-up several manufacturing processes, when not removing this parallel connection or series connection, not only can the electric checking of active formula substrate 2 be counteracted, also can the practical operation of liquid crystal indicator be counteracted.As removing the measure that electrically connects, can utilize laser light illumination to make and evapotranspire, or utilize the mechanical type that strikes off to remove, quite simple, but omit detailed explanation herein.
Covering earlier the reason of pixel electrode 22 with photoresist pattern 83A, is not only not need pixel electrode 22 anodic oxidations, also need not be via the insulated gate electrode transistor npn npn, and serve as must be more than the value with the kinetic current of guaranteeing to flow to drain electrode 21.
At last, remove above-mentioned photoresist pattern 83A to 83C, shown in Fig. 1 (h) and Fig. 2 (h), finish active formula substrate 2 (semiconductor device that is used for display device).Active formula substrate 2 that order obtains in this way and colored filter are fitted and liquid crystal panelization is finished the first embodiment of the present invention.Formation about storage capacitors 15, then shown in Fig. 1 (h), illustration capacitor storage beam 16 and pixel electrode 22 sandwich gate insulator 30B form the configuration example of plane overlapping (upper left oblique line part) toward the bottom right, but the formation of storage capacitors 15 is not limited to this, also can be between pixel electrode 22 and leading portion sweep trace 11, sandwich contains the insulation course of gate insulator 30A and constitutes.In addition, other formation also is passable, but omits its detailed explanation.Similarly, because the formation that has sweep trace 11 contacts operation,, carry out the static countermeasure and also be easier to so use conductive material or semiconductor layer beyond the transparency conducting layer.
First embodiment, because it is that then source electrode, drain electrode wiring form operation and carry out that pixel electrode forms operation, therefore can reduce because the short circuit of source wiring and pixel electrode easily produces yield rate, and overlapping with sweep trace, the effect of performance stray capacitance, make pixel electrode become big, aperture opening ratio improves, and is very undesirable.So, in order to improve aperture opening ratio again, use thick transparent resin, with source electrode, drain electrode wiring in addition the liquid crystal indicator of passivation illustrate in a second embodiment.
Second embodiment
Second embodiment shown in Fig. 3 (c) and Fig. 4 (c), till the side formation insulation course 76 of gate electrode 11A, carries out with the manufacturing process identical with first embodiment.Then, use the PCVD device, on whole of glass substrate 2, with for example thickness about 0.05 μ m, after covering second amorphous silicon layer 33 of impure for example phosphorus, use SPT equal vacuum film forming apparatus, cover in regular turn: the thin layers 34 such as Ti, Ta about thickness 0.1 μ m, as heat resistant metal layer; With thickness be Al thin layer 35 about 0.3 μ m, as the low resistance wiring layer.And, utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern, the source electrode that etching in regular turn is made of this three-layer thin-film, drain electrode wiring material, second amorphous silicon layer 33 and the first amorphous silicon layer 31A, 31B, and expose gate insulator 30A, 30B.Shown in Fig. 3 (d) and Fig. 4 (d), optionally form: the drain electrode 21 of the insulated gate electrode transistor npn npn that is constituted by 34A, 35A and 36a lamination and the signal wire 12 of double as source electrode.And if the restriction of resistance value pine, then the formation of source electrode, drain electrode also can be simplified to the Ta individual layer, and selects to add the Al alloy of Nd, the stromatolithic structure of source electrode, drain electrode wiring 12,21 is made two-layer formation also be fine.
Then, shown in Fig. 3 (e) and Fig. 4 (e), on whole of glass substrate 2, the transparency that coating thickness 1.5 μ m are above and the photonasty polyacrylic resin 39 of excellent heat resistance are as transparent insulating layer, be preferably with the thickness about 0.3 μ m and be coated with, by using the selectivity ultraviolet ray irradiation of mask plate, on drain electrode 21 and image displaying part beyond the zone, respectively on the part 5 of sweep trace and on the part 6 of signal wire and the electrode terminal of capacitor storage beam form on the zone, form opening portion 62,63,64,65.And, after bake and bank up with earth after, as mask, respectively gate insulator 30A, the 30B in the selective removal opening portion 63,65 exposes the part 73 (5) of sweep trace and the part 75 of capacitor storage beam with photonasty polyacrylic resin 39.In opening portion 62,64, after developing, expose the part 21 of drain electrode and the part 74 (6) of signal wire.And aperture opening ratio has reduction slightly, yet can be without photonasty polyacrylic resin 39, and adopts the SiNx layer as passivation insulation, also can use transparent insulating layer to form above-mentioned opening portion 62,63,64,65 at the SiNx layer usually.
The last SPT equal vacuum film forming apparatus that on whole of glass substrate 2, uses, with for example thickness about 0.1 to 0.2 μ m, for example cover ITO as transparency conducting layer, shown in Fig. 3 (f) and Fig. 4 (f), pass through Micrometer-Nanometer Processing Technology, on the polyacrylic resin 39 of the part intermediate conductive layer 36A that comprises the drain electrode 21 that is exposed in the opening portion 62, optionally form pixel electrode 22.Photonasty polyacrylic resin 39 is very thick, so pixel electrode 22 forms greatly as far as possible, even part is overlapping with sweep trace 11 or signal wire 12, also can not produce image quality deterioration such as crosstalk.Ci Time to comprise part of scanning line 73 in the opening portion 63 and the segment signal line 74 in the opening portion 64, forms electrode terminal 5A, the 6A of transparent conductivity.Then, in this and conventional example similarly, by short-circuit line 40, forming elongated wire with high resistanceization between electrode terminal 5A, 6A and the short-circuit line 40, as the static countermeasure at the arranged outside transparent conductivity of electrode terminal 5A, 6A.
Make the active formula substrate 2 and the chromatic color filter applying of gained according to this, liquid crystal panelization, and finish the second embodiment of the present invention.The formation of relevant storage capacitors 15, shown in Fig. 3 (e), illustration capacitor storage beam 16 and drain electrode 21 sandwich gate insulator 30B and the first amorphous silicon layer 31B and second amorphous silicon layer and overlapping areas 50 (upper left oblique line part) toward the bottom right, constitute the example of accumulating electric capacity 15, again, the sweep trace 11 sandwich gate insulator 30A of drain electrode 21 and leading portion constitute storage capacitors 15 and also are fine, but omit its detailed description at this.
Among first and second embodiment; at the formation operation of so-called sweep trace and the lower layer of pattern precision such as formation operation of path protection layer (etch stop layer); use the halftone exposure technology; reduce the lithography operation; make active formula substrate with four road mask plates, but adopt the formation that one mask plate comes processed pixels electrode and sweep trace, can further reduce operation again; can make active formula substrate with three road mask plates, this part will illustrate in the 3rd to the 5th embodiment.
The 3rd embodiment
Among the 3rd embodiment, at first on an interarea of glass substrate 2, use SPT equal vacuum film forming apparatus, cover: thickness is the transparency conducting layer 91 about 0.1 to 0.2 μ m, for example ITO; With thickness be transparency conducting layer 91 about 0.1 to 0.2 μ m; With thickness be the first metal layer 92 about 0.1 to 0.3 μ m.Be appreciated that by follow-up explanation among the 3rd to the 5th embodiment, sweep trace is the lamination of transparency conducting layer and metal level, so can't utilize anodic oxidation to form insulation course in the side of sweep trace.So, form organic insulator because be by electroplating at insulation course, so with regard to the sweep trace material, can adopt not can with the first metal layer that cell reaction takes place as the ITO of transparency conducting layer, for example refractory metal or these alloy or silicides such as Cr, Ta, Mo.When realizing low resistance, if adopt Al, the individual layer of Al (Nd) alloy is the simplest, and then, the lamination of establishing Ta/Al (Zr, Hf) that Ta constitutes or Ta/AL/Ta of being situated between is comparatively complicated.
Secondly; on whole of glass substrate 2; use the PCVD device; respectively with for example 0.3 μ m; 0.05 μ m; 0.1 the thickness about μ m; cover in regular turn: as a SiNx layer 30 of gate insulator; as first amorphous silicon layer 31 of impure hardly insulated gate electrode transistor npn npn passage and as the 2nd SiNx layer 32 in order to the insulation course of protection passage; then; shown in Fig. 5 (a) and Fig. 6 (a); utilize the halftone exposure technology; forming the zone at the protection insulation course is that the thickness of regional 82A on the gate electrode 11A for example is 2 μ m; form sweep trace 11 and the analog pixel electrode 93 of Film Thickness Ratio corresponding to double as gate electrode 11A; simulation electrode terminal 94; the also thick photoresist pattern 82A of thickness 1 μ m of 95 photoresist pattern 82B; 82B; and with photoresist pattern 82A; 82B is as mask; add the 2nd SiNx layer 32 (path protection layer); first amorphous silicon layer 31; gate insulator 30 and the first metal layer 92; and also optionally remove transparency conducting layer 91, and expose glass substrate 2.
In the above described manner; behind the multilayer film pattern of acquisition corresponding to the sweep trace 11 of double as gate electrode 11A and analog pixel electrode 93 and simulation electrode terminal 94,95; then; utilize ashing means such as oxygen plasma, make the thickness of above-mentioned photoresist pattern 82A, 82B reduce by 1 μ m when above, photoresist pattern 82B disappears; expose the 2nd SiNx layer 33A to 33C; simultaneously, can only form on the zone, optionally form photoresist pattern 82C at the protection insulation course.Above-mentioned oxygen plasma treatment preferably forms the mode that the mask alignment precision of operation can not reduce with follow-up source electrode, drain electrode wiring, strengthens anisotropy to suppress the variation of pattern dimension, and this is identical with the reason of having stated.And, shown in Fig. 5 (b) and Fig. 6 (b), with photoresist pattern 82C as mask, etching the 2nd SiNx layer 32A to 32C optionally, the SiNx layer 32D that pattern width is also thinner than gate electrode 11A remains on the gate electrode 11A, respectively exposing the first amorphous silicon layer 31A on the sweep trace 11 He on the simulation electrode terminal 94, on analog pixel electrode 93, expose the first amorphous silicon layer 31B simultaneously, and on simulation electrode terminal 95, expose the first amorphous silicon layer 31C.
Then, remove above-mentioned photoresist pattern 82C after, shown in Fig. 5 (c) and Fig. 6 (c), form insulation course 76 in the side of gate electrode 11A.Therefore, use the connection means of crocodile clips etc., give sweep trace 11+ (just) current potential at connection pattern shown in Figure 21 78, however also can be according to the composition of electroplate liquid, and give-(bearing) current potential.And, with regard to organic insulator,, form polyimide resin bed with 0.3 μ m thickness for example to count the V electroplating voltage.Analog pixel electrode 93 is because electrically independently, so can not form insulation course 76 around analog pixel electrode 93.
Then, use the PCVD device, on whole of glass substrate 2, with for example thickness about 0.05 μ m, cover second amorphous silicon layer 33 of impure for example phosphorus, shown in Fig. 5 (d) and Fig. 6 (d), Micrometer-Nanometer Processing Technology by usability photosensitiveness resin pattern 88, on analog pixel electrode 93, form opening portion 38, with form opening portion 63A on the simulation electrode terminal 94 of sweep trace 11 in zone beyond the image displaying part, with formation opening portion 64A on the simulation electrode terminal 95 of signal wire, add second amorphous silicon layer 33 and the first amorphous silicon layer 31A to 31C and gate insulator 30A to 30C in the above-mentioned opening portion, also optionally remove the first metal layer 92A to 92C, expose the electrode terminal 5A of the sweep trace that transparency conducting layer and transparency conducting layer constitute and the electrode terminal 6A of signal wire, pixel electrode 22.
At last, use SPT equal vacuum film forming apparatus, cover in regular turn: the heating resisting metal thin layers 34 such as Ti, Ta about thickness 0.1 μ m are as heat resistant metal layer, and are that Al thin layer 35 about 0.3 μ m is as the low resistance wiring layer with thickness.Utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 85, etching in regular turn is by second amorphous silicon layer 33 and the first amorphous silicon layer 31A, and expose gate insulator 30A, shown in Fig. 5 (e) and Fig. 6 (e), optionally form: contain the part of pixel electrode 22 and the drain electrode 21 of the insulated gate electrode transistor npn npn that constituted by 34A and 35A lamination; The signal wire 12 that contains the double as source electrode of the part of electrode terminal 6A of signal wire and the insulated gate electrode transistor npn npn that constituted by 34A and 35A lamination equally.When the electrode terminal 5A of sweep trace and the electrode terminal 6A of signal wire finish in the etching of source electrode, drain electrode wiring 12,21, can on glass substrate 2, expose.In addition, with regard to the formation of source electrode, drain electrode wiring 12,21,, then also can simplify individual layers such as forming Ta, Cr, MoW if the restriction of resistance value is loose.
Active formula substrate 2 that order is made in this way and colored filter are fitted, liquid crystal panelization, and finish third embodiment of the invention.Among the 3rd embodiment, because photoresist pattern 85 is connected to liquid crystal, so photoresist pattern 85 is not to be the general photoresist of Main Ingredients and Appearance with lacquer with phenolic aldehyde (novolac) resin, and the high photonasty organic insulator of thermotolerance that uses purity height and Main Ingredients and Appearance to contain allyl resin or polyimide resin is very important, and, also can heat according to material, make its liquidation, constitute in the mode that covers source electrode, drain electrode wiring 12,21 sides, at this moment, can further promote the reliability of liquid crystal panel.Formation about storage capacitors 15, shown in Fig. 5 (e), illustration contain source electrode, drain electrode wiring 12,21 with the part of pixel electrode 22, and storage electrode 72 that forms and the jut that is located at leading portion sweep trace 11, sandwich gate insulator 30B, the first amorphous silicon layer 31A, second amorphous silicon layer forms the overlapping example in plane (upper left oblique line part 52 toward the bottom right), but the formation of storage capacitors 15 is not limited thereto, with first embodiment similarly, also can and the sweep trace 11 shared electric capacity line 16 and pixel electrode 21 that form simultaneously between, the insulation course that sandwich contains gate insulator 30 constitutes.Static countermeasure line 40 is to constitute with the transparency conducting layer that is connected to electrode terminal 5A, 6A, yet forms operation because of it provides the opening portion to gate insulator 30A to 30C, so also can adopt other antistatic countermeasure.
Among the 3rd embodiment, the electrode terminal that can produce the electrode terminal of sweep trace like this and signal wire all is the restriction on the device of transparency conducting layer constitutes, but, also can use device, the technology of removing this restriction, this part will illustrate in the 4th, the 5th embodiment.
The 4th embodiment
The 4th embodiment is shown in Fig. 7 (d) and Fig. 8 (d), till formation contact operation, is to carry out with the operation that is approximately identical to the 3rd embodiment.Yet, learn by reason described later, not necessarily need simulation electrode terminal 95.Thereafter, form operation at source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the heating resisting metal thin layers 34 such as Ti, Ta about thickness 0.1 μ m are as heat resistant metal layer; With thickness be that Al thin layer 35 about 0.3 μ m is as the low resistance wiring layer.Utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 86, the source electrode that etching in regular turn is made of this double-layer films, drain electrode wiring material, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A, and expose gate insulator 30A.Shown in Fig. 7 (e) and Fig. 8 (e), optionally form: contain the part of pixel electrode 22 and the drain electrode 21 of the insulated gate electrode transistor npn npn that constituted by 34A and 35A lamination; With the signal wire 12 of double as source wiring, and be contained in a part of 5A of the sweep trace that exposes when source electrode, drain electrode wiring 12,21 forms, also form simultaneously by the electrode terminal 5 of sweep trace and the electrode terminal that a part constituted 6 of signal wire.That is to say, not necessarily need to have simulation electrode terminal 95 as the 3rd embodiment.At this moment, the key character of the 4th embodiment is, utilize the halftone exposure technology, form in advance photoresist pattern 86A, 86B, and the thickness of this photoresist pattern 86A, 86B to be the thickness of the regional 86A on the signal wire 12 for example be 3 μ m, greater than on the drain electrode 21, on the electrode terminal 5,6 and the thickness 1.5 μ m of the 86B on the storage electrode 72.With the minimum dimension of electrode terminal 5,6 corresponding 86B be several 10 μ m, bigger, mask plate is made, finished size is managed than being easier to, and with the minimum dimension of signal wire 12 corresponding regional 86A be 4 to 8 μ m, dimension precision requirement is than higher, so half-tone regions must form thinner slit pattern.Yet, the explanation of regulations as usual, compare with the source electrode, the drain electrode wiring 12,21 that utilize single exposure processing and twice etch processes formation, because source electrode of the present invention, drain electrode wiring the 12, the 21st form by single exposure processing and an etch processes, so it is less to influence the factor of pattern width change, and the size management of source electrode, drain electrode wiring 12,21, source electrode, 12,21 of drain electrode wirings are the size management of passage length, compared to the halftone exposure technology of routine, the management of its pattern precision is more or less freely.And, when comparing with the insulated gate transistor of channel etch type, the ON electric current of decision insulated gate electrode transistor npn npn; it is the size of path protection insulation course 32D; rather than the size of 12,21 of source electrodes, drain electrode wiring, by this some as can be known, process management is more easy.
Source electrode, drain electrode wiring 12, after 21 formation, utilize ashing means such as oxygen plasma, make above-mentioned photoresist pattern 86A, the thickness of 86B reduces by 1.5 μ m when above, photoresist pattern 86B disappears, shown in Fig. 7 (f) and Fig. 8 (f), drain electrode 21, with electrode terminal 5,6 expose, simultaneously can only on signal wire 12, optionally form photoresist pattern 86C, still, owing to utilize above-mentioned oxygen plasma treatment, when the pattern width of photoresist pattern 86C is attenuated, expose above the signal wire 12, reliability reduces, so preferably strengthen anisotropy, suppress the variation of pattern dimension.In addition, with regard to the formation of source electrode, drain electrode wiring 12,21,, then also can be simplified to individual layers such as Ta, Cr, Mo if the restriction of resistance value is loose.
Active formula substrate 2 that order is made in this way and colored filter are fitted, liquid crystal panelization, and finish fourth embodiment of the invention.Because among the 4th embodiment, photoresist pattern 86C is connected to liquid crystal, so photoresist pattern 86C is not to be the general photoresist of Main Ingredients and Appearance with lacquer with phenolics, the high photonasty organic insulator of thermotolerance that uses purity height and Main Ingredients and Appearance to contain allyl resin or polyimide resin is very important, and can to heat and to make liquidation, cover the mode of believing wire size line 12 sides and constitute with the material difference.At this moment, can further promote the reliability of liquid crystal panel.Formation about storage capacitors 15 is shown in Fig. 7 (f), illustration contain the part of source electrode, drain electrode wiring 12,21 and pixel electrode 22, and storage electrode 72 that forms and the jut that is located at leading portion sweep trace 11, sandwich gate insulator 30B, the first amorphous silicon layer 31A, second amorphous silicon layer form the overlapping example in plane (upper left oblique line part 52 toward the bottom right).Then, by will be in order to the electrically conducting transparent layer pattern of coupling part sweep trace 5A and signal wire 12 formed transparent conductivity pattern 6A (simulation electrode terminal 91C) and short-circuit line 40, its shape forms elongated wire, can form the high resistance wiring of static countermeasure, yet, can certainly use other electroconductive component as antistatic countermeasure.
In the fourth embodiment of the present invention, only on signal wire 12, form organic insulator, drain electrode 21 is to expose at the state of guaranteeing electric conductivity, the reason that also can obtain sufficient reliability by this formation be because, the drive signal that is applied to the liquid crystal structure cell exchanges basically, 22 of counter electrode 12 and pixel electrodes, the mode that tails off with the DC voltage composition, when checking, image adjusts the voltage of counter electrode 14, (adjustment that flicker reduces), therefore, only on signal wire 12, form insulation course in advance, the direct current composition can not circulated get final product.
Among third and fourth embodiment of the present invention, only respectively on source electrode, the drain electrode wiring and on the signal wire, optionally form organic insulator, to reach the minimizing of manufacturing process, still, because the thickness of organic insulator is generally more than the 1 μ m, therefore high-precision thin panel pixels hour, use plain grinding to handle with the orientation of the alignment film of cloth, probably can be because of there being difference in height to cause non-orientation state, or on the guaranteeing of the gap precision of liquid crystal structure cell the possible type of generation obstacle.At this, the 5th embodiment possesses by setting up minimal process number, to become the passivating technique of organic insulator.
The 5th embodiment
The 5th embodiment is shown in Fig. 9 (d) and Figure 10 (d), till formation contact operation, carries out with the operation that is approximately identical to the 3rd, the 4th embodiment.Next, form in the operation at source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the heating resisting metal thin layers such as Ti, Ta 34 about thickness 0.1 μ m are as carrying out anodised heat resistant metal layer; Can carry out anodised low resistance wiring layer with Al thin layer 35 conducts about thickness 0.3 μ m.Then, utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 87, the source electrode that etching in regular turn is made of this double-layer films, drain electrode wiring material, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A, and expose gate insulator 30A.Shown in Fig. 9 (e) and Figure 10 (e), optionally form: contain the part of pixel electrode 22 and the drain electrode 21 of the insulated gate electrode transistor npn npn that constituted by 34A and 35A lamination and the signal wire 12 of double as source wiring, also form simultaneously: the electrode terminal 5 of sweep trace, it comprises the part of scanning line 5A that is exposed when forming source electrode, drain electrode wiring 12,21; With electrode terminal 6 by segment signal line constituted.At this moment, the key character of the 5th embodiment is, utilize the halftone exposure technology, form photoresist pattern 87A, 87B in advance, and the thickness of this photoresist pattern 87A, 87B is the thickness of the regional 87A (black region) on the electrode terminal 5,6 for example is 3 μ m, greater than the thickness 1.5 μ m of the regional 87B (middle tone zone) on source electrode, the drain electrode 12,21 and on the storage electrode 72.
After source electrode, drain electrode wiring 12,21 form, utilize ashing means such as oxygen plasma, make the thickness of above-mentioned photoresist pattern 87A, 87B reduce by 1.5 μ m when above, photoresist pattern 87C disappears, source electrode, drain electrode wiring 12,21 and storage electrode 72 expose, and can only optionally form photoresist pattern 87C simultaneously on sweep trace 12.The feature of being worth mentioning is, even utilize above-mentioned oxygen plasma treatment, the pattern width of photoresist pattern 87C is attenuated, because only around electrode terminal 5,6 with big pattern dimension, form anodic oxide coating, so can impact electric characteristics and yield rate and quality hardly.Then, with photoresist pattern 87C as mask, irradiates light, shown in Fig. 9 (f) and Figure 10 (f), source electrode, drain electrode wiring 12,21 are carried out anodic oxidation and form oxide layer 68,69, the second amorphous silicon layer 33A that source electrode, drain electrode wiring 12,21 downsides are exposed carries out anodic oxidation simultaneously, and forms the silicon oxide layer (SiO as insulation course
2) 66.
After anodic oxidation finishes, when removing photoresist pattern 87C, shown in Fig. 9 (g) and Figure 10 (g), expose the electrode terminal 5,6 that is constituted by the low resistance thin film layer 35A that forms anodic oxide coating in its side.The side of scan-line electrode terminal 6 is via static countermeasure high resistance shorts line 40 (91C) as can be known, the circulation oxidation current, so compare with the electrode terminal 5 of signal wire, the anodized layer thickness that is formed on the side is thinner.In addition, with regard to the formation of source electrode, drain electrode wiring 12,21,, then also can be simplified to and be carried out anodised Ta individual layer if the restriction of resistance value is loose.Active formula substrate 2 that order is made in this way and colored filter are fitted, liquid crystal panelization, and finish fifth embodiment of the invention.Formation about storage capacitors 15, be shown in Fig. 9 (g), exemplified a part that contains source electrode, drain electrode wiring 12,21 and pixel electrode 22, and storage electrode 72 that forms and the jut that is located at leading portion sweep trace 11 clip gate insulator 30A, the first amorphous silicon layer 31A, the overlapping example (upper left oblique line part 52 toward the bottom right) in second amorphous silicon layer formation plane.
Among the 5th embodiment, like this, when source electrode, drain electrode wiring 12,21 and the second amorphous silicon layer 33B carried out anodic oxidation, the pixel electrode 22 that electrically is mutually with drain electrode 21 also can expose, so pixel electrode 22 also simultaneously can be by anodic oxidation, this point is very different with first embodiment.Therefore, along with the membranous difference of the transparency conducting layer that constitutes pixel electrode 22, resistance value can increase because of anodic oxidation sometimes, at this moment, must suitably change the film forming condition of transparency conducting layer earlier, form the membranous of hypoxgia, but the transparency of transparency conducting layer can not reduce because of anodic oxidation.Then, for drain electrode 21, pixel electrode 22 and storage electrode 72 anodised electric currents also is to supply with via the passage of insulated gate electrode transistor npn npn, yet, because the area of pixel electrode 22 is bigger, therefore need big kinetic current or reaction for a long time, no matter shine how strong outer light, the resistance of channel part can not produce obstruction, on drain electrode 21 and storage electrode 72, form with signal wire 12 on the anodic oxide coating of equal membranous and thickness, only utilize the prolongation in reaction time that difficulty in the adaptation is arranged really.Yet some is incomplete even be formed on anodic oxide coating on the drain electrode wiring 21, can obtain not have the reliability that hinders in fact mostly.Why so be because as mentioned above, only on signal wire 12, the mode that can not circulate with the direct current composition forms insulation course in advance and gets final product.
The liquid crystal indicator of above-mentioned explanation is to use the formation of the liquid crystal structure cell of TN type, and by with pixel electrode across formed a pair of counter electrode of specific range and pixel electrode, in the liquid crystal indicator of IPS (In-Plain-Swticing) mode of control transverse direction electric field, it is useful that the operation of institute of the present invention motion reduces, and this part will illustrate in follow-up embodiment.
The 6th embodiment
The 6th embodiment, be shown in Figure 11 (e) and Figure 12 (e), on whole of glass substrate 2, with the thickness more than the 1.5 μ m, the thickness that is preferably about 3 μ m is coated with photonasty polyacrylic resin 39 as the transparency and the excellent transparent resin of thermotolerance, by using the selectivity ultraviolet ray irradiation of mask plate, on drain electrode 21 and image displaying part beyond the zone, respectively on the part 5 of sweep trace and on the part 6 of signal wire and the electrode terminal of capacitor storage beam form the zone and form opening portion 62,63,64,65, after bake and bank up with earth after, with photonasty polyacrylic resin 39 as mask, selective removal opening portion 63, gate insulator 30A in 65,30B, till the part 75 of a part 73 (5) of exposing sweep trace respectively and capacitor storage beam, be to utilize the manufacturing process identical to carry out with second embodiment.In opening portion 62,64, after developing, expose the part 74 (6) of drain electrode 21 and signal wire.
Then, on whole of glass substrate 2, use SPT equal vacuum film forming apparatus, be coated with for example ITO about thickness 0.1 to 0.2 μ m as transparency conducting layer, shown in Figure 11 (f) and Figure 12 (f), use Micrometer-Nanometer Processing Technology, in optionally formation on a part of transparent resin 39 of the intermediate conductive layer 36A that comprises the drain electrode 21 that exposes opening portion 62 in: pixel electrode 41 and comprise on the sweep trace 11 with signal wire 12 on counter electrode 42.At this moment, comprise electrode terminal 5A, the 6A of the part 74 of the part 73 of the sweep trace in the opening portion 63 and the signal wire in the opening portion 64 as transparent conductivity, same with conventional example, be provided with the short-circuit line 40 of electrically conducting transparent position, by will forming elongated wire between electrode terminal 5A, 6A and the short-circuit line 40, but high resistanceization and form antistatic countermeasure.
In IPS type liquid crystal indicator, the gap affects of pixel electrode 41 and counter electrode 42 shows, yet pixel electrode 41 and counter electrode 42, current potential in its electrode is certain, influence does not show, so form pixel electrode 41 and counter electrode 42, not necessarily the most suitable selection with transparency conducting layer.When using metallic for example Ti, Cr, MoW alloy replacement transparency conducting layer, resistance value descends, so the thickness of pixel electrode 41 and counter electrode 42 can attenuation, promote regiospecific, or must be by not selecting Ti/Al alloy lamination, top section at source electrode, drain electrode wiring 12,21 disposes intermediate metal layers such as Ti or Ta, and the formation of source electrode, drain electrode wiring 12,21 can be simplified.But when selecting metallic electrode, when not implementing the static countermeasure different with above-mentioned static countermeasure, high resistanceization is had any problem.Pixel electrode 41 and counter electrode 42 adopt transparency conducting layer to have good advantage, this is because produce in the volume production factory of TN type liquid crystal panel and IPS type liquid crystal panel simultaneously, do not need to change the target of sputtering unit, or do not need two kinds of reasons such as sputtering unit.
Among the 6th embodiment, also configurable counter electrode on the invalid sweep trace 11 and on the signal wire 12 on the conventional optics, this result, the zone of giving demonstration can enlarge, can obtain the IPS type display panels of high aperture, but, be difficult for reducing more worker ordinal number.So, passivation is formed rationalization, further reduce the invention of worker ordinal number, in the 7th and the 8th embodiment explanation.
The 7th embodiment
Among the 7th embodiment, at first, with conventional example similarly, use SPT equal vacuum film forming apparatus, on an interarea of glass substrate 2, the alloy or the silicide of for example Cr, the Ta about covering thickness 0.1 to 0.3 μ m, Mo etc. or these metals are as the first metal layer.
Then, use the PCVD device, on whole of glass substrate 2,, cover in regular turn: as a SiNx layer 30 of gate insulator respectively with for example thickness about 0.3 μ m, 0.05 μ m, 0.1 μ m; With as first amorphous silicon layer 31 of impure insulated gate electrode transistor npn npn passage hardly; With three kinds of thin layers such as the 2nd SiNx layer 32 grade as the insulation course of protecting passage; then shown in Figure 13 (a) and Figure 14 (a); utilize the halftone exposure technology; making the protection insulation course form the zone is that the thickness of the regional 84A on the gate electrode 11A for example forms 2 μ m; ratio is corresponding to the thicker photoresist 84A of thickness 1 μ m on the regional 84B of the counter electrode 16 of double as sweep trace 11 and capacitor storage beam; 84B; and with photoresist pattern 84A; 84B is a mask; optionally remove the 2nd SiNx layer 32 (path protection layer); first amorphous silicon layer 31; gate insulator 30 and the first metal layer, and expose glass substrate 2.
Then; utilize ashing means such as oxygen plasma; make the thickness of above-mentioned photoresist pattern 84A, 84B reduce by 1 μ m when above; photoresist pattern 84B disappears; on sweep trace 11, expose the 2nd SiNx layer 32A; on counter electrode 16, expose the 2nd SiNx layer 32B; simultaneously can be only the protection insulation course form peak width than thinner optionally etching the 2nd SiNx layer 32A of gate electrode 11A as the 2nd SiNx layer 32D; simultaneously on sweep trace 11, expose the first amorphous silicon layer 31A, and on counter electrode 16, expose the first amorphous silicon layer 31B.
After removing above-mentioned photoresist pattern 84C, shown in Figure 13 (c) and Figure 14 (c), form insulation course 76 in the side of gate electrode 11A.Therefore, as shown in figure 25, must have that (capacitor storage beam 16 too with sweep trace 11, then omit diagram herein) wiring 77 of binding side by side with electroplate at the outer peripheral portion of glass substrate 2 or be connected pattern 78 in order to what give current potential during anodic oxidation, then, use is to be limited to by connecting the inboard of pattern 78 according to the system diaphragm area 79 of the suitable plasma means of the amorphous silicon layer 31 of plasma CVD and silicon nitride layer 30,32, must expose at least and connect pattern 78.Adopt organic insulator and that one deck of anodic oxide coating all can.
Use the PCVD device, on whole of glass substrate 2, with for example thickness about 0.05 μ m, after covering second amorphous silicon layer 33 of impure for example phosphorus, shown in Figure 13 (d) and Figure 14 (d), zone beyond image displaying part, use Micrometer-Nanometer Processing Technology, on sweep trace 11, form opening portion 63A and capacitor storage beam 16, or on the electrode terminal of the electrode that bundlees capacitor storage beam 16 side by side, form opening portion 65A, and optionally remove second amorphous silicon layer 33 and the first amorphous silicon layer 31A and gate insulator 30A in the opening portion 63A, and optionally remove the part 73 of sweep trace, with second amorphous silicon layer 33 in the opening portion 65A, with the first amorphous silicon layer 31B, with gate insulator 30B, expose the part 75 of capacitor storage beam 16.
Then, in the formation operation of source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the thin layer 34 such as heating resisting metal such as for example Ti, Ta etc. about thickness 0.1 μ m is as heat resistant metal layer, and is that Al thin layer 35 about 0.3 μ m is as the low resistance wiring layer with thickness.Then, utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 86, etching in regular turn is by source electrode, drain electrode wiring material and second amorphous silicon layer 33 and the first amorphous silicon layer 31A, 31B that this double-layer films constituted, expose gate insulator 30A, 30B, shown in Figure 13 (e) and Figure 14 (e), optionally form: the drain electrode 21 that is constituted by 34A and 35A lamination as the insulated gate electrode transistor npn npn of pixel electrode; With the signal wire 12 of double as source wiring, also form simultaneously: electrode terminal 6, it contains the part of scanning line 73 that source electrode, drain electrode wiring 12,21 are exposed when forming, and is made of the electrode terminal 5 and the segment signal line of sweep trace.At this moment, utilize the halftone exposure technology, the thickness that forms in advance the 86A on the signal wire 12 for example is 3 μ m, than thickness photoresist pattern 86A, the 86B that for example 1.5 μ m are thicker of the 86B on drain electrode 21 and the electrode terminal 5,6, this is the key character of the 7th embodiment.
Source electrode, drain electrode wiring 12, after 21 formation, utilize ashing means such as oxygen plasma, make above-mentioned photoresist pattern 86A, the thickness of 86B reduces by 1.5 μ m when above, photoresist pattern 86B disappears, shown in Figure 13 (f) and Figure 14 (f), and expose drain electrode 21 and electrode terminal 5,6, simultaneously can only on signal wire 12, optionally form photoresist pattern 86C, still, owing to utilize above-mentioned oxygen plasma treatment, when the pattern width of photoresist pattern 86C is attenuated, expose above the signal wire 12, reliability reduces, so preferably strengthen anisotropy, suppress the variation of pattern dimension.And, with regard to the formation of source electrode, drain electrode wiring 12,21,, then also can simplify individual layers such as forming Ta, Cr, MoW alloy if the restriction of resistance value is loose.
Active formula substrate 2 that order is made in this way and colored filter are fitted, liquid crystal panelization, and finish seventh embodiment of the invention.IPS type liquid crystal indicator is appreciated that on active formula substrate 2 by above-mentioned explanation, does not need the pixel electrode 22 of transparent conductivity, and does not also need the counter electrode 14 of transparent conductivity on the opposite face of colored filter.Thereby, do not need the intermediate conductive layer in the source drain wiring 12,21 yet.The 7th embodiment, because photoresist pattern 86C is connected to liquid crystal, so photoresist pattern 86C is not to be the general photoresist of Main Ingredients and Appearance with lacquer with phenolic aldehyde (novolac) resin, and use purity height and Main Ingredients and Appearance to contain the high photonasty organic insulator of thermotolerance of allyl resin or polyimide resin be very important.Formation about storage capacitors 15, be shown in Figure 15 (f), illustration the part of pixel electrode (drain electrode wiring) 21 and the counter electrode 16 of double as capacitor storage beam, sandwich gate insulator 30B, the first amorphous silicon layer 31B, second amorphous silicon layer form the overlapping example that constitutes in plane (upper left oblique line part 50 toward the bottom right).Then, about the static countermeasure, then the descriptions thereof are omitted.
In the seventh embodiment of the present invention, only on signal wire, form organic insulator respectively, to reach the minimizing of manufacturing process, but, because the thickness of organic insulator is generally more than the 1 μ m, so high-precision thin panel pixels hour, uses plain grinding to handle with the orientation of the alignment film of cloth, probably can be because of there being difference in height to cause non-orientation state, or on the guaranteeing of the gap precision of liquid crystal structure cell the possibility of generation obstacle.At this, the 8th embodiment possesses by setting up minimal process number, to become the passivating technique of organic insulator.
The 8th embodiment
The 8th embodiment is shown in Figure 15 (d) and Figure 16 (d), till formation contact operation, is to carry out with the manufacturing process that is approximately identical to the 7th embodiment.Then, form in the operation at source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is as carrying out anodised heat resistant metal layer; Can carry out anodised low resistance wiring layer with Al thin layer 35 conducts about thickness 0.3 μ m.Then, utilize Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 87, the source electrode that etching in regular turn is made of this double-layer films, drain electrode wiring material, second amorphous silicon layer 33 and the first amorphous silicon layer 31A, 31B, and expose gate insulator 30A, 30B.Shown in Figure 15 (e) and Figure 16 (e), optionally form: by the drain electrode 21 of the insulated gate electrode transistor npn npn of 34A and 35A pixel electrode that lamination constitutes and the signal wire 12 of double as source wiring, also form simultaneously: electrode terminal 6, it contains the part of scanning line of being exposed when source electrode, drain electrode wiring 12,21 forms 73, and is made of the electrode terminal 5 and the segment signal line of sweep trace.At this moment, utilize the halftone exposure technology, the thickness that forms the 87A (black region) on the signal wire 12 in advance for example is 3 μ m, than thicker photoresist pattern 86A, the 86B of thickness 1.5 μ m of the regional 87B (middle tone zone) on drain electrode 21 and the electrode terminal 5,6, this is the key character of the 7th embodiment.
After source electrode, drain electrode wiring 12,21 form, utilize ashing means such as oxygen plasma, make the thickness of above-mentioned photoresist pattern 87A, 87B reduce by 1.5 μ m when above, photoresist pattern 87B disappears, source electrode, drain electrode wiring 12,21 expose, and can only optionally form photoresist pattern 87C simultaneously on electrode terminal 5,6.At this, with photoresist pattern 87C as mask plate, irradiates light is simultaneously shown in Figure 15 (f) and Figure 16 (f), source electrode, drain electrode wiring 12,21 are carried out anodic oxidation, and formation oxide layer 68,69, the second amorphous silicon layer 33A that source electrode, drain electrode wiring 12,21 downsides are exposed carries out anodic oxidation simultaneously, and forms the silicon oxide layer (SiO as insulation course
2) 66.
After anodic oxidation finishes, when removing photoresist pattern 87C, shown in Figure 15 (g) and Figure 16 (g), expose the electrode terminal 5,6 that its surface has low resistance thin film layer 35A.But, among Figure 15 (f) and Figure 16 (f), with high resistance part part, connect the static countermeasure between scan-line electrode terminal 5 and the signal line electrode terminal 6, do not illustrate especially, so electrical terminal 5 sides at sweep trace, do not form anodic oxide coating, yet, owing to give opening portion 63A is set, the operation of exposing the part 73 of sweep trace 11 is so the static countermeasure is easy.In addition, with regard to the formation of source electrode, drain electrode wiring 12,21,, then also can be simplified to and be implemented anodised Ta individual layer if the restriction of resistance value is loose.Active formula substrate 2 that order is made in this way and colored filter are fitted, liquid crystal panelization, and finish eighth embodiment of the invention.Formation about storage capacitors 15, shown in Figure 15 (g), exemplified partial pixel electrode 21 and counter electrode 16, clipped the gate insulator 30B and the first noncrystalline silicon layer 31B and the second noncrystalline silicon layer and overlapping areas 50 (bottom right oblique line part), constitute storage capacitors 15 example.
In the ninth embodiment of the present invention, rationalize the operation that is connected to form of gate insulator, when the opening portion to passivation insulation forms, carry out it and handle, can obtain further to reduce the IPS type liquid crystal indicator of worker ordinal number.
The 9th embodiment
Among the 9th embodiment, be shown in Figure 17 (d) and Figure 18 (d), on glass substrate 2, optionally form: by 34A and 35A lamination constituted as the drain electrode 21 of the insulated gate electrode transistor npn npn of pixel electrode and the signal wire 12 of double as source wiring, forming simultaneously till the electrode terminal 6 that is made of segment signal line, is to carry out with roughly identical with the 6th embodiment technology.Its difference is the pattern form that is capacitor storage beam 16, among the 9th embodiment, and capacitor storage beam 16 double as counter electrodes.
Then, shown in Figure 17 (e) and Figure 18 (e), with thicker than 0.5 μ m, the thickness that is preferably about 1.5 μ m is coated with photonasty polyacrylic resin 39 as the transparency and the excellent transparent resin of thermotolerance, by using the selectivity ultraviolet ray irradiation of mask plate, zone beyond image displaying part is forming opening portion 62,63,64,65 respectively on the part 5 of sweep trace and on the part 6 of signal wire and on the part 75 of capacitor storage beam 16.And after bake and bank up with earth after, with photonasty polyacrylic resin 39 as mask, gate insulator 30A, 30B in the selective removal opening portion 63,65, and expose the part 5 of sweep trace and capacitor storage beam 16 a part 75 and respectively as the electrode terminal 5 of sweep trace and the electrode terminal of capacitor storage beam.Then, in the 9th embodiment, learn that the SiNx layer that also can use as inorganic material replaces photonasty polyacrylic resin 39 as transparent insulating layer, uses the opening portion of photoresist to form operation.
Formation about storage capacitors 15, be shown in Figure 17 (e), a part and the counter electrode 16 of pixel electrode 22 have been exemplified, sandwich gate insulator 30B, the first amorphous silicon layer 31A, second amorphous silicon layer and overlapping areas 50 (bottom right oblique line part), constitute the example of storage capacitors 15, the sweep trace 11 of pixel electrode 21 and leading portion, sandwich gate insulator 30A constitutes storage capacitors 15 and also is fine.
The tenth embodiment
In the 9th embodiment, use the transparency high photonasty polyacrylic resin or SiNx layer in passivation insulation, yet when using the anodised passivation formation technology by the source electrode, drain electrode wiring and the passage that are adopted at the new rationalization technology that is connected to form operation and the 5th, the 7th embodiment, use the twice mask plate can obtain IPS type liquid crystal indicator, so this part is in the tenth embodiment explanation.
Among first embodiment, earlier on an interarea of glass substrate 2, use SPT equal vacuum film forming apparatus, cover about thickness 0.1 to 0.3 μ m can anodised the first metal layer.Secondly; on whole of glass substrate 2; use the PCVD device; respectively with for example 0.3 μ m; 0.05 μ m; 0.1 the thickness about μ m; cover in regular turn: as a SiNx layer 30 of gate insulator; first amorphous silicon layer 31 under the passage of impure hardly insulated gate electrode transistor npn npn; and three kinds of thin layers such as the 2nd SiNx layer 32 that become insulation course that are used for protecting passage; and shown in Figure 19 (a) and Figure 20 (a); utilize the halftone exposure technology; forming the zone at semiconductor layer is regional 84A1 on the gate electrode 11A; with the regional 84A2 on the zone near sweep trace 11 and signal wire 12 intersections; with the regional 84A3 on the zone near counter electrode 16 and signal wire 12 intersections; form on the regional 84A4 on the part that the zone is a counter electrode 16 with storage capacitors; thickness on the regional 84A5 on the nearby zone that intersects with pixel electrode 21 and counter electrode 16 for example is 2 μ m; ratio is corresponding to the sweep trace 11 of double as gate electrode 11A and thicker photoresist pattern 84A1 to 84A5 and the 85B of thickness 1 μ m of the photoresist pattern 84B of counter electrode 16; with photoresist pattern 81A to 84A5 and 81B as mask; add the 2nd SiNx layer 32; first amorphous silicon layer 31 and gate insulator 30 and optionally remove the first metal layer expose glass substrate 2.
After making multilayer film pattern in this way corresponding to the sweep trace 11 of double as gate electrode 11A and counter electrode 16, then utilize ashing means such as oxygen plasma, when making above-mentioned photoresist pattern 84A1 to 84A5 and 84B reduction thickness 1 μ m above, photoresist pattern 84B disappears, shown in Figure 19 (b) and Figure 20 (b), on sweep trace 11, expose the 2nd SiNx layer 32A, and on counter electrode 16, expose the 2nd SiNx layer 32B, simultaneously only on gate electrode 11A, on the near zone that intersects with sweep trace 11 and signal wire 12, on the near zone that intersects with counter electrode 16 and signal wire 12, form on the zone with storage capacitors, on the near zone that intersects with pixel electrode 21 and counter electrode 16, optionally form photoresist pattern 84C1 to 84C5.Above-mentioned oxygen plasma treatment is strengthened anisotropy to suppress the variation of pattern dimension, as mentioned above preferably not reduce the mode that follow-up source electrode, drain electrode wiring form the mask plate alignment precision of operation.
Different with other embodiment, the tenth embodiment must expose sweep trace 11 when etch stop layer forms, insulation course 76 carries out oxygen plasma treatment after forming, therefore along with the reduction thickness of insulation course 76, it is complicated that the mode that solves becomes, so suggestion is adopted anodic oxide coating at insulation course 76.Therefore,, use connection means such as crocodile clip, give sweep trace 11 and counter electrode 16 (figure does not show)+(just) current potential at connection pattern 78 shown in Figure 22.
After sweep trace 11 sides form insulation course 76, shown in Figure 19 (c) and Figure 20 (c), with photoresist pattern 84C1 to 84C5 as mask, on gate electrode 11A, on zone near sweep trace 11 and signal wire 12 intersections, optionally residual the 2nd SiNx layer 32A, the lamination of the first amorphous silicon layer 31A and gate insulator 30A, and on the nearby zone of counter electrode 16 and signal wire 12 intersections, form on the zone with storage capacitors, on zone near pixel electrode 21 and counter electrode 16 intersections, optionally residual the 2nd SiNx layer 32B, the lamination of the first amorphous silicon layer 31B and gate insulator 30B, the 2nd SiNx layer 32A on the sweep trace of etching simultaneously 11, the first amorphous silicon layer 31A and gate insulator 30A, with the 2nd SiNx layer 32B on the counter electrode 16, the first amorphous silicon layer 31B and gate insulator 30B expose sweep trace 11 and counter electrode 16 respectively.
And carry out oxygen plasma treatment, make the thickness of above-mentioned photoresist pattern 84C1 to 84C5, when isotropically reducing about 0.5 μ m as photoresist pattern 84D1 to 84D5, around 84D1 to 84D5, the 2nd SiNx layer 32A, 32B expose about width 0.5 μ m.This; shown in Figure 19 (d) and Figure 20 (d); as mask, optionally remove the 2nd SiNx layer 32A on the gate electrode 11A with photoresist pattern 84D1 to 84D5 as protection insulation course (the 2nd SiNx layer) 32D, part expose the first amorphous silicon layer 31A.
Then, after removing above-mentioned photoresist pattern 84D1 to 84D5, use the PCVD device, on whole of glass substrate 2, cover second amorphous silicon layer 33 of impure for example phosphorus with for example thickness about 0.05 μ m, in the formation operation of source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, cover in regular turn: the thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is as can anodised heat resistant metal layer, and the Al thin layer about thickness 0.3 μ m 35 is same as can anodised low resistance wiring layer.Then, by little Fine process technology, usability photosensitiveness resin pattern 87, etching in regular turn: by the source electrode that this double-layer films constituted, the drain electrode wiring material, second amorphous silicon layer 33 and the first amorphous silicon layer 31A, 31B, expose gate insulator 30A, 30B, shown in Figure 19 (e) and Figure 20 (e), optionally form by 34A and 35A lamination constituted as the drain electrode 21 of the insulated gate electrode transistor npn npn of pixel electrode and the signal wire 12 of double as source wiring, at source electrode, drain electrode wiring 12,21 form on the part of scanning line that De Tong Time are exposed, and also form the electrode terminal 6 that electrode terminal 5 and segment signal line by sweep trace are constituted.At this moment, use the halftone exposure technology, formation than the thickness (black region) of the 87A on the electrode terminal 5,6 for example be 3 μ m, than corresponding to the thicker photoresist pattern 87A of the thickness 1.5 μ m of the regional 87B (middle tone zone) of source electrode, drain electrode wiring 12,21, the situation of 87B, also be the key character of the tenth embodiment.
After source electrode, drain electrode wiring 12,21 form, utilize ashing means such as oxygen plasma, when making above-mentioned photoresist pattern 87A, 87B reduction thickness 1.5 μ m above, photoresist pattern 87B disappears, expose source electrode, drain electrode wiring 12,21, while only on electrode terminal 5,6, optionally forms photoresist pattern 87C.At this, with photoresist pattern 87C as mask plate, irradiates light, simultaneously shown in Figure 19 (f) and Figure 20 (f), with source electrode, drain electrode wiring 12,21 as anodic oxidation, form oxide layer 68,69, the second amorphous silicon layer 33A that source electrode, drain electrode wiring 12,21 downsides are exposed carries out anodic oxidation simultaneously, forms the silicon oxide layer (SiO as insulation course
2) 66.Ci Time, sweep trace 11 that is exposed and counter electrode 16 be anodic oxidation simultaneously also, forms oxide layer 71 on its surface.Also shown in the 22nd figure, on active formula substrate 2, form the wiring 77 of binding sweep trace 11 side by side and be connected pattern 78, so source electrode, 12,21 anodised whiles of drain electrode wiring, the anodic oxidation of sweep trace 11 also is easy to enforcement.Then, also carry out anodic oxidation at sweep trace 11 with above the counter electrode 16, form the event of insulation course, forming at sweep trace 11 can anodised metal, the situation that can select laminations such as individual layer formation such as Ta individual layer, Al (Zr, Ta) alloy or Al/Ta, Ta/Al/Ta, Al/Al (Ta, Zr) alloy to constitute, as previously discussed.
After anodic oxidation finishes, when removing photoresist pattern 87C, shown in Figure 19 (g) and Figure 20 (g), have anodic oxide coating, and expose the electrode terminal 5,6 that is constituted by low resistance metal layer 35A in its side.And with regard to the formation of source electrode, drain electrode wiring 12,21, the restriction of resistance value is pine, and also can simplify formation can anodised Ta individual layer.
The invention effect
As mentioned above; liquid crystal indicator of the present invention; the insulated gate electrode transistor npn npn has the protection insulation course on passage; so only on the source electrode in image displaying part, the drain electrode wiring; or only optionally form the photonasty organic insulator on the signal wire, or will by can anodised source electrode, drain electrode wiring the material source electrode, the drain electrode wiring that are constituted carry out anodic oxidation, and forms insulation course on its surface; in this way, can give active formula substrate deactivation function.Similarly, in other parts of liquid crystal indicator of the present invention, be on passage, to form silicon oxide layer by anodic oxidation, so can anodised source electrode, drain electrode wiring the material source electrode, drain electrode wiring and the passage that are constituted carry out anodic oxidation simultaneously, and at its surface formation insulation course, in this way, can give active formula substrate deactivation function.Therefore, do not need to possess special heating process,, do not need excessive thermotolerance with the insulated gate transistor of amorphous silicon layer as semiconductor layer.In other words, form, also have the additional effect that the electrical performance deterioration can not take place by passivation.In addition, when anodic oxidation is carried out in source drain wiring,, optionally protect on the electrode terminal of sweep trace or signal wire, and can obtain the effect that can stop the lithography process number to increase by introducing the halftone exposure technology.
Aim of the present invention is, can be by introducing the halftone exposure technology, handle the formation operation of sweep trace and the formation operation of etch stop layer with one mask plate, reach the minimizing of operation, when the sweep trace side of exposing was formed with machine insulation course or anodic oxide coating, the gate insulator on sweep trace was also filled up the pin hole that exists with organic insulator or anodic oxide coating simultaneously, reduce the layer short circuit between sweep trace and the signal wire, additional effect is big.
Add, by introducing the analog pixel electrode, the rationalization that pixel electrode is formed etc. with mask plate with sweep trace, can make of 5 the further minimizings of lithography process number from routine, and use 4 roads or 3 road mask plates to make liquid crystal indicator, from the viewpoint that the cost of liquid crystal indicator reduces, the value of industry is very big.And the pattern precision of these operations is not a height so, thus can not cause very big influence to yield rate or quality, so production management is also implemented than being easier to.
And, in the IPS type liquid crystal indicator of the 6th embodiment, the electric field that is produced between counter electrode and pixel electrode, only be applied to liquid crystal layer, in the IPS type liquid crystal indicator of the 7th embodiment, can be applied to gate insulator and liquid crystal layer on the counter electrode equally, in addition in the IPS type liquid crystal indicator of the 8th embodiment, can be applied to the gate insulator on the counter electrode equally, the anodic oxide coating of liquid crystal layer and pixel electrode, and in the IPS type liquid crystal indicator of the tenth embodiment, can be applied to the anodic oxide coating on the counter electrode equally, anodic oxide coating on liquid crystal layer and the pixel electrode, therefore wherein any one can not have the passivation insulation inferior of conventional many defectives, has the advantage of burning ghost phenomena that is difficult to produce display image.This is because the anodic oxide coating of drain electrode wiring (pixel electrode) is compared with insulation course, can bring into play the function of resistive formation, so can not produce electric charge accumulation.And, in the IPS type liquid crystal indicator of the 9th embodiment, if adopt the words of transparent resin layer as Dunization Jue Vela layer, the electric field that is produced between counter electrode and the pixel electrode, can be applied to gate insulator, liquid crystal layer and transparent resin layer, therefore can not have the passivation insulation inferior of conventional many defectives, though yet the possibility of burning ghost phenomena that produces display image because of the curing condition of transparent resin layer is arranged, but having an even surface of active formula substrate, therefore do not handle because of the orientation condition just can form the high orientation of homogeneity, acquisition does not have the image of the hard contrast ratio of non-orientation.
And, main points of the present invention can be understood by above-mentioned explanation, in etch-stop type insulated gate electrode transistor npn npn, can be by introducing the halftone exposure technology, handle the formation operation of sweep trace and the formation operation of etch stop layer with one mask plate, while is in the side of sweep trace that is exposed and counter electrode, form the point of organic insulator or anodic oxide coating, about formation in addition, pixel electrode, the different semiconductor devices that are used for display device such as materials such as gate insulator or thickness, perhaps the difference of its manufacture method all belongs to category of the present invention, and know and use in the reflection-type liquid-crystal display device, practicality of the present invention is also constant, and the semiconductor layer of insulated gate electrode transistor npn npn also is not limited to amorphous silicon.
The figure number explanation
1: liquid crystal panel
2: active formula substrate (glass substrate)
3: semiconductor integrated circuit chip
The 4:TCP film
5: the electrode terminal of scan line, the part of scan line
6: the electrode terminal of holding wire, the part of holding wire
9: colored filter (relative glass substrate)
10: the insulated gate electrode transistor npn npn
11: scan line (gate electrode)
11A: grid wiring, gate electrode
12: holding wire (source wiring, source electrode)
16: capacitor storage beam (IPS type counter electrode)
17: liquid crystal
18: Polarizer
20: alignment film
21: drain electrode (IPS type pixel electrode)
The 22:(transparent conductivity) pixel electrode
30,30A, 30B, 30C: gate insulator (a SiNx layer)
31,31A, 31B, 31C:(are free from foreign meter) first amorphous silicon layer
32,32A, 32B, 32C: the 2nd SiNx layer
32D: path protection insulating barrier (etch stop layer, protection insulating barrier)
33,33A, 33B, 33C:(are impure) second amorphous silicon layer
But 34,34A:(anodic oxidation) heat resistant metal layer
But 35,35A:(anodic oxidation) low resistance metal layer (Al)
But 36,36A:(anodic oxidation) intermediate conductive layer
37: passivation insulation
The pixel electrode of 41:IPS type liquid crystal indicator
The counter electrode of 42:IPS type liquid crystal indicator
50,51,52: storage capacitors forms the zone
On the 62:(drain electrode) opening portion
63, on the 63A:(sweep trace) opening portion
64, on the 64A:(signal wire) opening portion
65, on the 65A:(counter electrode) opening portion
66: impure silicon oxide layer
68: anodic oxide coating (titanium dioxide, TiO
2)
69: anodic oxide coating (aluminium oxide, Al
2O
3)
70: anodic oxide coating (tantalum pentoxide, Ta
2O
5)
The 71:(counter electrode) anodic oxide coating
72: storage electrode
73: the part of sweep trace
74: the part of signal wire
76: the insulation course that is formed on the sweep trace side
80A, 80B, 81A, 81B, 82A, 82B, 84A, 84B, 87A, 87B:(form with halftone exposure) the photoresist pattern
83A:(is general for pixel electrode formation) the photoresist pattern
85: the photonasty organic insulator
86A, 86B:(form with halftone exposure) the photonasty organic insulator
91: transparency conducting layer
92: the first metal layer
Claims (13)
1, a kind of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes is characterized by between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter:
At least on an interarea of the first transparent insulated substrate, forms and constituted, and its side has the sweep trace of insulation course by the first metal layer more than one deck,
Gate insulator more than formation one deck on the gate electrode and first semiconductor layer free from foreign meter,
On above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode,
On the part of above-mentioned protection insulation course, on first semiconductor layer and on the first transparent insulated substrate, form source wiring that lamination constituted and drain electrode wiring by second impure semiconductor layer and second metal level more than one deck,
On the first transparent insulated substrate, be formed on the above-mentioned drain electrode wiring and the electrode terminal of sweep trace and signal wire forms the transparent resin layer that has opening portion on the zone,
The electrode terminal of removing above-mentioned sweep trace forms the gate insulator on the zone,
Comprise above-mentioned opening portion electric conductivity pixel electrode and be included on the sweep trace counter electrode with electric conductivity on signal wire, be formed on the above-mentioned transparent resin layer.
2, a kind of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes is characterized by between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter:
At least on an interarea of the first transparent insulated substrate, forms and constituted, and its side has the sweep trace and the counter electrode of insulation course by the first metal layer more than one deck,
Be formed with the gate insulator more than one deck on the counter electrode and be formed with gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode,
On above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode,
Zone beyond image displaying part, the gate insulator on sweep trace forms opening portion,
On the part of above-mentioned protection insulation course; on first semiconductor layer and on the first transparent insulated substrate; be formed with source wiring that lamination constituted and drain electrode wiring by second impure semiconductor layer and second metal level more than one deck; the electrode terminal of the sweep trace that is constituted with first semiconductor layer that comprises above-mentioned opening portion periphery and second semiconductor layer and by second metal level; with the electrode terminal by the signal wire that segment signal line constituted in image displaying part zone in addition
On the electrode terminal of above-mentioned signal wire, on signal wire, form the photonasty organic insulator.
3, a kind of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes is characterized by between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter:
At least on an interarea of the first transparent insulated substrate, forms and constituted, and its side has the sweep trace and the counter electrode of insulation course by the first metal layer more than one deck,
At the gate insulator that forms on the counter electrode more than one deck; With forming gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode,
On above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode,
Zone beyond image displaying part, the gate insulator on sweep trace forms opening portion,
On the part of above-mentioned protection insulation course, on first semiconductor layer and on the first transparent insulated substrate, form: by the second impure semiconductor layer and more than one deck can anodised metal level source wiring that lamination constituted and drain electrode wiring; With first semiconductor layer that comprises above-mentioned opening portion periphery and second semiconductor layer and by electrode terminal that can the sweep trace that anodised metal level constituted; With the electrode terminal that forms in image displaying part zone in addition by the signal wire that a part constituted of signal wire,
On the electrode terminal of above-mentioned signal wire, form anodic oxide coating on the surface of source wiring and drain electrode wiring.
4, a kind of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the liquid crystal indicator that constitutes is characterized by between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter:
At least on an interarea of the first transparent insulated substrate, forms and constituted, and its side has the sweep trace and the counter electrode of insulation course by the first metal layer more than one deck,
At the gate insulator that forms on the counter electrode more than one deck; With forming gate insulator more than one deck and first semiconductor layer free from foreign meter on the gate electrode,
On above-mentioned first semiconductor layer, form the width protection insulation course also thinner than gate electrode,
On the part of above-mentioned protection insulation course, on first semiconductor layer and on the first transparent insulated substrate, form source wiring that lamination constituted and drain electrode wiring by second impure semiconductor layer and second metal level more than one deck,
Zone beyond the image displaying part, the electrode terminal that forms on the first transparent insulated substrate at sweep trace form on the zone with electrode terminal by the signal wire that segment signal line constituted on have the transparent insulating layer of opening portion,
In above-mentioned opening portion, expose as the part of scanning line of the electrode terminal of sweep trace and the electrode terminal of signal wire.
5, as each described liquid crystal indicator among the claim 1-4, wherein, the insulation course that is formed on the side of sweep trace is an organic insulator.
6, as each described liquid crystal indicator among the claim 1-4, wherein, the first metal layer is by can being constituted by anodised metal level, and the insulation course that is formed on the side of sweep trace is an anodic oxide coating.
7, a kind of manufacture method of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter, it is characterized by and have:
At least on an interarea of the first transparent insulated substrate, be capped in regular turn: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above;
Corresponding to sweep trace, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone;
With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer;
Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course;
On gate electrode, stay width exposes first amorphous silicon layer than the also thin protection insulation course of gate electrode operation;
After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace;
Be capped the operation of the second impure amorphous silicon layer comprehensively;
With part and the overlapping mode of above-mentioned protection insulation course, form by second amorphous silicon layer and the source wiring that lamination constituted of second metal level more than one deck and the operation of drain electrode wiring;
With will form on the zone at the electrode terminal of the sweep trace in the zone on the drain electrode wiring, beyond the image displaying part and on the electrode terminal by the signal wire that segment signal line constituted, the transparent resin layer that has opening portion respectively is formed on the operation on the above-mentioned first transparent insulated substrate;
The electrode terminal of removing above-mentioned sweep trace forms gate insulator on the zone and the operation of exposed portions serve sweep trace; And
To comprise the opening portion on the above-mentioned drain electrode wiring electric conductivity pixel electrode and be included on the sweep trace counter electrode with electric conductivity on signal wire, be formed on the operation on the above-mentioned transparent resin layer.
8, a kind of manufacture method of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in aforementioned dielectric grid type transistor drain pixel electrode, and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter, it is characterized by and have:
At least on an interarea of the first transparent insulated substrate, be capped in regular turn: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above;
Corresponding to sweep trace and counter electrode, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone;
With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer;
Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course;
On gate electrode, stay the width protection insulation course also thinner, and expose the operation of first amorphous silicon layer than gate electrode;
After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace and counter electrode;
Be capped the operation of the second impure amorphous silicon layer comprehensively;
Zone beyond the image displaying part forms the zone at the electrode terminal of sweep trace and forms opening portion, second amorphous silicon layer, first amorphous silicon layer and gate insulator in the above-mentioned opening portion of selective removal, and the operation of exposed portions serve sweep trace;
After being capped the second above metal level of one deck, formation corresponding to part and above-mentioned protection insulation course overlapping source wiring and drain electrode wiring, comprise electrode terminal, the zone beyond image displaying part that above-mentioned opening portion forms sweep trace and form electrode terminal by the signal wire that segment signal line constituted, form the operation of the also thick photonasty organic insulation layer pattern in other zone of Film Thickness Ratio on the signal wire;
With above-mentioned photonasty organic insulation layer pattern as mask, selective removal second metal level, second amorphous silicon layer and first amorphous silicon layer, and form sweep trace and the electrode terminal of signal wire and the operation of source wiring and drain electrode wiring; And
Reduce the thickness of above-mentioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
9, a kind of manufacture method of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter, it is characterized by and have:
At least on an interarea of the first transparent insulated substrate, be capped in regular turn: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above;
Corresponding to sweep trace and counter electrode, and form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone;
With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer;
Reduce the thickness of the photoresist pattern that has reduced above-mentioned thickness, and expose the operation of protecting insulation course;
On gate electrode, stay the width protection insulation course also thinner, and expose the operation of first amorphous silicon layer than gate electrode;
After above-mentioned photoresist pattern is removed, form the operation of insulation course in the side of sweep trace and counter electrode;
Be capped the operation of the second impure amorphous silicon layer comprehensively;
Zone beyond the image displaying part forms the zone at the electrode terminal of sweep trace and forms opening portion, second amorphous silicon layer, first amorphous silicon layer and gate insulator in the selective removal opening portion, and the operation of exposed portions serve sweep trace;
Be capped one deck above can anodised metal level after, form counterpart and above-mentioned protection insulation course overlapping source wiring and drain electrode wiring, comprise above-mentioned opening portion form the electrode terminal of sweep trace, in image displaying part zone exceptionally corresponding to electrode terminal by the signal wire that segment signal line constituted, form the operation of other the regional also thick photoresist pattern of Film Thickness Ratio on the electrode terminal of sweep trace and signal wire;
As mask, selective removal can anodised metal level, second amorphous silicon layer and first amorphous silicon layer, and forms sweep trace and the electrode terminal of signal wire and the operation of source wiring and drain electrode wiring with above-mentioned photoresist pattern;
Reduce the thickness of above-mentioned photoresist pattern, and expose the operation of source wiring and drain electrode wiring; And
Protect above-mentioned electrode terminal, simultaneously the operation of anodic oxidation source wiring and drain electrode wiring.
10, a kind of manufacture method of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in the pixel electrode of aforementioned dielectric grid type transistor drain and become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter, it is characterized by and have:
At least on an interarea of the first transparent insulated substrate, be capped in regular turn: gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course that the first metal layer that one deck is above and one deck are above;
Corresponding to sweep trace and counter electrode, form the operation that the protection insulation course forms the also thick photoresist pattern in other zone of Film Thickness Ratio on the zone;
With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer;
Reduce the thickness of above-mentioned photoresist pattern and expose the operation of protecting insulation course;
On gate electrode, stay the also thin protection insulation course of width gate electrode, and expose the operation of first amorphous silicon layer;
After the above-mentioned photoresist pattern of minimizing thickness is removed, form the operation of insulation course in the side of sweep trace and counter electrode;
Be capped the operation of the second impure amorphous silicon layer comprehensively;
With part and the overlapping mode of above-mentioned protection insulation course, form by second amorphous silicon layer and the source wiring that lamination constituted of second metal level more than one deck and the operation of drain electrode wiring;
Zone beyond image displaying part forms the operation that has the transparent insulating layer of opening portion on the electrode terminal that reaches on the zone by the signal wire that segment signal line constituted at the electrode terminal that is formed on sweep trace on the first transparent insulated substrate; And
Removal forms gate insulator on the zone at the electrode terminal of above-mentioned sweep trace, and the operation of exposed portions serve sweep trace.
11, a kind of manufacture method of liquid crystal indicator, on an interarea, have at least sweep trace, the double as source wiring of insulated gate electrode transistor npn npn, the transistorized gate electrode of double as aforementioned dielectric grid type signal wire, be connected in aforementioned dielectric grid type transistor drain pixel electrode, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment across the unit picture element of the formed counter electrode of specific range with aforementioned pixel electrode; And filling liquid crystal and the manufacture method of the liquid crystal indicator that constitutes between the second transparent insulated substrate relative with the aforementioned first transparent insulated substrate or between this first transparent insulated substrate and the colored filter, it is characterized by and have:
At least on an interarea of the first transparent insulated substrate, be capped in regular turn: above gate insulator, first amorphous silicon layer free from foreign meter and the operation of protecting insulation course of the first metal layer, one deck that one deck is above;
Corresponding to sweep trace and counter electrode, the operation of the photoresist pattern that be formed on the gate electrode, on the intersection region of sweep trace and signal wire, on the intersection region of counter electrode and signal wire and other zone of Film Thickness Ratio on the intersection region of counter electrode and pixel electrode is also thick;
With above-mentioned photoresist pattern as mask, etching in regular turn: the operation of protection insulation course, first amorphous silicon layer, gate insulator and the first metal layer;
Form the operation of insulation course in the side of sweep trace and counter electrode;
Reduce the thickness of above-mentioned photoresist pattern and expose the protection insulation course, remove on the sweep trace with counter electrode on protection insulation course, first amorphous silicon layer, gate insulator, and expose the operation of sweep trace and counter electrode;
Further minimizing has reduced the thickness of the above-mentioned photoresist pattern of thickness, stays the width protection insulation course also thinner than gate electrode on gate electrode, and exposes the operation of first amorphous silicon layer;
Be capped the operation of the second impure amorphous silicon layer comprehensively;
Be capped one deck above can anodised metal level after, form overlapping source wiring of part and above-mentioned protection insulation course and drain electrode wiring, the zone beyond image displaying part comprise part of scanning line form the electrode terminal of sweep trace, corresponding to electrode terminal by the signal wire that segment signal line constituted, form the operation of the also thick photoresist pattern in other zone of Film Thickness Ratio on the above-mentioned electrode terminal;
As mask, selective removal can anodised metal level, second amorphous silicon layer and first amorphous silicon layer, and forms sweep trace and the electrode terminal of signal wire and the operation of source wiring and drain electrode wiring with above-mentioned photoresist pattern;
Reduce the thickness of above-mentioned photoresist pattern and expose the operation of source wiring and drain electrode wiring; And
Protect above-mentioned electrode terminal, simultaneously the operation of anodic oxidation source wiring and drain electrode wiring and counter electrode.
12, as the manufacture method of each described liquid crystal indicator among the claim 7-11, wherein, the insulation course that is formed on the side of sweep trace is an organic insulator, is to utilize to electroplate to form.
13, as the manufacture method of each described liquid crystal indicator among the claim 7-11, wherein, the first metal layer is by can being constituted by anodised metal level, and the insulation course that is formed on the side of sweep trace is to utilize anodic oxidation to form.
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