WO2022142430A1 - Procédé de préparation d'un détecteur à panneau plat - Google Patents

Procédé de préparation d'un détecteur à panneau plat Download PDF

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WO2022142430A1
WO2022142430A1 PCT/CN2021/115934 CN2021115934W WO2022142430A1 WO 2022142430 A1 WO2022142430 A1 WO 2022142430A1 CN 2021115934 W CN2021115934 W CN 2021115934W WO 2022142430 A1 WO2022142430 A1 WO 2022142430A1
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layer
flat panel
panel detector
electrode
thickness
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PCT/CN2021/115934
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Chinese (zh)
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解海艇
金利波
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上海奕瑞光电子科技股份有限公司
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Publication of WO2022142430A1 publication Critical patent/WO2022142430A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H01L27/14663—Indirect radiation imagers, e.g. using luminescent members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention belongs to the field of flat panel detectors, and relates to a preparation method of a flat panel detector.
  • Digital Radio Graphy is a new technology of X-ray photography developed in the 1990s. It has become the leading direction of digital X-ray photography technology, and has been recognized by clinical institutions and imaging experts all over the world. Its application in medical imaging diagnostic imaging, industrial flaw detection, security inspection and other fields is becoming more and more extensive. In the application of X-ray radiation imaging, the area of the flat panel detector is generally required to reach 43cm ⁇ 43cm. The design of the X-ray detector TFT panel has its function implementation played a big role.
  • a flat panel detector is a detector that uses semiconductor technology to convert X-ray energy into electrical signals to generate X-ray images.
  • the flat panel detector is composed of millions or even tens of millions of pixel unit circuits, which are generally composed of thin film transistors (TFTs) and photodiodes (PDs).
  • TFTs thin film transistors
  • PDs photodiodes
  • the traditional flat panel detector is mainly an amorphous silicon flat panel detector, and its pixel unit circuit is composed of a-Si TFT and a-Si PD.
  • amorphous oxide (AOS) TFT has higher field-effect mobility (about a-Si TFT).
  • the advantages of Si TFT mobility are more than 10 times) and lower off-state current (fA level), which can be applied to the preparation of dynamic flat panel detectors with the advantages of high frame rate and low noise.
  • the purpose of the present invention is to provide a method for preparing a flat panel detector, which is used to solve the problem that the a-Si PD array film-forming process has an adverse effect on AOS TFTs when preparing a flat panel detector in the prior art.
  • the present invention provides a preparation method of a flat panel detector, comprising the following steps:
  • amorphous oxide film forming an amorphous oxide film, and patterning the amorphous oxide film to form a first amorphous oxide channel layer and a second amorphous oxide channel layer in contact with the source electrode and the drain electrode;
  • the gate insulating layer covering the first amorphous oxide channel layer and the second amorphous oxide channel layer, and exposing part of the source electrode;
  • first protective layer covering the first TFT, the second TFT, the photodiode and the transparent top electrode
  • the metal layer forming a metal layer, patterning the metal layer, forming a common electrode and a light shielding layer, the light shielding layer is located above the first TFT and the second TFT, and the common electrode fills the common electrode through hole;
  • a scintillator layer is formed, and the scintillator layer covers the second protective layer.
  • the buffer layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer;
  • the thickness range is
  • the insulating isolation layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer; the insulating isolation layer The thickness of the layer ranges from
  • the source electrode includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; the thickness of the source electrode ranges from The drain electrode includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, a Ti layer and a Nb layer; the thickness of the drain electrode is in the range of
  • the amorphous oxide film includes one or a combination of a-IGZO layer, a-IZO layer, a-IGO layer, In 2 O 3 layer, ZnO layer, a-IZTO layer and AlZnO x layer ; the thickness range of the amorphous oxide film is
  • the gate insulating layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer; the gate insulating layer The thickness of the layer ranges from
  • the metal isolation layer includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal isolation layer is The metal layer includes one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal layer is
  • the first protective layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer;
  • the thickness of a protective layer is in the range of
  • the second protective layer includes one or a combination of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer; The thickness range is
  • the transparent top electrode includes an ITO layer; the thickness of the transparent top electrode is in the range of
  • the scintillator layer includes one or a combination of a CsI layer, a GOS layer and a perovskite layer.
  • the preparation method of the flat panel detector of the present invention has the following beneficial effects:
  • the invention adopts one-layer or stacked metal isolation layers to isolate the AOS TFT, which can avoid damage to the amorphous oxide channel layer in the AOS TFT in the subsequent process of preparing the photodiode film, and avoid the amorphous oxide.
  • the performance of the channel layer is degraded, thereby improving the quality and performance of the flat panel detector;
  • the buffer layer can reduce the entry of impurity ions in the substrate into the device, and can reduce the influence of the stress of the film or substrate on the device;
  • the metal isolation layer After one patterning, the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be formed at the same time, and directly using the remaining metal isolation layer as the bottom electrode of the PD is beneficial to reduce the Lag value of the flat panel detector, and the formed
  • the dual AOS TFTs with vertical structure are insensitive to the film stress in the flat panel detector, which improves the dynamic reading frame rate of the flat panel detector.
  • FIG. 1 is a schematic diagram of a manufacturing process flow diagram of a flat panel detector in an embodiment of the present invention.
  • FIG. 2 to FIG. 14 are schematic structural diagrams of each step of preparing a flat panel detector in the embodiment.
  • spatially relative terms such as “below,” “below,” “below,” “below,” “above,” “on,” etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures.
  • a layer when referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between” means including both endpoints.
  • references where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.
  • this embodiment provides a method for fabricating a flat panel detector.
  • This embodiment uses a one-layer or stacked metal isolation layer to isolate the AOS TFT, which can avoid subsequent photodiode film formation processes. , causing damage to the amorphous oxide channel layer in the AOS TFT, avoiding the performance degradation of the amorphous oxide channel layer, thereby improving the quality and performance of the flat panel detector; the buffer layer can reduce the impurity ions in the substrate entering the device.
  • the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be simultaneously formed, and the remaining metal can be directly
  • the isolation layer as the bottom electrode of the PD is beneficial to reduce the Lag value of the flat panel detector, and the dual AOS TFTs with vertical structure formed are not sensitive to the film stress in the flat panel detector, which improves the dynamic reading frame rate of the flat panel detector. .
  • a substrate 110 is provided first, and a buffer layer 120 is formed on the substrate 110 .
  • the substrate 110 may include a glass substrate or a flexible PI, PET substrate, etc., but is not limited thereto.
  • An insulating layer with one or more structures can be prepared by CVD, PVD or solution method to serve as the buffer layer 120, and the buffer layer 120 can include a SiO x layer, a SiN x layer, a SiO x N y layer, and an AlO x layer. layer, ZrO x layer, TiO x layer and organic insulating layer, one or a combination; the thickness range of the buffer layer 120 may be like and Wait.
  • the buffer layer 120 does not need to be patterned, which can reduce the entry of impurity ions in the substrate 110 into the device, and can reduce the influence of the stress of the film or the substrate on the device.
  • the specific material, structure, thickness, and formation method of the buffer layer 120 can be selected according to requirements, which are not excessively limited here.
  • a source electrode 130 is formed on the buffer layer 120 .
  • one or more layers of metal thin films can be deposited by PVD, and then the metal thin films can be patterned by dry or wet etching to form the source electrode 130.
  • the source electrode 130 can include Mo layer, Al layer, AlNb layer, Cr layer, Cu layer, Ti layer and Nb layer or combination; the thickness range of the source electrode 130 may be like and Wait.
  • the specific material, structure, thickness, and forming method of the source electrode 130 can be selected according to requirements, which are not excessively limited here.
  • a patterned insulating isolation layer 140 is formed on the source electrode 130 , and a patterned drain electrode 150 is formed on the insulating isolation layer 140 to expose part of the source electrode 130 .
  • the insulating isolation layer 140 may be prepared by CVD, PVD or solution method, and the insulating isolation layer 140 may include a SiOx layer, a SiNx layer, a SiOxNy layer, an AlOx layer, a ZrO layer One or a combination of x layer, TiO x layer and organic insulating layer; the thickness of the insulating isolation layer 140 can be like and Wait.
  • the specific material, structure, thickness, and forming method of the insulating isolation layer 140 can be selected according to requirements, which are not excessively limited here.
  • one or more metal thin films can be deposited by PVD method to serve as the drain electrode 150 of the subsequent TFT.
  • the drain electrode 150 can include a Mo layer, an Al layer, an AlNb layer, a Cr layer, a Cu layer, and a Ti layer. and one or a combination of Nb layers; the thickness range of the drain electrode 150 may be like and Wait.
  • the specific material, structure, thickness, and forming method of the drain electrode 150 can be selected according to requirements, which are not excessively limited here.
  • dry or wet etching is used to first obtain the patterned drain electrode 150 , and then obtain the patterned insulating isolation layer 140 to expose part of the source electrode 130 and facilitate subsequent electrical connect.
  • an amorphous oxide film is formed, and the amorphous oxide film is patterned to form a first amorphous oxide channel layer 161 and a first amorphous oxide channel layer 161 in contact with the source electrode 130 and the drain electrode 150 .
  • Two amorphous oxide channel layers 162 are amorphous oxide channel layers 162 .
  • PVD method or solution method can be used to prepare one or more layers of the amorphous oxide film, and wet etching or dry etching method is used to pattern the amorphous oxide film to form the first An amorphous oxide channel layer 161 and a second amorphous oxide channel layer 162, wherein the amorphous oxide film may include a-IGZO layer, a-IZO layer, a-IGO layer, In 2 O One or a combination of 3 layers, ZnO layer, a-IZTO layer and AlZnO x layer; the thickness range of the amorphous oxide film can be like and and so on; it can be seen that the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 can be formed with the same material and the same thickness.
  • the specific material, structure, thickness, and formation method of the amorphous oxide thin film can be selected according to requirements, which are not excessively limited here.
  • a gate insulating layer 170 is formed, the gate insulating layer 170 covers the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 , and exposes part of the source electrode 130.
  • one or more layers of gate insulating layer films may be prepared by CVD, PVD or solution method, and then patterned by dry or wet etching to form exposed portions of the source electrode 130
  • the gate insulating layer 170 of the TFT, the gate insulating layer 170 may include one of a SiO x layer, a SiN x layer, a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer kind or combination; the thickness range of the gate insulating layer 170 is like and etc., the specific material, structure, thickness, and formation method of the gate insulating layer 170 can be selected according to requirements, which are not excessively limited here.
  • a metal isolation layer 180 is formed, the metal isolation layer 180 covers the gate insulating layer 170 and the exposed source electrode 130 , and a photodiode 190 and a transparent top are formed on the metal isolation layer 180 electrode 111 .
  • PVD method can be used to deposit one or more layers of metal films, and then, the amorphous silicon PIN photodiode layer is prepared by CVD method on it, and finally the ITO electrode layer is prepared by PVD method, so as to form the stacked said Metal isolation layer 180 , photodiode 190 and transparent top electrode 111 .
  • the metal isolation layer 180 may include one or a combination of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer; the thickness of the metal isolation layer 180 may be like and etc., the specific material, structure, thickness, and formation method of the metal isolation layer 180 can be selected according to requirements, which are not excessively limited here.
  • the transparent top electrode 111 can be an ITO layer, but not limited to, and the thickness of the transparent top electrode 111 can be like and etc., the specific material, structure, thickness, and forming method of the transparent top electrode 111 can be selected according to requirements, which are not excessively limited here.
  • the photodiode 190 and the transparent top electrode 111 are patterned to expose part of the metal isolation layer 180 .
  • dry etching or wet etching can be used to first pattern the ITO electrode layer to form the patterned transparent top electrode 111, and then pattern the amorphous silicon PIN photodiode layer.
  • the photodiode 190 is formed patterned.
  • the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 161 of the TFT can be protected.
  • the role of the crystalline oxide channel layer 162 is to prevent the first amorphous oxide channel layer 161 and the second amorphous oxide channel layer 162 from being affected by the deposition process of the photodiode 190 and avoid the TFT Deterioration of performance.
  • the metal isolation layer 180 is patterned to form a first gate electrode 181 and a second gate electrode 182 to obtain a first TFT and a second TFT, and the bottom electrode 183 of the photodiode 190 .
  • the metal isolation layer 180 can be patterned by dry or wet etching, so that the first gate electrode 181 , the second gate electrode 182 and the photodiode 190 can be simultaneously formed by one patterning.
  • the bottom electrode 183 of the photodiode 190 is directly used as the bottom electrode of the photodiode 190 to reduce the complexity of the process; and it is beneficial to reduce the Lag value of the flat panel detector; thus, the first TFT, The second TFT and PD.
  • a first protective layer 112 is formed, the first protective layer 112 covers the first TFT, the second TFT, the photodiode 190 and the transparent top electrode 111 ; and the first protective layer 112 is patterned , forming a common electrode through hole 1111 exposing the transparent top electrode 111 .
  • one or more insulating layer films may be prepared by CVD, PVD or solution method to form the first protective layer 112, and the first protective layer 112 may include a SiOx layer, a SiNx layer, a SiOx layer, and a SiOx layer.
  • the first protective layer 112 may include a SiOx layer, a SiNx layer, a SiOx layer, and a SiOx layer.
  • One or a combination of the xNy layer, the AlOx layer, the ZrOx layer, the TiOx layer and the organic insulating layer to cover the photodiode 190 as a protective layer for the photodiode 190 .
  • it is patterned by wet or dry etching to form the common electrode through hole 1111 exposing part of the transparent top electrode 111 .
  • the thickness range of the first protective layer 112 may be like and etc., the specific material, structure, thickness, and formation method of the first protective layer 112 can be selected according to requirements, which are not excessive
  • a metal layer is formed, and the metal layer is patterned to form a common electrode 1131 and a light shielding layer 1132, the light shielding layer 1132 is located above the first TFT and the second TFT, and the common electrode 1131
  • the common electrode through hole 1111 is filled.
  • PVD method can be used to prepare a metal thin film with one or several layered structures to form the metal layer, and the metal layer can include one of a Mo layer, an Al layer, an AlNb layer, a Cr layer and a Cu layer. or a combination; the thickness of the metal layer can be like
  • the metal layer can be patterned to form the common electrode 1131 and the light shielding layer 1132, wherein the common electrode 1131 and the light shielding layer 1132 have the same plane, and have the same material and thickness.
  • the material, thickness and formation method of the metal layer are not limited to this, and can be selected as required.
  • a second protective layer 114 is formed, and the second protective layer 114 covers the common electrode 1131 and the light shielding layer 1132 .
  • CVD, PVD or solution method can be used to prepare an insulating layer with a one-layer or stacked-layer structure to form the second protective layer 114, wherein the second protective layer 114 can include a SiOx layer, a SiNx layer , one or a combination of a SiO x N y layer, an AlO x layer, a ZrO x layer, a TiO x layer and an organic insulating layer.
  • the thickness of the second protective layer 114 can be like etc., the material, thickness and formation method of the second protective layer 114 are not limited to this, and can be selected as required.
  • a scintillator layer 115 is formed, and the scintillator layer 115 covers the second protective layer 114 .
  • the scintillator layer 115 may include one or a combination of a CsI layer, a GOS layer, and a perovskite layer, so as to convert X-rays into visible light through the scintillator layer 115 .
  • the material, thickness and formation method of the scintillator layer 115 are not limited to this, and can be selected as required.
  • the preparation method of the flat panel detector of the present invention adopts a single layer or a stacked metal isolation layer to isolate the AOS TFT, which can avoid the subsequent process of preparing the photodiode film formation.
  • the oxide channel layer can cause damage to avoid the performance degradation of the amorphous oxide channel layer, thereby improving the quality and performance of the flat panel detector;
  • the buffer layer can reduce the impurity ions in the substrate entering the device, and can reduce the film or lining The influence of the bottom stress on the device; after the metal isolation layer is patterned once, the two gate electrodes of the dual AOS TFT and the bottom electrode of the PD can be simultaneously formed, and the remaining metal isolation layer is directly used as the bottom electrode of the PD. It is beneficial to reduce the Lag value of the flat panel detector, and the formed double AOS TFT with vertical structure is not sensitive to the film stress in the flat panel detector, and improves the dynamic reading frame rate of the flat panel detector.

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Abstract

La présente invention concerne un procédé de préparation d'un détecteur à panneau plat. Une couche d'isolation métallique simple ou empilée est utilisée pour isoler un TFT AOS, de telle sorte que l'endommagement d'une couche de canal d'oxyde amorphe dans le TFT AOS est évité lors du processus de formation de film suivant d'une photodiode (PD), et la dégradation de performances de la couche de canal d'oxyde amorphe est évitée, et ainsi la qualité et les performances du détecteur à panneau plat sont améliorées. Des ions d'impureté dans un substrat peuvent être réduits dans un dispositif à l'aide d'une couche tampon, et l'influence de la contrainte d'un film mince ou du substrat sur le dispositif peut être réduite. Deux électrodes de grille du TFT AOS double et une électrode inférieure du PD peuvent être formées en même temps après que la couche d'isolation métallique a été structurée une fois ; la couche d'isolation métallique réservée est directement utilisée comme électrode inférieure du PD, ce qui facilite la réduction de la valeur Lag du détecteur à panneau plat, le TFT AOS double form présentant la structure verticale étant insensible à la contrainte de film mince dans le détecteur à panneau plat, et la vitesse de trame de lecture dynamique du détecteur à panneau plat étant améliorée.
PCT/CN2021/115934 2020-12-28 2021-09-01 Procédé de préparation d'un détecteur à panneau plat WO2022142430A1 (fr)

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