TW202314970A - 包含通孔的積體電路裝置及其形成方法 - Google Patents
包含通孔的積體電路裝置及其形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 179
- 239000002356 single layer Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Abstract
本發明提供包含通孔的積體電路裝置及其形成方法。方法可包含在基底上形成導電線結構。導電線結構可包含第一絕緣層及第一絕緣層中的導電線堆疊,且導電線堆疊可包含堆疊於基底上的導電線及罩幕層。方法亦可包含:藉由移除罩幕層在第一絕緣層中形成凹槽,所述凹槽暴露導電線;在第一絕緣層上及在第一絕緣層的凹槽中形成蝕刻終止層且接著形成第二絕緣層;以及形成延伸穿過第二絕緣層及蝕刻終止層且接觸導電線的導通孔。
Description
[相關申請案的交叉引用]
本申請案主張2021年9月9日在USPTO中申請的題為包含完全對準通孔的積體電路裝置(INTEGRATED CIRCUIT DEVICES INCLUDING FULLY ALIGNED VIA)的美國臨時申請案序列號63/242,193的優先權,所述申請案的揭露內容特此以全文引用的方式併入本文中。
本揭露大體上是關於電子領域,且更特定言之,是關於包含通孔的積體電路裝置。
已提議各種通孔結構以提供通孔觸點與金屬線之間的穩定電連接且降低通孔觸點與鄰近導電元件之間的非預期電連接的可能性。
根據本發明的一些實施例,形成積體電路裝置的方法可包含在基底上形成導電線結構。導電線結構可包含第一絕緣層及第一絕緣層中的導電線堆疊,且導電線堆疊可包含堆疊於基底上的導電線及罩幕層。方法亦可包含:藉由移除罩幕層在第一絕緣層中形成凹槽,所述凹槽暴露導電線;在第一絕緣層上及在第一絕緣層的凹槽中形成蝕刻終止層且接著形成第二絕緣層;以及形成延伸穿過第二絕緣層及蝕刻終止層且接觸導電線的導通孔。
根據本發明的一些實施例,形成積體電路裝置的方法可包含在基底上形成導電線堆疊。導電線堆疊可包含堆疊於基底上的導電線及罩幕層。方法亦可包含:在導電線堆疊上形成第一初步絕緣層;藉由對第一初步絕緣層執行平坦化製程直至暴露罩幕層而形成第一絕緣層;藉由移除罩幕層在第一絕緣層中形成凹槽,所述凹槽暴露導電線;在第一絕緣層上及在第一絕緣層的凹槽中形成蝕刻終止層且接著形成第二絕緣層;形成延伸穿過第二絕緣層及蝕刻終止層的開口;以及在開口中形成導通孔。開口可暴露導電線的上部表面的第一部分及第一絕緣層的最上部表面的一部分。
根據本發明的一些實施例,積體電路裝置可包含:第一絕緣層,位於基底上;第二絕緣層,位於第一絕緣層上;蝕刻終止層,位於第一絕緣層與第二絕緣層之間;以及導電線,位於第一絕緣層中。導電線的上部表面可相對於第一絕緣層的最上部表面朝向基底凹陷。積體電路裝置亦可包含延伸穿過第二絕緣層及蝕刻終止層且接觸導電線的上部表面的導通孔。導通孔可接觸導電線的上部表面的第一部分,且蝕刻終止層的一部分可位於導電線的上部表面的第二部分與第二絕緣層之間且接觸導通孔的側表面。在一些實施例中,蝕刻終止層可包含氧化鋁層及/或氮氧化鋁層。
根據本發明的一些實施例,下部導電線(例如,第一金屬線)可各自包含相對於絕緣層的存在下部導電線的上部表面凹陷的上部表面。下部導電線的凹陷上部表面可增大下部導電線與電連接至鄰近下部導電線的通孔之間的距離,且因此可降低下部導電線與通孔之間的非預期電連接的可能性。可藉由選擇性地移除下部導電線上的罩幕層而形成下部導電線的凹陷上部表面,使得可更精確地控制下部導電線的凹陷上部表面與絕緣層的上部表面之間的距離。
圖1、圖2以及圖3為根據本發明的一些實施例的形成積體電路裝置的方法的流程圖,且圖4至圖13為示出根據本發明的一些實施例的形成積體電路裝置的方法的橫截面圖。
參考圖1、圖2以及圖4至圖7,方法可包含在基底10上形成包括第一絕緣層32及導電線堆疊24的導電線結構(區塊110)。在一些實施例中,形成導電線結構可包含在基底10上形成導電線12及罩幕層14(區塊112)。在一些實施例中,罩幕層14可包含第一罩幕層14_1及第二罩幕層14_2。儘管圖4示出包含兩個堆疊層的罩幕層14,但本發明不限於此。罩幕層14可為單層或包含三個或大於三個層的多層。
基底10可包含面向導電線12的上部表面10U及與上部表面10U相對的下部表面10L。上部表面10U可平行於第一方向D1及不同於第一方向D1的第二方向D2。第一方向D1及第二方向D2可分別為第一水平方向及第二水平方向。導電線12及罩幕層14可在第三方向D3上依序堆疊於基底10上。第三方向D3可垂直於第一方向D1及第二方向D2且可為豎直方向。
基底10可包含一或多種半導體材料,例如Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC及/或InP。在一些實施例中,基底10可為塊狀基底(例如,塊狀矽基底)或絕緣體上半導體(semiconductor on insulator;SOI)基底。
導電線12可為依序堆疊於基底10上的單層或多層。導電線12可包含金屬層(例如,釕層、鉬層、銅層、鋁層及/或鎢層)及/或金屬氮化物層(例如,氮化鈦層及/或氮化鉭層)。舉例而言,導電線12可為釕層或鉬層。
罩幕層14可包含具有相對於導電線12的蝕刻選擇性的層。在一些實施例中,罩幕層14可包含有機硬質罩幕層及/或無機硬質罩幕層。舉例而言,罩幕層14可為單一氮化矽層或可為在第三方向D3上堆疊的多個層(例如,第一罩幕層14_1及第二罩幕層14_2)。
第一罩幕層14_1可改良導電線12與第二罩幕層14_2之間的黏著力,且可在圖8中所示出的後續製程期間移除第一罩幕層14_1時保護導電線12。舉例而言,第一罩幕層14_1可具有在約0.1奈米(nm)至50奈米範圍內的厚度,且第二罩幕層14_2可具有在約5奈米至50奈米範圍內的厚度。第一罩幕層14_1可包含氮化鈦層、氮化鋁及/或碳化鈦層,且第二罩幕層14_2可包含氮化矽層。在一些實施例中,第一罩幕層14_1可為氮化鈦層,且第二罩幕層14_2可為氮化矽層。圖4中的罩幕層14經由如圖5中所示出的後續製程圖案化,且亦可稱為初步罩幕層。此外,圖4中的導電線12經由如圖5中所示出的後續製程圖案化,且亦可稱為導電線。
參考圖5,形成導電線結構亦可包含藉由圖案化罩幕層14及導電線12而形成導電線堆疊24(區塊114)。在一些實施例中,額外罩幕層22(例如,光阻層)可形成於罩幕層14上以圖案化罩幕層14及導電線12。可在形成導電線堆疊24之後移除額外罩幕層22。在一些實施例中,可在圖案化罩幕層14之後移除額外罩幕層22,且接著可使用罩幕層14作為蝕刻罩幕來圖案化罩幕層14。
罩幕層14可包含在第三方向D3上依序堆疊於基底10上的第一罩幕層14_1及第二罩幕層14_2。在一些實施例中,導電線12中的每一者可在第二方向D2上縱向延伸。
參考圖6,第一初步絕緣層31可形成於導電線堆疊24上(區塊116)。在一些實施例中,第一初步絕緣層31可覆蓋如圖6中所示出的導電線堆疊24。第一初步絕緣層31可為單層或多層,且可包含氧化矽層、氮氧化矽層、碳化矽層及/或具有低於二氧化矽的介電常數的較低介電層。
參考圖7,第一絕緣層32可藉由移除第一初步絕緣層31的上部部分而形成於導電線堆疊24上(區塊118)。在一些實施例中,可藉由平坦化製程(例如,化學機械研磨(Chemical Mechanical Polishing;CMP)製程、乾式蝕刻製程及/或濕式蝕刻製程)移除第一初步絕緣層31的上部部分,直至暴露罩幕層14的上部表面。第一絕緣層32的上部表面及罩幕層14的上部表面可彼此共面,如圖7中所示出。
參考圖1及圖8,方法亦可包含藉由移除罩幕層14在第一絕緣層32中形成凹槽33(區塊120)。可藉由可選擇性地移除罩幕層14直至暴露導電線12的上部表面的一或多個製程(例如,乾式蝕刻製程及/或濕式蝕刻製程)而移除罩幕層14。舉例而言,使用包含磷酸的蝕刻劑的等向性反應離子蝕刻(reactive-ion etching;RIE)製程及/或濕式蝕刻製程可用於移除罩幕層14。在一些實施例中,蝕刻劑可加熱至約50℃至約200℃範圍內的溫度。凹槽33可具有深度33d。可相對於導電線12及第一絕緣層32兩者選擇性地移除罩幕層14。
在一些實施例中,可完全移除罩幕層14,且因此可暴露導電線12的整個上部表面。可選擇製程條件及化學反應以避免移除導電線12的大部分。在移除罩幕層14時,可移除導電線12在第三方向D3上的厚度的小於5%(例如,1%)。
參考圖1及圖9,方法可更包含在第一絕緣層32上(亦即,在第一絕緣層32的最上部表面上)及在凹槽33中形成蝕刻終止層42及第二絕緣層44(區塊130)。在一些實施例中,蝕刻終止層42可沿著如圖9中所示出的底層結構的表面具有均勻厚度,且蝕刻終止層42可不完全填充凹槽33。蝕刻終止層42可包含例如氧化鋁層、氮化鋁層及/或氮氧化鋁層,且氧化鋁層可包含濃度在0.01原子%至50原子%範圍內的金屬摻雜劑(例如,鉿、鋯、鈦及/或重過渡金屬)。
參考圖1、圖3以及圖9至圖12,方法可另外包含在導電線12上形成導通孔48(區塊140)。形成導通孔48可包含移除第二絕緣層44的一部分直至暴露蝕刻終止層42,藉此在第二絕緣層44中形成初步開口45(區塊142),及移除蝕刻終止層42的一部分直至暴露導電線12,藉此形成開口47(區塊144)。在一些實施例中,如圖11中所示出,開口47可暴露第一絕緣層32的最上部表面32U的一部分。此外,在一些實施例中,凹槽33在第一方向D1上的中心及開口47在第一方向D1上的中心可彼此對準,如圖11中所示出。
可藉由執行蝕刻製程(例如,乾式蝕刻及/或濕式蝕刻製程)移除第二絕緣層44及蝕刻終止層42的經移除部分。在一些實施例中,可藉由等向性蝕刻製程(例如,濕式蝕刻製程)移除蝕刻終止層42的部分以減少在移除蝕刻終止層42的部分時對導電線12的損壞。在一些實施例中,RIE製程可不用於移除蝕刻終止層42的部分。
形成導通孔48亦可包含在開口47中形成導通孔48(區塊146)。可藉由在開口47中及在第二絕緣層44上形成導電層且接著藉由執行例如CMP製程、乾式蝕刻製程及/或濕式蝕刻製程來移除導電層的形成於第二絕緣層44上的一部分而形成導通孔48。導通孔48的上部表面可與第二絕緣層44的上部表面共平面。儘管圖12示出導通孔48為單層,但本發明不限於此。在一些實施例中,導通孔48可包含多層(例如,障壁金屬層及/或金屬層)。
如圖12中所示出,第一絕緣層32上的導通孔48的一部分(亦即,導通孔48的上部部分)與鄰近導電線12之間的距離可由於凹槽33而增大。若導電線12不相對於第一絕緣層32凹陷,則導通孔48的上部部分與鄰近導電線12可彼此間隔開第一距離DT1,所述第一距離DT1比根據本發明的一些實施例的裝置中的第二距離DT2更短。第二距離DT2可與凹槽33的深度33d成比例。
參考圖13,第二導電層52可形成於導通孔48上。導電層52可接觸導通孔48的上部表面且可在第一方向D1上縱向延伸。導通孔48及第二導電層52中的每一者可包含金屬層(例如,釕層、鉬層、銅層、鋁層及/或鎢層)及/或金屬氮化物層(例如,氮化鈦層及/或氮化鉭層)。
圖14至圖16為示出根據本發明的一些實施例的形成積體電路裝置的方法的橫截面圖。方法可與參考圖4至圖13所描述的方法類似或相同,其中主要差異在於,凹槽33的中心可自開口47'在第一方向D1上的中心偏移,如圖16中所示出。
方法可包含與參考圖4至圖9所描述的製程相同或類似的製程,且亦可包含形成延伸穿過第二絕緣層44的初步開口45',如圖14中所示出,及形成暴露導電線12的上部表面的一部分的開口47'。當開口47'的中心自凹槽33的中心偏移時,開口47'可不暴露導電線12的上部表面的一部分,且蝕刻終止層42的一部分42p可保持於導電線12與第二絕緣層44之間,如圖15中所示出。
參考圖16,方法可更包含在開口47'中形成導通孔48'。蝕刻終止層42的部分42p可接觸導通孔48'的側表面,如圖16中所示出。
本文中參考隨附圖式來描述實例實施例。在不偏離本發明的範疇的情況下,許多不同形式及實施例為可能的。因此,本發明不應視為限於本文中所闡述的實例實施例。實情為,提供此等實例實施例使得本揭露將為透徹且完整的,且將向所屬領域中具有通常知識者傳達本發明的範疇。在圖式中,出於清楚起見,可放大層及區的大小及相對大小。貫穿全文,相同附圖標號指代相同元件。
本發明的實例實施例在本文中參考橫截面圖進行描述,所述橫截面圖為實例實施例的理想化實施例及中間結構的示意圖。因而,將預期到因例如製造技術及/或公差所致的圖示的形狀的變化。因此,除非上下文另外清楚地指示,否則本發明的實例實施例不應視為受限於本文中所示出的特定形狀,但包含例如因製造所致的形狀偏差。
除非另外定義,否則本文中所使用的所有術語(包含技術及科學術語)具有與本發明所屬領域的一般技術者通常理解的相同意義。應進一步理解,諸如常用詞典中所定義的術語的術語應解釋為具有與其在相關技術的上下文中的含義一致的含義,且將不在理想化或過度正式意義上進行解釋,除非明確地如此定義。
本文中所使用的術語僅出於描述特定實施例的目的且並不意欲限制本發明。如本文中所使用,單數形式「一(a、an)」及「所述(the)」意欲亦包含複數形式,除非上下文另外清楚地指示。應進一步理解,術語「包括(comprise/comprising)」及/或「包含(include/including)」在用於本說明書中時指定所述特徵、步驟、操作、元件及/或組件的存在,但不排除一或多個其他特徵、步驟、操作、元件、組件及/或其群組的存在或添加。如本文中所使用,術語「及/或」包含相關聯的所列項目中的一或多者的任何及所有組合。
應理解,儘管術語第一、第二等可在本文中用於描述各種元件,但此等元件不應受此等術語限制。此等術語僅用於將一個元件與另一元件進行區分。因此,在不脫離本發明的範疇的情況下,第一元件可稱為第二元件。
上文所揭露的標的物應視為說明性且非限制性的,且隨附申請專利範圍意欲涵蓋屬於本發明的範疇內的所有此類修改、增強以及其他實施例。因此,在法律所允許的最大程度上,範疇應藉由以下申請專利範圍及其等效物的最廣泛容許的解釋來判定,而不應受前述詳細描述約束或限制。
10:基底
10L:下部表面
10U:上部表面
12:導電線
14:罩幕層
14_1:第一罩幕層
14_2:第二罩幕層
22:額外罩幕層
24:導電線堆疊
31:第一初步絕緣層
32:第一絕緣層
32U:最上部表面
33:凹槽
33d:深度
42:蝕刻終止層
42p:部分
44:第二絕緣層
45、45'、47、47':開口
48、48':導通孔
52:第二導電層
110、112、114、116、118、120、130、140、142、144、146:區塊
D1:第一方向
D2:第二方向
D3:第三方向
DT1:第一距離
DT2:第二距離
圖1、圖2以及圖3為根據本發明的一些實施例的形成積體電路裝置的方法的流程圖。
圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12以及圖13為示出根據本發明的一些實施例的形成積體電路裝置的方法的橫截面圖。
圖14、圖15以及圖16為示出根據本發明的一些實施例的形成積體電路裝置的方法的橫截面圖。
110、120、130、140:區塊
Claims (20)
- 一種形成積體電路裝置的方法,所述方法包括: 在基底上形成導電線結構,所述導電線結構包括第一絕緣層及所述第一絕緣層中的導電線堆疊,且所述導電線堆疊包括堆疊於所述基底上的導電線及罩幕層; 藉由移除所述罩幕層在所述第一絕緣層中形成凹槽,所述凹槽暴露所述導電線; 在所述第一絕緣層上及在所述第一絕緣層的所述凹槽中形成蝕刻終止層且接著形成第二絕緣層;以及 形成延伸穿過所述第二絕緣層及所述蝕刻終止層且接觸所述導電線的導通孔。
- 如請求項1所述的形成積體電路裝置的方法,其中所述罩幕層包括有機硬質罩幕層及/或無機硬質罩幕層。
- 如請求項2所述的形成積體電路裝置的方法,其中所述罩幕層為單一氮化矽層,或包括堆疊於所述導電線上的第一罩幕層及第二罩幕層,且 所述第一罩幕層包括氮化鈦層、氮化鋁層及/或碳化鈦層,且所述第二罩幕層包括氮化矽層。
- 如請求項1所述的形成積體電路裝置的方法,其中所述第一絕緣層的上部表面與所述罩幕層的上部表面彼此共面。
- 如請求項1所述的形成積體電路裝置的方法,其中形成所述導通孔包括: 形成延伸穿過所述第二絕緣層及所述蝕刻終止層的開口,所述開口暴露所述導電線;以及 在所述開口中形成所述導通孔。
- 如請求項5所述的形成積體電路裝置的方法,其中形成所述開口包括: 藉由執行第一蝕刻製程移除所述第二絕緣層的一部分,直至暴露所述蝕刻終止層;以及接著 藉由執行作為等向性蝕刻製程的第二蝕刻製程移除所述蝕刻終止層的一部分,直至暴露所述導電線。
- 如請求項6所述的形成積體電路裝置的方法,其中所述第二蝕刻製程為濕式蝕刻製程。
- 如請求項1所述的形成積體電路裝置的方法,其中所述蝕刻終止層包括氧化鋁層、氮化鋁層及/或氮氧化鋁層。
- 如請求項1所述的形成積體電路裝置的方法,其中形成所述導電線結構包括: 在所述基底上形成導電層且接著形成所述罩幕層; 藉由使用所述罩幕層作為蝕刻罩幕來圖案化所述導電層而形成所述導電線; 在所述導電線及所述罩幕層上形成第一初步絕緣層;以及 對所述第一初步絕緣層執行平坦化製程,直至暴露所述罩幕層。
- 一種形成積體電路裝置的方法,所述方法包括: 在基底上形成導電線堆疊,所述導電線堆疊包括堆疊於所述基底上的導電線及罩幕層; 在所述導電線堆疊上形成第一初步絕緣層; 藉由對所述第一初步絕緣層執行平坦化製程直至暴露所述罩幕層而形成第一絕緣層; 藉由移除所述罩幕層在所述第一絕緣層中形成凹槽,所述凹槽暴露所述導電線; 在所述第一絕緣層上及在所述第一絕緣層的所述凹槽中形成蝕刻終止層且接著形成第二絕緣層; 形成延伸穿過所述第二絕緣層及所述蝕刻終止層的開口,所述開口暴露所述導電線的上部表面的第一部分及所述第一絕緣層的最上部表面的一部分;以及 在所述開口中形成導通孔。
- 如請求項10所述的形成積體電路裝置的方法,其中所述罩幕層為單一氮化矽層,或包括堆疊於所述導電線上的第一罩幕層及第二罩幕層,且 所述第一罩幕層包括氮化鈦層、氮化鋁層及/或碳化鈦層,且所述第二罩幕層包括氮化矽層。
- 如請求項10所述的形成積體電路裝置的方法,其中所述導電線包括釕及/或鉬。
- 如請求項10所述的形成積體電路裝置的方法,其中所述蝕刻終止層包括氧化鋁層、氮化鋁層及/或氮氧化鋁層。
- 如請求項10所述的形成積體電路裝置的方法,其中所述蝕刻終止層在形成所述開口之前在所述第一絕緣層上及所述第一絕緣層的所述凹槽中具有均勻厚度。
- 如請求項10所述的形成積體電路裝置的方法,其中形成所述開口包括: 藉由執行第一蝕刻製程移除所述第二絕緣層的一部分,直至暴露所述蝕刻終止層;以及接著 藉由執行作為等向性蝕刻製程的第二蝕刻製程移除所述蝕刻終止層的一部分,直至暴露所述導電線。
- 如請求項10所述的形成積體電路裝置的方法,其中所述導通孔接觸所述第一絕緣層的所述最上部表面的所述部分。
- 如請求項10所述的形成積體電路裝置的方法,其中所述導通孔接觸所述導電線的所述上部表面的所述第一部分,且 所述蝕刻終止層的一部分位於所述導電線的所述上部表面的第二部分與所述第二絕緣層之間,且接觸所述導通孔的側表面。
- 一種積體電路裝置,包括: 第一絕緣層,位於基底上; 第二絕緣層,位於所述第一絕緣層上; 蝕刻終止層,位於所述第一絕緣層與所述第二絕緣層之間; 導電線,位於所述第一絕緣層中,其中所述導電線的上部表面相對於所述第一絕緣層的最上部表面朝向所述基底凹陷;以及 導通孔,延伸穿過所述第二絕緣層及所述蝕刻終止層且接觸所述導電線的所述上部表面, 其中所述導通孔接觸所述導電線的所述上部表面的第一部分,且 所述蝕刻終止層的一部分位於所述導電線的所述上部表面的第二部分與所述第二絕緣層之間,且接觸所述導通孔的側表面。
- 如請求項18所述的積體電路裝置,其中所述蝕刻終止層包括氧化鋁層及/或氮氧化鋁層。
- 如請求項19所述的積體電路裝置,其中所述蝕刻終止層包括所述氧化鋁層,所述氧化鋁層包括濃度在0.01原子%至50原子%範圍內的金屬摻雜劑。
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US202163242193P | 2021-09-09 | 2021-09-09 | |
US63/242,193 | 2021-09-09 | ||
US17/546,470 US11978668B2 (en) | 2021-09-09 | 2021-12-09 | Integrated circuit devices including a via and methods of forming the same |
US17/546,470 | 2021-12-09 |
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Country Status (5)
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US (1) | US11978668B2 (zh) |
EP (1) | EP4148775B1 (zh) |
KR (1) | KR20230037438A (zh) |
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Family Cites Families (24)
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US9054109B2 (en) * | 2012-05-29 | 2015-06-09 | International Business Machines Corporation | Corrosion/etching protection in integration circuit fabrications |
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US9583429B2 (en) | 2013-11-14 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of forming same |
US9105700B2 (en) | 2013-12-12 | 2015-08-11 | Lam Research Corporation | Method for forming self-aligned contacts/vias with high corner selectivity |
WO2016105350A1 (en) | 2014-12-22 | 2016-06-30 | Intel Corporation | Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme |
US9576894B2 (en) | 2015-06-03 | 2017-02-21 | GlobalFoundries, Inc. | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same |
US9627215B1 (en) | 2015-09-25 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for interconnection |
US10020224B2 (en) * | 2015-12-28 | 2018-07-10 | Globalfoundries Inc. | Self-aligned via forming to conductive line and related wiring structure |
US10354912B2 (en) | 2016-03-21 | 2019-07-16 | Qualcomm Incorporated | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) |
US9679804B1 (en) | 2016-07-29 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-patterning to form vias with straight profiles |
US10566232B2 (en) | 2017-05-18 | 2020-02-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Post-etch treatment of an electrically conductive feature |
US10157790B1 (en) * | 2017-09-28 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10347528B1 (en) | 2018-03-06 | 2019-07-09 | Globalfoundries Inc. | Interconnect formation process using wire trench etch prior to via etch, and related interconnect |
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US10867805B2 (en) | 2018-06-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective removal of an etching stop layer for improving overlay shift tolerance |
US10727124B2 (en) | 2018-10-29 | 2020-07-28 | International Business Machines Corporation | Structure and method for forming fully-aligned trench with an up-via integration scheme |
US11362030B2 (en) | 2020-05-29 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability |
-
2021
- 2021-12-09 US US17/546,470 patent/US11978668B2/en active Active
-
2022
- 2022-06-09 EP EP22178086.9A patent/EP4148775B1/en active Active
- 2022-07-06 TW TW111125361A patent/TW202314970A/zh unknown
- 2022-07-11 KR KR1020220085307A patent/KR20230037438A/ko unknown
- 2022-09-05 CN CN202211095057.5A patent/CN115799168A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US11978668B2 (en) | 2024-05-07 |
EP4148775B1 (en) | 2024-05-01 |
US20230074982A1 (en) | 2023-03-09 |
KR20230037438A (ko) | 2023-03-16 |
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