TW202135272A - 半導體封裝及製造半導體封裝的方法 - Google Patents

半導體封裝及製造半導體封裝的方法 Download PDF

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TW202135272A
TW202135272A TW109131584A TW109131584A TW202135272A TW 202135272 A TW202135272 A TW 202135272A TW 109131584 A TW109131584 A TW 109131584A TW 109131584 A TW109131584 A TW 109131584A TW 202135272 A TW202135272 A TW 202135272A
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wiring pad
chip
electrode
semiconductor package
pad
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TW109131584A
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TWI741787B (zh
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楊吳德
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南亞科技股份有限公司
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Abstract

提供一種半導體封裝，包含封裝基板、第一晶片、第二晶片、互連構件以及複數個接合引線。第一晶片設置於封裝基板上。第二晶片設置於第一晶片上。互連構件包含連接板、複數個重分佈結構、及複數個焊球。連接板連接至第一晶片。重分佈結構連接至第二晶片。焊球耦接連接板至重分佈結構。複數個接合引線耦接互連構件至封裝基板及第一晶片。

Description

半導體封裝及製造半導體封裝的方法
本揭露是關於一種半導體封裝及其製造方法。
半導體裝置對於許多現代應用是必不可少的。隨著電子技術的進步，半導體裝置的尺寸越來越小，同時具有更大的功能和更多的積體電路。由於半導體裝置的小型化，晶片堆疊封裝技術現在被廣泛用於製造半導體裝置。
根據本揭露之一態樣，提供一種半導體封裝。半導體封裝包含封裝基板、第一晶片、第二晶片、互連構件以及複數個接合引線.第一晶片設置於封裝基板上。第二晶片設置於第一晶片上。互連構件設置以耦接第一晶片及第二晶片，且包含連接板、複數個重分佈結構及複數個焊球.連接板連接至第一晶片。重分佈結構連接至第二晶片。複數個焊球耦接連接板至複數個重分佈結構。複數個接合引線耦接互連構件至封裝基板及第一晶片。
根據本發明之一些實施方式，第一晶片包含第一接線墊及與第一接線墊相鄰的第二接線墊，且連接板具有通孔暴露出第一接線墊及第二接線墊。
根據本發明之一些實施方式，第一接線墊及第二接線墊分別藉由穿過通孔的第一接合引線及第二接合引線耦接至連接板。
根據本發明之一些實施方式，第二晶片包括第三接線墊及與第三接線墊相鄰的第四接線墊，且第三接線墊及第四接線墊分別耦接至不同的重分佈結構。
根據本發明之一些實施方式，重分佈結構中的每一個包括焊球接點及具有第一端及第二端的導電跡線，其中第一端耦接至焊球接點，第二端耦接至第三接線墊及第四接線墊中之一者。
根據本發明之一些實施方式，焊球接點及連接板連接至對應焊球的相對兩側。
根據本發明之一些實施方式， 第一接線墊對準第四接線墊，第二接線墊對準第三接線墊。
根據本發明之一些實施方式，連接板包含支撐層、第一電極及第二電極。支撐層具有第一邊緣及與第一邊緣相對的第二邊緣。第一電極及第二電極設置於支撐層上，其中第一電極及第二電極分別接近第一邊緣及第二邊緣。
根據本發明之一些實施方式，第一電極及第二電極中的每一個藉由兩條接合引線連接至封裝基板及第一晶片。
根據本發明之一些實施方式，半導體封裝更包括封裝材料封裝第一晶片、第二晶片、互連構件及接合引線。
本揭露的另一態樣提供一種製造上述任一實施例的半導體封裝的方法。此方法包含提供封裝基板；放置第一晶片於封裝基板上；放置第二晶片於第一晶片上；藉由互連構件耦接第一晶片及第二晶片，其中互連構件包括連接板連接至第一晶片、複數個重分佈結構連接至第二晶片、以及複數個焊球耦接連接板至重分佈結構；以及藉由複數個接合引線耦接互連構件至封裝基板及第一晶片。
應當理解，前述的一般性描述和下文的詳細描述都是示例，並且旨在提供對所要求保護的本揭示內容的進一步解釋。
以下揭露提供許多不同的實施方式或實施例，用於實施所提供的範疇的不同特徵。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。當然，這些僅是實施例，並且不旨在限制。舉例來說，以下所述之第一特徵形成於第二特徵上的敘述包含兩者直接接觸，或兩者之間隔有其他額外特徵而非直接接觸。此外，本揭露在多個實施例中可重複參考數字及/或符號。這樣的重複是為了簡化和清楚，而並不代表所討論的各實施例及/或配置之間的關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一特徵與另一特徵在圖示中的相對關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含在使用或操作中的設備之不同定向。置/設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣地解讀本揭露所使用之空間相對性描述詞。
應當理解的是，當一元件被稱為『連接』或『耦接』至另一元件時，它可以為直接連接或耦接至另一元件，又或是其中有一額外元件存在。相對的，當一元件被稱為『直接連接』或『直接耦接』至另一元件時，其中是沒有額外元件存在。
根據本揭露的部分實施例，一種製造半導體封裝的方法說明如下。
第1圖至第5圖為根據本揭露之某些實施方式繪示的半導體封裝下部部分的製程中的各步驟的俯視圖。請參考第1圖，準備半導體封裝的下部部分的步驟從提供第一晶片10開始。在一些實施方式中，第一晶片10包括由半導體材料製成的半導體基板，該半導體材料包括但不限於塊狀矽、半導體晶片、絕緣體上矽（silicon-on-insulator，SOI）基板或矽鍺基板。也可以使用包括III族、IV族和V族元素的其他半導體材料。
此外，第一晶片10可以也包含電子層。電子層可以包括多個微電子元件。微電子元件的示例包括電晶體（例如，金屬氧化物半導體場效應電晶體（MOSFET）、互補金屬氧化物半導體電晶體（CMOS）、雙極型接面電晶體（BJT）、高壓電晶體、高頻電晶體、p通道和/或n通道場效應電晶體（PFET/NFET）等）；電阻器二極管;電容器;電感器;保險絲;和其他合適的裝置。各種加工可用於形成上述微電子元件，包括沉積、蝕刻、注入、微影、退火和其他合適的加工。微電子元件互連以形成積體電路，例如邏輯裝置、儲存裝置（例如SRAM）、射頻裝置、輸入/輸出（I / O）裝置、系統整合晶片（system-on-chip，SOC）裝置、系統晶片（system-in-chip，SIC）裝置、動態存取記憶體(dynamic random-access memory，DRAM)，其組合以及其他合適類型的裝置。
在一些實施方式中，第一晶片10包含第一接線墊12及與第一接線墊12相鄰的第二接線墊14。如第1圖所示，複數個第一接線墊12及複數個第二接線墊14可以形成在第一晶片10的作動表面11上。在一些實施方式中，第一接線墊12及第二接線墊14分別電連接至第一晶片10中的微電子元件。第一接線墊12可以沿作動表面11的中心區域對齊，且第二接線墊14可以平行於第一接線墊12。第一接線墊12及第二接線墊14代表形成在半導體晶片表面附近的各種端子中的任何一個，晶片中的積體電路通過該端子與外部電路之間進行電連接。
請參考第2圖，準備半導體封裝的下部部分更包含提供連接板20。在一些實施方式中，連接板20包含支撐層21、第一電極22以及第二電極24。支撐層21可以為印刷電路板。在一些實施方式中， 支撐層21可以由陶瓷、有機物、玻璃和/或半導體材料或結構製成。如第2圖所示，形成通孔H1以穿透支撐層21。通孔H1位於支撐層21的中央區域，且作動區域25及作動區域26位於通孔H1的兩側。作動區域25及作動區域26可以分別將內邊緣230連接到支撐層21的外邊緣（即，第一邊緣210和第二邊緣220）。
第一電極22與第二電極24設置在支撐層21的上表面上。如第2圖所示，複數個第一電極22及複數個第二電極24分別靠近第一邊緣210及第二邊緣220。具體而言，第一電極22佈置在作動區域 25上，且第二電極24佈置在作動區域 26上。在一些實施方式中，每個第一電極22包含連接部221、焊球接點222以及兩個導線接點223、224。類似地，在一些實施方式中，每個第二電極24包括連接部241、焊球接點242以及兩個導線接點243、244。連接部221及連接部241可以具有條形形狀，並且連接部221及連接部241的延伸方向可以垂直於內邊緣230和外邊緣（即，第一邊緣210和第二邊緣220）。焊球接點222及焊球接點242分別形成在連接部221及連接部241的中央。導線接點223形成在連接部221與第一邊緣210相鄰的一端，導線接點224形成在連接部221與內邊緣230相鄰的另一端。類似地，導線接點243形成在連接部241與第二邊緣220相鄰的一端，導線接點244形成在連接部221與內邊緣230相鄰的另一端。焊球接點222、242及導線接點223、224、243、244的寬度可以比連接部221、241的寬度大，以利導電元件的電連接。
請參考第3圖，準備半導體封裝的下部部分更包含將連接板20連接至第一晶片10。在一些實施方式中，支撐層21與其上表面相對的後表面與第一晶片10的作動表面11直接接觸。支撐層21可以使用本領域已知的常規方法通過黏合劑層（未示出）附接到第一晶片10的作動表面11上。在組裝第一晶片10及連接板20後，連接板20的通孔H1暴露出第一接線墊12及第二接線墊14。如第3圖所示，第一接線墊12可以與第一電極22相鄰，第二接線墊14可以與第二電極24相鄰。也就是說，第一接線墊12及第二接線墊14可以與第一電極22及第二電極24對準。
在一些實施方式中，支撐層21的尺寸與作動表面11的尺寸實質上相同，並且在第一晶片10組裝至連接板20後，支撐層21的外邊緣110與第一晶片10的外邊緣重疊。然而，應當理解，可以對本揭露的實施例做出許多變化和修改。在支撐層21的尺寸小於作動表面11的尺寸的情況下，在第一晶片10和連接板20組裝之後，支撐層21的外邊緣可以遠離作動表面11的外邊緣110。
請參考第4圖，準備半導體封裝的下部部分更包含將連接板20耦接至第一晶片10。第一晶片10的第一接線墊12及第二接線墊14分別藉由穿過通孔H1的第一接合引線32及第二接合引線34耦接至連接板20。具體而言，第一接合引線32從第一接線墊12形成到相鄰的導線接點224，第二接合引線34 從第二接線墊14形成到相鄰的導線接點244。
請參考第5圖，準備半導體封裝的下部部分更包含將第一晶片10與連接板20放置到封裝基板40上。在一些實施方式中，封裝基板40可以為印刷電路板、陶瓷、有機物、玻璃和/或半導體材料或結構，以提供電源、接地、控制、監視等功能的基礎。
在一些實施方式中，封裝基板40包含佈線特徵，例如焊盤42、44或走線層（未示出），以將電子訊號傳送往返於第一晶片10。具體而言，複數個接合引線43、45分別從焊盤42、44形成到相鄰的導線接點223、243，以將第一晶片10連接至封裝基板40。如此形成半導體封裝10的下部部分1L。封裝基板40可進一步包括形成在封裝基板40的底面上的多個焊球46（繪示於第9圖），用於將電子訊號傳送至其他電器裝置（例如，主機板或其他晶片組）。
第6圖至第8圖為根據本揭露之某些實施方式繪示的半導體封裝上部部分的製程中的各步驟的俯視圖。
請參考第6圖，準備半導體封裝的上部部分的步驟從提供第二晶片50開始。第二晶片50可以包括由半導體材料製成的半導體基板，該半導體材料包括但不限於塊狀矽、半導體晶片、絕緣體上矽（silicon-on-insulator，SOI）基板或矽鍺基板。也可以使用包括III族、IV族和V族元素的其他半導體材料。
此外，第二晶片50可以也包含電子層。電子層可以包括多個微電子元件。微電子元件的示例包括電晶體（例如，金屬氧化物半導體場效應電晶體（MOSFET）、互補金屬氧化物半導體電晶體（CMOS）、雙極型接面電晶體（BJT）、高壓電晶體、高頻電晶體、p通道和/或n通道場效應電晶體（PFET/NFET）等）；電阻器二極管;電容器;電感器;保險絲;和其他合適的裝置。各種加工可用於形成上述微電子元件，包括沉積、蝕刻、注入、微影、退火和其他合適的加工。微電子元件互連以形成積體電路，例如邏輯裝置、儲存裝置（例如SRAM）、射頻裝置、輸入/輸出（I / O）裝置、系統整合晶片（system-on-chip，SOC）裝置、系統晶片（system-in-chip，SIC）裝置、動態存取記憶體(dynamic random-access memory，DRAM)，其組合以及其他合適類型的裝置。
在一些實施方式中，第二晶片50包含第三接線墊52及與第三接線墊52相鄰的第四接線墊54。如第6圖所示，複數個第三接線墊52及複數個第四接線墊54可以形成在第二晶片50的作動表面51上。在一些實施方式中，第三接線墊52及第四接線墊54分別電連接至第二晶片50中的微電子元件。第三接線墊52可以沿作動表面51的中心區域對齊，且第四接線墊54可以平行於第三接線墊52。第三接線墊52及第四接線墊54代表形成在半導體晶片表面附近的各種端子中的任何一個，晶片中的積體電路通過該端子與外部電路之間進行電連接。
請參考第7圖，準備半導體封裝的上部部分更包含將複數個重分佈結構60連接至第二晶片50。在一些實施方式中，重分佈結構60包含連接至第三接線墊52的第一重分佈結構60a、以及連接至第四接線墊54的第二重分佈結構60b。即，第三接線墊52與第四接線墊54分別耦接至不同的重分佈結構。
如第7圖所示，每個重分佈結構60可以包含焊球接點及導電跡線。導電跡線的第一端耦接至焊球接點，導電跡線的第二端耦接至第三接線墊52及第四接線墊54中之一者。具體而言，鄰近第四接線墊54的焊球接點62藉由導電跡線63耦接至第三接線墊52，鄰近第三接線墊52的焊球接點64藉由導電跡線65耦接至第四接線墊54。
請參考第8圖，準備半導體封裝的上部部分更包含分配複數個焊球70至重分佈結構60的焊球接點62、64之上。在一些實施方式中，焊球70包含錫球。如此形成半導體封裝10的上部部分1U。
請參考第9圖，在下部部分1L與上部部分1U完成後，製作半導體封裝1的方法更包括藉由上下翻轉第8圖所示的上部部分1U使焊球70位於對應的一對焊球接點之間，以組裝下部部分1L及上部部分1U。例如，在焊球接點62、222之間的焊球70將連接板20耦接至重分佈結構60，如第9圖所示。在本揭露中，由於連接板20、重分佈結構60及焊球70配置用於在第一晶片10和第二晶片50傳送訊號，第一連接板20、重分佈結構60及焊球70亦稱作「互連構件80」。
如第9圖所示，當上部部分1U堆疊在下部部分1L之上時，第一晶片10的作動表面11面向上，第二晶片50的作動表面51面向下。在一些實施方式中，第一晶片10的第一接線墊12及第二接線墊14分別與第二晶片50的第四接線墊54及第三接線墊52對準。互連構件80位於作動表面11和作動表面51之間。第一重分佈結構60a的焊球接點62及連接板20的焊球接點222連接到同一焊球70的兩側，且焊球接點64、242連接到同一焊球70的兩側。
應當理解的是，雖然接合引線32、接合引線34、接合引線43和接合引線45各自用於將第一晶片10連接到連接板20，並且將封裝基板40連接到第一晶片10，但本揭露並不僅此為限。在一些實施方式中，在第一晶片10中形成有層間連接點(未示出），並且省略了接合引線43、45。第一晶片10經由形成在第一晶片10背面上諸如凸塊的連接件連接至封裝基板40。
製作半導體封裝1的方法更包括藉由封裝材料90封裝第一晶片10、第二晶片50、互連構件80及接合引線32、34、43、45。封裝材料90可以包含熱固性環氧樹脂。如此完成半導體封裝1。
如上所述，提供一種新穎的面對面的雙晶片封裝（face to face dual die package，F2F DDP）及其製造方法。本揭露的封裝適用於耦接其上具有兩行接線墊的半導體晶片，這與常規技術中僅具有單行接線墊的半導體晶片不同。設置在一個半導體晶片上的重分佈結構使半導體晶片的接線墊能夠以更簡單的方法與另一半導體晶片的接線墊耦接。因此，降低了半導體封裝的製造成本及降低了產品設計複雜度性。
儘管本揭示內容已根據某些實施方式具體描述細節，其他實施方式也是可行的。因此，所附請求項的精神和範圍不應限於本文所記載的實施方式。
本領域技術人員也應當理解，在不脫離本揭示內容的精神和範圍的情況下，對於本揭示內容所做的各種修改和變形是可行的。根據前述內容，本揭示內容旨在涵蓋可落入後續請求項範圍內的本揭示內容中的各種修改和變形。
1:半導體封裝 1U:上部部分 1L:下部部分 10:第一晶片 11,51:作動表面 12:第一接線墊 14:第二接線墊 20:連接板 21:支撐層 22:第一電極 24:第二電極 25,26:作動區域 32:第一接合引線 34:第二接合引線 40:封裝基板 42,44:焊盤 43,45:接合引線 46,70:焊球 50:第二晶片 51:作動表面 52:第三接線墊 54:第四接線墊 60:重分佈結構 60a:第一重分佈結構 60b:第二重分佈結構 62,64,222,242:焊球接點 63,65:導電跡線 80:互連構件 90:封裝材料 110:外邊緣 210:第一邊緣 220:第二邊緣 221,241:連接部 222,242:焊球接點 223,224,243,244:導線接點 230:內邊緣 H1:通孔
當與圖示一起閱讀時，從以下詳細描述可以最好地理解本揭露的態樣。應注意，根據業界標準實務，各種特徵未按比例繪製。事實上，為了清楚地討論，各個特徵的尺寸可任意地增加或減小。 第1圖至第5圖為根據本揭露之某些實施方式繪示的半導體封裝下部部分的製程中的各步驟的俯視圖。 第6圖至第8圖為根據本揭露之某些實施方式繪示的半導體封裝上部部分的製程中的各步驟的俯視圖。 第9圖為根據本揭露之某些實施方式繪示的半導體封裝的截面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
1:半導體封裝
1U:上部部分
1L:下部部分
10:第一晶片
11,51:作動表面
12:第一接線墊
14:第二接線墊
20:連接板
32:第一接合引線
34:第二接合引線
40:封裝基板
43、45:接合引線
46、70:焊球
50:第二晶片
52:第三接線墊
54:第四接線墊
60:重分佈結構
60a:第一重分佈結構
60b:第二重分佈結構
62,64,222,242:焊球接點
80:互連構件
90:封裝材料

Claims (20)

  1. 一種半導體封裝，包括： 一封裝基板； 一第一晶片，設置於該封裝基板上； 一第二晶片設置於該第一晶片上； 一互連構件，包括： 一連接板，連接至該第一晶片； 複數個重分佈結構，連接至該第二晶片；以及 複數個焊球，耦接該連接板至該些重分佈結構；以及 複數個接合引線耦接該互連構件至該封裝基板及該第一晶片。
  2. 如請求項1所述之半導體封裝，其中該第一晶片包括一第一接線墊及與該第一接線墊相鄰的一第二接線墊，且該連接板具有一通孔暴露出該第一接線墊及該第二接線墊。
  3. 如請求項2所述之半導體封裝，其中該第一接線墊及該第二接線墊分別藉由穿過該通孔的一第一接合引線及一第二接合引線耦接至該連接板。
  4. 如請求項2所述之半導體封裝，其中該第二晶片包括一第三接線墊及與該第三接線墊相鄰的一第四接線墊，且該第三接線墊及該第四接線墊分別耦接至不同的該些重分佈結構。
  5. 如請求項4所述之半導體封裝，其中該些重分佈結構中的每一個包括一焊球接點及具有一第一端及一第二端的一導電跡線，其中該第一端耦接至該焊球接點，該第二端耦接至該第三接線墊及該第四接線墊中之一者。
  6. 如請求項5所述之半導體封裝，其中該焊球接點及該連接板連接至該對應焊球的相對兩側。
  7. 如請求項4所述之半導體封裝，其中該第一接線墊對準該第四接線墊，該第二接線墊對準該第三接線墊。
  8. 如請求項1所述之半導體封裝，其中該連接板包括： 一支撐層，具有一第一邊緣及與該第一邊緣相對的一第二邊緣；以及 一第一電極及一第二電極設置於該支撐層上，其中該第一電極及該第二電極分別接近該第一邊緣及該第二邊緣。
  9. 如請求項8所述之半導體封裝，其中該第一電極及該第二電極中的每一個藉由兩條該些接合引線連接至該封裝基板及該第一晶片。
  10. 如請求項1所述之半導體封裝，更包括一封裝材料封裝該第一晶片、該第二晶片、該互連構件及該些接合引線。
  11. 一種半導體封裝的製造方法，包括： 提供一封裝基板； 放置一第一晶片於該封裝基板上； 放置一第二晶片於該第一晶片上； 藉由一互連構件耦接該第一晶片及該第二晶片，其中該互連構件包括一連接板連接至該第一晶片、複數個重分佈結構連接至該第二晶片、以及複數個焊球連接該連接板至該些重分佈結構；以及 藉由複數個接合引線耦接該互連構件至該封裝基板及該第一晶片。
  12. 如請求項11所述之方法，其中該連接板具有一通孔暴露出該第一晶片的一第一接線墊及一第二接線墊，其中該第二接線墊與該第一接線墊相鄰。
  13. 如請求項12所述之方法，其中耦接該互連構件至該第一晶片包括分別藉由穿過該通孔的一第一接合引線及一第二接合引線耦接該連接板至該第一接線墊及該第二接線墊。
  14. 如請求項12所述之方法，其中該第二晶片 包括一第三接線墊及與該第三接線墊相鄰的一第四接線墊，且該第三接線墊及該第四接線墊分別耦接至不同的該些重分佈結構。
  15. 如請求項14所述之方法，其中該些重分佈結構中的每一個包括一焊球接點及具有一第一端及一第二端的一導電跡線，其中該第一端耦接至該焊球接點，該第二端耦接至該第三接線墊及該第四接線墊中之一者。
  16. 如請求項15所述之方法，其中該焊球接點及該連接板連接至該對應焊球的相對兩側。
  17. 如請求項14所述之方法，其中該第一接線墊對準該第四接線墊，該第二接線墊對準該第三接線墊。
  18. 如請求項11所述之方法，其中該連接板包括： 一支撐層，具有一第一邊緣及與該第一邊緣相對的一第二邊緣；以及 一第一電極及一第二電極設置於該支撐層上，其中該第一電極及該第二電極分別接近該第一邊緣及該第二邊緣。
  19. 如請求項18所述之方法，其中該第一電極及該第二電極中的每一個藉由兩條該些接合引線連接至該封裝基板及該第一晶片。
  20. 如請求項11所述之方法，更包括由一封裝材料封裝該第一晶片、該第二晶片、該互連構件及該些接合引線。
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