TW202115902A - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TW202115902A
TW202115902A TW109133755A TW109133755A TW202115902A TW 202115902 A TW202115902 A TW 202115902A TW 109133755 A TW109133755 A TW 109133755A TW 109133755 A TW109133755 A TW 109133755A TW 202115902 A TW202115902 A TW 202115902A
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semiconductor structure
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TW109133755A
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TWI756853B (zh
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楊建勳
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台灣積體電路製造股份有限公司
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Abstract

本揭露描述一種具有氣隙的閘極間隔物結構的形成方法，以減少電晶體的閘極結構和源極∕汲極接觸件之間的寄生電容（parasitic capacitance）。在一些實施例中，方法包括在基底上形成閘極結構，以及在閘極結構的側壁表面上形成間隔物堆疊，其中間隔物堆疊包括接觸閘極結構的內間隔物層、在內間隔物層上的犧牲間隔物層、和在犧牲間隔物層上的外間隔物層。方法更包括移除犧牲間隔物層以形成介於內間隔物層和外間隔物層之間的開口、在內間隔物層和外間隔物層的頂面上沉積聚合物材料、蝕刻內間隔物層和外間隔物層的頂側壁表面以形成錐形頂部、以及沉積密封材料。

Description

半導體結構及其形成方法
本發明實施例是關於半導體結構及其形成方法，特別是關於間隔物氣隙的形成。
在半導體晶粒中，可在近距離形成的導電結構（藉由介電層分隔開）位置形成寄生電容（parasitic capacitance）。導電結構可為，例如，走線、導孔、接觸件、閘極結構、或磊晶層。在密集設置的晶粒電路佈局中避免寄生電容的方法為採用具有較低介電常數（dielectric constant）的絕緣材料。
一種半導體結構，包括：閘極結構，於鰭片上；蓋層（capping layer），於閘極結構上；導電結構，鄰近於閘極結構；以及間隔物結構（spacer structure），插入閘極結構和導電結構之間，其中間隔物結構包括：第一間隔物層，與閘極結構和蓋層的側壁表面（sidewall surface）接觸；第二間隔物層，藉由間隙（gap）與第一間隔物層分隔開；以及密封層（seal layer），設置於第一間隔物層和第二間隔物層之間的間隙上。
一種半導體結構的形成方法，包括：形成閘極結構於基底上；形成間隔物堆疊於閘極結構的側壁表面上，其中間隔物堆疊包括：內間隔物層，與閘極結構接觸；犧牲間隔物層，於內間隔物層上；以及外間隔物層，於犧牲間隔物層上；移除犧牲間隔物層以形成介於內間隔物層和外間隔物層之間的開口；沉積聚合物材料於內間隔物層和外間隔物層的頂面上；蝕刻內間隔物層和外間隔物層的頂側壁表面以形成錐形頂部；以及沉積密封材料以塞住錐形頂部並形成介於內間隔物層和外間隔物層之間的間隙。
一種半導體結構，包括：閘極結構，於基底上；導電結構，與閘極結構分隔開；以及間隔物結構，插入閘極結構和導電結構之間，其中間隔物結構包括：第一間隔物，具有第一內側壁表面；第二間隔物，具有相對於第一間隔物的第一內側壁表面的第二內側壁表面；密封材料，設置在間隔物結構介於第一內側壁表面和第二內側壁表面之間的頂部上；以及間隙，形成介於第一間隔物和第二間隔物之間，並被第一內側壁表面、第二內側壁表面、和密封材料圍繞。
以下揭露提供了許多不同的實施例或範例，用於實施本揭露的不同部件。組件和配置的具體範例描述如下，以簡化本揭露。當然，這些僅僅是範例，並非用以限定本揭露。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。
此外，此處可使用空間上相關的用語，例如「在…下方」、「下方的」、「低於」、「上方的」、「上方」等，以便描述一元件或部件和其他元件或部件之間的關係，如在圖式中所示。空間上相關的用語企圖涵蓋這些元件除了在圖式中所描繪的方位以外的不同方位。當裝置被轉至其他方位（旋轉90°或其他方位），則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
此處使用的用語「標稱上的（nominal）」，表示在產品或製程的設計階段期間所設定之組件或製程步驟的特徵或參數之期望值或目標值，以及高於及/或低於此期望值之數值範圍。此數值範圍一般是由製造過程或容許差度的所造成的微小變化。
在一些實施例中，「約」和「實質上地（substantially）」的用語可表示一給定量的數值，其差異介於目標值的5％以內（例如目標值的±1％、±2％、±3％、±4％、±5％）。
此處使用的用語「垂直的」，意指標稱上地垂直於基底的表面。
半導體晶粒可在每單位區域中容納較大的電晶體密度，以增加晶粒功能性並降低製造成本。然而，具有較大電晶體密度的半導體晶粒可遭受因導電結構（如電晶體閘極、接觸件、導孔、和走線）距離更加接近所導致的寄生電容（parasitic capacitance）。舉例來說，在晶粒的前段（front-end-of-the-line）區中，多餘的寄生電容可形成在電晶體閘極結構和鄰近的源極∕汲極（source/drain, S/D）接觸件之間、電晶體閘極結構和源極∕汲極端之間、源極∕汲極接觸件之間、和電晶體閘極之間。
為了解決寄生電容的問題，本揭露是關於具有氣隙的閘極間隔物結構的形成方法，其氣隙微型化閘極間隔物結構的有效介電常數，因而減少電晶體閘極結構和鄰近的源極∕汲極接觸件之間的寄生電容。在一些實施例中，氣隙的形成可藉由形成閘極間隔物堆疊，其具有設置在兩個間隔物層之間的犧牲間隔物，從閘極間隔物堆疊選擇性地移除犧牲間隔物以形成介於剩餘間隔物層之間的開口，蝕刻開口的頂部以形成錐形輪廓，以及後續以密封材料塞住蝕刻後的開口頂部以形成在閘極間隔物結構之內的永久氣隙。在一些實施例中，形成錐形輪廓包括使用帶狀束蝕刻機台（ribbon beam etcher）以進行一或多次聚合物材料沉積和間隔物層蝕刻的循環。沉積後的聚合物材料被配置以作為蝕刻步驟期間的蝕刻遮罩，以保護不意欲被蝕刻的結構部件。在一些實施例中，可能有多次的聚合物沉積和蝕刻的循環，直到達到所欲的開口輪廓。在一些實施例中，可選擇用來沉積的聚合物材料和蝕刻化學品以達到閘極間隔物堆疊的聚合物材料和間隔物層之間的最佳蝕刻選擇比。
根據一些實施例，第1圖為鰭式場效電晶體（fin field-effect transistor, finFET）結構100的部分等角（isometric）示意圖，其建構在基底102的鰭片104上。第1圖繪示鰭式場效電晶體結構100的所選部分，而其他部分可不繪示以簡化本揭露的實施例。這些其他部分可包括額外結構部件，如額外膜層、額外電晶體、摻雜區、隔離區、和其他類似部件。再者，第1圖中的鰭式場效電晶體結構100的繪示為例示性目的，且可不按照比例繪製。
如第1圖中所示，在半導體鰭片104（也被稱為鰭片104）上形成鰭式場效電晶體結構100。形成鰭片104垂直於基底102的頂面，並透過隔離區106與彼此電性隔離。可藉由任何合適方法圖案化鰭片104。舉例來說，可使用一或多道光微影製程（包括雙圖案化或多重圖案化製程）圖案化鰭片104。雙圖案化或多重圖案化製程可結合光微影和自我對準（self-aligned）製程，讓創造出的圖案具有例如小於使用單一直接光微影製程所獲得的節點。舉例來說，在一實施例中，在基底上形成並使用光微影製程圖案化犧牲層。使用自我對準製程沿著圖案化後的犧牲層形成間隔物。接著移除犧牲層，而可使用剩餘的間隔物以圖案化鰭片104。在一些實施例中，以介電材料（如氧化矽或矽基氧化物）填入隔離區106，而在鰭片104之間形成淺溝槽隔離（shallow trench isolation, STI）區。
在一些實施例中，基底102和鰭片104包括（1）矽，（2）化合物半導體，如砷化鎵（GaAs）、磷化鎵（GaP）、磷化銦（InP）、砷化銦（InAs）、及∕或銻化銦（InSb），（3）合金半導體包括矽鍺（SiGe）、磷化砷鎵（GaAsP）、砷化鋁銦（AlInAs）、砷化鋁鎵（AlGaAs）、砷化鎵銦（GaInAs）、磷化鎵銦（GaInP）、及∕或砷磷化鎵銦（GaInAsP），或（4）其組合。作為範例的目的，基底102和鰭片104將以結晶矽的情境描述。基於此處所揭露，可使用如上述的其他材料。這些其他材料都屬於本揭露的精神和範圍。
鰭式場效電晶體結構100，如第1圖所示，包括包覆鰭片104的頂面和側壁表面的閘極結構108，設置在閘極結構108的側壁表面上的間隔物114，和成長在鰭片104未被閘極結構108和間隔物114覆蓋的部分上的源極∕汲極磊晶結構116。可設置額外的閘極結構（未繪示於第1圖中）鄰近於閘極結構108的源極∕汲極磊晶結構116。
在第1圖中，合併來自鄰近鰭片104的源極∕汲極磊晶結構116成為單一磊晶結構。然而，這並非用以限制，成長在鰭片104的源極∕汲極磊晶結構116可維持不合併。在一些實施例中，合併一或多個源極∕汲極磊晶結構促進導電結構118的形成。在一些實施例中，在導電結構118和源極∕汲極磊晶結構116之間成長矽化物層120以減少接觸電阻。在一些實施例中，源極∕汲極磊晶結構116包括針對P型鰭式場效電晶體結構100的硼摻雜矽鍺磊晶層，以及針對N型鰭式場效電晶體結構100的碳摻雜矽（Si:C）或磷摻雜（Si:P）矽磊晶層。
根據一些實施例，每個閘極結構108包括多膜層，如閘極介電質108A、功函數層108B、和金屬填充物108C。閘極結構108也可包括為了簡化而沒有繪示於第1圖中的額外膜層。這些膜層可包括插入鰭片104和閘極介電質108A之間的介面介電層、設置於閘極介電質108A和功函數層108B之間的蓋層和阻障層、以及功函數層108B和金屬填充物108C之間的額外阻障層。
在一些實施例中，閘極介電質108A包括高介電常數（high-k）介電質，如鉿基氧化物；功函數層108B包括金屬層的堆疊，如氮化鈦、鈦鋁、鈦鋁碳等；而金屬填充物108C包括金屬和襯物，如鎢和氮化鈦。
在一些實施例中，藉由蓋層122覆蓋並藉由介電層124（在第1圖中以虛線代表）圍繞閘極結構108、間隔物結構114、和源極∕汲極磊晶結構116。在一些實施例中，間隔物結構114電性隔離閘極結構108與源極∕汲極磊晶結構116，而蓋層122進一步隔離矽化物層120和導電結構118與閘極結構108，如第1圖和第3圖所示，第3圖為橫跨第1圖切線AB的剖面示意圖。
在一些實施例中，可存在鰭式場效電晶體結構100的各種變化，這些變化都屬於本揭露的精神和範圍。舉例來說，鄰近的閘極結構108可藉由介電層124分隔開，而非藉由源極∕汲極磊晶結構116，如第11圖所示。在其他實施例中，蓋層可為可選的膜層。
在一些實施例中，可在兩個相鄰閘極結構108之間（藉由介電層124、間隔物結構114、和蓋層122分隔開）形成寄生電容。也可在閘極結構108和個別導電結構118或源極∕汲極磊晶結構116之間形成寄生電容。基於平行板電容公式，閘極結構108和鰭式場效電晶體結構100的其他導電部件之間的距離越短，寄生電容越高。
Figure 02_image001
， 其中C為寄生電容的電容值，k為電容板（例如電極）之間的絕緣體的介電常數，ε0 為自由空間的介電常數，A為電容板的面積，而d為電容板之間的距離。
在一些實施例中，閘極結構108相對於間隔物結構114凹入，以促進閘極蓋層126的形成，閘極蓋層126可在形成導電結構118的開口期間保護閘極結構108。在一些實施例中，閘極蓋層126包括氮化物層，如氮化矽。
在一些實施例中，第2圖為在第1圖所示的鰭式場效電晶體結構100的間隔物結構114中形成氣隙或空洞的方法200的流程圖。根據一些實施例，具有氣隙或空洞的間隔物結構114能減少有效介電常數，而獲得較低的寄生電容。可在方法200的各種操作之間進行其他製造操作，在此處僅為了清楚起見而省略。作為範例而非限制，方法200將參考第3～10圖詳述。
參考第2圖，方法200始於操作202和形成閘極間隔物結構的製程，其閘極間隔物結構具有插入兩個間隔物層之間的犧牲間隔物層。作為範例而非限制，在第1圖和第3圖中所示的間隔物結構114可為一堆疊，其堆疊包括犧牲間隔物層300夾在內間隔物層310和外間隔物層320之間。在一些實施例中，在方法200的後續操作中移除（例如蝕刻）犧牲間隔物層300。
作為範例而非限制，犧牲間隔物層300包括硼摻雜矽（Si:B）或硼摻雜矽鍺（SiGe:B）材料。在一些實施例中，內間隔物層310包括低介電常數（low-k）材料（例如具有低於約3.9的k值），如氮化矽氧碳（SiOCN）或氧碳化矽（SiOC）。作為範例而非限制，外間隔物層320包括氮化矽（Si3 N4 ，也被稱為SiN）。
在一些實施例中，可依下列形成間隔物結構114。一開始，依序地毯覆式沉積內間隔物層310、犧牲間隔物層300、和外間隔物層320，作為在犧牲閘極結構上的堆疊，其犧牲閘極結構並未繪示於第1圖中，因其將在金屬閘極替換製程期間以閘極結構108替換。後續地，以異向性（anisotropic）蝕刻製程蝕刻沉積後的堆疊，其製程從犧牲閘極結構的水平表面上（例如犧牲閘極結構的頂面）選擇性地移除沉積後的堆疊，以形成間隔物結構114。替代地，可先沉積內間隔物層310和犧牲間隔物層300，接著以異向性蝕刻製程移除部分犧牲間隔物層300，接著沉積外間隔物層320，再接著以異向性蝕刻製程移除部分外間隔物層320以形成間隔物結構114。之後的製造步驟將形成繪示於第3～5和7～10圖中的L形內間隔物層310。
在形成間隔物結構114之後，後續進行金屬閘極替換製程，以閘極結構108替換犧牲閘極結構。以濕蝕刻製程移除犧牲閘極結構。以硼摻雜犧牲間隔物層300可避免在金屬閘極替換製程期間移除犧牲間隔物層300。
如上所述，在形成閘極結構108的閘極介電質108A、功函數層108B、和金屬填充物108C之前形成間隔物結構114。在一些實施例中，沉積每個內、犧牲、和外間隔物層至具有約2nm和3nm之間的厚度。因此，每個間隔物結構114可具有介於約6nm和9nm之間的寬度114W。可能有較薄或較厚的間隔物層，這些間隔物層都屬於本揭露的精神和範圍。
參考第2圖，方法200持續於操作204和移除犧牲間隔物層300的製程，以形成內間隔物層310和外間隔物層320之間的開口。作為範例而非限制，以乾蝕刻製程移除內間隔物層310，其製程使用氫氣和氟的混合物，或對於犧牲間隔物層300具有高選擇性並對內間隔物層310和外間隔物層320具有低選擇性。所得的結構繪示於第4圖中。犧牲間隔物層300的移除留下在間隔物結構114中介於內間隔物層310和外間隔物層320之間的間隔物開口。在一些實施例中，間隔物開口400具有介於2nm和3nm之間的寬度，對應於被蝕刻的犧牲間隔物層300的厚度。在一些實施例中，L形內間隔物層310在移除犧牲間隔物層300的期間可保護鰭片104。舉例來說，若沒有保護鰭片104，則會被用於移除犧牲間隔物層300的乾蝕刻化學品部分蝕刻。
參考第2圖，方法200持續於操作206和在意欲不被蝕刻的表面上沉積聚合物材料的製程，如內間隔物層310、外間隔物層320、蓋層122、閘極蓋層126、和導電結構118的頂面。換句話說，聚合物材料的作為在後續蝕刻製程期間的蝕刻遮罩。作為範例而非限制，第5圖是根據操作206，繪示在沉積聚合物材料500之後的鰭式場效電晶體結構100。在一些實施例中，主要在鰭式場效電晶體結構100的水平表面上沉積聚合物材料500至具有介於約0.5nm和1nm之間的厚度。在一些實施例中，以聚合物材料的薄層（約在水平表面上聚合物材料的一半厚度）塗布於間隔物開口400的垂直側壁510的頂部。舉例來說，在間隔物開口400的垂直側壁510的頂部上的聚合物材料500可介於約0.25nm和0.5nm之間的厚度。
在一些實施例中，在帶狀束蝕刻機台600中沉積聚合物材料500，其機台的剖面示意圖繪示於第6圖中。作為範例而非限制，帶狀束蝕刻機台600可包括基底檯座（substrate stage）610，在聚合物材料的沉積製程期間，基底102（如第1圖所示）放置於基底檯座610上。在一些實施例中，將基底檯座610耦合至外部電源（未繪示於第6圖中），配置外部電源以施加電壓於基底102。帶狀束蝕刻機台600也可包括設置於基底102上的電漿腔體620。帶狀束蝕刻機台600可包括未繪示於第6圖中的額外組件。作為範例而非限制，未繪示於第6圖中的組件包括氣體導管、外部電源、磁性元件、機械和電性組件、電腦、感測器、幫浦等。
在一些實施例中，在電漿腔體620中導入氟碳氣體（如甲烷（methane, CH4 ）、六氟-2-丁炔（hexafluoro-2-butyne, C4 F6 ）、八氟環丁烷（octafluorocyclobutane, C4 F8 ）、氟甲烷（fluoromethane, CH3 F））、四氯矽烷（tetrachlorosilane, SiCl4 ），或二氧化硫（sulfur dioxide, SO2 ）稀釋於氬氣、氮氣、氦氣、或氫氣中並與氧氣混合，以產生電漿630。透過孔徑（例如離子光學抽提）抽提來自電漿630的離子以形成雙離子束640，其後續加速往基底102。在一些實施例中，雙離子束640包括一對離子束，各由基底102頂面垂直的方向傾斜一角度θ，如第6圖所示。在一些實施例中，角度θ（也被稱為「射束角度θ」或「傾斜角度θ」）係介於約1.3°和9°之間。根據一些實施例，雙離子束640與基底102的露出表面互動，以形成聚合物材料500（例如Cx Hy ）繪示於第5圖中。在一些實施例中，抽提電壓（例如由電漿630抽提離子和形成雙離子束640所需的電壓施加於基底102）等於或小於約0.5kV（例如介於約0kV和0.5kV之間）。根據一些實施例，抽提電壓為脈衝直流（pulsed direct current, PDC）電壓（例如具有矩形脈衝）。
作為範例而非限制，在聚合物的沉積製程期間，電漿腔體620的孔徑和基底102的頂面之間的垂直距離D設定在約12nm和16nm之間。由於電漿腔體620可為靜置的，可配置基底檯座610在X-Y平面上移動以達到聚合物材料500均勻沉積在基底102的整體表面。在一些實施例中，可使用垂直距離D以調整在基底102表面上雙離子束640的射束分隔S。舉例來說，較短垂直距離（例如7nm）在基底102表面上產生較小的射束分隔S。相反的，較大垂直距離（例如20nm）在基底102表面上產生較大的射束分隔S。
在一些實施例中，抽提電壓、射束角度θ、和垂直距離D為用來調整聚合物材料沉積各面向的一些參數，如在垂直側壁510頂部上的聚合物材料500的沉積率和厚度。在一些實施例中，在氣體混合物中納入氧氣係用作額外參數以控制聚合物材料500的沉積率。舉例來說，氧氣的加入可減少聚合物材料500的沉積率。再者，可選擇不同類型的氟碳氣體（如甲烷、六氟-2-丁炔、八氟環丁烷、氟甲烷）、四氯矽烷、或二氧化硫以產生針對一給定蝕刻化學品具有不同蝕刻率的聚合物材料。
在一些實施例中，在操作206中在聚合物材料500的沉積之後，間隔物開口400的頂寬度520等於或大於約1.5nm（例如≧1.5nm）。若頂寬度520小於約1.5nm（例如＜1.5nm），針對間隔物開口400形成的錐形輪廓可變得有挑戰性，且可能需要額外製程。
參考第2圖，方法200進行至操作208和蝕刻間隔物開口400頂部的製程以形成錐形輪廓。在一些實施例中，操作208包括蝕刻內間隔物層310和外間隔物層320露出的側壁部分以形成漏斗形頂開口。在一些實施例中，在第6圖所示的帶狀束蝕刻機台600中進行蝕刻步驟。舉例來說，在沉積聚合物材料500之後，導入蝕刻化學品於電漿腔體620中以產生電漿，如電漿630，而離子可由此抽提以形成離子束，如雙離子束640，其選擇性地蝕刻內間隔物層310和外間隔物層320未被聚合物材料500覆蓋的部分。在一些實施例中，蝕刻化學品（不同於用於聚合物材料500的沉積化學品）包括四氟甲烷（tetrafluoromethane, CF4 ）或三氟甲烷（fluoroform, CHF3 ）稀釋於氬氣、氮氣、氦氣、或氫氣，並與氧氣混合。在一些實施例中，基於聚合物材料500（例如蝕刻遮罩）和要被蝕刻的材料（例如內間隔物層310和外間隔物層320的露出部分）之間所欲的選擇比，選擇蝕刻化學品和聚合物材料的沉積化學品。
在一些實施例中，配置上述蝕刻化學品，以在比內間隔物層310和外間隔物層320的露出部分較低的蝕刻率蝕刻聚合物材料500。因此，在操作208期間，在鰭式場效電晶體結構100的水平表面上的聚合物材料500的厚度減少，而在間隔物開口400的垂直側壁510頂部上的聚合物材料500則被消耗（例如被蝕刻）。
在一些實施例中，在操作208的蝕刻製程期間，射束角度θ設定介於約5°和30°之間，而垂直距離D設定介於約6nm和12nm之間。射束角度θ結合垂直距離D可針對間隔物開口400產生不同蝕刻輪廓。舉例來說，寬射束角度θ（例如約30°）結合短垂直距離D（例如約7nm）相較於窄射束角度θ（例如約1.3°）結合大垂直距離D（例如約16nm）提供了較淺且更類似錐形的蝕刻輪廓。在一些實施例中，雙離子束640的指向性將離子傳送至內間隔物層310和外間隔物層320要被蝕刻的所欲區域。舉例來說，可配置射束角度θ和垂直距離D，使得雙離子束640朝向間隔物開口400的垂直側壁510的頂部。在蝕刻期間，雙離子束640一開始移除覆蓋間隔物開口400的垂直側壁510頂部的聚合物材料500，然後開始蝕刻內間隔物層310和外間隔物層320露出於雙離子束640直接路徑的部分。具有錐形輪廓700（也在此處被稱為「漏斗700」）的所得的結構繪示於第7圖中。在一些實施例中，針對內間隔物層310和外間隔物層320的上述蝕刻製程被稱為「拉回（pull back）」。
在一些實施例中，在操作208的蝕刻製程的結果是，錐形輪廓或漏斗700發展出側壁角度ξ介於70°和80°之間的範圍，由第7圖所示的水平軸x量測。再者，錐形輪廓或漏斗700具有介於約4.5nm和5.5nm之間的頂開口710，和介於約5nm和9nm之間的深度720。
在一些實施例中，可依需求重複操作206和208以達到在間隔物結構114中的間隔物開口400的所欲輪廓。舉例來說，參考第2圖，接續操作208為檢查站點操作210。根據操作210，若所欲的輪廓未達到，可根據操作206沉積新的聚合物材料500膜層，接著根據操作208進行另一道蝕刻製程。另一方面，若所欲的輪廓已達到，則方法200進行至操作212。在一些實施例中，當重複沉積操作206和蝕刻操作208時，可重新調整沉積操作206和蝕刻操作208的個別製程參數以達到所欲的錐形輪廓。舉例來說，當重複操作206和操作208時，可相應地調整在帶狀束蝕刻機台600中的射束角度θ、垂直距離D、和抽提電壓。
參考第2圖，方法200持續於操作212和在間隔物開口400蝕刻後的頂部上沉積密封材料的製程，以塞住間隔物開口400並形成介於兩個間隔物層（例如內間隔物層310和外間隔物層320）之間的氣隙。舉例來說，參考第8圖，在鰭式場效電晶體結構100上沉積密封材料800並填入漏斗700。在一些實施例中，密封材料800包括氧碳化矽在介於約300°C和400°C的溫度下，以電漿促進化學氣相沉積（plasma-enhanced chemical vapor deposition, PECVD）或電漿輔助原子層沉積（plasma-assisted atomic layer deposition, PEALD）做沉積。在一些實施例中，密封材料800包括介於約25原子百分比（atomic percentage, at. %）和40原子百分比之間的矽、介於約25原子百分比和50原子百分比之間的氧、和介於約4原子百分比和40原子百分比之間的碳。再者，密封材料800具有小於約4（例如3.6）的介電常數以減少寄生電容的衝擊。在一些實施例中，剛沉積的密封材料800進行約400°C的氮氣或氫氣中的後沉積退火以使其緻密化。可配置密封材料800的沉積率，使得反應氣體沒有足夠時間到達間隔物開口400的深處並在間隔物開口400的底部形成密封材料800。在一些實施例中，在漏斗700底部的密封材料800沉積形成縮頸點，其避免反應物深入間隔物開口400中在間隔物開口400底部形成密封材料800。
在一些實施例中，沉積密封材料800至大於約11nm的厚度以充足地填入漏斗700。在一些實施例中，沉積密封材料800至間隔物開口400內的深度820，其介於7nm和11nm之間的範圍。所得的氣隙或空洞具有介於約40nm和70nm之間的高度810，和寬度實質上等於被移除的犧牲間隔物層300的厚度（例如介於約2nm和3nm之間）。
在一些實施例中，具有小於約5nm的深度720和小於約4.5nm的頂開口710的錐形輪廓或漏斗700可導致有限的密封材料800形成於漏斗700內。於是，後續化學機械平坦化（chemical mechanical planarization, CMP）製程的漿料可能進入間隔物開口400並侵蝕間隔物結構114，這是不希望發生的。另一方面，具有大於5.5nm的頂開口710的錐形輪廓或漏斗700可導致氣隙體積減少，由於密封材料800可被沉積更深入間隔物開口400。在漏斗700非常寬且非常深（例如寬度大於約5.5nm和深度大於約9nm）的情況下，密封材料800可能填入整個間隔物開口400，這是不希望發生的，因為間隔物結構114無法具有低介電常數為1的氣隙或空洞的優勢。
在一些實施例中，在密封材料800的沉積和熱處理之後，化學機械平坦化製程移除在間隔物開口400外的多餘密封材料800，如第9圖所示。在一些實施例中，前述的化學機械平坦化製程減少深度820至深度900，從介於約7nm和11nm之間至約4nm。這是因為化學機械平坦化製程也移除部分閘極蓋層126、部分間隔物結構114、和部分導電結構118。在前述的化學機械平坦化製程之後，鰭式場效電晶體結構100的頂面大抵為平坦的。在一些實施例中，在前述的化學機械平坦化製程之後，密封材料800具有沿著x軸介於約3nm和5.5nm之間的頂面寬度800w和介於約1nm和4nm之間的深度900。舉例來說，密封材料800的深寬比介於約0.2和1.3的範圍之間，其中深寬比的定義為深度900和頂面寬度800w的比例。在一些實施例中，密封材料800佔據約間隔物開口400的5％和9％之間，剩餘的間隔物開口400則被氣隙或空洞佔據。在一些實施例中，剩餘密封材料800具有漏斗形，其頂面比底面更寬。然而，這並非用以限制，取決於密封材料800在前述化學機械平坦化製程期間被移除的量，密封材料800的頂面寬度800w可實質上等於間隔物開口400的寬度（例如約3nm）。
參考第10圖，根據一些實施例，可在閘極結構108和導電結構118上形成額外的導電結構1004和1006。作為範例而非限制，可如下列形成導電結構1004和1006：在鰭式場效電晶體結構100上毯覆式沉積金屬氧化物蝕刻停止層（etch stop layer, ESL）1000（例如氧化鋁）和介電層1002（例如矽基氧化物），如第10圖所示。之後，蝕刻製程在介電層1002和金屬氧化物蝕刻停止層1000中形成開口，其大抵對準閘極結構108和導電結構118。在一些實施例中，使用不同蝕刻化學品從金屬氧化物蝕刻停止層1000蝕刻介電層1002。根據一些實施例，配置用來蝕刻金屬氧化物蝕刻停止層1000的蝕刻化學品以對於密封材料800（例如氧碳化矽）、內間隔物層310（例如氮化矽）、外間隔物層320（例如氧碳化矽）、和蓋層122（例如氮化矽）具有較低的選擇比。當用於導電結構1004和1006的開口意外地與閘極結構108和導電結構118錯位時，如錯位虛線1004’和1006’所示，這樣是有利的。有這樣的錯位，對於密封材料800（例如氧碳化矽）、內間隔物層310（例如氮化矽）、外間隔物層320（例如氧碳化矽）、和蓋層122（例如氮化矽）的較低蝕刻率可防止蝕刻化學品實質上移除這些結構的部分。一旦形成開口，導電材料填入開口以形成導電結構1004和1006。在一些實施例中，導電結構1004和1006，如導電結構118，包括金屬填充物，如鎢、鈷、或其他合適導電材料。在一些實施例中，導電結構1004和1006，如導電結構118，包括襯層或阻障層，如在金屬填充物前沉積的氮化鈦，或鈦和氮化鈦的堆疊。
在一些實施例中，方法200並非限制於第1圖中所示的鰭式場效電晶體結構100，而是可應用於其他類型的電晶體或對寄生電容敏感的鰭式場效電晶體結構100的其他變化。舉例來說，方法200可套用於平面電晶體和全繞式閘極（gate-all-around, GAA）電晶體。再者，方法200可套用至晶粒中的選擇性電晶體，例如方法200可套用至在晶粒高密度區域中的電晶體。
本揭露是針對具有氣隙的閘極間隔物結構的形成方法，以微型化閘極間隔物結構的有效介電常數，並減少電晶體閘極結構和鄰近源極∕汲極接觸件之間的寄生電容。在一些實施例中，氣隙的形成可藉由形成具有犧牲間隔物設置於兩個間隔物層之間的閘極間隔物堆疊，選擇性地從閘極間隔物堆疊移除犧牲間隔物以形成介於剩餘間隔物層之間的開口，蝕刻開口頂部以形成錐形輪廓，以及後續以密封材料塞住蝕刻後的開口頂部以在鄰近於閘極結構的閘極間隔物結構內形成永久的氣隙。在一些實施例中，形成錐形輪廓包括使用帶狀束蝕刻機台以進行一或多次的聚合物材料沉積和間隔物層蝕刻的循環。配置沉積後的聚合物材料以用作在蝕刻步驟期間的蝕刻遮罩，以保護不意欲被蝕刻的結構元件。在一些實施例中，可能有多重聚合物沉積和蝕刻循環，直到達成所欲的開口輪廓。在一些實施例中，可選擇要沉積的聚合物材料和蝕刻化學品以達到閘極間隔物堆疊的聚合物材料和間隔物層之間的最佳蝕刻選擇比。聚合物材料的沉積和蝕刻需要不同化學品和離子束特性，如射束角度和離子能量。在一些實施例中，在聚合物材料沉積期間的射束角度係介於約1.3°和9°之間，而在蝕刻製程期間的射束角度係介於約5°和30°之間。在一些實施例中，密封材料為低介電常數介電質，其包括氧碳化矽，具有介於約25原子百分比和40原子百分比之間的矽、介於約25原子百分比和50原子百分比之間的氧、和介於約4原子百分比和40原子百分比之間的碳。
在一些實施例中，一種半導體結構，包括：於鰭片上的閘極結構，於閘極結構上的蓋層，鄰近於閘極結構的導電結構，以及插入閘極結構和導電結構之間的間隔物結構。間隔物結構更包括與閘極結構和蓋層的側壁表面接觸的第一間隔物層，藉由間隙與第一間隔物層分隔開的第二間隔物層，以及設置於第一間隔物層和第二間隔物層之間的間隙上的密封層。
在一些實施例中，一種半導體結構的形成方法，包括：於基底上形成閘極結構，和於閘極結構的側壁表面上形成間隔物堆疊，其中間隔物堆疊包括與閘極結構接觸的內間隔物層，於內間隔物層上的犧牲間隔物層，以及於犧牲間隔物層上的外間隔物層。半導體結構的形成方法更包括移除犧牲間隔物層以形成介於內間隔物層和外間隔物層之間的開口，於內間隔物層和外間隔物層的頂面上沉積聚合物材料，蝕刻內間隔物層和外間隔物層的頂側壁表面以形成錐形頂部，以及沉積密封材料以塞住錐形頂部並形成介於內間隔物層和外間隔物層之間的間隙。
在一些實施例中，一種半導體結構包括於基底上的閘極結構，與閘極結構分隔開的導電結構，以及插入閘極結構和導電結構之間的間隔物結構。間隔物結構額外地包括具有第一內側壁表面的第一間隔物，具有相對於第一間隔物的第一內側壁表面的第二內側壁表面的第二間隔物，設置在間隔物結構介於第一內側壁表面和第二內側壁表面之間的頂部上的密封材料，以及形成介於第一間隔物和第二間隔物之間，並被第一內側壁表面、第二內側壁表面、和密封材料圍繞的間隙。
應理解的是，實施方式的部分，而非發明摘要的部分，是企圖用以解讀請求項。發明摘要的部分可闡述本揭露的一或多個實施例，但並非發明人所思及本揭露所有可能的實施例。因此，實施例並非企圖以任何方式限制附屬請求項。
以上概述數個實施例之部件，以便在所屬技術領域中具有通常知識者可以更加理解本揭露的觀點。在所屬技術領域中具有通常知識者應理解，他們能輕易地以本揭露為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露之精神和範圍下，做各式各樣的改變、取代和替換。
100:鰭式場效電晶體結構 102:基底 104:（半導體）鰭片 106:隔離區 108:閘極結構 108A:閘極介電質 108B:功函數層 108C:金屬填充物 114:間隔物結構 114W:寬度 116:源極∕汲極磊晶結構 118:導電結構 120:矽化物層 122:蓋層 124:介電層 126:閘極蓋層 200:方法 202,204,206,208,210,212:操作 300:犧牲間隔物層 310:內間隔物層 320:外間隔物層 400:間隔物開口 500:聚合物材料 510:垂直側壁 520:頂寬度 600:帶狀束蝕刻機台 610:基底檯座 620:電漿腔體 630:電漿 640:雙離子束 700:錐形輪廓（漏斗） 710:頂開口 720:深度 800:密封材料 800w:頂面寬度 810:高度 820:深度 900:深度 1000:金屬氧化物蝕刻停止層 1002:介電層 1004,1006:導電結構 1004’,1006’:錯位虛線 AB:切線 D:垂直距離 S:射束分隔 θ:射束角度 ξ:側壁角度
以下將配合所附圖式詳述本揭露實施例的面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種部件的尺寸，以清楚地表現出本發明實施例的特徵。 第1圖是根據一些實施例，鰭式場效電晶體（fin field-effect transistor, finFET）結構的等角（isometric）示意圖。 第2圖是根據一些實施例，具有氣隙或空洞在其中的閘極間隔物結構的形成方法的流程圖。 第3～10圖是根據一些實施例，在具有氣隙或空洞在其中的閘極間隔物結構的形成期間的鰭式場效電晶體結構的剖面示意圖。 第11圖是根據一些實施例，鰭式場效電晶體結構的等角示意圖。
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100:鰭式場效電晶體結構
104:(半導體)鰭片
108:閘極結構
114:間隔物結構
116:源極/汲極磊晶結構
118:導電結構
122:蓋層
126:閘極蓋層
400:間隔物開口
700:錐形輪廓(漏斗)
800:密封材料
810:高度
820:深度

Claims (20)

  1. 一種半導體結構，包括： 一閘極結構，於一鰭片上； 一蓋層（capping layer），於該閘極結構上； 一導電結構，鄰近於該閘極結構；以及 一間隔物結構（spacer structure），插入該閘極結構和該導電結構之間，其中該間隔物結構包括： 一第一間隔物層，與該閘極結構和該蓋層的多個側壁表面（sidewall surface）接觸； 一第二間隔物層，藉由一間隙（gap）與該第一間隔物層分隔開；以及 一密封層（seal layer），設置於該第一間隔物層和該第二間隔物層之間的該間隙上。
  2. 如請求項1之半導體結構，其中該間隙被該第一間隔物層和該第二間隔物層的多個側壁表面、該第一間隔物層的底部、和該密封層圍繞。
  3. 如請求項1之半導體結構，其中該密封層填入該第一間隔物層和該第二間隔物層的該些側壁表面的頂部。
  4. 如請求項1之半導體結構，其中該蓋層、該間隔物結構、和該導電結構的頂面大抵共面。
  5. 如請求項1之半導體結構，其中該間隙具有介於約2nm和3nm之間的寬度，以及介於約40nm和70nm之間的高度。
  6. 如請求項1之半導體結構，其中該間隔物結構的寬度約介於6nm和9nm之間。
  7. 如請求項1之半導體結構，其中該第一間隔物層包括氮化矽氧碳（silicon oxy-carbon nitride），該第二間隔物層包括氮化矽（silicon nitride），而該密封層包括氧碳化矽（silicon oxycarbide）。
  8. 如請求項1之半導體結構，更包括： 一金屬氧化物蝕刻停止層，設置在該蓋層、該間隔物結構、和該導電結構上； 一介電層，於該金屬氧化物蝕刻停止層上；以及 一額外導電結構，於該閘極結構上，其中該額外導電結構跨過該蓋層、該金屬氧化物蝕刻停止層、和該介電層。
  9. 一種半導體結構的形成方法，包括： 形成一閘極結構於一基底上； 形成一間隔物堆疊於該閘極結構的多個側壁表面上，其中該間隔物堆疊包括： 一內間隔物層，與該閘極結構接觸； 一犧牲間隔物層，於該內間隔物層上；以及 一外間隔物層，於該犧牲間隔物層上； 移除該犧牲間隔物層以形成介於該內間隔物層和該外間隔物層之間的一開口； 沉積一聚合物材料於該內間隔物層和該外間隔物層的頂面上； 蝕刻該內間隔物層和該外間隔物層的多個頂側壁表面以形成一錐形頂部；以及 沉積一密封材料以塞住該錐形頂部並形成介於該內間隔物層和該外間隔物層之間的一間隙。
  10. 如請求項9之半導體結構的形成方法，其中移除該犧牲間隔物層包括使用一乾蝕刻製程以蝕刻該犧牲間隔物層。
  11. 如請求項9之半導體結構的形成方法，其中該犧牲間隔物層包括硼摻雜矽（boron-doped silicon）或硼摻雜矽鍺（boron-doped silicon germanium）。
  12. 如請求項9之半導體結構的形成方法，其中沉積該密封材料包括沉積氧碳化矽，其包括介於約25原子百分比（atomic percentage, at. %）和40原子百分比之間的矽、介於約25原子百分比和50原子百分比之間的氧、和介於約4原子百分比和40原子百分比之間的碳。
  13. 如請求項9之半導體結構的形成方法，更包括在沉積該密封材料之後，將該密封材料在氮氣和氫氣中約400°C下進行一後沉積退火（post deposition anneal）。
  14. 如請求項9之半導體結構的形成方法，其中蝕刻該內間隔物層和該外間隔物層的該些頂側壁表面包括形成具有介於約70°和80°之間側壁角度的該錐形頂部。
  15. 如請求項9之半導體結構的形成方法，其中沉積該聚合物材料包括形成大於或等於約1.5nm的一間隔於該開口的頂部上。
  16. 如請求項9之半導體結構的形成方法，其中沉積該聚合物材料包括沉積該聚合物材料介於約0.5nm和1nm之間的厚度。
  17. 一種半導體結構，包括： 一閘極結構，於一基底上； 一導電結構，與該閘極結構分隔開；以及 一間隔物結構，插入該閘極結構和該導電結構之間，其中該間隔物結構包括： 一第一間隔物，具有多個第一內側壁表面； 一第二間隔物，具有相對於該第一間隔物的該些第一內側壁表面的多個第二內側壁表面； 一密封材料，設置在該間隔物結構介於該些第一內側壁表面和該些第二內側壁表面之間的一頂部上；以及 一間隙，形成介於該第一間隔物和該第二間隔物之間，並被該些第一內側壁表面、該些第二內側壁表面、和該密封材料圍繞。
  18. 如請求項17之半導體結構，其中該間隙具有一寬度，該寬度等於第一間隔物和第二間隔物的該些第一內側壁表面和該些第二內側壁表面的距離。
  19. 如請求項17之半導體結構，其中該間隙具有一高度，該高度大抵等於該第一間隔物的底部和該第二間隔物的底部之間的距離。
  20. 如請求項17之半導體結構，其中以該密封材料填入的該間隔物結構的該頂部具有一錐形。
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