CN112582401A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN112582401A
CN112582401A CN202010288169.7A CN202010288169A CN112582401A CN 112582401 A CN112582401 A CN 112582401A CN 202010288169 A CN202010288169 A CN 202010288169A CN 112582401 A CN112582401 A CN 112582401A
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杨建勋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述了用于形成具有气隙的栅极间隔件结构以减小晶体管的栅极结构和源极/漏极接触件之间的寄生电容的方法。在一些实施例中，该方法包括在衬底上形成栅极结构，并且在栅极结构的侧壁表面上形成间隔件堆叠件—其中，间隔件堆叠件包括与栅极结构接触的内部间隔件层、位于内部间隔件层上的牺牲间隔件层和位于牺牲间隔件层上的外部间隔件层。该方法还包括去除牺牲间隔件层以在内部间隔件层和外部间隔件层之间形成开口，在内部和外部间隔件层的顶面上沉积聚合物材料，蚀刻内部和外部间隔件层的顶部侧壁表面以形成锥形顶部，以及沉积密封材料。本发明的实施例还涉及半导体结构及其形成方法。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体结构及其形成方法。
背景技术
在半导体芯片中，可以在由介电层分隔开的紧邻形成的导电结构的位置处形成寄生电容。导电结构可以是例如线、通孔、接触件、栅极结构或外延层。一种避免密集封装芯片布局中的寄生电容的方法是采用介电常数降低的绝缘材料。
发明内容
本发明的一些实施例提供了一种半导体结构，包括：栅极结构，位于鳍上；覆盖层，位于所述栅极结构上；导电结构，与所述栅极结构相邻；以及间隔件结构，介于所述栅极结构和所述导电结构之间，其中，所述间隔件结构包括：第一间隔件层，与所述栅极结构和所述覆盖层的侧壁表面接触；第二间隔件层，通过间隙与所述第一间隔件层间隔开；以及密封层，设置在所述第一间隔件层和所述第二间隔件层之间的所述间隙之上。
本发明的另一些实施例提供了一种形成半导体结构的方法，包括：在衬底上形成栅极结构；在所述栅极结构的侧壁表面上形成间隔件堆叠件，其中，所述间隔件堆叠件包括：内部间隔件层，与所述栅极结构接触；牺牲间隔件层，位于所述内部间隔件层上；以及外部间隔件层，位于所述牺牲间隔件层上；去除所述牺牲间隔件层以在所述内部间隔件层和所述外部间隔件层之间形成开口；在所述内部间隔件层和所述外部间隔件层的顶面上沉积聚合物材料；蚀刻所述内部间隔件层和所述外部间隔件层的顶部侧壁表面以形成锥形顶部；以及沉积密封材料以堵塞所述锥形顶部，并且在所述内部间隔件层和所述外部间隔件层之间形成间隙。
本发明的又一些实施例提供了一种半导体结构，包括：栅极结构，位于衬底上；导电结构，与所述栅极结构间隔开；以及间隔件结构，介于所述栅极结构和所述导电结构之间，其中，所述间隔件结构包括：第一间隔件，具有第一内部侧壁表面；第二间隔件，具有与所述第一间隔件的所述第一内部侧壁表面相对的第二内部侧壁表面；密封材料，设置在所述第一内部侧壁表面和所述第二内部侧壁表面之间的所述间隔件结构的顶部上；以及间隙，形成在所述第一间隔件和所述第二间隔件之间且由所述第一内部侧壁表面和所述第二内部侧壁表面以及所述密封材料围绕。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的鳍式场效应晶体管(finFET)结构的等轴视图。
图2是根据一些实施例的用于形成其中具有气隙或空隙的栅极间隔件结构的方法的流程图。
图3至图10是根据一些实施例的在其中具有气隙或空隙的栅极间隔件结构的形成期间的鳍式场效应晶体管(finFET)结构的截面图。
图11是根据一些实施例的鳍式场效应晶体管(finFET)结构的等轴视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
如本文使用的术语“标称”是指在产品或工艺的设计阶段设置的，用于组件或工艺操作的特性或参数的期望值或目标值，以及高于和/或低于期望值的值的范围。值的范围通常是由于制造工艺或公差中的轻微变化而引起的。
在一些实施例中，术语“约”和“基本”可以指示给定数量的值，该值在目标值的5％内(例如，目标值的±1％、±2％、±3％、±4％和±5％)变化。
如本文使用的术语“垂直”是指标称垂直于衬底的表面。
半导体芯片可以在每单位面积上具有较大的晶体管密度，以增加芯片功能并且降低制造成本。然而，由于导电结构(诸如晶体管栅极、接触件、通孔和线)彼此间隔更近，具有较大晶体管密度的半导体芯片可能遭受寄生电容的影响。例如，在芯片的前段制程(FEOL)区域中，在晶体管栅极结构和相邻的源极/漏极(S/D)接触件之间、晶体管栅极结构和S/D端子之间、S/D接触件之间以及晶体管栅极之间可能会形成不期望的寄生电容。
为了解决寄生电容问题，本发明针对用于形成具有气隙的栅极间隔件结构的方法，该气隙使栅极间隔件结构的有效介电常数最小化，从而减小了晶体管栅极结构和相邻S/D接触件之间的寄生电容。在一些实施例中，通过形成栅极间隔件堆叠件来形成气隙，其中牺牲间隔件设置在栅极间隔件堆叠件的两个间隔件层之间，从栅极间隔件堆叠件中选择性地去除牺牲间隔件，以在其余间隔件层之间形成开口，蚀刻开口的顶部以形成锥形轮廓，并且随后用密封材料堵塞开口的蚀刻顶部，以在栅极间隔件结构内形成永久的气隙。在一些实施例中，形成锥形轮廓包括使用带状束蚀刻机实施聚合物材料沉积和间隔件层蚀刻的一个或多个循环。沉积的聚合物材料被配置为在蚀刻操作期间用作蚀刻掩模，以保护不旨在被蚀刻的结构元件。在一些实施例中，可以进行多个聚合物沉积和蚀刻循环，直至获得所需的开口轮廓。在一些实施例中，可以选择沉积的聚合物材料和蚀刻化学物质，以在聚合物材料和栅极间隔件堆叠件的间隔件层之间实现最佳的蚀刻选择性。
根据一些实施例，图1是在鳍104上的衬底102上方构建的鳍式场效应晶体管(finFET)结构100的局部等轴视图。图1示出了finFET结构100的选择性部分，并且为简单起见可能未示出其它部分。这些其它部分可以包括诸如附加层、附加晶体管、掺杂区域、隔离区域等的附加结构元件。此外，图1中的finFET结构100示出为用于示例性目的，并且可能未按比例绘制。
如图1所示，FinFET结构100形成在半导体鳍104(也称为“鳍104”)上。鳍104垂直于衬底102的顶面形成，并且经由隔离区域106彼此电隔离。鳍104可以通过任何合适的方法图案化。例如，可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺图案化鳍104。双重图案化或多重图案化工艺可以结合光刻和自对准工艺，从而允许创建例如间距小于使用单个直接光刻工艺所获得的间距的图案。例如，在实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后可以使用剩余的间隔件来图案化鳍104。在一些实施例中，隔离区域106填充有诸如氧化硅或基于硅的氧化物的介电材料，并且在鳍104之间形成浅沟槽隔离(STI)区域。
在一些实施例中，衬底102和鳍104包括(i)硅，(ii)化合物半导体，诸如砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)和/或锑化铟(InSb)，(iii)合金半导体，包括硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)和/或磷砷化镓铟(GaInAsP)，或(iv)它们的组合。出于示例性目的，将在晶体硅的上下文中描述衬底102和鳍104。基于本文公开的内容，可以使用如上所述的其它材料。这些其它材料在本发明的精神和范围内。
如图1所示，FinFET结构100包括：栅极结构108，其包裹鳍104的顶面和侧壁表面；间隔件结构114，其设置在栅极结构108的侧壁表面上；以及源极/漏极(“S/D”)外延结构116，其生长在鳍104的未由栅极结构108和间隔件结构114覆盖的凹进部分上。未在图1中示出的其它栅极结构可以与栅极结构108的S/D外延结构116相邻设置。
在图1中，来自相邻鳍104的S/D外延结构116合并为单个外延结构。然而，这不是限制性的，并且生长在鳍104上的S/D外延结构116可以保持未合并。在一些实施例中，合并一个或多个S/D外延结构有助于导电结构118的形成。在一些实施例中，在导电结构118和S/D外延结构116之间生长硅化物层120以减小接触电阻。在一些实施例中，S/D外延结构116包括用于p型finFET结构100的硼掺杂的硅锗(SiGe)外延层、用于n型finFET结构100的碳掺杂的硅(Si:C)或磷掺杂的硅(S:P)外延层。
根据一些实施例，每个栅极结构108包括多层，诸如栅极电介质108A、功函层108B和金属填充物108C。为了简化，栅极结构108还可以包括图1中未示出的附加层。这些层可以包括介于鳍104和栅极电介质108A之间的界面介电层、设置在栅极电介质108A和功函层108B之间的覆盖层和阻挡层以及位于功函层108B和金属填充物108C之间的附加阻挡层。
在一些实施例中，栅极电介质108A包括高k电介质，诸如铪基氧化物；功函层108B包括金属层的堆叠件，诸如氮化钛、钛铝、钛铝碳等；以及金属填充物108C包括金属和衬垫，诸如钨和氮化钛。
在一些实施例中，栅极结构108、间隔件结构114和S/D外延结构116由覆盖层122覆盖并且由图1中的虚线表示的介电层124围绕。在一些实施例中，间隔件结构114将栅极结构108与S/D外延结构116电隔离，同时覆盖层122进一步将硅化物层120和导电结构118与栅极结构108隔离，如图1和图3所示，图3是横跨切线AB的图1的截面图。
在一些实施例中，finFET结构100的变化可以存在并且在本发明的精神和范围内。例如，与S/D外延结构116相反，相邻的栅极结构108可以通过介电层124间隔开，如图11所示。在其它实施例中，覆盖层122可以是可选层。
在一些实施例中，可以在由介电层124、间隔件结构114和覆盖层122分隔开的在两个相邻的栅极结构之间形成寄生电容。寄生电容也可以形成在栅极结构108和它相应的导电结构108或S/D外延结构116之间。基于平行板电容公式，在栅极结构108和finFET结构100的其它导电元件之间的距离越短，寄生电容越高。
Figure BDA0002449324970000061
其中C是寄生电容器的电容，k是电容器板(例如，电极)之间的绝缘体的介电常数，εo是自由空间的介电常数，A是板的面积，并且d是板之间的距离。
在一些实施例中，栅极结构108相对于间隔件结构114凹进，以利于形成栅极覆盖层126，该覆盖层在形成用于导电结构118的开口期间保护栅极结构108。在一些实施例中，栅极覆盖层126包括氮化物层，诸如氮化硅。
在一些实施例中，图2是用于在图1所示的finFET结构100的间隔件结构114中形成气隙或空隙的方法200的流程图。根据一些实施例，具有气隙或空隙的间隔件结构具有降低的有效介电常数，并且可以产生较低的寄生电容。可以在方法200的各个操作之间实施其它制造操作，并且仅为了清楚起见而省略。作为实例而非限制，将参考图3至图10描述方法200。
参考图2，方法200开始于操作202和形成栅极间隔件结构的工艺，其中牺牲间隔件层介于两个间隔件层之间。作为实例而非限制，图1和图3所示的间隔件结构114可以是包括夹在“内部”间隔件层310和“外部”间隔件层320之间的牺牲性间隔件层300的堆叠件。在一些实施例中，在方法200的后续操作中去除(例如，蚀刻)牺牲间隔件层300。
作为实例而非限制，牺牲间隔件层300包括硼掺杂的硅(Si:B)或硼掺杂的硅锗(SiGe:B)材料。在一些实施例中，内部间隔件层310包括低k材料(例如，k值小于约3.9)，诸如碳氮氧化硅(SiOCN)或碳氧化硅(SiOC)。作为实例而非限制，外部间隔件层320包括氮化硅(Si3N4；也称为“SiN”)。
在一些实施例中，间隔件结构114可以如下形成。最初，将内部间隔件层310、牺牲间隔件层300和外部间隔件层320依次在牺牲栅极结构上方毯式沉积为堆叠件，它们在图1中未示出，因为它们将在“金属栅极替换工艺”期间由栅极结构108替换。随后，利用各向异性蚀刻工艺蚀刻沉积的堆叠件，该蚀刻工艺从牺牲栅极结构的水平表面(诸如牺牲栅极结构的顶面)选择性地去除沉积的堆叠件，以形成间隔件结构114。可选地，可以首先沉积内部间隔件层310和牺牲间隔件层300，随后进行去除部分牺牲间隔件层300的各向异性蚀刻工艺，随后进行外部间隔件层320的沉积，以及随后进行去除部分外部间隔件层320以形成间隔件结构114的各向异性蚀刻工艺。之后的制造顺序将形成图3至图5和图7至图10所示的“L形”内部间隔件层310。
在形成间隔件结构114之后，随后实施金属栅极替换工艺，以用栅极结构108替换每个牺牲栅极结构。用湿蚀刻工艺去除牺牲栅极结构。用硼掺杂牺牲间隔件层300可防止在金属栅极替换工艺期间去除牺牲间隔件层300。
如上所述，在形成栅极结构108的栅极电介质108A、功函层108B和金属填充物108C之前，形成间隔件结构114。在一些实施例中，内部间隔件层、牺牲间隔件层和外部间隔件层的每个沉积为具有介于约2nm和约3nm之间的厚度。因此，每个间隔件结构114可以具有介于约6nm和约9nm之间的宽度114W。较薄或较厚的间隔件层是可能的，并且在本发明的精神和范围内。
参考图2，方法200继续操作204以及去除牺牲间隔件层300以在内部间隔件层310和外部间隔件层320之间形成开口的工艺。作为实例而非限制，使用氢和氟的混合物或气体化学物质通过干蚀刻工艺去除内部间隔件层310，该混合物或气体化学物质对牺牲间隔件层300具有高选择性，而对内部间隔件层310和外部间隔件层320具有低选择性。产生的结构如图4所示。牺牲间隔件层300的去除在内部间隔件层310和外部间隔件层320之间的间隔件结构114中留下间隔件开口。在一些实施例中，间隔件开口400的宽度在2nm和3nm之间的范围内，该宽度对应于蚀刻的牺牲间隔件层300的厚度。在一些实施例中，L形内部间隔件层310在去除牺牲间隔件层300期间保护鳍104。例如，如果鳍104没有被保护，则它将通过用于去除牺牲间隔件层300的干蚀刻化学物质而被部分地蚀刻。
参考图2，方法200继续操作206，以及在不旨在被蚀刻的表面上沉积聚合物材料的工艺，不旨在被蚀刻的表面诸如内部间隔件层310、外部间隔件层320、覆盖层122、栅极覆盖层126和导电结构118的顶面。换句话说，聚合物材料在随后的蚀刻工艺期间用作蚀刻掩模。作为实例而非限制，图5示出了根据操作206在沉积聚合物材料500之后的finFET结构100。在一些实施例中，聚合物材料500主要沉积在finFET结构100的水平表面上约0.5nm和约1nm之间的厚度。在一些实施例中，间隔件开口400的垂直侧壁510的顶部涂覆有聚合物材料的薄层，该聚合物材料的薄层约是水平表面上的一半。例如，间隔件开口400的垂直侧壁510的顶部上的聚合物材料500的厚度可以在约0.25nm和约0.5nm之间。
在一些实施例中，聚合物材料500沉积在带状束蚀刻机600中，该带状束蚀刻机600的截面在图6中示出。作为实例而非限制，带状束蚀刻机600可以包括衬底台610，在聚合物材料沉积工艺期间，衬底102(例如，图1所示)抵靠在衬底台610上。在一些实施例中，衬底台610耦接至配置为向衬底102施加电压的外部电源(图6中未示出)。带状束蚀刻机600还可包括设置在衬底102上方的等离子体室620。带状束蚀刻机600可以包括图6中未示出的附加组件。作为实例而非限制，图6中未示出的组件包括气体管线、外部电源、磁性元件、机械和电组件、计算机、传感器、泵等。
在一些实施例中，将稀释在氩气(Ar)、氮气(N2)、氦气(He)或氢气(H2)中并且与氧(O2)混合的碳氟化合物气体(例如，甲烷(CH4)、六氟-2-丁炔(C4F6)、八氟环丁烷(C4F8)或氟甲烷(CH3F))、四氯硅烷(SiCl4)或二氧化硫(SO2)引入至等离子体室620中以产生等离子体630。通过孔(例如，离子提取光学器件)提取来自等离子体630的离子，以形成双离子束640，随后将它朝衬底102加速。在一些实施例中，双离子束640包括一对离子束，每个离子束从垂直于衬底102的顶面的方向倾斜角度θ，如图6所示。在一些实施例中，角度θ(也称为“光束角θ”或“倾斜角θ”)在约1.3°和约9°之间。根据一些实施例，双离子束640与衬底102的暴露表面相互作用以形成图5所示的聚合物材料500(例如，CxHy)。在一些实施例中，提取电压(例如，从等离子体630提取离子并且形成双离子束640所需的施加至衬底的电压)等于或小于约0.5kV(例如，在约0kV和约0.5kV之间)。根据一些实施例，提取电压是脉冲直流(PDC)电压(例如，由矩形脉冲组成)。
作为实例而非限制，在聚合物沉积工艺期间，在等离子体室620的孔和衬底102的顶面之间的垂直距离D设置在约12nm和约16nm之间。由于等离子体室620可以是固定的，因此衬底台610可以配置为在x-y平面中移动，以实现聚合物材料500在衬底102的整个表面上的均匀沉积。在一些实施例中，垂直距离D可用于调制衬底102的表面上的双离子束640的光束间距S。例如，短的垂直距离(例如，7nm)在衬底102的表面上产生较小的光束间距S。相反地，大的垂直距离(例如，20nm)在衬底102的表面上产生较大的光束间距S。
在一些实施例中，提取电压、光束角θ和垂直距离D是用于调制聚合物材料沉积的各个方面(诸如垂直侧壁510的顶部上的聚合物材料500的沉积速率和厚度)的一些参数。在一些实施例中，结合至气体混合物中的O2用作控制聚合物材料500的沉积速率的附加参数。例如，添加O2可以降低聚合物材料500的沉积速率。此外，对于给定的蚀刻化学物质，可以选择不同类型的碳氟化合物气体(例如，CH4、C4F6、C4F8或CH3F)、SiCl4或SO2来产生具有不同蚀刻速率的聚合物材料。
在一些实施例中，在操作206中沉积聚合物材料500之后，间隔件开口400的顶部宽度520等于或大于约1.5nm(例如，≥1.5nm)。如果顶部宽度520小于约1.5nm(例如，＜1.5nm)，则用于间隔件开口400的锥形轮廓的形成可能变得具有挑战性，并且可能需要额外的工艺。
参考图2，方法200进入操作208以及蚀刻间隔件开口400的顶部以形成锥形轮廓的工艺。在一些实施例中，操作208包括蚀刻内部间隔件层310和外部间隔件层320的暴露的侧壁部分，以形成漏斗形的顶部开口。在一些实施例中，蚀刻操作在图6所示的带状束蚀刻机600中实施。例如，在沉积聚合物材料500之后，将蚀刻化学物质引入至等离子室620以产生等离子体，类似于等离子体630，可以从中提取离子以形成离子束，类似于双离子束640，该离子束选择性地蚀刻内部间隔件层310和外部间隔件层320的未由聚合物材料500覆盖的部分。在一些实施例中，蚀刻化学物质—与用于聚合物材料500的沉积化学物质不同—包括稀释在Ar、N2、He或H2中并且与O2混合的四氟甲烷(CF4)或氟仿(CHF3)。在一些实施例中，在基于聚合物材料500(例如，蚀刻掩模)和待蚀刻的材料(例如，内部间隔件层310和外部间隔件层320的暴露部分)之间的期望选择性来选择蚀刻化学物质和聚合物材料沉积化学物质。
在一些实施例中，以上蚀刻化学物质被配置为以比内部间隔件层310和外部间隔件层320的暴露部分更低的蚀刻速率蚀刻聚合物材料500。因此，在操作208期间，减小了finFET结构100的水平表面上的聚合物材料500的厚度，并且消耗(例如，蚀刻)间隔件开口400的垂直侧壁510的顶部上的聚合物材料500。
在一些实施例中，在操作208的蚀刻工艺期间，光束角θ设置在约5°和约30°之间，而垂直距离D设置在约6nm和约12nm之间。光束角θ与垂直距离D结合可以为间隔件开口400产生不同的蚀刻轮廓。例如，与窄光束角θ(例如，约1.3°)与约16nm的较大垂直距离D结合相比，宽光束角θ(例如，约30°)与较短垂直距离D(例如，约7nm)结合提供了较浅且更锥形的蚀刻轮廓。在一些实施例中，双离子束640的方向性将离子传递至内部间隔件层310和外部间隔件层320的待蚀刻的期望区域。例如，光束角θ和距离D可以配置为使得双离子束640被引导至间隔件开口400的垂直侧壁510的顶部。在蚀刻期间，双离子束640首先去除覆盖间隔件开口400的垂直侧壁510的顶部的聚合物材料500，并且然后开始蚀刻暴露于双离子束640的直接路径的内部间隔件层310和外部间隔件层320的部分。在图7中示出了具有锥形轮廓700(在本文中也称为“漏斗700”)的所得结构。在一些实施例中，用于内部间隔件层310和外部间隔件层320的上述蚀刻工艺称为“回拉”。
在一些实施例中，由于操作208中的蚀刻工艺，锥形轮廓或漏斗700产生从水平轴x测得的在约70°和80°之间的侧壁角ξ，如图7所示。此外，锥形轮廓或漏斗700具有在约4.5nm和约5.5nm之间的顶部开口710以及在约5nm和约9nm之间的深度720。
在一些实施例中，可以根据需要重复操作206和208，以实现用于间隔件结构114中的间隔件开口400的期望轮廓。例如，参考图2，在操作208之后是检查点操作210。根据操作210，如果尚未实现期望的轮廓，则可以根据操作208沉积新的聚合物材料层500，然后根据操作208进行另一蚀刻工艺。另一方面，如果已经实现期望的轮廓，则方法200进入操作212。在一些实施例中，当重复时，可以分别重新调整用于沉积和蚀刻操作206和208的工艺参数，以实现期望的锥形轮廓。例如，当重复操作206和208时，可以相应地调整蚀刻机600中的光束角θ、距离D和提取电压。
参考图2，方法200继续操作212，以及在间隔件开口400的蚀刻顶部上沉积密封材料以堵塞间隔件开口400并且在两个间隔件层(例如，内部间隔件层310和外部间隔件层320)之间形成气隙的工艺。例如，参考图8，密封材料800沉积在finFET结构100上方并且填充漏斗700。在一些实施例中，密封材料800包括在约300℃和约400℃之间的温度下通过等离子体增强化学汽相沉积(PECVD)或等离子体辅助原子层沉积(PEALD)而沉积的碳氧化硅(SiOC)。在一些实施例中，密封材料800包括在约25原子％(at.％)和约40at.％之间的硅、约25at.％和约50at.％之间的氧以及约4at.％和约40at.％之间的碳。此外，密封材料800的介电常数小于约4(例如，3.6)，以减小寄生电容的影响。在一些实施例中，为了致密的目的，在N2或H2中在约400℃下对所沉积的密封材料800进行沉积后退火。密封材料800的沉积速率可以被配置为使得反应物气体没有足够的时间到达间隔件开口400的深处并且在间隔件开口400的底部处形成密封材料800。在一些实施例中，沉积在漏斗底部处的密封材料形成颈缩点，以防止反应物进一步进入间隔件开口400中而在间隔件开口400底部处形成密封材料800。
在一些实施例中，密封材料800沉积为大于约11nm的厚度以充分填充漏斗700。在一些实施例中，密封材料800沉积至间隔件开口400内的深度820在约7nm和11nm之间的范围内。所得的气隙或空隙的高度810在约40nm和约70nm之间，并且宽度基本等于去除的牺牲间隔件层300的厚度(例如，在约2nm和约3nm之间)。
在一些实施例中，深度小于约5nm的锥形轮廓或漏斗700和顶部开口710小于约4.5nm可以导致漏斗700内部形成有限的密封材料。因此，来自随后的化学机械平坦化(CMP)工艺的浆料可能进入间隔件开口400并且侵蚀间隔件结构114，这是不期望的。另一方面，具有宽于5.5nm的顶部开口710的锥形轮廓或漏斗700可能导致气隙体积减小，因为密封材料800可以更深地沉积至间隔件开口400中。在漏斗700非常宽和深的情况下(例如，宽于约5.5nm并且深于约9nm)，密封材料800可以填充整个间隔件开口400，这是不期望的，因为间隔件结构114不能利用具有低介电常数为1的气隙或空隙形成的优势。
在一些实施例中，在密封材料800的沉积和热处理之后，如图9所示，CMP工艺去除了间隔件开口400外部的过量密封材料800。在一些实施例中，上述CMP工艺将从在约7nm和约11nm之间的深度820减小至约4nm之间的深度900。这是因为CMP工艺还去除了部分栅极覆盖层126、部分间隔件结构114和部分导电结构118。在上述CMP工艺之后，finFET结构100的顶面是基本平坦的。在一些实施例中，在上述CMP工艺之后，密封材料800沿x轴的顶面宽度800w在约3nm和约5.5nm之间，并且深度900在约1nm和约4nm之间。例如，密封材料800的高宽比在约0.2和约1.3之间；其中高宽比定义为深度900与表面宽度800w之比。在一些实施例中，密封材料800占据约5％和约9％之间的间隔件开口400；开口400的其余部分由气隙或空隙占据。在一些实施例中，剩余的密封材料800具有漏斗形状，其顶面比其底面宽。然而，这不是限制性的，并且取决于在上述CMP工艺期间去除的密封材料800的量，密封材料800的宽度800w可以基本等于间隔件开口400的宽度(例如，约3nm)。
参考图10，根据一些实施例，可以在栅极结构108和导电结构118上形成附加的导电结构1004和1006。作为实例而非限制，可以如下形成导电结构1004和1006：可以在finFET结构100上方毯式沉积金属氧化物蚀刻停止层(ESL)1000(例如，氧化铝)和介电层1002(例如，基于硅的氧化物)，如图10所示。随后，蚀刻工艺在介电层1002和金属氧化物ESL1000中形成与栅极结构108和导电结构118基本对准的开口。在一些实施例中，使用不同的蚀刻化学物质从金属氧化物ESL 1000蚀刻介电层1002。根据一些实施例，用于蚀刻金属氧化物ESL1000的蚀刻化学物质被配置为对密封材料800(例如，SiOC)、内部间隔件层310(例如，SiN)、外部间隔件层320(例如，SiOC)和覆盖层122(例如，SiN)具有较低的选择性。当用于导电结构1004和1006的开口相对于栅极结构108和导电结构118不期望地未对准时，这将是有益的，如未对准的虚线1004'和1006'所示。由于这种未对准，密封材料800(例如，SiOC)、内部间隔件层310(例如，SiN)、外部间隔件层320(例如，SiOC)和覆盖层122(例如，SiN)的较低蚀刻速率可以防止蚀刻化学物质基本去除这些结构的部分。一旦形成开口，导电材料填充开口以形成导电结构1004和1006。在一些实施例中，导电结构1004和1006(类似于导电结构118)包括金属填充物，诸如钨、钴或其它合适的导电材料。在一些实施例中，导电结构1004和1006(类似于导电结构118)包括在金属填充物之前沉积的衬垫或阻挡层，诸如氮化钛，或钛和氮化钛的堆叠件。
在一些实施例中，方法200不限于图1所示的finFET结构100，并且可以应用于对寄生电容敏感的其它类型的晶体管或finFET结构100的变型。例如，方法200可以应用于平面晶体管和全环栅晶体管。此外，方法200可以应用于芯片中的选择晶体管，例如，可以将方法应用于芯片的高密度区域中的晶体管。
本发明针对用于形成具有气隙的栅极间隔件结构以最小化栅极间隔件结构的有效介电常数并且减小晶体管栅极结构和相邻的S/D接触件之间的寄生电容的方法。在一些实施例中，通过形成栅极间隔件堆叠件而形成气隙，其中牺牲间隔件设置在栅极间隔件堆叠件的两个间隔件层之间，从栅极间隔件堆叠件中选择性地去除牺牲间隔件，以在其余间隔件层之间形成开口，蚀刻开口的顶部以形成锥形轮廓，并且随后用密封材料堵塞蚀刻的开口顶部，以在与栅极结构相邻的栅极间隔件结构内形成永久气隙。在一些实施例中，形成锥形轮廓包括使用带状束蚀刻机来实施聚合物材料沉积和间隔件层蚀刻的一个或多个循环。沉积的聚合物材料被配置为在蚀刻操作期间用作蚀刻掩模，以保护不旨在蚀刻的结构元件。在一些实施例中，多个聚合物沉积和蚀刻循环是可能的，直至实现期望的开口轮廓。在一些实施例中，沉积的聚合物材料和蚀刻化学物质可以选择为在聚合物材料和栅极间隔件堆叠件的间隔件层之间实现最佳的蚀刻选择性。聚合物材料沉积和蚀刻需要不同的化学性质和离子束特性，诸如光束角和离子能量。在一些实施例中，聚合物材料沉积期间的光束角在约1.3°和约9°之间，而蚀刻工艺期间的光束角在5°和约30°之间。在一些实施例中，密封材料是低k电介质，其包括含有约25原子％(at.％)和约40at.％之间的硅、约25at.％和约50at.％之间的氧以及约4at.％和约40at.％之间的碳的SiOC。
在一些实施例中，结构包括位于鳍上的栅极结构、位于栅极结构上的覆盖层、与栅极结构相邻的导电结构以及介于栅极结构和导电结构之间的间隔件结构。间隔件结构还包括与栅极结构和覆盖层的侧壁表面接触的第一间隔件层、通过间隙与第一间隔件层间隔开的第二间隔件层以及设置在第一间隔件层和第二间隔件层之间的间隙之上的密封层。在一些实施例中，所述间隙由所述第一间隔件层和所述第二间隔件层的侧壁表面、所述第一间隔件层的底部以及所述密封层围绕。在一些实施例中，所述密封层填充所述第一间隔件层和所述第二间隔件层的侧壁表面的顶部。在一些实施例中，所述覆盖层、所述间隔件结构和所述导电结构的顶面基本共面。在一些实施例中，所述间隙的宽度在约2nm和约3nm之间，并且高度在约40nm和约70nm之间。在一些实施例中，所述间隔件结构的宽度在约6nm和约9nm之间。在一些实施例中，所述第一间隔件层包括碳氮氧化硅，所述第二间隔件层包括氮化硅，并且所述密封层包括碳氧化硅。在一些实施例中，半导体结构还包括：金属氧化物蚀刻停止层，设置在所述覆盖层、所述间隔件结构和所述导电结构上；介电层，位于所述金属氧化物蚀刻停止层上；以及另一导电结构，位于所述栅极结构上，其中，所述另一导电结构横穿所述覆盖层、所述金属氧化物蚀刻停止层和所述介电层。
在一些实施例中，方法包括在衬底上形成栅极结构，并且在该栅极结构的侧壁表面上形成间隔件堆叠件—其中间隔件堆叠件包括与栅极结构接触的内部间隔件层、位于内部间隔件层上的牺牲间隔件层以及位于牺牲间隔件层上的外部间隔件层。该方法还包括去除牺牲间隔件层以在内部和外部间隔件层之间形成开口，在内部和外部间隔件层的顶面上沉积聚合物材料，蚀刻内部和外部间隔件层的顶部侧壁表面以形成锥形顶部，并且沉积密封材料以堵塞锥形顶部并且在内部和外部间隔件层之间形成间隙。在一些实施例中，去除所述牺牲间隔件层包括使用干蚀刻工艺来蚀刻所述牺牲间隔件层。在一些实施例中，所述牺牲间隔件层包括硼掺杂的硅或硼掺杂的硅锗。在一些实施例中，沉积所述密封材料包括：沉积包含约25原子％(at.％)和约40at.％之间的硅、约25at.％和约50at.％之间的氧以及约4at.％和约40at.％之间的碳的碳氧化硅。在一些实施例中，该方法还包括，在沉积所述密封材料之后，在约400℃下在氮气或氢气中对所述密封材料进行沉积后退火。在一些实施例中，蚀刻所述内部间隔件层和所述外部间隔件层的所述顶部侧壁表面包括形成具有介于约70°和80°之间的侧壁角的所述锥形顶部。在一些实施例中，沉积所述聚合物材料包括在所述开口的顶部上形成等于或大于约1.5nm的间隔。在一些实施例中，沉积所述聚合物材料包括沉积所述聚合物材料的厚度在约0.5nm和约1nm之间。
在一些实施例中，结构包括位于衬底上的栅极结构、与栅极结构间隔开的导电结构以及介于栅极结构和导电结构之间的间隔件结构。间隔件结构还包括具有第一内部侧壁表面的第一间隔件、具有与第一间隔件的第一内部侧壁表面相对的第二内部侧壁表面的第二间隔件、设置在第一和第二内部侧壁表面之间的间隔件结构的顶部上的密封材料以及形成在第一和第二间隔件之间且由第一和第二内部侧壁表面以及密封材料围绕的间隙。在一些实施例中，所述间隙的宽度等于相应的第一间隔件和第二间隔件的所述第一内部侧壁表面和所述第二内部侧壁表面之间的距离。在一些实施例中，所述间隙的高度基本等于所述第一间隔件的底部和所述密封材料的底部之间的距离。在一些实施例中，填充有所述密封材料的所述间隔件结构的顶部具有锥形形状。
应当理解，具体实施方式部分，而不是摘要部分，旨在用于解释权利要求。如发明人所预期的，公开的摘要部分可以阐述本发明的一个或多个但不是所有可能的实施例，并且因此，不旨在以任何方式限制所附权利要求。
上面公开概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
栅极结构，位于鳍上；
覆盖层，位于所述栅极结构上；
导电结构，与所述栅极结构相邻；以及
间隔件结构，介于所述栅极结构和所述导电结构之间，其中，所述间隔件结构包括：
第一间隔件层，与所述栅极结构和所述覆盖层的侧壁表面接触；
第二间隔件层，通过间隙与所述第一间隔件层间隔开；以及
密封层，设置在所述第一间隔件层和所述第二间隔件层之间的所述间隙之上。
2.根据权利要求1所述的半导体结构，其中，所述间隙由所述第一间隔件层和所述第二间隔件层的侧壁表面、所述第一间隔件层的底部以及所述密封层围绕。
3.根据权利要求1所述的半导体结构，其中，所述密封层填充所述第一间隔件层和所述第二间隔件层的侧壁表面的顶部。
4.根据权利要求1所述的半导体结构，其中，所述覆盖层、所述间隔件结构和所述导电结构的顶面基本共面。
5.根据权利要求1所述的半导体结构，其中，所述间隙的宽度在约2nm和约3nm之间，并且高度在约40nm和约70nm之间。
6.根据权利要求1所述的半导体结构，其中，所述间隔件结构的宽度在约6nm和约9nm之间。
7.根据权利要求1所述的半导体结构，其中，所述第一间隔件层包括碳氮氧化硅，所述第二间隔件层包括氮化硅，并且所述密封层包括碳氧化硅。
8.根据权利要求1所述的半导体结构，还包括：
金属氧化物蚀刻停止层，设置在所述覆盖层、所述间隔件结构和所述导电结构上；
介电层，位于所述金属氧化物蚀刻停止层上；以及
另一导电结构，位于所述栅极结构上，其中，所述另一导电结构横穿所述覆盖层、所述金属氧化物蚀刻停止层和所述介电层。
9.一种形成半导体结构的方法，包括：
在衬底上形成栅极结构；
在所述栅极结构的侧壁表面上形成间隔件堆叠件，其中，所述间隔件堆叠件包括：
内部间隔件层，与所述栅极结构接触；
牺牲间隔件层，位于所述内部间隔件层上；以及
外部间隔件层，位于所述牺牲间隔件层上；
去除所述牺牲间隔件层以在所述内部间隔件层和所述外部间隔件层之间形成开口；
在所述内部间隔件层和所述外部间隔件层的顶面上沉积聚合物材料；
蚀刻所述内部间隔件层和所述外部间隔件层的顶部侧壁表面以形成锥形顶部；以及
沉积密封材料以堵塞所述锥形顶部，并且在所述内部间隔件层和所述外部间隔件层之间形成间隙。
10.一种半导体结构，包括：
栅极结构，位于衬底上；
导电结构，与所述栅极结构间隔开；以及
间隔件结构，介于所述栅极结构和所述导电结构之间，其中，所述间隔件结构包括：
第一间隔件，具有第一内部侧壁表面；
第二间隔件，具有与所述第一间隔件的所述第一内部侧壁表面相对的第二内部侧壁表面；
密封材料，设置在所述第一内部侧壁表面和所述第二内部侧壁表面之间的所述间隔件结构的顶部上；以及
间隙，形成在所述第一间隔件和所述第二间隔件之间且由所述第一内部侧壁表面和所述第二内部侧壁表面以及所述密封材料围绕。
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US11923366B2 (en) 2021-05-05 2024-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor isolation regions and methods of forming the same
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150228754A1 (en) * 2014-02-12 2015-08-13 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN105280608A (zh) * 2014-07-25 2016-01-27 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
CN105529297A (zh) * 2014-10-17 2016-04-27 朗姆研究公司 用于改进的fin器件性能的气隙间隔件集成
CN106549059A (zh) * 2015-09-18 2017-03-29 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN108122744A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN108231664A (zh) * 2016-12-14 2018-06-29 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US10283600B2 (en) * 2017-08-01 2019-05-07 Samsung Electronics Co., Ltd. Integrated circuit device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180988B1 (en) * 1997-12-04 2001-01-30 Texas Instruments-Acer Incorporated Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
US8637930B2 (en) * 2011-10-13 2014-01-28 International Business Machines Company FinFET parasitic capacitance reduction using air gap
KR101887414B1 (ko) * 2012-03-20 2018-08-10 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9536982B1 (en) * 2015-11-03 2017-01-03 International Business Machines Corporation Etch stop for airgap protection
US9608065B1 (en) * 2016-06-03 2017-03-28 International Business Machines Corporation Air gap spacer for metal gates
KR20180093798A (ko) * 2017-02-13 2018-08-22 램 리써치 코포레이션 에어 갭들을 생성하는 방법
DE102017126049B4 (de) * 2017-08-29 2024-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zur herstellung einer halbleitervorrichtung
US10411114B2 (en) * 2017-12-21 2019-09-10 International Business Machines Corporation Air gap spacer with wrap-around etch stop layer under gate spacer
US10367076B1 (en) * 2018-01-31 2019-07-30 International Business Machines Corporation Air gap spacer with controlled air gap height

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150228754A1 (en) * 2014-02-12 2015-08-13 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN105280608A (zh) * 2014-07-25 2016-01-27 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
CN105529297A (zh) * 2014-10-17 2016-04-27 朗姆研究公司 用于改进的fin器件性能的气隙间隔件集成
CN106549059A (zh) * 2015-09-18 2017-03-29 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN108122744A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN108231664A (zh) * 2016-12-14 2018-06-29 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US10283600B2 (en) * 2017-08-01 2019-05-07 Samsung Electronics Co., Ltd. Integrated circuit device

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