TW202109686A - 調節器電路封裝技術 - Google Patents

調節器電路封裝技術 Download PDF

Info

Publication number
TW202109686A
TW202109686A TW108140978A TW108140978A TW202109686A TW 202109686 A TW202109686 A TW 202109686A TW 108140978 A TW108140978 A TW 108140978A TW 108140978 A TW108140978 A TW 108140978A TW 202109686 A TW202109686 A TW 202109686A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
package
passive devices
exposed area
circuit die
Prior art date
Application number
TW108140978A
Other languages
English (en)
Inventor
雷納德 雪泰果
札福 卡路
約翰恩得候 加德納
Original Assignee
愛爾蘭商安洛格裝置國際無限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 愛爾蘭商安洛格裝置國際無限公司 filed Critical 愛爾蘭商安洛格裝置國際無限公司
Publication of TW202109686A publication Critical patent/TW202109686A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/346—Passive non-dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本發明之技術係用於控制積體切換器封裝產生之磁場，及用於降低來自積體切換器封裝之電磁干擾。

Description

調節器電路封裝技術
本發明係關於切換式調控器封裝之散熱及電磁干擾圍阻。
切換式調節器，如其名稱，係以高頻之切換產生所輸之輸出電壓。於此高頻率產生之小電流迴路可產生顯著之磁場。若該切換係於積體電路（IC）內形成，則電流迴路可發生於整體積體電路內或積體電路之部分內部及部分外部。若迴路因電力開關接通或同步整流器開關接通而導通起始瞬變電流，則相對較高之di/dt造成高磁場，其可引起電磁干擾（EMI）。
本發明之技術係用於控制積體切換器封裝產生之磁場，及用於降低來自積體切換器封裝之電磁干擾。於其一例示，積體電路（IC）封裝可包括支撐至少二傳導層之介電基板、位於該介電基板上之至少二被動裝置、位於該介電基板上之積體電路（IC）晶粒，及密封材，其中密封材覆蓋至少二被動裝置之整體，且界定積體電路晶粒之外露區域。於某些例示，外露區域之至少一部分係可電性耦合至一電路，該電路係經積體電路晶粒界定。於某些例示，經至少二被動裝置之位置界定之配置係沿至少一軸實質對稱，且至少二被動裝置中，由介電基板提供至積體電路晶粒之電性相互連結係沿該至少一軸實質對稱。
此概述係用以提供本發明申請案主體之概要。其非用以提供本發明唯一或徹底之解釋。詳細說明係用以提供有關本發明申請案更進一步之資訊。
於典型之切換式調節器，成對開關（高側開關及低側開關）可選擇性執行以將電壓供給耦合至輸出端，或選擇性地將輸出端耦合至接地面。於某些例示，電感器如降壓調控器可經耦合至輸出端以作為輸出電路之一部分。於某些例示，控制器可經連接至高側開關及低側開關中各開關之閘極。若控制器係為脈寬調控控制器，則各開關之工作循環係可經控制以提供經調節之電壓或經調節之電流。於某些例示，工作循環可經控制以響應於回饋電壓與參考電壓之間之比較，回饋電壓係為調節器輸出電壓之表示。於某些例示，其一開關係可為電源開關，且另一係可為同步整流器，其可作為低壓差二極體。一般而言，不會同時執行成對開關以避免短路。
調節器係可為任意類型（如，降壓、升壓、返馳式等），且成對開關連接至電感器之特定連結係取決於調節器之類型。本發明可使用任意類型之切換式調節器，且於某些例示中係透過標準降壓調節器切換組態描述本發明之概念。
於某些調節器，習用之旁路電容器可經連接於電壓供應及接地面之間。旁路電容器通常可經使用於習用之切換器電路。當成對開關切換於閉路及接通之間時，旁路電容器可平穩地瞬變。舉例而言，當調節器控制器接通高側開關以對電感器充電時，其係以浪湧電流對寄生電容充電。浪湧電流係可源自經充電之旁路電容器而非直接由電壓供應提供。源自旁路電容器之浪湧電流有助於減輕因浪湧電流引起之供應電壓衰減，且有助於平穩切換瞬變。旁路電容器可形成電流迴路之一部分，電流迴路可包括成對開關、及調節器之供應端、接地端與輸出端。成對開關之寄生電容亦可形成電流迴路之一部分。
如前述且作為其一例示，控制器每次於高側開關切換時，可於其切換頻率下產生極快且強之脈衝電流（具有大電流變化率［di/dt］）。此脈衝或熱電流迴路可產生電磁干擾（electromagnetic interference, EMI），其可干擾或使鄰近之電路失真。應理解，其他產生磁場及電磁干擾之高能脈衝可於成對開關之每一瞬變產生。磁場可向各方向發散。
近期之研究進展已提供經大幅降低總磁場之切換式調節器技術，其中磁場係與快速改變之切換電流有關。該技術將習用之單一電流迴路分為複數電流迴路，其中複數電流迴路經連接至相反之磁場以彼此抵銷，藉此，相較於習用之設計，形成極低之總磁場及電磁干擾。此降低電磁干擾之技術係適用於切換模式電源供應之平面及三維（3D）切換電路。平面組態包括積體電路及印刷電路板。三維組態包括堆疊（垂直向）迴路組件、堆疊積體電路元件及堆疊印刷電路板。然而，於裝置電路板上整合該等技術係可與對裝置或其功能重要之其他配置技術爭用。
本發明之發明人認識到之封裝技術係用以提供電磁干擾靜默或至少電磁干擾寂靜之切換器封裝。圖1A圖示本發明切換器控制封裝100之示意圖。圖1B圖示圖1A切換器控制封裝之簡化電路圖120。切換器控制封裝100可包括基板101、控制器積體電路（IC）102、一對被動組件如切換電容器103及104、第一供應輸入端106、第二供應輸入端107，及輸出切換端（SW）108。應理解，於本發明之範圍內，切換器控制封裝100可包括其他組件如自舉電容器109。於某些例示，基板101係可為複數層層壓基板。於某些例示，基板可支援兩金屬或傳導層。於某些例示，控制器積體電路係可為倒裝晶片積體電路。於某些例示，控制器積體電路可包括複數功率電晶體110、111、112及113以選擇性耦合第一及第二供應端至輸出端。於某些例示，控制器積體電路102可包括厚基板，藉此，當安裝於封裝基板時，控制器積體電路之高度係高於切換電容器之高度。於某些例示，控制器積體電路102之較高高度可使密封材116完整覆蓋封裝之所有組件，除了控制器積體電路之上表面117。於現有之封裝技術，控制器積體電路之外露表面可增加控制器積體電路及整合至控制器積體電路之功率電晶體之散熱能力。
於某些例示，控制器積體電路之外露表面可承載散熱裝置以進一步增加散熱能力。於某些例示，控制器積體電路之厚基板可使介電密封材經應用於封裝之板材，各封裝接著自板材經切割或分割。密封材之應用可降低切換器封裝之成本。於某些例示，密封材之應用亦可包括去除程式如研磨或打磨程式以露出控制器積體電路之表面。
於某些例示，經密封封裝之板材可經進一步處理，加上與控制器積體電路之外露表面機械性及電性連接之遮蔽以形成整體，其形成切換器封裝上表面之至少一部分。於某些例示，遮蔽係可為傳導性，且可覆蓋控制器積體電路晶粒（die）及切換器封裝之電流迴路途徑130或互相連結。此覆蓋可提供散熱裝置以協助切換器封裝之散熱，亦可協助控制與切換器封裝高di/dt切換率相關之磁場。控制與電流迴路途徑130有關之磁場可降低切換器封裝產生之電磁干擾。將傳導性遮蔽應用於切換器封裝之板材後，各切換器封裝係可自板材經切割或分割。相較於將傳導性遮蔽應用於單一部分，同時處理大量之封裝係較為經濟。
於某些例示，傳導性遮蔽可包括導電性或導熱性材料之一或多個層體。於其一例示，傳導性遮蔽係包括於不銹鋼層之間之銅層。於某些例示，傳導性遮蔽係可透過濺鍍、黏合、化學氣相沉積等方式經應用。於某些例示，濺鍍可製造極薄之傳導性遮蔽，如大約數微米之層體。
圖2A圖示切換器控制封裝其一例示之剖面圖。切換器控制封裝可包括介電基板、被動裝置、一或多個積體電路晶粒，及密封材，該密封材覆蓋被動組件及一或多個積體電路晶粒之大部分，但使至少一積體電路之至少一表面經露出。於某些例示，該表面係可為基板之相反側。於某些例示，介電基板可包括複數層有機基板。於某些例示，介電基板包括或支持至少二傳導層。於某些例示，介電基板可包括用於一或多個積體電路晶粒之安裝墊，如至多50微米之微凸塊間距（micro-bump pitch）。於某些例示，積體電路晶粒上微凸塊118之陣列可用於積體電路之散熱，且提供積體電路及其他封裝組件之互相電連結，或切換連接之封裝。
於某些例示，一或多個積體電路晶粒可包括功率電晶體，其與被動裝置一起運作。於其一例示，被動裝置係可為電容器，且，於功率電晶體過渡狀態，其可經上述高di/dt事件時降低電磁干擾之方式配置。於某些例示，積體電路晶粒包括功率電晶體及用以控制功率電晶體之控制邏輯。於某些例示，功率電晶體係可位於積體電路晶粒，其獨立於包括控制邏輯之積體電路晶粒。此一例示可具有切換器控制封裝，其包括基於鎵之功率電晶體或基於其他半導體之晶片或裝置，而非基於矽之功率電晶體。於此例示，功率電晶體積體電路可具有厚基板基體，且包括控制邏輯之積體電路可選擇性包括厚基板基體。至少一積體電路晶粒之外露區域可用於散熱。於某些例示，散熱裝置可經耦合至外露區域以協助散熱。於某些例示，透過一或多個積體電路晶粒之外露表面散熱可空出晶粒相反側用於散熱之空間。舉例而言，於晶粒底面空出之空間可經用於更多之相互連結。
於某些例示，切換器控制封裝可包括可選之傳導性遮蔽119。於某些例示，傳導性遮蔽可協助散熱，且可僅覆蓋一或多個積體電路晶粒之外露區域。於某些例示，傳導性遮蔽延伸自晶粒之外露區域。舉例而言，傳導性遮蔽延伸超過熱電流迴路途徑及切換器控制封裝之相關電容器，其可顯著地控制切換器控制封裝產生之電磁干擾。圖2B圖示傳導性遮蔽119之其一例示，其可經放置於密封材116及切換器封裝積體電路之外露區域之上。於某些例示，傳導性遮蔽可包括材料之一或多個層體。於某些例示，傳導性遮蔽可包括傳導性金屬120，如銅。於某些例示，傳導性金屬層120係可透過傳導性障壁材料121如不鏽鋼、鈦、氮化鈦等，化學性絕緣於晶粒之外露表面。於某些例示，傳導性遮蔽可包括第二障蔽材料122以將傳導層與切換器封裝外圍之外界環境隔離。於某些例示，遮蔽可包括傳導層及絕緣層之組合。絕緣層可包括但不限於氮化鋁或鋁。於某些例示，傳導性遮蔽係可透過濺鍍、黏合、化學氣相沉積等方式經應用。於某些例示，濺鍍可製造極薄之傳導性遮蔽，如大約數微米之層體。
圖3A圖示切換器封裝300之板材350之其一例示，其等可出現於製造程式中。如圖所示，切換器封裝300之板材350可包括基板301、經設置於基板301之複數被動組件303、304及309、及至少一積體電路302。積體電路302可包括功率電晶體開關及控制邏輯或用以操作切換器封裝之電路系統。用於各封裝之一或多個積體電路302可包括厚基板。被動組件303及304之至少一部分可相對一或多個軸界定對稱之配置。此對稱可有助於降低與切換器封裝熱電流迴路之高di/dt事件有關之電磁干擾。於某些例示，密封材316係可應用於切換器封裝之全部板材350以覆蓋被動組件303、304及309。於某些例示，密封材316可經應用以覆蓋被動組件303、304及309，及各切換器封裝300之積體電路302。於後續之操作，去除程式如研磨、打磨或蝕刻程式可經使用以露出各切換器封裝300中其一積體電路302之上表面317，或使其平整。於某些例示，切換器封裝之板材350可經切割或分割以提供獨立之切換器封裝。於某些例示，於密封材316經應用於積體電路302之外露區域317之後，金屬遮蔽（圖中未示）可經應用至板材350，接著，獨立切換器封裝300可自板材350經分割。
圖3B圖示製造切換器封裝300之板材350之一種可選製造方法。圖3C圖示圖3B板材之側視圖。於某些例示，於密封材316經加工且應用於積體電路302之外露區域317之後，可執行第一切割或潰散程式，其並未切斷封裝300但露出各封裝300之至少一部分側壁318。接著，如前述之金屬遮蔽可經放置於板材350之上，藉此，不僅各封裝300之上表面經遮蔽覆蓋，各封裝300一或多個側壁318之至少一部分亦經遮蔽覆蓋。金屬遮蔽應用至板材350後，獨立之切換器封裝300可接著經分割。
圖4圖示製造低噪音或靜音切換器積體電路封裝之其一例示方法400。於步驟401，積體電路晶粒及被動組件可經設置於基板。於某些例示，部分被動組件係可關於發出實質電磁干擾之電流迴路。此被動組件可沿至少一軸經對稱設置於基板上。此對稱設置可使與其一被動組件有關之電流迴路磁場至少部分抵銷與其對稱設置之被動組件有關之電流迴路磁場，反之亦然。
於步驟403，被動組件經密封材如介電材覆蓋。密封材可形成極佳之積體電路封裝，且可物理性保護設置於基板之組件。於步驟405，將密封材應用至基板或透過其他程式如研磨、打磨或蝕刻等程式，可露出積體電路晶粒之一區域。於某些例示，外露區域係積體電路晶粒之上表面，其為基板之相反側。於步驟407，積體電路晶粒之外露區域可經電耦合至積體電路晶粒之電路。於某些例示，積體電路晶粒之外露區域經電耦合至積體電路晶粒電路之接地面。
於某些例示，散熱裝置經設置與積體電路晶粒之外露區域接觸，其提供積體電路封裝之額外散熱能力。舉例而言，於某些例示，積體電路晶粒可包括功率切換電晶體以提供電壓或功率轉換器至切換器積體電路封裝。透過積體電路晶粒之外露區域，且將散熱裝置連接至外露表面或使散熱裝置與外露區域接觸，使切換器封裝可與較高功率轉換器一起使用。於某些例示，晶粒外露區域係位於切換器積體電路封裝外部連結之相反側，相較於相似結構但不具積體電路晶粒外露區域之切換器封裝，透過其之散熱可使相同尺寸之功率切換電晶體經使用於轉換器內以提供X倍之較大功率。於某些例示，外露區域可容設金屬遮蔽，其可作為散熱裝置，亦可作為圍阻障壁以減緩與切換器積體電路封裝之切換組件相關之電流迴路產生的電磁干擾。
圖5圖示更有效率地大量製造靜音或無聲切換器積體電路封裝之其一例示方法500之流程圖。於步驟501，積體電路晶粒及被動組件可設置於基板板材之基板以界定複數之切換器封裝。於某些例示，某些被動組件可與電流迴路相關，其可實質發出電磁干擾。此被動組件係沿著各積體電路切換器封裝之至少一軸經對稱設置於基板上。此對稱可使與其一被動組件相關之電流迴路磁場至少部分抵銷與其對稱設置之被動組件相關之電流迴路磁場，且反之亦然。於某些例示，組件於基板之設置係可經設置於獨立封裝基板，且經部分製造之封裝可經設置以形成板材。
於步驟503，密封材可經製造於板材上以覆蓋被動組件。於步驟505，密封材經應用至板材上或透過其他程式如研磨、打磨或蝕刻等程式，使各積體電路晶粒之一區域外露。於某些例示，外露區域係為積體電路晶粒之上側，其係基板之相反側。於某些實施例，積體電路晶粒之外露區域係可電性耦合至積體電路晶粒之電路。於某些例示，積體電路晶粒之外露區域係可電性耦合至積體電路晶粒電路之接地面。
於步驟507，可選之金屬或傳導性遮蔽可經應用至封裝板材各晶粒之外露區域。於某些實施例，傳導性遮蔽係可經設置於板材之全部上表面，其係為十分有效且可確保各積體電路切換器封裝之遮蔽可覆蓋積體電路切換器封裝之全部上表面。於某些例示，傳導性遮蔽可透過圖1、圖2A及圖2B論述之方法經應用。於步驟509，無論是否具有遮蔽，板材係可經切割或分割以提供複數之獨立積體電路切換器封裝。於某些實施例，積體電路切換器封裝係可為功率轉換器控制封裝。 例示和注釋
在第一例示即例示1中，一種積體電路（IC）封裝可以包括:介電基板，其支撐至少二傳導層；至少二被動裝置，其等位於該介電基板上；積體電路（IC）晶粒，其位於該介電基板上；密封材，其覆蓋該至少二被動裝置之整體，且界定該積體電路晶粒之外露區域；其中該外露區域之至少一部分係電性耦合至電路，該電路係經該積體電路晶粒界定；且其中經該至少二被動裝置之位置界定之配置係沿至少一軸實質對稱，且於該至少二被動裝置，其由該介電基板提供至該積體電路晶粒之電性相互連結係沿該至少一軸實質對稱。
在例示2中，例示1的標的可選地包括：其中該至少二被動裝置包括第一電容器及第二電容器。
在例示3中，例示2的標的可選地包括：其中該積體電路晶粒包括複數電晶體，其等經設置以耦合至下列一者或多者：該第一電容器、該第二電容器、及該積體電路封裝之輸出端。
在例示4中，例示3的標的可選地包括：其中經該複數電晶體之位置界定之配置係沿該至少一軸實質對稱。
在例示5中，例示3-4的標的可選地包括：其中該積體電路晶粒包括控制邏輯，其經設置以控制該複數電晶體中各電晶體之控制閘極。
在例示6中，例示1-5的標的可選地包括：其中該積體電路晶粒包括微凸塊間距之陣列，其經設置以電性及熱性耦合至該介電基板。
在例示7中，例示1-6的標的可選地包括：其中該積體電路晶粒之該外露區域經設置以耦合至散熱裝置。
在例示8中，例示1-7的標的可選地包括：金屬遮蔽，該金屬遮蔽經耦合至該積體電路晶粒之該外露區域，且該金屬遮蔽經設置以減輕與電流迴路有關之磁場，該電流迴路係與該至少二被動裝置有關。
在例示9中，例示8的標的可選地包括：其中該至少二被動裝置包括第一電容器及第二電容器；其中該積體電路晶粒包括複數電晶體，其等經設置以耦合至下列一者或多者：該第一電容器、該第二電容器、及該積體電路封裝之輸出端；且其中該金屬遮蔽係經設置以消散該複數電晶體產生之熱能。
在例示10中，例示8-9的標的可選地包括：其中該金屬遮蔽係經耦合至該積體電路晶粒之接地面。
在例示11中，例示8-10的標的可選地包括：其中該金屬遮蔽延伸以覆蓋該積體電路封裝之側壁之至少一部分。
在例示12中，例示8-11的標的包括：其中該金屬遮蔽延伸超過該積體電路晶粒之該外露區域，以覆蓋該至少二被動裝置之位置，及於該至少二被動裝置由該介電基板提供至該積體電路晶粒之該電性相互連結。
在例示13中，例示8-12的標的包括：其中該金屬遮蔽包括銅層。
在例示14中，例示13的標的包括：其中該金屬遮蔽包括至少二不鏽鋼層；且其中該銅層係位於該至少二不鏽鋼層之間。
例示15是一種形成功率轉換器控制電路封裝之方法，該方法包含：將積體電路晶粒及至少二被動裝置設置於基板上，該基板支援至少二傳導層，其中經該至少二被動裝置之位置界定之配置係沿至少一軸實質對稱，且於該至少二被動裝置，其由該介電基板提供至該積體電路晶粒之電性相互連結係沿該至少一軸實質對稱；以密封材覆蓋該至少二被動裝置之整體，以提供經密封之該功率轉換器控制封裝之板材；以該密封材界定該積體電路晶粒之外露區域；及將該外露區域之至少一部分電性耦合至經該積體電路晶粒界定之電路。
在例示16中，例示15的標的包括：於該積體電路之該外露區域上形成散熱裝置。
在例示17中，例示15-16的標的包括：於該積體電路之該外露區域上設置遮蔽。
在例示18中，例示17的標的包括：其中於該積體電路之該外露區域上設置遮蔽，係包括於該積體電路之該外露區域上設置不鏽鋼與銅之可選層體。
在例示19中，例示15-18的標的包括：其中以密封材覆蓋該至少二被動裝置之該整體，係包括覆蓋該功率轉換器控制封裝之板材之該至少二被動裝置之整體；且其中以該密封材界定該積體電路晶粒之外露區域，係包括界定該經密封功率轉換器控制封裝之該板材之該複數積體電路晶粒之該複數外露區域。
在例示20中，例示19的標的包括：自該功率轉換器控制封裝之該板材分割獨立功率轉換器控制封裝。
在例示21中，例示19-20的標的包括：其中以密封材覆蓋該至少二被動裝置之該整體，係包括於該複數外露區域設置遮蔽，其延伸超過該經密封功率轉換器控制封裝之該板材；及自該功率轉換器控制封裝之該板材分割獨立功率轉換器控制封裝。
以上詳細說明包括附圖之參考，附圖形成詳細說明之一部分。透過圖示之方式圖式顯示出可實施本發明之具體實施例。該等實施例於此亦稱為「例示」。該等例示可包括除已顯示或所述元件外之元件。然而，本發明人亦考量僅顯示或所述該等元件之例示。此外，本發明人亦考量利用所示或所述該等元件之任何組合或排列（或其一或多個態樣），關於特定例示（或其一或多個態樣）或關於本文所示或所述之其他例示（或其一或多個態樣）。
如果本發明與透過引用方式併入本文之任何文件之間用法上有不一致之情形，則以本發明之用法為準。
於本文件中，專利文件中常見之用語「一」或「一個」係包括一個或多於一個，係獨立於「至少一」或「一或多個」之任何其他例示或用途。於本文件中，該用語「或」係用以指一非排他性用語，除非另有說明，否則如「A或B」包括「A但非B」、「B但非A」以及「A與B」。於本檔中，用語「包括」與「於其中」係分別作該用語「包含」與「其中」簡明英文之同義詞。此外，於以下申請專利範圍中，該等用語「包括」與「包含」係開放式，即一系統、裝置、物件、組合、配方或程序包括已列出之元件外之元件，亦落入本發明之申請專利範圍內。再者，於以下申請專利範圍中，該等語「第一」、「第二」與「第三」等僅作為標示之用，並不用以對該等標的施加數字意義上之要求。
於此所述之方法例示可至少部分為機器或電腦所實施。某些例示可包括一電腦可讀取媒介或機器可讀取媒介，其等係編碼具有可操作以設置一電子裝置以執行上述例示中所述之方法之指令。該方法之實施可包括編碼如微代碼、彙編語言代碼、更高級語言代碼等。該代碼可包括用以執行各種方法之電腦可讀取指令。該代碼可形成電腦軟體產品之一部分。此外，於一例示中，該代碼如於執行期間或其他時點可有形儲存於一或多個依電性（volatile）、非暫態或非依電性之有形電腦可讀取媒介上。該些有形之電腦可讀取媒介之例示可包括但不限於，硬碟、可移動磁碟、可移動式光碟（如，光碟與數位光碟）、磁帶、記憶卡或棒、隨機存取記憶體（RAM）、唯讀記憶體（ROM）等。
上述說明係為說明性而非限制性。例如，上述例示（或其等一或多個態樣）可彼此相互組合使用。如該技術領域通常知識者於閱讀上述說明後可使用其他實施例。所提供之摘要係符合37 C.F.R. §1.72（b）以使讀者能快速理解本發明技術內容之本質。應理解為，其非用以解釋或限制申請專利範圍之範圍或含義。此外，於上述詳細說明中，各種特徵可經分群以簡化本發明所揭露之內容。此不應解釋為未見於申請專利範圍中之技術特徵對於任何本發明之申請專利範圍係相當重要的。相反地，本發明之目標主體可能比一特定揭露之實施例之所有特徵要來的少。因此，以下態樣係併入至該詳細說明中作為例示或實施例，其中各態樣係各自作為一單獨實施例，且可預期該些實施例可以各種組合方式或排列方式彼此相互組合使用。
100:切換器控制封裝 101:基板 102:控制器積體電路 103:切換電容器 104:切換電容器 106:第一供應輸入端 107:第二供應輸入端 108:輸出切換端 109:自舉電容器 110:功率電晶體 111:功率電晶體 112:功率電晶體 113:功率電晶體 116:密封材 117:上表面 118:微凸塊 119:傳導性遮蔽 120:傳導性金屬 121:傳導性障壁材料 122:第二障壁材料 130:電流迴路途徑 300:切換器封裝 301:基板 302:積體電路 303:被動組件 304:被動組件 309:被動組件 316:密封材 317:上表面 318:側壁 350:板材
圖式未必以實際比例繪製，相同標號可描述不同圖式中相似元件。具有不同字尾之相同標號可表示相似元件之不同例示。圖式通常係以舉例方式而非限定方式圖示本發明中所述各種實施例。
圖1A圖示本發明切換器控制封裝之示意圖。
圖1B圖示圖1A切換器控制封裝之簡化電路圖。
圖2A圖示切換器控制封裝其一例示之剖面圖。
圖2B圖示傳導性遮蔽之其一例示，其可經放置於密封材及切換器封裝積體電路之外露區域之上。
圖3A圖示切換器封裝之板材之其一例示，其等可出現於製造程式中。
圖3B圖示製造切換器封裝之板材之一種可選製造方法。
圖3C圖示圖3B板材之側視圖。
圖4圖示製造低噪音或靜音切換器積體電路封裝之其一例示方法。
圖5圖示更有效率地大量製造靜音或無聲切換器積體電路封裝之其一例示方法之流程圖。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
100:切換器控制封裝
101:基板
102:控制器積體電路
103:切換電容器
104:切換電容器
109:自舉電容器
116:密封材
117:上表面

Claims (21)

  1. 一種積體電路（IC）封裝，其包含： 一介電基板，其支撐至少二傳導層； 至少二被動裝置，其等位於該介電基板上； 一積體電路（IC）晶粒，其位於該介電基板上； 一密封材，其覆蓋該至少二被動裝置之一整體，且界定該積體電路晶粒之一外露區域； 其中該外露區域之至少一部分係電性耦合至一電路，該電路係經該積體電路晶粒界定；且 其中經該至少二被動裝置之位置界定之一配置係沿至少一軸實質對稱，且於該至少二被動裝置，其由該介電基板提供至該積體電路晶粒之一電性相互連結係沿該至少一軸實質對稱。
  2. 如請求項1之積體電路封裝，其中該至少二被動裝置包括一第一電容器及一第二電容器。
  3. 如請求項2之積體電路封裝，其中該積體電路晶粒包括複數電晶體，其等經設置以耦合至下列至少一者：該第一電容器、該第二電容器、及該積體電路封裝之一輸出端。
  4. 如請求項3之積體電路封裝，其中經該複數電晶體之位置界定之一配置係沿該至少一軸實質對稱。
  5. 如請求項3之積體電路封裝，其中該積體電路晶粒包括一控制邏輯，其經設置以控制該複數電晶體中各電晶體之一控制閘極。
  6. 如請求項1-5中任一項之積體電路封裝，其中該積體電路晶粒包括一微凸塊間距之一陣列，其經設置以電性及熱性耦合至該介電基板。
  7. 如請求項1-5中任一項之積體電路封裝，其中該積體電路晶粒之該外露區域經設置以耦合至一散熱裝置。
  8. 如請求項1-5中任一項之積體電路封裝，其包括一金屬遮蔽，該金屬遮蔽經耦合至該積體電路晶粒之該外露區域，且該金屬遮蔽經設置以減輕與一電流迴路有關之一磁場，該電流迴路係與該至少二被動裝置有關。
  9. 如請求項8之積體電路封裝，其中該至少二被動裝置包括一第一電容器及一第二電容器； 其中該積體電路晶粒包括複數電晶體，其等經設置以耦合至下列至少一者：該第一電容器、該第二電容器、及該積體電路封裝之一輸出端；且 其中該金屬遮蔽係經設置以消散該複數電晶體產生之一熱能。
  10. 如請求項8之積體電路封裝，其中該金屬遮蔽係經耦合至該積體電路晶粒之一接地面。
  11. 如請求項8之積體電路封裝，其中該金屬遮蔽延伸以覆蓋該積體電路封裝之一側壁之至少一部分。
  12. 如請求項8之積體電路封裝，其中該金屬遮蔽延伸超過該積體電路晶粒之該外露區域，以覆蓋該至少二被動裝置之位置，及於該至少二被動裝置由該介電基板提供至該積體電路晶粒之該電性相互連結。
  13. 如請求項8之積體電路封裝，其中該金屬遮蔽包括一銅層。
  14. 如請求項13之積體電路封裝，其中該金屬遮蔽包括至少二不鏽鋼層；且 其中該銅層係位於該至少二不鏽鋼層之間。
  15. 一種形成一功率轉換器控制電路封裝之方法，其包含以下步驟： 將一積體電路晶粒及至少二被動裝置設置於一基板上，該基板支援至少二傳導層，其中經該至少二被動裝置之位置界定之一配置係沿至少一軸實質對稱，且於該至少二被動裝置，其由該介電基板提供至該積體電路晶粒之一電性相互連結係沿該至少一軸實質對稱； 以一密封材覆蓋該至少二被動裝置之一整體，以提供經密封之該功率轉換器控制封裝之一板材； 以該密封材界定該積體電路晶粒之一外露區域；及 將該外露區域之至少一部分電性耦合至經該積體電路晶粒界定之一電路。
  16. 如請求項15之方法，其包括以下步驟：於該積體電路之該外露區域上形成一散熱裝置。
  17. 如請求項15之方法，其包括以下步驟：於該積體電路之該外露區域上設置一遮蔽。
  18. 如請求項17之方法，其中於該積體電路之該外露區域上設置一遮蔽，係包括以下步驟：於該積體電路之該外露區域上設置不鏽鋼與銅之一可選層體。
  19. 如請求項15-18中任一項之方法，其中以一密封材覆蓋該至少二被動裝置之該整體，係包括以下步驟：覆蓋該功率轉換器控制封裝之一板材之該至少二被動裝置之整體；且 其中以該密封材界定該積體電路晶粒之一外露區域，係包括以下步驟：界定該經密封功率轉換器控制封裝之該板材之該複數積體電路晶粒之該複數外露區域。
  20. 如請求項19之方法，其包括以下步驟：自該功率轉換器控制封裝之該板材分割獨立功率轉換器控制封裝。
  21. 如請求項19之方法，其中以一密封材覆蓋該至少二被動裝置之該整體，係包括以下步驟：於該複數外露區域設置一遮蔽，其延伸超過該經密封功率轉換器控制封裝之該板材；及 自該功率轉換器控制封裝之該板材分割獨立功率轉換器控制封裝。
TW108140978A 2018-11-16 2019-11-12 調節器電路封裝技術 TW202109686A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/193,843 US11037883B2 (en) 2018-11-16 2018-11-16 Regulator circuit package techniques
US16/193,843 2018-11-16

Publications (1)

Publication Number Publication Date
TW202109686A true TW202109686A (zh) 2021-03-01

Family

ID=70470574

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108140978A TW202109686A (zh) 2018-11-16 2019-11-12 調節器電路封裝技術

Country Status (4)

Country Link
US (2) US11037883B2 (zh)
CN (1) CN111199965B (zh)
DE (1) DE102019007881A1 (zh)
TW (1) TW202109686A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11955437B2 (en) 2018-11-16 2024-04-09 Analog Devices International Unlimited Company Regulator circuit package techniques

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0720920Y2 (ja) * 1987-05-25 1995-05-15 日本電信電話株式会社 Ｉｃパツケ−ジ
TW200832875A (en) 2007-01-19 2008-08-01 Murata Manufacturing Co DC-DC converter module
US7868431B2 (en) * 2007-11-23 2011-01-11 Alpha And Omega Semiconductor Incorporated Compact power semiconductor package and method with stacked inductor and integrated circuit die
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7618846B1 (en) * 2008-06-16 2009-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the device
US8373264B2 (en) 2008-07-31 2013-02-12 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture thereof
US7948045B2 (en) 2008-08-18 2011-05-24 Seagate Technology Llc Magnet-assisted transistor devices
JP4977101B2 (ja) * 2008-08-26 2012-07-18 株式会社東芝 積層型半導体装置
JP2011114198A (ja) 2009-11-27 2011-06-09 Renesas Electronics Corp プリミティブセル及び半導体装置
JP5318150B2 (ja) * 2011-04-19 2013-10-16 三菱電機株式会社 スイッチング電源装置
US9765934B2 (en) * 2011-05-16 2017-09-19 The Board Of Trustees Of The University Of Illinois Thermally managed LED arrays assembled by printing
US9059642B2 (en) 2012-08-22 2015-06-16 Atmel Corporation Digitally controlled spur management technique for integrated DC-DC converters
US8963335B2 (en) * 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US8823345B2 (en) 2012-10-19 2014-09-02 Linear Technology Corporation Magnetic field cancellation in switching regulators
US9484313B2 (en) 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
JP6106127B2 (ja) * 2014-05-29 2017-03-29 株式会社ソニー・インタラクティブエンタテインメント スイッチングコンバータおよびそれを用いた電子機器
TWI614870B (zh) 2014-07-25 2018-02-11 矽品精密工業股份有限公司 封裝結構及其製法
JP6639931B2 (ja) * 2016-02-02 2020-02-05 Ｔｏｗａ株式会社 電子部品の製造装置及び製造方法並びに電子部品
TWI624915B (zh) 2017-04-25 2018-05-21 力成科技股份有限公司 封裝結構
WO2019066986A1 (en) * 2017-09-30 2019-04-04 Intel Corporation STACK OF NON-TSV CHIPS USING PLATED PILLARS / CROSSING MOLD INTERCONNECTION
US11037883B2 (en) 2018-11-16 2021-06-15 Analog Devices International Unlimited Company Regulator circuit package techniques
US11257747B2 (en) * 2019-04-12 2022-02-22 Powertech Technology Inc. Semiconductor package with conductive via in encapsulation connecting to conductive element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11955437B2 (en) 2018-11-16 2024-04-09 Analog Devices International Unlimited Company Regulator circuit package techniques

Also Published As

Publication number Publication date
US20210257313A1 (en) 2021-08-19
US11955437B2 (en) 2024-04-09
CN111199965B (zh) 2023-11-03
US11037883B2 (en) 2021-06-15
US20200161253A1 (en) 2020-05-21
CN111199965A (zh) 2020-05-26
DE102019007881A1 (de) 2020-05-20

Similar Documents

Publication Publication Date Title
KR101834389B1 (ko) 웨이퍼 레벨의 적층형 다이 패키지
KR102376119B1 (ko) 이면 도전성 플레이트를 가진 무선 다이 패키지
US10593656B2 (en) Three-dimensional package structure
US8837168B2 (en) Electronic package structure
US11056421B2 (en) Package structure for power converter and manufacture method thereof
EP3252812B1 (en) Embedded package structure
US9373567B2 (en) Lead frame, manufacture method and package structure thereof
US9437542B2 (en) Chip package structure
US10784213B2 (en) Power device package
CN104347540B (zh) 电路模块以及电路模块的制造方法
TW201639426A (zh) 單積層式電流隔離器總成
US20140103505A1 (en) Die down integrated circuit package with integrated heat spreader and leads
US20180366393A1 (en) Chip packaging method and package structure
US20200260586A1 (en) Power module and manufacturing method thereof
US20200273782A1 (en) Semiconductor package with heatsink
TW202109686A (zh) 調節器電路封裝技術
US8064202B2 (en) Sandwich structure with double-sided cooling and EMI shielding
CN111726932B (zh) 一种磁性装置和堆叠式电子结构
US7545021B1 (en) Apparatus and method for making integrated circuit packages having integrated circuits mounted onto passive electrical components
KR20120138984A (ko) 전력 모듈 패키지 및 그 제조방법
US20220084736A1 (en) Tandem magnetics in package
KR20200128263A (ko) 감소된 emi를 가지는 hv 컨버터