TW202036913A - 包含場效電晶體的半導體裝置及其製作方法 - Google Patents

包含場效電晶體的半導體裝置及其製作方法 Download PDF

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TW202036913A
TW202036913A TW108136443A TW108136443A TW202036913A TW 202036913 A TW202036913 A TW 202036913A TW 108136443 A TW108136443 A TW 108136443A TW 108136443 A TW108136443 A TW 108136443A TW 202036913 A TW202036913 A TW 202036913A
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semiconductor
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semiconductor layer
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TW108136443A
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TWI818097B (zh
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李演光
姜聲珉
金炅泯
禹珉希
姜俊求
金榮睦
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南韓商三星電子股份有限公司
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Abstract

一種半導體裝置包含基板，在基板中依序堆疊有下部半導體層、絕緣間隙填充層及上部半導體層。閘極結構設置於上部半導體層上。源極/汲極電極設置於閘極結構的側壁上。半導體圖案設置於源極/汲極電極與上部半導體層之間。閘極結構包含閘極電極及間隔件結構。間隔件結構包含依序設置於閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案。半導體圖案延伸至位於第三間隔件圖案的底表面下方的區且連接至第二間隔件圖案。

Description

包含場效電晶體的半導體裝置
本揭露是有關於一種半導體裝置，且更具體而言是有關於一種包含場效電晶體的半導體裝置。 [相關申請案的交叉參考]
本美國非臨時專利申請案基於35 U.S.C. §119主張於2019年3月22日在韓國智慧財產局提出申請的韓國專利申請案第10-2019-0033101號的優先權，所述韓國專利申請案的全部內容併入本案供參考。
由於半導體裝置可在維持非常小的形式因數的同時用於提供各種功能，因此半導體裝置在電子行業中被廣泛使用。常見類型的半導體裝置包括用於儲存資料的記憶體裝置、用於處理資料的邏輯裝置以及在單個裝置內既儲存資料亦處理資料的混合裝置。
本發明概念的示例性實施例提供具有期望的電性特性的電晶體。根據本發明概念的示例性實施例的製作半導體裝置的方法可具有減少的製程變化及複雜度。根據本發明概念的示例性實施例，電晶體可被形成為具有各種臨限電壓。
根據本發明概念的示例性實施例，一種半導體裝置可包含基板。在所述基板上依序堆疊有下部半導體層、絕緣間隙填充層及上部半導體層。閘極結構設置於所述上部半導體層上。源極/汲極電極設置於所述閘極結構的側壁上。半導體圖案設置於所述源極/汲極電極與所述上部半導體層之間。所述閘極結構可包含閘極電極及間隔件結構。所述間隔件結構可包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案。所述半導體圖案可延伸至位於所述第三間隔件圖案的底表面下方的區且可連接至所述第二間隔件圖案。
根據本發明概念的示例性實施例，一種半導體裝置可包含基板。在所述基板上依序堆疊有下部半導體層、絕緣間隙填充層及上部半導體層。閘極結構設置於所述上部半導體層上。源極/汲極電極設置於所述閘極結構的側壁上。半導體圖案設置於所述源極/汲極電極與所述上部半導體層之間。所述閘極結構可包含閘極電極及間隔件結構。所述間隔件結構可包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案。所述半導體圖案可包含上部部分及下部部分，所述上部部分連接至所述第三間隔件圖案的側壁，所述下部部分在位於所述第三間隔件圖案的底表面下方的區中延伸且連接至所述第二間隔件圖案。
根據本發明概念的示例性實施例，一種半導體裝置可包含基板。在所述基板上依序堆疊有下部半導體層、絕緣間隙填充層及上部半導體層。第一電晶體及第二電晶體設置於所述基板上。所述第一電晶體可包含：第一閘極結構，位於所述上部半導體上；第一源極/汲極電極，位於所述第一閘極結構的側壁上；以及第一半導體圖案，設置於所述第一源極/汲極電極與所述上部半導體層之間。所述第一閘極結構可包含閘極電極及第一間隔件結構。所述第一間隔件結構可包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案。所述第一半導體圖案可在位於所述第三間隔件圖案的底表面下方的區中延伸且可接觸所述第二間隔件圖案。
根據本發明概念的示例性實施例，一種製作半導體裝置的方法可包含在基板上形成閘極電極。在所述基板上依序堆疊下部半導體層、絕緣間隙填充層及上部半導體層。在所述閘極電極的側壁上依序形成第一間隔件層及第二間隔件層。對所述上部半導體層執行第一離子植入製程。在所述第二間隔件層的側壁上形成第三間隔件圖案。移除放置於所述第三間隔件圖案的底表面下方的所述第二間隔件層的一部分，以形成凹槽區。自所述上部半導體層生長第一半導體圖案。所述第一半導體圖案延伸至所述凹槽區。對所述第一半導體圖案及所述上部半導體層執行第二離子植入製程。所述第一離子植入製程可在所述形成所述第三間隔件圖案之前執行。
在闡述本發明概念的示例性實施例的過程中，為清晰起見採用特定術語。然而，本揭露並非旨在僅限於如此選擇的特定術語，且應理解，每一特定元件包含以相似的方式運作的所有技術等效形式。
應注意，該些圖旨在示出本發明概念的某些示例性實施例中所利用的方法、結構及/或材料的示例性特性且旨在對以下提供的書面說明進行補充。該些圖式的元件可能未必按比例繪製且為清晰起見可被誇大。然而，應理解，可以所示出的精密結構、相對大小及角度作為實例，且因此儘管本發明並非僅限於所示出的精密結構，然而此所示出的結構示出本發明的至少一個示例性實施例。舉例而言，為清晰起見，可減小或誇大分子、層、區及/或結構元件的相對厚度及位置。另外，在本說明書中及各種圖式中可使用相似或相同的參考編號來表示相似或相同的元件或特徵的存在。
圖1是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。圖2及圖3是圖1所示部分「P1」的放大圖。
參照圖1至圖3，在基板10上可設置有第一電晶體TR1。基板10可為絕緣體上矽（silicon-on-insulator，SOI）基板。作為實例，基板10可為完全耗盡型SOI（fully-depleted SOI，FD-SOI）晶圓。基板10可包含下部半導體層100、絕緣間隙填充層101及上部半導體層105。作為實例，下部半導體層100及上部半導體層105可分別為矽層。絕緣間隙填充層101可由氧化矽形成或可以其他方式包含氧化矽。上部半導體層105的厚度t2可小於絕緣間隙填充層101的厚度t1。作為實例，絕緣間隙填充層101的厚度t1可大於或等於上部半導體層105的厚度t2的兩倍。上部半導體層105可處於未經摻雜或本質狀態（intrinsic state），但在某些實施例中，上部半導體層105可包含n型雜質或p型雜質。
第一電晶體TR1可包含設置於上部半導體層105上的閘極結構。閘極結構可包含閘極絕緣層GI及設置於閘極絕緣層GI上的閘極電極GE。閘極絕緣層GI可包含下部閘極絕緣層111及上部閘極絕緣層113。下部閘極絕緣層111可由例如氧化矽形成或可以其他方式包含氧化矽。上部閘極絕緣層113可由例如介電常數高於氧化矽的介電常數的高介電常數介電材料（例如，氧化鉿）形成或可以其他方式包含介電常數高於氧化矽的介電常數的高介電常數介電材料（例如，氧化鉿）。上部閘極絕緣層113可厚於下部閘極絕緣層111。
閘極電極GE可包含金屬閘極電極層115及半導體閘極電極層117。金屬閘極電極層115可包含導電金屬氮化物層，例如氮化鈦層、氮化鉭層及/或氮化鎢層。半導體閘極電極層117可由多晶矽形成或可以其他方式包含多晶矽。半導體閘極電極層117可包含n型雜質或p型雜質。半導體閘極電極層117可厚於金屬閘極電極層115。作為實例，半導體閘極電極層117可較金屬閘極電極層115厚約5倍至約10倍。在半導體閘極電極層117上可設置有接觸電極153。接觸電極153可由至少一種金屬-半導體化合物形成或可以其他方式包含至少一種金屬-半導體化合物。作為實例，接觸電極153可由至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）。
在閘極電極GE的側壁上可設置有間隔件結構ST。間隔件結構ST可包含依序堆疊於閘極電極GE的側壁上的第一間隔件圖案122、第二間隔件圖案124及第三間隔件圖案126。第三間隔件圖案126的厚度W3可大於第一間隔件圖案122的厚度W1及/或第二間隔件圖案124的厚度W2。作為實例，第三間隔件圖案126的厚度W3可為第二間隔件圖案124的厚度W2的約5倍至約10倍。第一間隔件圖案122的厚度W1可大於第二間隔件圖案124的厚度W2。
第二間隔件圖案124可包含對於第一間隔件圖案122及第三間隔件圖案126具有蝕刻選擇性的材料。作為實例，第二間隔件圖案124可由氧化矽形成或可以其他方式包含氧化矽，且第一間隔件圖案122及第三間隔件圖案126可由氮化矽形成或可以其他方式包含氮化矽。第一間隔件圖案122可由與第三間隔件圖案126相同的材料形成或可以其他方式包含與第三間隔件圖案126相同的材料。由於第二間隔件圖案124設置於第一間隔件圖案122與第三間隔件圖案126之間，因此間隔件結構ST中的電荷陷獲現象可得到緩解。
第二間隔件圖案124可包含側壁部分SP及突出部分PP，側壁部分SP主要在與基板10的頂表面垂直的第一方向D1上延伸，突出部分PP主要在與第一方向D1垂直的第二方向D2上自側壁部分SP延伸。側壁部分SP可延伸至第一間隔件圖案122與第三間隔件圖案126之間的區中。突出部分PP可放置於第三間隔件圖案126的底表面下方。第二間隔件圖案124可具有實質上呈字母「L」形的截面。在間隔件結構ST下方可設置有朝閘極電極GE凹陷的凹槽區RS。凹槽區RS中的每一者可由第三間隔件圖案126的底表面及突出部分PP的側壁界定。作為實例，突出部分PP可僅覆蓋第三間隔件圖案126的底表面的一部分。
第一電晶體TR1可包含設置於間隔件結構ST的側壁上的源極/汲極電極151。源極/汲極電極151可由至少一種金屬-半導體化合物形成或可以其他方式包含至少一種金屬-半導體化合物。作為實例，源極/汲極電極151可由至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）。源極/汲極電極151的底表面可位於較第三間隔件圖案126的底表面高或與第三間隔件圖案126的底表面相等的水平高度處。
本文中所用的片語「源極/汲極」旨在表示源極及/或汲極。在某種程度上，該些元件在本文所述的結構中可互換，且因此應理解，對於元件（例如電晶體），可存在兩個源極/汲極，其中一個是源極，且另一個是汲極，但對於結構而言哪一個是源極以及哪一個是汲極可能並不重要，且因此在本文中源極及汲極中的每一者皆可被稱為「源極/汲極」。
上部半導體層105的厚度t2可小於源極/汲極電極151的厚度t3。作為實例，上部半導體層105的厚度t2可等於或小於源極/汲極電極151的厚度t3的一半。
在源極/汲極電極151與上部半導體層105之間可設置有第一半導體圖案141。第一半導體圖案141可為藉由磊晶製程（epitaxial process）自上部半導體層105的頂表面生長的磊晶層。作為實例，上部半導體層105可包含矽層、矽-鍺層及/或碳化矽層。
第一半導體圖案141的厚度可小於源極/汲極電極151的厚度t3。作為實例，第一半導體圖案141的厚度可小於或等於源極/汲極電極151的厚度t3的一半。第一半導體圖案141的厚度可小於上部半導體層105的厚度t1。
第一半導體圖案141可延伸至凹槽區RS中。長度WA與長度WB的和可等於第三間隔件圖案126的厚度W3，其中長度WA是延伸至位於第三間隔件圖案126下方的區中的第二間隔件圖案124的突出部分PP的長度，且長度WB可為延伸至凹槽區RS中的第一半導體圖案141的一部分的長度。第一半導體圖案141的頂表面可位於與第三間隔件圖案126的底表面相等或較第三間隔件圖案126的底表面高的水平高度處。作為實例，第一半導體圖案141的頂表面可位於與第三間隔件圖案126的底表面實質上相同的水平高度處，如圖2中所示。作為實例，第一半導體圖案141的頂表面可位於較第三間隔件圖案126的底表面高的水平高度處，如圖3中所示。在此種情形中，第一半導體圖案141中的每一者可包含較第三間隔件圖案126的底表面低的下部部分LP及較第三間隔件圖案126的底表面高的上部部分UP。下部部分LP可嵌入至凹槽區RS中，以接觸第二間隔件圖案124。上部部分UP可連接至第三間隔件圖案126的側壁。舉例而言，第一半導體圖案141中的每一者可在其中第一半導體圖案141連接至第三間隔件圖案126的連接區中具有台階式結構。
在上部半導體層105及第一半導體圖案141二者中可分別設置有源極/汲極區133。源極/汲極區133可依據第一電晶體TR1的種類而摻雜有p型摻雜劑或n型摻雜劑。源極/汲極區133可延伸至上部半導體層105的底表面。舉例而言，源極/汲極區133可具有大到足以到達絕緣間隙填充層101的頂表面的深度。源極/汲極區133可延伸至位於第三間隔件圖案126下方的區中。
在上部半導體層105中可設置有輕摻雜區131。輕摻雜區131可為具有較源極/汲極區133低的摻雜濃度的雜質區。輕摻雜區131可具有與源極/汲極區133相同的導電類型。輕摻雜區131可為自源極/汲極區133朝閘極電極GE延伸的區。
應力層161可至少局部地覆蓋閘極結構。應力層161可對閘極結構施加張應力（tensile stress）或壓縮應力（compressive stress）。作為實例，應力層161可由氮化矽形成或可以其他方式包含氮化矽。層間絕緣層171可至少局部地覆蓋應力層161。層間絕緣層171可由氧化矽形成或可以其他方式包含氧化矽。
第一接觸件181可穿透層間絕緣層171且可連接至源極/汲極電極151。第一接觸件181的下部部分可設置於源極/汲極電極151的上部部分中。第一導電圖案186可設置於層間絕緣層171上且可連接至第一接觸件181。在本發明概念的示例性實施例中，第一接觸件181及第一導電圖案186可由至少一種金屬（例如，銅、鋁、鎢、鈦及/或鉭）及/或其金屬氮化物形成，或可以其他方式包含至少一種金屬（例如，銅、鋁、鎢、鈦及/或鉭）及/或其金屬氮化物。
根據本發明概念的示例性實施例，第一電晶體TR1可設置於具有相對小的厚度的上部半導體層105上。因此，當第一電晶體TR1運作時，源極/汲極區133之間的通道可遍及源極/汲極區133之間的整個區形成。舉例而言，源極/汲極區133之間的區可為完全耗盡的。
第一半導體圖案141與閘極電極GE之間的距離可確定源極/汲極區133之間的距離，且因此亦可確定第一電晶體TR1的通道長度。在第一半導體圖案141與閘極電極GE之間的距離過小的情形中，漏電流（leakage current）可能會增大。相反，在第一半導體圖案141與閘極電極GE之間的距離過大的情形中，電流路徑的長度可能會增大，且在此種情形中，電晶體的效能可能會惡化。
根據本發明概念的示例性實施例，在第一電晶體TR1中，第一半導體圖案141與閘極電極GE之間的距離可由第二間隔件圖案124的突出部分PP的長度確定。舉例而言，藉由調整第二間隔件圖案124的突出部分PP的長度，電晶體可被製作成具有期望的電性特性（例如，低的漏電流）。
圖4是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。為使說明簡潔起見，先前闡述的元件可由相同的參考編號來標識，而不再對重複說明予以贅述。因此，在省略了對特定元件的詳細說明的程度上，可假設所述特定元件至少相似於在本揭露內的其他地方詳細闡述的對應的元件。
參照圖4，在基板10上可設置有第六電晶體TR6。基板10可包含下部半導體層100、絕緣間隙填充層101及上部半導體層105。第六電晶體TR6可包含設置於間隔件結構ST的側壁上的源極/汲極電極151。絕緣間隙填充層101的厚度t1可小於源極/汲極電極151的厚度t3。作為實例，絕緣間隙填充層101的厚度t1可實質上等於或小於上部半導體層105的厚度t2。
在本發明概念的示例性實施例中，半導體裝置可包含閘極區GR及背側偏壓區BR，閘極區GR與背側偏壓區BR彼此間隔開且在閘極區GR與背側偏壓區BR之間夾置有絕緣隔離圖案102。絕緣隔離圖案102可由氧化矽形成或可以其他方式包含氧化矽。在閘極區GR上可設置有閘極結構。背側偏壓區BR可用於調整第六電晶體TR6的臨限電壓且可被配置成使得背側偏壓施加至絕緣間隙填充層101下方的下部半導體層100。絕緣間隙填充層101可被設置成具有相對小的厚度，且在此種情形中，可更容易地執行背側偏壓。
背側偏壓區BR可包含設置於下部半導體層100的上部部分中的拾取雜質區（pick-up impurity region）134及設置於拾取雜質區134上的拾取電極154。拾取雜質區134可具有與源極/汲極區133不同的導電類型。拾取電極154可由至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）。與閘極區GR不同，在背側偏壓區BR中可不設置絕緣間隙填充層101及上部半導體層105。
第二接觸件182可穿透層間絕緣層171且可連接至拾取電極154。第二導電圖案187可設置於層間絕緣層171上且可連接至第二接觸件182。作為實例，第二接觸件182及第二導電圖案187可由至少一種金屬（例如，銅、鋁、鎢、鈦及/或鉭）及/或其金屬氮化物形成，或可以其他方式包含至少一種金屬（例如，銅、鋁、鎢、鈦及/或鉭）及/或其金屬氮化物。
圖5是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
參照圖5，根據本發明概念的示例性實施例的半導體裝置可包含第一電晶體TR1及第二電晶體TR2。第一電晶體TR1與第二電晶體TR2可彼此間隔開且在第一電晶體TR1與第二電晶體TR2之間夾置有絕緣隔離圖案102。
第一電晶體TR1可包含第一閘極電極GE1、第一閘極絕緣層GI1及第一間隔件結構ST1。第二電晶體TR2可包含第二閘極電極GE2、第二閘極絕緣層GI2及第二間隔件結構ST2。作為實例，第一電晶體TR1可為包含邏輯電路的邏輯電晶體，且第二電晶體TR2可為用作類比裝置的一部分且被配置成使用較第一電晶體TR1的電壓高的電壓的電晶體。
第一電晶體TR1可包含第一下部雜質區135，第一下部雜質區135與絕緣間隙填充層101相鄰地設置於上部半導體層105的上部部分中。第一下部雜質區135可設置於第一閘極電極GE1及第一源極/汲極區133下方。第一下部雜質區135可藉由離子植入製程（ion implantation process）形成，所述離子植入製程在形成第一閘極電極GE1及第一閘極絕緣層GI1之前執行。在第一電晶體TR1是N通道金屬氧化物半導體（N-channel metal oxide semiconductor，NMOS）電晶體的情形中，第一下部雜質區135可為n型雜質區。在本發明概念的一些示例性實施例中，在第一電晶體TR1是NMOS電晶體的情形中，第一下部雜質區135可為p型雜質區。相較於第一下部雜質區135具有與源極/汲極區133的導電類型不同的導電類型的情形，在第一下部雜質區135具有與源極/汲極區133相同的導電類型的情形中，第一電晶體TR1可具有低的臨限電壓。絕緣隔離圖案102的底表面可位於較第一下部雜質區135的底表面低的水平高度處。
第二電晶體TR2可形成於下部半導體層100的其中絕緣間隙填充層101及上部半導體層105被移除的區上。舉例而言，第一電晶體TR1的第一源極/汲極區133可設置於第一半導體圖案141及上部半導體層105中，而第二電晶體TR2的第二源極/汲極區136可設置於下部半導體層100的上部部分中。在第二源極/汲極區136上可設置有第二源極/汲極電極156。第二源極/汲極電極156可藉由對下部半導體層100的上部部分執行矽化物製程（silicide process）來形成。第二源極/汲極電極156可由例如至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）。
第二電晶體TR2的第二閘極絕緣層GI2可包含閘極絕緣部分179。第二閘極絕緣層GI2可包含設置於閘極絕緣部分179上的下部閘極絕緣層111及/或上部閘極絕緣層113。然而，在本發明概念的示例性實施例中，可省略下部閘極絕緣層111及上部閘極絕緣層113。作為實例，下部閘極絕緣層111可由氧化矽形成或可以其他方式包含氧化矽。作為實例，上部閘極絕緣層113可由至少一種高介電常數介電材料（例如氧化鉿）形成或可以其他方式包含至少一種高介電常數介電材料（例如氧化鉿）。
閘極絕緣部分179可厚於下部閘極絕緣層111及上部閘極絕緣層113。作為實例，閘極絕緣部分179可厚於第二閘極電極GE2。作為實例，閘極絕緣部分179可厚於第一電晶體TR1下方的絕緣間隙填充層101。閘極絕緣部分179可由氧化矽形成或可以其他方式包含氧化矽。
與第一間隔件結構ST1不同，第二間隔件結構ST2可不包含凹槽區。作為實例，與第一間隔件結構ST1的第二間隔件圖案124不同，第二間隔件結構ST2的第二間隔件圖案124a可不朝第二閘極電極GE2凹陷。作為實例，第二間隔件圖案124的側壁可與閘極絕緣部分179的側壁對準。
圖6是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。圖7是圖6所示部分「P2」的放大圖。
參照圖6及圖7，根據本發明概念的示例性實施例的半導體裝置可包含第一電晶體TR1及第三電晶體TR3。第一電晶體TR1可包含第一閘極電極GE1、第一閘極絕緣層GI1及第一間隔件結構ST1。第三電晶體TR3可包含第三閘極電極GE3、第三閘極絕緣層GI3及第三間隔件結構ST3。作為實例，第一電晶體TR1與第三電晶體TR3可具有相同的導電類型。第一電晶體TR1可被配置成具有與本文中參照圖5所述的第一電晶體TR1實質上相同的特徵。圖6中的部分「P1」可對應於圖3中的部分「P1」。
除第二間隔件圖案124b的形狀之外，第三電晶體TR3可具有與第一電晶體TR1相同的結構。在下文中，將基於與圖2所示部分「P1」的比較來闡述第二間隔件圖案124b。
如圖7中所示，第三電晶體TR3的第二間隔件圖案124b可包含突出部分PP，突出部分PP短於第一電晶體TR1的第二間隔件圖案124中的突出部分PP。舉例而言，第二間隔件圖案124b的突出部分PP的長度WA可短於第一電晶體TR1的突出部分PP的長度WA。延伸至凹槽區RS中的第一半導體圖案141的長度WB可長於第一電晶體TR1的第一半導體圖案141的長度WB。因此，第三電晶體TR3可具有較第一電晶體TR1的通道長度短的通道長度，且第三電晶體TR3的臨限電壓可低於第一電晶體TR1的臨限電壓。
第一電晶體TR1可包含第一下部雜質區135，第一下部雜質區135與絕緣間隙填充層101相鄰地設置於上部半導體層105的上部部分中。第三電晶體TR3可包含第二下部雜質區137，第二下部雜質區137與絕緣間隙填充層101相鄰地設置於上部半導體層105的上部部分中。在第一電晶體TR1與第三電晶體TR3具有相同的導電類型的情形中，第二下部雜質區137可為具有與第一下部雜質區135不同的導電類型的雜質區。舉例而言，在第一電晶體TR1與第三電晶體TR3是NMOS電晶體的情形中，第一下部雜質區135可為n型雜質區，且第二下部雜質區137可為p型雜質區。在此種情形中，第一電晶體TR1可具有較第三電晶體TR3的臨限電壓低的臨限電壓。
圖8是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
參照圖8，根據本發明概念的示例性實施例的半導體裝置可包含第一電晶體TR1及第四電晶體TR4。第一電晶體TR1可包含第一閘極電極GE1、第一閘極絕緣層GI1及第一間隔件結構ST1。第四電晶體TR4可包含第四閘極電極GE4、第四閘極絕緣層GI4及第四間隔件結構ST4。第一電晶體TR1可具有與第四電晶體TR4不同的導電類型。作為實例，第一電晶體TR1可為NMOS電晶體，且第四電晶體TR4可為P通道金屬氧化物半導體（P-channel metal oxide semiconductor，PMOS）電晶體。
第一電晶體TR1可包含位於源極/汲極電極151與上部半導體層105之間的第二半導體圖案142。第四電晶體TR4可包含位於源極/汲極電極151與上部半導體層105之間的第三半導體圖案143。第二半導體圖案142及/或第三半導體圖案143可包含與上部半導體層105不同的材料。作為實例，第三半導體圖案143可由能夠對第四電晶體TR4的通道區施加壓縮應變的材料形成。舉例而言，第三半導體圖案143可包含矽鍺（SiGe）。第二半導體圖案142可由能夠對第一電晶體TR1的通道區施加張應變的材料形成。舉例而言，第二半導體圖案142可包含碳化矽（SiC）。
第一電晶體TR1可包含第一下部雜質區135，第一下部雜質區135與絕緣間隙填充層101相鄰地設置於上部半導體層105的上部部分中。第四電晶體TR4可包含第三下部雜質區138，第三下部雜質區138與絕緣間隙填充層101相鄰地設置於上部半導體層105的上部部分中。第三下部雜質區138可為具有與第一下部雜質區135不同的導電類型的雜質區。舉例而言，在第一電晶體TR1是NMOS電晶體且第四電晶體TR4是PMOS電晶體的情形中，第一下部雜質區135可為n型雜質區，且第三下部雜質區138可為p型雜質區。
圖9是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
參照圖9，根據本發明概念的示例性實施例的半導體裝置可包含第一電晶體TR1及第五電晶體TR5。第一電晶體TR1可包含第一閘極電極GE1、第一閘極絕緣層GI1及第一間隔件結構ST1。第五電晶體TR5可包含第五閘極電極GE5、第五閘極絕緣層GI5及第五間隔件結構ST5。第一電晶體TR1可具有與第五電晶體TR5不同的導電類型。作為實例，第一電晶體TR1可為NMOS電晶體，且第五電晶體TR5可為PMOS電晶體。
上面設置有第五電晶體TR5的第二上部半導體層105b的厚度t5可大於上面設置有第一電晶體TR1的第一上部半導體層105a的厚度t4。作為實例，第一上部半導體層105a及第二上部半導體層105b二者皆可為矽層。在某些實施例中，第一上部半導體層105a可為矽層，且第二上部半導體層105b可更包含與第一上部半導體層105a的材料不同的材料（例如，矽-鍺）。
第二上部半導體層105b可在形成第五電晶體TR5的第五閘極電極GE5之前藉由在基板10的區上形成附加半導體材料（例如矽）的沈積製程來形成。作為實例，沈積製程可為磊晶製程。
第一電晶體TR1可包含設置於源極/汲極電極151與第一上部半導體層105a之間的第二半導體圖案142。第五電晶體TR5可包含設置於源極/汲極電極151與第二上部半導體層105b之間的第三半導體圖案143。第三半導體圖案143可包含例如矽鍺（SiGe）。第二半導體圖案142可包含例如碳化矽（SiC）。
第一電晶體TR1可包含第一下部雜質區135，第一下部雜質區135設置於第一上部半導體層105a的上部部分中。第五電晶體TR5可包含第三下部雜質區138，第三下部雜質區138設置於第二上部半導體層105b的上部部分中。第三下部雜質區138可為具有與第一下部雜質區135相同的導電類型的雜質區。舉例而言，第一電晶體TR1是NMOS電晶體且第四電晶體TR4是PMOS電晶體，第一下部雜質區135及第三下部雜質區138可為p型雜質區。
圖10及圖11是示出根據本發明概念的示例性實施例的製作半導體裝置的製程的流程圖。圖12至圖18是示出根據本發明概念的示例性實施例的製作半導體裝置的方法的剖視圖。
參照圖12，可在基板10上形成閘極結構。基板10可為絕緣體上矽（SOI）基板。作為實例，基板10可為完全耗盡型SOI（FD-SOI）晶圓。基板10可包含下部半導體層100、絕緣間隙填充層101及上部半導體層105。上部半導體層105可處於未經摻雜或本質狀態，但本發明概念並非僅限於此實例。
閘極結構可包含依序堆疊於上部半導體層105上的閘極絕緣層GI及閘極電極GE。作為實例，形成閘極結構可包含在上部半導體層105上依序形成下部閘極絕緣層111、上部閘極絕緣層113、金屬閘極電極層115、半導體閘極電極層117及硬遮罩圖案119，且接著使用硬遮罩圖案119執行圖案化製程。
作為實例，下部閘極絕緣層111可由氧化矽形成或可以其他方式包含氧化矽。作為實例，上部閘極絕緣層113可由至少一種高介電常數介電材料（例如氧化鉿）形成或可以其他方式包含至少一種高介電常數介電材料（例如氧化鉿）。金屬閘極電極層115可由至少一種導電金屬氮化物（例如氮化鈦、氮化鉭及/或氮化鎢）形成或可以其他方式包含至少一種導電金屬氮化物（例如氮化鈦、氮化鉭及/或氮化鎢）。半導體閘極電極層117可由多晶矽形成或可以其他方式包含多晶矽。硬遮罩圖案119可由氧化矽、氮化矽及/或氮氧化矽中的至少一者形成或可以其他方式包含氧化矽、氮化矽及/或氮氧化矽中的至少一者。
第一間隔件層121可覆蓋設置有閘極電極GE的基板10（在步驟S10中示出）。作為實例，第一間隔件層121可由氮化矽形成或可以其他方式包含氮化矽。可藉由化學氣相沈積（chemical vapor deposition）製程或原子層沈積（atomic layer deposition）製程形成第一間隔件層121。
參照圖10、圖11及圖13，在形成第一間隔件層121之後，可執行第一離子植入製程IM1（在步驟S30中示出）。可執行第一離子植入製程IM1以在上部半導體層105中形成輕摻雜區131。輕摻雜區131可被形成為具有大到足以使輕摻雜區131接觸上部半導體層105的底表面的深度。在第一離子植入製程IM1中使用的雜質的導電類型可依據電晶體的種類而為n型或p型。
可在形成將在以下進行闡述的第三間隔件圖案126之前執行第一離子植入製程IM1。根據圖10中所示的方法，若完成第一離子植入製程IM1，則可對第一間隔件層121進行蝕刻以形成第一間隔件圖案122，第一間隔件圖案122彼此間隔開而使得閘極電極GE夾置於第一間隔件圖案122之間，且第一間隔件圖案122暴露出硬遮罩圖案119（在步驟S11中示出）。舉例而言，可在形成第一間隔件圖案122之前執行第一離子植入製程IM1。在形成第一間隔件圖案122之後，可形成第二間隔件層123（在步驟S20中示出）。
根據圖11中所示的方法，可在對第一間隔件層121進行蝕刻以形成第一間隔件圖案122（在步驟S11中示出）及向第一間隔件圖案122形成第二間隔件層123（在步驟S20中示出）之後，執行第一離子植入製程IM1（在步驟S30中示出）。在此種情形中，第一離子植入製程IM1中的雜質可存留於第二間隔件層123的一部分中。
第二間隔件層123可由對於第一間隔件圖案122具有蝕刻選擇性的材料形成。舉例而言，在第一間隔件層121包含氮化矽的情形中，第二間隔件層123可由氧化矽形成或可以其他方式包含氧化矽。第二間隔件層123可被形成為共形地覆蓋第一間隔件圖案122、上部半導體層105及硬遮罩圖案119。可利用化學氣相沈積製程或原子層沈積製程來執行第二間隔件層123的形成。
參照圖10、圖11及圖14，可在第二間隔件層123的側壁上形成第三間隔件圖案126（在步驟S40中示出）。可藉由形成第三間隔件層以覆蓋第二間隔件層123並執行各向異性蝕刻製程（anisotropic etching process）來形成第三間隔件圖案126。第三間隔件層126可被形成為厚於第一間隔件層121或第二間隔件層123，且亦可被形成為具有和組合於一起的第一間隔件層121與第二間隔件層123相等的厚度或厚於組合於一起的第一間隔件層121與第二間隔件層123。在各向異性蝕刻製程期間，可將第二間隔件層123的一部分與第三間隔件層一起進行蝕刻。第二間隔件層123可防止上部半導體層105被各向異性蝕刻製程損壞。第三間隔件圖案126可由與第一間隔件圖案122相同的材料形成或可以其他方式包含與第一間隔件圖案122相同的材料。作為實例，第三間隔件圖案126可由氮化矽形成或可以其他方式包含氮化矽。
參照圖10、圖11及圖15，可移除第二間隔件層123的一部分以形成第二間隔件圖案124（在步驟S50中示出）。因此，可形成凹槽區RS以局部地暴露出第三間隔件圖案126的底表面。凹槽區RS可為自第三間隔件圖案126的側壁朝閘極電極GE凹陷的區。可藉由選擇性蝕刻製程形成凹槽區RS。舉例而言，可藉由執行在抑制對第一間隔件圖案122及第三間隔件圖案126的蝕刻的同時對第二間隔件層123進行蝕刻的製程形成凹槽區RS。作為實例，可利用濕式清潔製程（wet cleaning process）來執行凹槽區RS的形成。在下文中，包含第一間隔件圖案122、第二間隔件圖案124及第三間隔件圖案126的結構將被稱為間隔件結構ST。
參照圖10、圖11及圖16，可自上部半導體層105生長第一半導體圖案141。可藉由對上部半導體層105的被暴露出的表面執行的選擇性磊晶製程來形成第一半導體圖案141（在步驟S60中示出）。在本發明概念的示例性實施例中，第一半導體圖案141的材料可依據參照圖1至圖9闡述的半導體圖案的種類而改變。第一半導體圖案141可填充凹槽區RS且可沿第三間隔件圖案126的側壁或者在第一方向D1上生長。作為實例，第一半導體圖案141可被形成為具有位於較金屬閘極電極層115的頂表面高的水平高度處的頂表面。
可藉由單個磊晶製程將第一半導體圖案141形成為具有台階式結構。因此，相較於藉由多個磊晶製程形成第一半導體圖案141的情形，可減少製程變化及製程複雜度。由於第一半導體圖案141被形成為具有相對小的厚度，因此上部半導體層105可使源極/汲極電極及源極/汲極區達成所期望的厚度或足夠的深度，此將在以下進行闡述。另外，相較於藉由多個磊晶製程形成第一半導體圖案141的情形，可減少在形成間隔件圖案的製程中可能發生的第一半導體圖案141的蝕刻損壞。
可對第一半導體圖案141及上部半導體層105執行第二離子植入製程IM2（在步驟S70中示出）。可使用具有與第一離子植入製程IM1的雜質類型相同類型的雜質來執行第二離子植入製程IM2。第二離子植入製程IM2可在較第一離子植入製程IM1的劑量條件高的劑量條件下執行。如此一來，可在第一半導體圖案141及上部半導體層105中形成源極/汲極區133。源極/汲極區133可被形成為具有大到足以使源極/汲極區133接觸上部半導體層105的底表面的深度。舉例而言，在源極/汲極區133與絕緣間隙填充層101之間可不設置有未經摻雜或本質區。源極/汲極區133可形成於對凹槽區RS進行填充的第一半導體圖案141的一些部分中。
參照圖17，可移除硬遮罩圖案119。可利用選擇性蝕刻製程來執行硬遮罩圖案119的移除。在移除硬遮罩圖案119期間，可將第二間隔件圖案124的上部部分與硬掩模圖案119一起移除。作為移除硬遮罩圖案119的結果，半導體閘極電極層117的頂表面可被暴露出。
參照圖18，可在第一半導體圖案141上形成源極/汲極電極151。源極/汲極電極151可由至少一種金屬-半導體化合物形成或可以其他方式包含至少一種金屬-半導體化合物。作為實例，源極/汲極電極151可由至少一種金屬矽化物材料（例如矽化鈦或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦或矽化鎳）。可藉由矽化製程（silicidation process）形成源極/汲極電極151。作為實例，形成源極/汲極電極151可包含在第一半導體圖案141上形成金屬層且執行熱處理製程（thermal treatment process）以形成金屬-半導體化合物。之後，可移除金屬層的剩餘部分。舉例而言，可以消耗第一半導體圖案141的上部部分的方式來執行源極/汲極電極151的形成。
可在半導體閘極電極層117的被暴露出的部分上形成接觸電極153。接觸電極153可由至少一種金屬-半導體化合物形成或可以其他方式包含至少一種金屬-半導體化合物。作為實例，接觸電極153可由至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）形成或可以其他方式包含至少一種金屬矽化物材料（例如矽化鈦及/或矽化鎳）。可藉由單個製程同時形成接觸電極153與源極/汲極電極151。之後，可執行形成圖1中所示元件的製程。
根據本發明概念的示例性實施例的半導體裝置可包含至少一個電晶體，所述至少一個電晶體被配置成具有與每一圖中或各圖的任意組合中的特徵相同的特徵。舉例而言，圖1、圖4、圖5、圖6、圖8及圖9所示電晶體可彼此進行組合。作為實例，圖4所示第六電晶體TR6與圖5所示第二電晶體TR2可形成於同一基板上，或者圖6所示第三電晶體TR3與圖8所示第四電晶體TR4可形成於同一基板上。在某些實施例中，圖1、圖4、圖5、圖6、圖8及圖9所示電晶體中的三個或更多個電晶體可一同形成於同一基板上。
根據本發明概念的示例性實施例，半導體裝置可被設置成包含具有期望的電性特性的電晶體。根據本發明概念的示例性實施例，可減少在製作半導體裝置的製程中的製程變化及複雜度。根據本發明概念的示例性實施例，可容易地形成具有各種臨限電壓的電晶體。
儘管在各圖及本說明書中已具體示出並闡述了本發明概念的示例性實施例，然而熟習此項技術者應理解，在不背離本揭露的精神及範圍的條件下，可對本文作出形式及細節上的改變。
10:基板 100:下部半導體層 101:絕緣間隙填充層 102:絕緣隔離圖案 105:上部半導體層 105a:第一上部半導體層 105b:第二上部半導體層 111:下部閘極絕緣層 113:上部閘極絕緣層 115:金屬閘極電極層 117:半導體閘極電極層 119:硬遮罩圖案 121:第一間隔件層 122:第一間隔件圖案 123:第二間隔件層 124、124a、124b:第二間隔件圖案 126:第三間隔件圖案 131:輕摻雜區 133:源極/汲極區/第一源極/汲極區 134:拾取雜質區 135:第一下部雜質區 136:第二源極/汲極區 137:第二下部雜質區 138:第三下部雜質區 141:第一半導體圖案 142:第二半導體圖案 143:第三半導體圖案 151:源極/汲極電極 153:接觸電極 154:拾取電極 156:第二源極/汲極電極 161:應力層 171:層間絕緣層 179:閘極絕緣部分 181:第一接觸件 182:第二接觸件 186:第一導電圖案 187:第二導電圖案 BR:背側偏壓區 D1:第一方向 D2:第二方向 GE:閘極電極 GE1:第一閘極電極 GE2:第二閘極電極 GE3:第三閘極電極 GE4:第四閘極電極 GE5:第五閘極電極 GI:閘極絕緣層 GI1:第一閘極絕緣層 GI2:第二閘極絕緣層 GI3:第三閘極絕緣層 GI4:第四閘極絕緣層 GI5:第五閘極絕緣層 GR:閘極區 IM1:第一離子植入製程 IM2:第二離子植入製程 LP:下部部分 P1、P2:部分 PP:突出部分 RS:凹槽區 S10、S11、S20、S30、S40、S50、S60、S70:步驟 SP:側壁部分 ST:間隔件結構 ST1:第一間隔件結構 ST2:第二間隔件結構 ST3:第三間隔件結構 ST4:第四間隔件結構 ST5:第五間隔件結構 t1、t2、t3、t4、t5:厚度 TR1:第一電晶體 TR2:第二電晶體 TR3:第三電晶體 TR4:第四電晶體 TR5:第五電晶體 TR6:第六電晶體 UP:上部部分 W1、W2、W3:厚度 WA、WB:長度
結合附圖閱讀以下詳細說明，將更完整地領會本揭露並更清楚地理解本揭露的諸多伴隨態樣，在附圖中：
圖1是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖2及圖3是示出圖1所示部分「P1」的放大圖。
圖4是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖5是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖6是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖7是圖6所示部分「P2」的放大圖。
圖8是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖9是示出根據本發明概念的示例性實施例的半導體裝置的剖視圖。
圖10及圖11是示出根據本發明概念的示例性實施例的製作半導體裝置的製程的流程圖。
圖12至圖18是示出根據本發明概念的示例性實施例的製作半導體裝置的方法的剖視圖。
10:基板
100:下部半導體層
101:絕緣間隙填充層
105:上部半導體層
122:第一間隔件圖案
124:第二間隔件圖案
126:第三間隔件圖案
131:輕摻雜區
133:源極/汲極區/第一源極/汲極區
141:第一半導體圖案
151:源極/汲極電極
153:接觸電極
161:應力層
171:層間絕緣層
181:第一接觸件
186:第一導電圖案
D1:第一方向
D2:第二方向
GE:閘極電極
GI:閘極絕緣層
P1:部分
ST:間隔件結構
t1、t2:厚度
TR1:第一電晶體

Claims (25)

  1. 一種半導體裝置，包含： 基板，包含依序堆疊的下部半導體層、絕緣間隙填充層及上部半導體層； 閘極結構，位於所述上部半導體層上； 源極/汲極電極，位於所述閘極結構的側壁上；以及 半導體圖案，位於所述源極/汲極電極與所述上部半導體層之間， 其中所述閘極結構包含閘極電極及間隔件結構， 其中所述間隔件結構包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案，且 其中所述半導體圖案延伸至位於所述第三間隔件圖案的底表面下方的區且連接至所述第二間隔件圖案。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述第二間隔件包含側壁部分及突出部分，所述側壁部分主要在與所述基板的頂表面垂直的方向上延伸，所述突出部分自所述側壁部分朝所述半導體圖案突出。
  3. 如申請專利範圍第1項所述的半導體裝置，其中所述半導體圖案的頂表面位於與所述第三間隔件圖案的所述底表面相等或較所述第三間隔件圖案的所述底表面高的水平高度處。
  4. 如申請專利範圍第3項所述的半導體裝置，其中所述半導體圖案包含： 下部部分，延伸至位於所述第三間隔件圖案的所述底表面下方的區；以及 上部部分，連接至所述第三間隔件圖案的側壁。
  5. 如申請專利範圍第3項所述的半導體裝置，其中所述半導體圖案在其中所述半導體圖案連接至所述第三間隔件圖案的區中具有台階式結構。
  6. 如申請專利範圍第1項所述的半導體裝置，其中所述第三間隔件圖案厚於所述第一間隔件圖案或所述第二間隔件圖案。
  7. 如申請專利範圍第1項所述的半導體裝置，其中所述上部半導體層薄於所述源極/汲極電極。
  8. 如申請專利範圍第1項所述的半導體裝置，更包含設置於所述上部半導體層及所述半導體圖案中的源極/汲極區， 其中所述源極/汲極區具有足以到達所述上部半導體層的底表面的深度。
  9. 如申請專利範圍第1項所述的半導體裝置，其中所述下部半導體層包含下部雜質區，所述下部雜質區設置於與所述絕緣間隙填充層相鄰的所述下部半導體層的上部部分中且不電性連接至所述源極/汲極區。
  10. 如申請專利範圍第9項所述的半導體裝置，更包含絕緣隔離圖案，所述絕緣隔離圖案穿透所述上部半導體層及所述絕緣間隙填充層且嵌入至所述下部半導體層的所述上部部分中，且 其中所述絕緣隔離圖案的底表面位於較所述下部雜質區的底表面低的水平高度處。
  11. 如申請專利範圍第1項所述的半導體裝置，更包含絕緣隔離圖案，所述絕緣隔離圖案穿透所述上部半導體層及所述絕緣間隙填充層且嵌入至所述下部半導體層的上部部分中，且 其中所述半導體裝置包含閘極區及背側偏壓區，所述閘極結構設置於所述閘極區中，所述背側偏壓區與所述閘極區間隔開且使得所述絕緣隔離圖案夾置於所述背側偏壓區與所述閘極區之間， 其中所述背側偏壓區包含： 拾取雜質區，設置於所述下部半導體層的上部部分中；以及 拾取電極，位於所述拾取雜質區上。
  12. 如申請專利範圍第1項所述的半導體裝置，其中所述絕緣間隙填充層薄於所述源極/汲極電極。
  13. 一種半導體裝置，包含： 基板，包含依序堆疊的下部半導體層、絕緣間隙填充層及上部半導體層； 閘極結構，位於所述上部半導體層上； 源極/汲極電極，位於所述閘極結構的側壁上；以及 半導體圖案，位於所述源極/汲極電極與所述上部半導體層之間， 其中所述閘極結構包含閘極電極及間隔件結構， 其中所述間隔件結構包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案，且 其中所述半導體圖案包含上部部分及下部部分，所述上部部分連接至所述第三間隔件圖案的側壁，所述下部部分在位於所述第三間隔件圖案的底表面下方的區中延伸且連接至所述第二間隔件圖案。
  14. 一種半導體裝置，包含： 基板，包含依序堆疊的下部半導體層、絕緣間隙填充層及上部半導體層；以及 第一電晶體及第二電晶體，位於所述基板上， 其中所述第一電晶體包含： 第一閘極結構，位於所述上部半導體上； 第一源極/汲極電極，位於所述第一閘極結構的側壁上；以及 第一半導體圖案，位於所述第一源極/汲極電極與所述上部半導體層之間， 其中所述第一閘極結構包含閘極電極及第一間隔件結構， 其中所述第一間隔件結構包含依序設置於所述閘極電極的側壁上的第一間隔件圖案、第二間隔件圖案及第三間隔件圖案，且 其中所述第一半導體圖案在位於所述第三間隔件圖案的底表面下方的區中延伸且接觸所述第二間隔件圖案。
  15. 如申請專利範圍第14項所述的半導體裝置，其中所述第二電晶體包含閘極絕緣層，所述閘極絕緣層設置於所述下部半導體層上且厚於所述絕緣間隙填充層。
  16. 如申請專利範圍第14項所述的半導體裝置，其中所述第二電晶體包含位於所述下部半導體層的上部部分中的源極/汲極區。
  17. 如申請專利範圍第14項所述的半導體裝置，其中所述第二電晶體包含第二間隔件結構，所述第二間隔件結構包含第一間隔件圖案、第二間隔件圖案及第三間隔件圖案， 其中所述第一電晶體的所述第二間隔件圖案包含在位於所述第三間隔件圖案下方的區中延伸的第一突出部分， 其中所述第二電晶體的所述第二間隔件圖案包含在位於所述第三間隔件圖案下方的區中延伸的第二突出部分，且 其中所述第二突出部分的長度小於所述第一突出部分的長度。
  18. 如申請專利範圍第14項所述的半導體裝置，其中所述第二電晶體包含： 第二閘極結構，位於所述上部半導體上； 第二源極/汲極電極，位於所述第二閘極結構的側壁上；以及 第二半導體圖案，位於所述第二源極/汲極電極與所述上部半導體層之間，且 其中所述第二半導體圖案包含與所述第一半導體圖案不同的材料。
  19. 如申請專利範圍第14項所述的半導體裝置，其中所述第一電晶體包含設置於與所述絕緣間隙填充層相鄰的所述下部半導體層的上部部分中的第一下部雜質區， 其中所述第二電晶體包含與所述絕緣間隙填充層相鄰地設置於所述下部半導體層的上部部分中的第二下部雜質區，且 其中所述第二下部雜質區的導電類型不同於所述第一下部雜質區的導電類型。
  20. 如申請專利範圍第14項所述的半導體裝置，其中所述第二電晶體包含： 第二閘極結構，位於所述上部半導體上； 第二源極/汲極電極，位於所述第二閘極結構的側壁上；以及 第二半導體圖案，位於所述第二源極/汲極電極與所述上部半導體層之間， 其中所述第二半導體圖案的厚度大於所述第一半導體圖案的厚度。
  21. 一種製作半導體裝置的方法，包含： 在基板上形成閘極電極，在所述基板中依序堆疊有下部半導體層、絕緣間隙填充層及上部半導體層； 在所述閘極電極的側壁上依序形成第一間隔件層及第二間隔件層； 對所述上部半導體層執行第一離子植入製程； 在所述第二間隔件層的側壁上形成第三間隔件圖案； 移除位於所述第三間隔件圖案的底表面下方的所述第二間隔件層的一部分，以形成凹槽區； 自所述上部半導體層生長第一半導體圖案，所述第一半導體圖案延伸至所述凹槽區；以及 對所述第一半導體圖案及所述上部半導體層執行第二離子植入製程， 其中所述第一離子植入製程是在形成所述第三間隔件圖案之前執行。
  22. 如申請專利範圍第21項所述的製作半導體裝置的方法，其中所述第一離子植入製程及所述第二離子植入製程被執行至與所述上部半導體層的底表面對應的深度。
  23. 如申請專利範圍第21項所述的製作半導體裝置的方法，更包含：在形成所述閘極電極之前，在所述下部半導體層的上部部分中形成下部雜質區。
  24. 如申請專利範圍第21項所述的製作半導體裝置的方法，其中所述第一離子植入製程是在形成所述第二間隔件層與形成所述第三間隔件圖案之間執行。
  25. 如申請專利範圍第21項所述的製作半導體裝置的方法，更包含：對所述第一間隔件層進行蝕刻以形成第一間隔件圖案， 其中所述第一離子植入製程是在對所述第一間隔件層進行所述蝕刻之前執行。
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US5714412A (en) * 1996-12-02 1998-02-03 Taiwan Semiconductor Manufacturing Company, Ltd Multi-level, split-gate, flash memory cell and method of manufacture thereof
JPH10335508A (ja) * 1997-05-28 1998-12-18 Sony Corp 半導体装置の製造方法
KR100347544B1 (ko) * 1999-02-13 2002-08-07 주식회사 하이닉스반도체 반도체 소자의 접합 제조 방법
KR20010084592A (ko) * 2000-02-28 2001-09-06 윤종용 반도체 소자의 제조방법
EP1383166A3 (en) * 2002-07-16 2006-10-11 Interuniversitair Microelektronica Centrum ( Imec) FIN field effect transistor device and a method for manufacturing such device
TW588459B (en) * 2003-06-09 2004-05-21 United Microelectronics Corp Metal-oxide-semiconductor transistor with selective epitaxial growth films
US20050048732A1 (en) 2003-08-26 2005-03-03 International Business Machines Corporation Method to produce transistor having reduced gate height
KR100555569B1 (ko) * 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
KR100673018B1 (ko) * 2005-12-09 2007-01-24 삼성전자주식회사 이이피롬 및 그 제조 방법
WO2008102448A1 (ja) * 2007-02-22 2008-08-28 Fujitsu Microelectronics Limited 半導体装置と半導体装置の製造方法
US8609497B2 (en) 2010-02-12 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of dual EPI process for semiconductor device
US8574970B2 (en) 2010-09-15 2013-11-05 International Business Machines Corporation Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain
US9502418B2 (en) 2014-10-02 2016-11-22 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
TWI594420B (zh) * 2015-01-13 2017-08-01 Xinnova Tech Ltd Non-volatile memory components and methods of making the same
FR3042907B1 (fr) * 2015-10-22 2017-12-08 St Microelectronics Crolles 2 Sas Procede de fabrication d'un dispositif a transistors mos
US9704971B2 (en) 2015-12-09 2017-07-11 Globalfoundries Inc. Epi facet height uniformity improvement for FDSOI technologies
US9553093B1 (en) 2015-12-11 2017-01-24 International Business Machines Corporation Spacer for dual epi CMOS devices
KR102435521B1 (ko) * 2016-02-29 2022-08-23 삼성전자주식회사 반도체 소자
US9806170B1 (en) 2016-05-11 2017-10-31 Globalfoundries Inc. Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI
US9997409B1 (en) 2017-04-07 2018-06-12 International Business Machines Corporation Fabricating contacts of a CMOS structure

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US20200303512A1 (en) 2020-09-24
US10937882B2 (en) 2021-03-02
TWI818097B (zh) 2023-10-11

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