TW202027177A - 形成封裝結構的方法 - Google Patents

形成封裝結構的方法 Download PDF

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TW202027177A
TW202027177A TW108124122A TW108124122A TW202027177A TW 202027177 A TW202027177 A TW 202027177A TW 108124122 A TW108124122 A TW 108124122A TW 108124122 A TW108124122 A TW 108124122A TW 202027177 A TW202027177 A TW 202027177A
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Taiwan
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package
adhesive
die
cover
substrate
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TW108124122A
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English (en)
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文興 洪
胡憲斌
林宗澍
陳琮瑜
魏文信
勞禎祥
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台灣積體電路製造股份有限公司
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Publication of TW202027177A publication Critical patent/TW202027177A/zh

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Abstract

一種封裝式半導體元件及一種用於形成封裝式半導體元件的方法及裝置。在一實施例中，一種方法包括：將元件晶粒接合到基底的第一表面；在所述基底的所述第一表面上沉積黏合劑；在所述元件晶粒的與所述基底相對的表面上沉積熱介面材料；在所述元件晶粒及所述基底之上放置蓋，所述蓋接觸所述黏合劑及所述熱介面材料；對所述蓋及所述基底施加鉗緊力；以及在施加所述鉗緊力時，將所述黏合劑及所述熱介面材料固化。

Description

形成封裝結構的方法
本發明實施例是有關於一種形成封裝結構的方法。
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積集密度的持續提高，半導體行業已經歷快速增長。在很大程度上，積集密度的此種提高來自於最小特徵尺寸（minimum feature size）的重複減小，此使得更多元件能夠整合在一定的區域中。
隨著對縮小電子元件的需求的增長，需要更小且更具創造性的半導體晶粒封裝技術。這種封裝系統的一實例是疊層封裝（Package-on-Package，PoP）技術。在PoP元件中，頂部半導體封裝被堆疊在底部半導體封裝的頂部上，以提供高整合水準及元件密度。另一個實例是基底上晶圓上晶片（Chip-On-Wafer-On-Substrate，CoWoS）結構，其中半導體晶片被貼合到晶圓（例如，中介板）以形成晶圓上晶片（Chip-On-Wafer，CoW）結構。CoW結構接著被貼合到基底（例如，印刷電路板（printed circuit board，PCB））以形成CoWoS結構。這些封裝技術及其他先進封裝技術使得能夠生產出具有增強的功能性及小的佔用面積（footprint）的半導體元件。
本發明實施例提供一種形成封裝結構的方法，包括：將元件晶粒接合到基底的第一表面；在所述基底的所述第一表面上沉積黏合劑；在所述元件晶粒的與所述基底相對的表面上沉積熱介面材料；在所述元件晶粒及所述基底之上放置蓋，所述蓋接觸所述黏合劑及所述熱介面材料；對所述蓋及所述基底施加鉗緊力；以及在施加所述鉗緊力時，將所述黏合劑及所述熱介面材料固化。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號以及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例以及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括元件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
各種實施例提供用於形成三維積體電路元件（例如，基底上晶圓上晶片（CoWoS）元件）的改善的方法、用於執行所述方法的設備以及通過所述方法而形成的三維積體電路（3DIC）元件。所述方法包括在用於將黏合劑及熱介面材料（TIM）固化的固化製程期間對3DIC的蓋及基底施加鉗緊力，這使得基底及安置在所述基底上的晶圓上晶片（CoW）以熱及機械的方式貼合到蓋。在固化製程期間鉗緊3DIC有助於減小及控制黏合劑及TIM的厚度，這會使3DIC的厚度減小且使3DIC中的分層（delamination）及晶粒開裂問題減少。這會改善3DIC的熱穩定性及機械穩定性、減少3DIC中的缺陷、改善3DIC的熱性能，進而增加3DIC的產量。
圖1至圖4是根據各種實施例的製造三維積體電路（3DIC）封裝（例如，基底上晶圓上晶片（CoWoS）封裝100）的中間階段的剖視圖。在各種實施例中，CoWoS封裝100可包括晶片堆疊，例如疊層邏輯（logic-on-logic，LoL）、邏輯上記憶體（memory-on-logic，MoL）等。圖1繪示出接合到基底104的晶圓上晶片（CoW）封裝102。CoW封裝102可包括安置在兩個低功耗晶粒108之間的高功耗晶粒106。高功耗晶粒106及低功耗晶粒108可為晶粒堆疊且可稱作晶片。高功耗晶粒106消耗相對高的功率且因此與低功耗晶粒108相比產生相對大的熱量。舉例來說，高功耗晶粒106可消耗介於約100瓦（W）到約1,000 W的功率，而低功耗晶粒108可消耗介於約10 W到約100 W的功率。高功耗晶粒106所消耗的功率對低功耗晶粒108所消耗的功率的比率可介於約10到約30，例如約16。高功耗晶粒106可為處理器，例如中央處理器（central processing unit，CPU）、圖形處理單元（graphics processing unit，GPU）等。低功耗晶粒108可為記憶體晶粒，例如高頻寬記憶體（high bandwidth memory，HBM）、記憶體立方（memory cube）、記憶體堆疊（memory stack）等。儘管圖1繪示出CoW封裝102具有一個高功耗晶粒106及兩個低功耗晶粒108，然而其他實施例可包括任意數目的高功耗晶粒106以及/或低功耗晶粒108。
高功耗晶粒106及低功耗晶粒108可被包括模制化合物的包封體120所環繞。可將高功耗晶粒106、低功耗晶粒108及包封體120平坦化，進而使得高功耗晶粒106的頂表面、低功耗晶粒108的頂表面及包封體120的頂表面齊平。由於包封體120中可不產生熱，因此包封體120附近的區域的散熱需求可較低。
將高功耗晶粒106及低功耗晶粒108接合到封裝元件110的頂表面。可通過多個第一連接件112將高功耗晶粒106及低功耗晶粒108電耦合到且機械耦合到封裝元件110，多個第一連接件112可為導電凸塊、微凸塊、金屬柱等。儘管未單獨繪示，然而可在高功耗晶粒106及低功耗晶粒108與封裝元件110之間形成環繞第一連接件112的一種或多種底部填充材料（與底部填充材料118分隔開，如以下所論述）。
封裝元件110可為中介板基底，其可為例如矽基底等半導體基底。封裝元件110也可由例如矽鍺、矽碳等另一種半導體材料形成。根據一些實施例，在封裝元件110的表面處形成例如電晶體（未單獨繪示）等主動元件。也可在封裝元件110中形成例如電阻器以及/或電容器等被動元件（未單獨繪示）。根據本發明的替代性實施例，封裝元件110可為半導體基底或介電質基底，且各個封裝元件110中可不包括主動元件。根據這些實施例，封裝元件110可包括或可不包括形成在其中的被動元件。
可形成從封裝元件110的頂表面延伸到封裝元件110中的穿孔114。在其中封裝組件110為矽基底的實施例中，穿孔114可稱作基底穿孔或矽穿孔。在一些實施例中，封裝元件110可包括形成在用於電性連接到積體電路元件（如果有的話）的基底之上的內連線結構（未單獨繪示）以及CoW封裝102的穿孔114。內連線結構可包括多個介電層、形成在介電層中的金屬線及形成在金屬線之間並將金屬線內連、上覆在金屬線上且在金屬線之下的通孔。根據一些實施例，介電層30可由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合以及/或其多層形成。作為另外一種選擇，介電層可包括一種或多種具有低介電常數（k值）的低k介電層。舉例來說，介電層中的低k介電材料的k值可低於約3.0或低於約2.5。
將CoW封裝102的封裝元件110接合到基底104的頂表面。可通過多個第二連接件116將封裝元件110電耦合到且機械耦合到基底104，多個第二連接件116可為導電凸塊、微凸塊、金屬柱等。可在封裝元件110與基底104之間形成環繞第二連接件116的底部填充材料118。底部填充材料118也可在高功耗晶粒106及低功耗晶粒108與封裝元件110之間延伸而環繞第一連接件112。
基底104可為封裝基底，其可為印刷電路板（PCB）等。基底104可包括一個或多個介電層以及例如導電線及通孔等導電特徵。在一些實施例中，基底104可包括穿孔、主動元件、被動元件等。基底104可進一步包括形成在基底104的上表面及下表面處的導電接墊。可將第二連接件116耦合到位於基底104的頂表面處的導電接墊。
在圖2中，在基底104上且在包封體120、高功耗晶粒106及低功耗晶粒108之上分別沉積黏合劑122及熱介面材料（TIM）124。黏合劑122可為環氧樹脂（epoxy）、矽樹脂、膠水等。黏合劑122可具有比TIM 124好的黏合能力。黏合劑122可具有介於約1 W/m·K到約3 W/m·K、低於約0.5 W/m·K等的導熱係數（thermal conductivity）。可將黏合劑122定位成使得散熱特徵（例如，圖3中所繪示的蓋126）能夠貼合在CoW封裝102周圍。因此，在一些實施例中，可將黏合劑122安置在CoW封裝102的周界周圍或者甚至將黏合劑122安置成包圍CoW封裝102。
TIM 124可為具有良好導熱係數的聚合物，所述良好導熱係數可介於約3 W/m·K到約5 W/m·K。在一些實施例中，TIM 124可包括具有導熱填料的聚合物。導熱填料可使TIM 124的有效導熱係數增大到介於約10 W/m·K到約50 W/m·K或50 W/m·K以上。可應用的導熱填料材料可包括氧化鋁、氮化硼、氮化鋁、鋁、銅、銀、銦、其組合等。在其他實施例中，TIM 124可包括其他材料，例如包括銀、銦膏體等的金屬系材料或焊料系材料。在更進一步的實施例中，TIM 124可包括膜系材料或片材系材料，例如包括合成碳奈米管（synthesized carbon nanotube，CNT）的片材系材料或者具有垂直取向的石墨填料的導熱片材。儘管TIM 124被示為在高功耗晶粒106及低功耗晶粒108之上延伸的連續TIM，然而在其他實施例中，TIM 124可物理地斷開。舉例來說，可在鄰近晶粒（例如，高功耗晶粒106以及/或低功耗晶粒108）之間的TIM 124中安置空氣間隙（air gap）以減少所述晶粒之間的側向熱互作用。在一些實施例中，可在沉積黏合劑122之後沉積TIM 124；然而，也可在沉積黏合劑122之前沉積TIM 124。
在圖3中，將蓋126貼合到基底104及CoW封裝102以形成CoWoS封裝100。蓋126可被貼合以保護CoW封裝102及基底104，並使從CoW封裝102產生的熱擴散到更大的區域，從而消散掉來自CoW封裝102的熱。蓋126可由例如鋼、不銹鋼、銅、鋁、其組合等具有高導熱係數的材料形成。在一些實施例中，蓋126可為塗布有另一種金屬（例如金）的金屬。蓋126可由具有介於約100 W/m·K到約400 W/m·K（例如，約400 W/m·K）的導熱係數的材料形成。蓋126覆蓋且環繞CoW封裝102。在一些實施例中，蓋126為單一連續材料。在其他實施例中，蓋126可包括多個片件（piece），其可為相同材料或不同材料。
黏合劑122具有比TIM 124大的黏合能力，但具有比TIM 124低的導熱係數。因此，將黏合劑122安置在蓋126與基底104之間、CoW封裝102的周邊周圍以將蓋126黏合到基底104。將TIM 124安置在高功耗晶粒106與低功耗晶粒108上、高功耗晶粒106及低功耗晶粒108與蓋126之間以將來自高功耗晶粒106及低功耗晶粒108的熱消散到蓋126。
在圖4中，使用鉗夾130在蓋126與基底104之間施加鉗緊力。鉗夾130包括下部板132、上部板134、緊固件136及彈簧138。在用於將黏合劑122以及/或TIM 124固化的鉗緊固化製程期間，可使用鉗夾130施加介於約3千克力（kgf）到約100 kgf、介於約3 kgf到約20 kgf、介於約20 kgf到約50 kgf或者大於50 kgf的鉗緊力。在蓋126與基底104被鉗緊之後，黏合劑122可具有介於約100微米（µm）到約200 µm、介於約200 µm到約300 µm或者小於約100 µm的厚度T1 ，且TIM 124可具有介於約30 µm到約60 µm、介於約60 µm到約150 µm或者小於約200 µm的厚度T2 。
當蓋126與基底104被鉗緊，可通過對黏合劑122及TIM 124施加熱來固化黏合劑122及TIM 124。在一些實施例中，可通過將被鉗緊的CoWoS封裝100放置在固化烤箱中來固化黏合劑122及TIM 124。在鉗夾130施加鉗緊力時，可在介於100˚C到約260˚C的溫度下、介於約100˚C到約150˚C的溫度下、介於約150˚C到約260˚C的溫度下或任何其他適合的溫度下將黏合劑122及TIM 124固化達介於約20秒到約2小時、介於約30分鐘到約2小時或任何其他適合時間。
下部板132及上部板134可由例如鋁、不銹鋼、銅、鍍鎳銅、銅鎢、碳化鋁矽（aluminum silicon carbide）等材料形成。在一些實施例中，下部板132可由與上部板134相同的材料或與上部板134不同的材料形成。緊固件136可為螺釘型緊固件、推針型緊固件、磁性緊固件、彈簧鎖緊固件或任何其他類型的緊固件。可使用緊固件136及彈簧138來控制施加在下部板132與上部板134之間的鉗緊力。舉例來說，可通過提供具有不同彈簧常量（spring constant）的彈簧來變更鉗緊力，從而為螺釘型緊固件等提供不同的扭矩。在一些實施例中，可在下部板132與基底104之間以及/或上部板134與蓋126之間安置分佈板。分佈板可由彈性材料、橡膠材料等形成且可用以將鉗夾施加的力均勻地分佈在基底104的表面以及/或蓋126的表面。
在整個用於固化黏合劑122以及/或TIM 124的鉗緊固化製程中使用鉗夾130施加鉗緊力會使黏合劑122及TIM 124的接合線厚度（bond line thickness，BLT）減小、改善黏合劑122及TIM 124的厚度均勻性並提高TIM 124的覆蓋率。這些改善降低了蓋126將從CoW封裝102及基底104分層的可能性。因此，根據上述方法而形成的半導體封裝具有減小的厚度、改善的熱性能、提高的可靠性及減少的缺陷。
圖5A及圖5B是根據其中緊固件136包括推針緊固件的實施例的鉗夾130的剖視圖。如圖5A中所示，下部板132包括推針孔180，推針孔180具有第一寬度與大於第一寬度的第二寬度，第一寬度鄰近下部板132的頂表面，而第二寬度鄰近下部板132的底表面。推針孔180可完全延伸穿過下部板132，使得緊固件136可被移除。在實施例中，緊固件136包括推針緊固件，緊固件136包括具有梯形形狀且中空的推針頭182。如圖5B中所示，推針頭182的形狀使得推針頭182能夠在被按壓到推針孔180中時變形且在推針頭182被推按到下部板132的具有第二寬度的部分中時緊固。緊固件136可接著通過一起推按推針頭182的相對兩側並將推針頭182經由推針孔180往回推按而被從下部板132移除。按壓板（未單獨繪示）可同時按壓在若干個鉗夾130的緊固件上，以同時鉗緊若干個CoWoS封裝100。
圖6是根據其中上部板134包括一個或多個荷重元184的實施例的鉗夾130的剖視圖。在圖6中所示的實施例中，荷重元184安置在上部板134中且檢測上部板134與蓋126之間的力；然而，在其他實施例中，荷重元184可安置在下部板132中且可檢測下部板132與基底104之間的力。在更進一步的實施例中，荷重元184可包括在上部板134及下部板132二者中。荷重元184可用於判斷施加到CoWoS封裝100的力是否處於期望範圍內（例如，介於約2 kgf到約20 kgf或介於約20 kgf到約100 kgf）。荷重元184可與螺釘型緊固件136結合使用。如果荷重元184檢測到力過低，則螺釘型緊固件136可被扭轉以對CoWoS封裝100施加額外的力，且如果荷重元184檢測到力過高，則螺釘型緊固件136可被扭轉以對CoWoS封裝100施加更少的力。此外，螺釘型緊固件136可使用具有數位輸出的扭矩驅動器（torque driver）來扭轉，進而使得螺釘型緊固件136可扭轉到一致的扭矩。荷重元184可檢測介於約5 kgf到約100 kgf或介於約100 kgf到約200 kgf的力。在上部板134以及/或下部板132中可安置有任意數目的荷重元184。荷重元184可被安置成鄰近緊固件136以判斷各別緊固件是否需要被扭轉以對CoWoS封裝100施加更多或更少的力。
圖7A至圖9B繪示為可包括在CoWoS封裝100中的各種特徵以防止缺陷並提高可靠性。所述各種特徵可結合針對圖4至圖6所論述的鉗緊固化製程而在CoWoS封裝100中使用。圖7A及圖7B分別是CoWoS封裝100的其中密封環140被貼合到基底104且黏合劑122被放置在密封環140內的實施例的剖視圖及俯視圖。如圖7A及圖7B中所示，密封環140可包括外部部分及內部部分，外部部分包圍黏合劑122的外直徑，而內部部分安置在黏合劑122與CoW封裝102之間並環繞黏合劑122的內直徑。密封環140的外部部分防止黏合劑溢出蓋126的邊緣，黏合劑溢出蓋126的邊緣可能會造成外觀缺陷及其他缺陷。如圖7A中所示，密封環140的內部部分可在側向上安置在蓋126的內側邊緣內。密封環140的內部部分的定位可使得黏合劑能夠在蓋126被鉗緊時向上擴散到蓋126的內邊緣的垂直部分，這可增大蓋126與基底104之間的黏合。在一些實施例中，密封環140可僅包括外部部分。密封環140可由彈性材料、橡膠材料等形成。密封環140可具有介於約50 µm到約400 µm（例如，約100 µm）的高度及介於約50 µm到約200 µm（例如，約100 µm）的厚度。
圖8是CoWoS封裝100的其中在蓋126與基底104之間安置有間隔壁142的實施例。間隔壁142可在將蓋126鉗緊到基底104之前貼合到基底104、蓋126以及/或CoW封裝102。在一些實施例中，間隔壁142可包括在黏合劑122以及/或TIM 124中。間隔壁142可被構型為立方體、球體或任何其他適合的形狀。間隔壁142可具有介於約0.5毫米（mm）到約2 mm（例如，約1 mm）的長度/直徑。間隔壁142可由彈性材料、橡膠材料、焊料材料（例如，焊球、焊點或焊條）或者膜型材料或片材型材料（例如，多孔銅片材（perforated copper sheet）、多孔石墨片材（perforated graphite sheet）等）形成。
間隔壁142可用於控制黏合劑122及TIM 124的接合線厚度。將黏合劑122以及/或TIM 124形成得過薄可使黏合劑122及TIM 124出現例如開裂、分層等缺陷。間隔壁142防止黏合劑122及TIM 124在鉗緊固化製程期間變得過薄，藉此防止缺陷並提高包括間隔壁142的CoWoS封裝100的可靠性。
圖9A及圖9B是CoWoS封裝100的其中蓋126中包括緩衝特徵（relief featrue）144的實施例。如圖9A中所示，緩衝特徵144可為形成在蓋126中的凹槽（groove）、溝槽（trench）等。緩衝特徵144可被構型為條、同心正方形、同心圓，或者在俯視圖中具有任何其他形狀。由於蓋126、基底104及CoW封裝102之間存在熱膨脹係數（coefficient of thermal expansion，CTE）不匹配，因此在鉗緊固化製程期間且在CoWoS封裝100的整個使用壽命期間，蓋126、基底104及CoW封裝102可存在翹曲（warping）。緩衝特徵144可被設置成使得蓋126能夠變形且與由溫度變化等所造成的CoW封裝102以及/或基底104的任何翹曲共形。如此，通過包括緩衝特徵144，可防止由翹曲所造成的缺陷且提高CoWoS封裝100的可靠性。如在圖9A及圖9B中所進一步繪示，CoWoS封裝100可包括緩衝特徵144及密封環140二者。在又一些實施例中，CoWoS封裝100可包括密封環140、間隔壁142及緩衝特徵144的任意組合。
緩衝特徵144可在蓋126與TIM 124以及/或黏合劑122之間進一步提供增大的接觸面積。如圖9B中所示，緩衝特徵144可設置在CoW封裝102的散熱需求降低的區域上方（例如，包封體120上方）且黏合劑122可施加到CoW封裝102的與緩衝特徵144對應的區域。這可改善蓋126與CoW封裝102之間的黏合，而不會負面地影響CoW封裝102的散熱。在又一些實施例（未單獨繪示）中，緩衝特徵144可安置在CoW封裝102的散熱需求較高的區域上方（例如，高功耗晶粒106上方以及/或低功耗晶粒108上方），且TIM 124可施加到CoW封裝102的與緩衝特徵144對應的部分，從而增大從CoW封裝102到蓋126的散熱。因此，緩衝特徵144可增大蓋126對CoW封裝102的黏合且可改善CoW封裝102的散熱，從而防止缺陷並提高包括緩衝特徵144的CoWoS封裝100的可靠性。
圖9B進一步示出蓋126可在不同的區域中具有不同的厚度。舉例來說，蓋126的安置在高功耗晶粒106之上的部分所具有的厚度T3 可大於蓋126的安置在低功耗晶粒108之上的部分的厚度T4 。厚度T3 可介於約0.5 mm到約3 mm（例如，約1 mm），而厚度T4 可介於約0.5 mm到約3 mm（例如，約0.5 mm）。厚度T3 對厚度T4 的比率可介於約2到約6（例如，約2）。提供在不同區域中具有不同厚度的蓋126可有助於改善蓋126與基底104及CoW封裝102的可共形性，進一步防止缺陷並提高包括蓋126的CoWoS封裝100的可靠性。
圖10A至圖16是用於在CoW封裝102之上提供黏合劑122及TIM 124的各種圖案。所述各種圖案可用於改善蓋126與CoW封裝102之間的黏合及散熱。圖10A至圖16中所示的各種圖案化方案可與圖7A至圖9B中所說明的特徵及針對圖4所論述的鉗緊固化製程結合使用。
圖10A及圖10B分別是將黏合劑122施加在安置有包封體120在其中的CoW封裝102的部分之上並將TIM 124施加在安置有高功耗晶粒106及低功耗晶粒108在其中的CoW封裝102的部分之上的實施例的剖視圖及俯視圖。如前面所論述，高功耗晶粒106及低功耗晶粒108可產生熱，而包封體120可不產生熱。如此，高功耗晶粒106及低功耗晶粒108附近的產熱需求較大，且包封體120附近的產熱需求較低。在包封體120之上提供黏合劑122並在高功耗晶粒106及低功耗晶粒108之上提供TIM 124會增大蓋126與CoW封裝102之間的黏合，同時為高功耗晶粒106及低功耗晶粒108提供散熱。
圖11至圖13是其中黏合劑122及TIM 124（統稱為蓋貼合材料150）以從鄰近CoW封裝102的一個邊緣延伸到鄰近CoW封裝102的相對邊緣的蛇行圖案而在CoW封裝102之上進行分配的實施例。蓋貼合材料150可以任意數目的行（例如，介於10行到30行，或者19行）進行分配。蓋貼合材料150的奇數行可內連，且蓋貼合材料150的偶數行斷開。如圖11至圖13中所示，任意數目的偶數行（例如，5個中間偶數行（圖11）、7個中間偶數行（圖12）或9個中間偶數行（圖13））可包括黏合劑122，而蓋貼合材料的其餘部分包括TIM 124。黏合劑122也可在基底104的周界周圍進行分配。這些實施例可用於改善蓋126與CoW封裝102之間的黏合，同時為高功耗晶粒106及低功耗晶粒108提供散熱。
圖14至圖16是其中黏合劑122及TIM 124（統稱為蓋貼合材料150）以若干個蛇行圖案而在CoW封裝102之上進行分配的實施例。蓋貼合材料150可以從高功耗晶粒106的邊緣延伸到高功耗晶粒106的相對邊緣的第一蛇行圖案152及從低功耗晶粒108的邊緣延伸到低功耗晶粒108的相對邊緣的第二蛇行圖案154而在CoW封裝102之上進行分配。蓋貼合材料150可以任意數目的行（例如，介於10行到30行，或者19行）進行分配。蓋貼合材料150的奇數行可內連，且蓋貼合材料150的偶數行斷開。如圖14中所示，第二蛇行圖案154可包括黏合劑122，而第一蛇行圖案152包括TIM 124。因此，黏合劑122可在低功耗晶粒108及包封體120之上進行分配，且TIM 124可在高功耗晶粒106之上進行分配。在圖15中，第二蛇行圖案154可包括黏合劑122，且第一蛇行圖案152可包括TIM 124，第一蛇行圖案152中的一定數目的偶數行（例如，3個偶數行）包括黏合劑122。因此，黏合劑122可在低功耗晶粒108、包封體120以及高功耗晶粒106的中間部分之上進行分配，且TIM 124可在高功耗晶粒106之上進行分配。在圖16中，第一蛇行圖案152及第二蛇行圖案154可包括TIM 124，第一蛇行圖案152及第二蛇行圖案154的中間行及外側行包括黏合劑122。因此，黏合劑122可在包封體120以及高功耗晶粒106的中間部分及邊緣部分之上進行分配，且TIM 124可在高功耗晶粒106及低功耗晶粒108之上進行分配。黏合劑122也可在基底104的周界周圍進行分配。可使用任何其他適合的圖案在CoW封裝102之上分配黏合劑122及TIM 124，以在CoW封裝102及基底104與蓋126之間提供黏合，同時滿足高功耗晶粒106及低功耗晶粒108的散熱需求。這些實施例可用於改善蓋126與CoW封裝102之間的黏合，同時為高功耗晶粒106及低功耗晶粒108提供散熱。
圖17A及圖17B是根據實施例的夾具160的分解透視圖。夾具160可用於在鉗緊固化製程期間鉗緊多個CoWoS封裝100。如圖17A及圖17B中所示，夾具160包括下部板132、下部船式托盤（boat tray）164及上部板134。儘管上部板134被例示為對於每一CoWoS封裝100來說為單獨的板，然而上部板134中的每一者可用以鉗緊多個CoWoS封裝100。上部板134包括緊固件136。緊固件136可為螺釘型緊固件、推針型緊固件、磁性緊固件、彈簧鎖緊固件或適合於在鉗緊固化製程期間將上部板134緊固到下部板132的任何其他類型的緊固件。緊固件136可安置在上部板134或下部板132上。緊固件136可使用按壓板等而自動緊固（例如，通過機器人螺釘進給自動化（robotic screw feed automation））。
下部板包括鉗夾導銷162、緊固件接納孔168及封裝平臺170。鉗夾導銷162可用於將上部板134及下部船式托盤164與下部板132對準。緊固件接納孔168可用於接納緊固件136且可為帶螺紋的、可為磁性的或可包括其他特徵以固定緊固件136。在鉗緊固化製程期間，CoWoS封裝100可放置在封裝平臺170上。下部板132可由例如鋁、不銹鋼、銅、鍍鎳銅、銅鎢、碳化鋁矽等熱傳導材料形成。如圖17A中所示，各種封裝平臺170可安置在單一下部板132上。下部板132上可安置有任意數目的封裝平臺170，所述任意數目的封裝平臺170以任意數目的行及列（例如2行×4列）進行排列。
下部船式托盤164可用於將CoWoS封裝100與下部板132對準。舉例來說，如圖17A及圖17B中所示，下部船式托盤164可包括封裝導銷166，封裝導銷166可用於將CoWoS封裝100與封裝平臺170對準。下部船式托盤164可具有介於約1 mm到約2 mm（例如，約1.2 mm）的厚度。在一些實施例中，下部船式托盤164可用作下部板132與上部板134之間的間隔壁。在一些實施例中，下部船式托盤164的特徵可被整合到下部板132中，進而使得下部船式托盤164及下部板132包括單一整合材料。
在封裝平臺170上或在上部板134與CoWoS封裝100之間可安置有一個或多個分佈板（未單獨繪示）。分佈板可由彈性材料、橡膠材料等形成且可用以將在鉗緊固化製程期間施加的力均勻地分佈在CoWoS封裝100表面上。
圖17B是根據實施例的夾具160的局部裝配透視圖。如圖17B中所示，下部船式托盤164可使用鉗夾導銷162及封裝平臺170而與下部板132對準。封裝導銷166用於將CoWoS封裝100與封裝平臺170對準。使用夾具160來鉗緊CoWoS封裝100使得多個CoWoS封裝100能夠同時被鉗緊並經歷鉗緊固化製程，這會使成品CoWoS封裝100的產量增大。另外，使用夾具160而固化的CoWoS封裝100可經歷以上參照圖4所論述的鉗緊固化且具有減小的厚度、改善的熱性能、提高的可靠性及減少的缺陷。
根據實施例，一種方法包括：將元件晶粒接合到基底的第一表面；在所述基底的所述第一表面上沉積黏合劑；在所述元件晶粒的與所述基底相對的表面上沉積熱介面材料；在所述元件晶粒及所述基底之上放置蓋，所述蓋接觸所述黏合劑及所述熱介面材料；對所述蓋及所述基底施加鉗緊力；以及在施加所述鉗緊力時，將所述黏合劑及所述熱介面材料固化。在實施例中，在沉積所述熱介面材料之前沉積所述黏合劑。在實施例中，將所述黏合劑及所述熱介面材料固化20秒到2小時。在實施例中，在100˚C到150˚C的溫度下，將所述黏合劑及所述熱介面材料固化。在實施例中，所述鉗緊力介於3 kgf到100 kgf。在實施例中，施加所述鉗緊力包括：將所述蓋、所述元件晶粒及所述基底放置在上部板與下部板之間；以及在所述上部板與所述下部板之間緊固多個緊固件。在實施例中，緊固所述多個緊固件包括扭轉多個螺釘型緊固件。在實施例中，所述方法進一步包括在所述元件晶粒的與所述基底相對的所述表面上沉積所述黏合劑。
根據另一實施例，一種半導體元件包括：基底；元件晶粒，接合到所述基底的第一表面，所述元件晶粒被包封體環繞；第一黏合劑，安置在所述元件晶粒的相對兩側上的所述基底的所述第一表面上，所述第一黏合劑與所述元件晶粒分隔開；第二黏合劑，安置在所述元件晶粒的與所述基底相對的表面上，所述第二黏合劑接觸所述包封體；熱介面材料，安置在所述元件晶粒的與所述基底相對的所述表面上，所述熱介面材料接觸所述元件晶粒；蓋，通過所述第一黏合劑而接合到所述基底且通過所述熱介面材料及所述第二黏合劑而接合到所述元件晶粒；以及密封環，安置在所述第一黏合劑的相對兩側上且從所述蓋延伸到所述基底。在實施例中，所述第一黏合劑接觸所述蓋的底表面且所述蓋的內側壁與所述底表面垂直。在實施例中，所述半導體元件進一步包括將間隔壁安置在所述第一黏合劑及所述熱介面材料中，所述間隔壁將所述蓋與所述基底及所述元件晶粒分隔開。在實施例中，所述蓋進一步包括緩衝特徵用以使得所述蓋能夠變形，所述緩衝特徵安置在所述包封體之上，所述第二黏合劑延伸到所述緩衝特徵中。在實施例中，所述元件晶粒包括高功耗晶粒，所述半導體元件進一步包括鄰近所述高功耗晶粒的低功耗晶粒，所述蓋在所述高功耗晶粒之上具有第一厚度且在所述低功耗晶粒之上具有第二厚度，且所述第一厚度大於所述第二厚度。在實施例中，所述元件晶粒包括高功耗晶粒，所述半導體元件進一步包括鄰近所述高功耗晶粒的低功耗晶粒，所述熱介面材料安置在所述高功耗晶粒與所述蓋之間，且所述第二黏合劑安置在所述低功耗晶粒與所述蓋之間。
根據又一實施例，一種裝置包括：下部板，所述下部板包括多個封裝平臺以及多個導銷，所述多個封裝平臺用以固持多個半導體封裝；船式托盤，安置在所述下部板上，所述船式托盤與所述多個封裝平臺及所述多個導銷對準，所述船式托盤包括多個封裝導銷，所述多個封裝導銷用以將所述多個半導體封裝與所述多個封裝平臺對準；多個上部板，所述多個上部板中的每一者利用所述導銷而與所述多個封裝平臺中的每一者對準；以及多個緊固件，在所述下部板與所述多個上部板之間施加鉗緊力。在實施例中，所述多個緊固件包括螺釘型緊固件。在實施例中，所述多個緊固件包括推針型緊固件。在實施例中，所述裝置進一步包括安置在所述多個封裝平臺與所述多個上部板之間的多個分佈板，所述多個分佈板用以在所述多個半導體封裝的表面上均勻地分佈所述鉗緊力。在實施例中，所述多個分佈板包括彈性材料或橡膠材料。在實施例中，所述多個上部板及所述下部板包括鋁、不銹鋼、銅、鍍鎳銅、銅鎢或碳化鋁矽。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的以及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100:基底上晶圓上晶片（CoWoS）封裝 102:晶圓上晶片（CoW）封裝 104:基底 106:高功耗晶粒 108:低功耗晶粒 110:封裝組件 112:第一連接件 114:穿孔 116:第二連接件 118:底部填充材料 120:包封體 122:黏合劑 124:熱介面材料（TIM） 126:蓋 130:鉗夾 132:下部板 134:上部板 136:緊固件 138:彈簧 140:密封環 142:間隔壁 144:緩衝特徵 150:蓋貼合材料 152:第一蛇行圖案 154:第二蛇行圖案 160:夾具 162:鉗夾導銷 164:下部船式托盤 166:封裝導銷 168:緊固件接納孔 170:封裝平臺 180:推針孔 182:推針頭 184:荷重元 T1、T2、T3、T4:厚度
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖4是根據一些實施例的用於三維積體電路（three-dimensional integrated circuit，3DIC）鉗緊固化製程（clamped curing process）的剖視圖。 圖5A及圖5B是根據一些實施例的包括推針緊固件的鉗夾的剖視圖。 圖6是根據一些實施例的包括荷重元（load cell）的鉗夾的剖視圖。 圖7A及圖7B分別是根據一些實施例的包括密封環的3DIC的剖視圖及俯視圖。 圖8是根據一些實施例的包括間隔壁的3DIC的剖視圖。 圖9A及圖9B是根據一些實施例的包括緩衝特徵（relief feature）的3DIC的剖視圖。 圖10A至圖16是根據一些實施例的包括在3DIC中的黏合劑及熱介面材料（thermal interface material，TIM）的替代性配置的各種圖。 圖17A及圖17B是根據一些實施例的用以鉗緊3DIC的夾具（jig）的透視圖。
100:基底上晶圓上晶片(CoWoS)封裝
102:晶圓上晶片(CoW)封裝
104:基底
106:高功耗晶粒
108:低功耗晶粒
110:封裝組件
112:第一連接件
114:穿孔
116:第二連接件
118:底部填充材料
120:包封體
122:黏合劑
124:熱介面材料(TIM)
126:蓋
130:鉗夾
132:下部板
134:上部板
136:緊固件
138:彈簧
T1、T2:厚度

Claims (1)

  1. 一種形成封裝結構的方法，包括： 將元件晶粒接合到基底的第一表面； 在所述基底的所述第一表面上沉積黏合劑； 在所述元件晶粒的與所述基底相對的表面上沉積熱介面材料； 在所述元件晶粒及所述基底之上放置蓋，所述蓋接觸所述黏合劑及所述熱介面材料； 對所述蓋及所述基底施加鉗緊力；以及 在施加所述鉗緊力時，將所述黏合劑及所述熱介面材料固化。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778754B (zh) * 2021-03-26 2022-09-21 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
TWI779512B (zh) * 2021-01-15 2022-10-01 台灣積體電路製造股份有限公司 用於製造半導體封裝件的治具及半導體封裝件的製造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11581239B2 (en) * 2019-01-18 2023-02-14 Indium Corporation Lead-free solder paste as thermal interface material
US20200373220A1 (en) * 2019-05-22 2020-11-26 Intel Corporation Integrated circuit packages with thermal interface materials with different material compositions
KR102574409B1 (ko) * 2019-07-01 2023-09-04 삼성전기주식회사 반도체 패키지
CN113035801A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 存储器装置及其制造方法
US10777483B1 (en) * 2020-02-28 2020-09-15 Arieca Inc. Method, apparatus, and assembly for thermally connecting layers
KR20210120355A (ko) * 2020-03-26 2021-10-07 엘지마그나 이파워트레인 주식회사 양면 냉각형 파워 모듈
US11239136B1 (en) * 2020-07-28 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesive and thermal interface material on a plurality of dies covered by a lid
US20220052667A1 (en) * 2020-08-14 2022-02-17 Qorvo Us, Inc. Electronic device with solder interconnect and multiple material encapsulant
WO2022061682A1 (zh) * 2020-09-25 2022-03-31 华为技术有限公司 一种封装结构及封装方法、电子装置及其制造方法
US11545444B2 (en) 2020-12-31 2023-01-03 International Business Machines Corporation Mitigating cooldown peeling stress during chip package assembly
US11824037B2 (en) 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate
US20220301970A1 (en) * 2021-03-19 2022-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing semiconductor package
KR20220151442A (ko) * 2021-05-06 2022-11-15 삼성전자주식회사 반도체 패키지
US20220384304A1 (en) * 2021-05-27 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. High Efficiency Heat Dissipation Using Discrete Thermal Interface Material Films
US11705381B2 (en) * 2021-06-04 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. High efficiency heat dissipation using thermal interface material film
US11869822B2 (en) * 2021-07-23 2024-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
TWI821083B (zh) * 2022-12-23 2023-11-01 創意電子股份有限公司 半導體封裝裝置

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055909A (en) * 1990-05-14 1991-10-08 Vlsi Technology, Inc System for achieving desired bondlength of adhesive between a semiconductor chip package and a heatsink
US5109320A (en) * 1990-12-24 1992-04-28 Westinghouse Electric Corp. System for connecting integrated circuit dies to a printed wiring board
US5745344A (en) * 1995-11-06 1998-04-28 International Business Machines Corporation Heat dissipation apparatus and method for attaching a heat dissipation apparatus to an electronic device
US6130821A (en) * 1998-12-03 2000-10-10 Motorola, Inc. Multi-chip assembly having a heat sink and method thereof
US6292367B1 (en) * 2000-06-22 2001-09-18 International Business Machines Corporation Thermally efficient semiconductor chip
US6853064B2 (en) * 2003-05-12 2005-02-08 Micron Technology, Inc. Semiconductor component having stacked, encapsulated dice
US20040238947A1 (en) * 2003-05-28 2004-12-02 Intel Corporation Package and method for attaching an integrated heat spreader
US6870258B1 (en) * 2003-06-16 2005-03-22 Advanced Micro Devices Fixture suitable for use in coupling a lid to a substrate and method
US7168484B2 (en) * 2003-06-30 2007-01-30 Intel Corporation Thermal interface apparatus, systems, and methods
US7193318B2 (en) * 2004-08-18 2007-03-20 International Business Machines Corporation Multiple power density chip structure
US7609523B1 (en) * 2004-09-29 2009-10-27 Super Talent Electronics, Inc. Memory module assembly including heat sink attached to integrated circuits by adhesive and clips
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7256067B1 (en) * 2006-05-01 2007-08-14 Advanced Micro Devices, Inc. LGA fixture for indium assembly process
US7892883B2 (en) * 2008-05-30 2011-02-22 Intel Corporation Clipless integrated heat spreader process and materials
US7733655B2 (en) * 2008-07-22 2010-06-08 International Business Machines Corporation Lid edge capping load
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US8202765B2 (en) * 2009-01-22 2012-06-19 International Business Machines Corporation Achieving mechanical and thermal stability in a multi-chip package
KR101332866B1 (ko) * 2012-02-16 2013-11-22 앰코 테크놀로지 코리아 주식회사 반도체 장치
US20140091461A1 (en) * 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US20140167243A1 (en) * 2012-12-13 2014-06-19 Yuci Shen Semiconductor packages using a chip constraint means
US8907472B2 (en) * 2013-02-07 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package comprising perforated foil sheet
US9089051B2 (en) * 2013-06-27 2015-07-21 International Business Machines Corporation Multichip module with stiffening frame and associated covers
US9082743B2 (en) * 2013-08-02 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat dissipation structures
US9583415B2 (en) * 2013-08-02 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal interface material on the sidewalls of stacked dies
US9269694B2 (en) * 2013-12-11 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal management features for reduced thermal crosstalk and methods of forming same
KR101579673B1 (ko) * 2014-03-04 2015-12-22 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
KR102254104B1 (ko) * 2014-09-29 2021-05-20 삼성전자주식회사 반도체 패키지
US10269682B2 (en) * 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9806002B2 (en) * 2015-12-23 2017-10-31 Intel Corporation Multi-reference integrated heat spreader (IHS) solution
US10236229B2 (en) * 2016-06-24 2019-03-19 Xilinx, Inc. Stacked silicon package assembly having conformal lid
US10269669B2 (en) * 2016-12-14 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming the same
US10529645B2 (en) * 2017-06-08 2020-01-07 Xilinx, Inc. Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
US11101236B2 (en) * 2018-08-31 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI779512B (zh) * 2021-01-15 2022-10-01 台灣積體電路製造股份有限公司 用於製造半導體封裝件的治具及半導體封裝件的製造方法
US11804468B2 (en) 2021-01-15 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Manufacturing method of semiconductor package using jig
TWI778754B (zh) * 2021-03-26 2022-09-21 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US11915991B2 (en) 2021-03-26 2024-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having first heat spreader and second heat spreader and manufacturing method thereof

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