CN111415872A - 形成封装结构的方法 - Google Patents
形成封装结构的方法 Download PDFInfo
- Publication number
- CN111415872A CN111415872A CN201910537740.1A CN201910537740A CN111415872A CN 111415872 A CN111415872 A CN 111415872A CN 201910537740 A CN201910537740 A CN 201910537740A CN 111415872 A CN111415872 A CN 111415872A
- Authority
- CN
- China
- Prior art keywords
- package
- substrate
- adhesive
- die
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title description 8
- 239000000853 adhesive Substances 0.000 claims abstract description 79
- 230000001070 adhesive effect Effects 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000000463 material Substances 0.000 claims abstract description 61
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 18
- 125000006850 spacer group Chemical group 0.000 description 13
- 239000008393 encapsulating agent Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 10
- 230000017525 heat dissipation Effects 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000009826 distribution Methods 0.000 description 7
- 238000013036 cure process Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011231 conductive filler Substances 0.000 description 3
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 3
- 230000032798 delamination Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000013013 elastic material Substances 0.000 description 2
- 239000013536 elastomeric material Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 239000002537 cosmetic Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4878—Mechanical treatment, e.g. deforming
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
- H01L2023/405—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26135—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29012—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29012—Shape in top view
- H01L2224/29013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
- H01L2224/29018—Shape in side view comprising protrusions or indentations
- H01L2224/29019—Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/29076—Plural core members being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/29078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
- H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29309—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/29324—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/3207—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75314—Auxiliary members on the pressing surface
- H01L2224/75315—Elastomer inlay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7555—Mechanical means, e.g. for planarising, pressing, stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/759—Means for monitoring the connection process
- H01L2224/7592—Load or pressure adjusting means, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
- H01L2224/83096—Transient conditions
- H01L2224/83097—Heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8314—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83208—Compression bonding applying unidirectional static pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/8321—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8334—Bonding interfaces of the layer connector
- H01L2224/83345—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
一种封装式半导体器件及一种用于形成封装式半导体器件的方法及装置。在一实施例中,一种方法包括:将器件管芯接合到衬底的第一表面;在所述衬底的所述第一表面上沉积粘合剂;在所述器件管芯的与所述衬底相对的表面上沉积热界面材料;在所述器件管芯及所述衬底之上放置盖,所述盖接触所述粘合剂及所述热界面材料;对所述盖及所述衬底施加钳紧力;以及在施加所述钳紧力时,将所述粘合剂及所述热界面材料固化。
Description
技术领域
本发明实施例涉及一种形成封装结构的方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的持续提高,半导体行业已经历快速增长。在很大程度上,集成密度的此种提高来自于最小特征尺寸(minimum feature size)的重复减小,此使得更多组件能够集成在一定的区域中。
随着对缩小电子器件的需求的增长,需要更小且更具创造性的半导体管芯封装技术。这种封装系统的一实例是叠层封装(Package-on-Package,PoP)技术。在PoP器件中,顶部半导体封装被堆叠在底部半导体封装的顶部上,以提供高集成水平及组件密度。另一个实例是衬底上晶片上芯片(Chip-On-Wafer-On-Substrate,CoWoS)结构,其中半导体芯片被贴合到晶片(例如,中介板)以形成晶片上芯片(Chip-On-Wafer,CoW)结构。CoW结构接着被贴合到衬底(例如,印刷电路板(printed circuit board,PCB))以形成CoWoS结构。这些封装技术及其他先进封装技术使得能够生产出具有增强的功能性及小的占用面积(footprint)的半导体器件。
发明内容
本发明实施例提供一种形成封装结构的方法,包括:将器件管芯接合到衬底的第一表面;在所述衬底的所述第一表面上沉积粘合剂;在所述器件管芯的与所述衬底相对的表面上沉积热界面材料;在所述器件管芯及所述衬底之上放置盖,所述盖接触所述粘合剂及所述热界面材料;对所述盖及所述衬底施加钳紧力;以及在施加所述钳紧力时,将所述粘合剂及所述热界面材料固化。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1至图4是根据一些实施例的用于三维集成电路(three-dimensionalintegrated circuit,3DIC)钳紧固化工艺(clamped curing process)的剖视图。
图5A及图5B是根据一些实施例的包括推针紧固件的卡钳的剖视图。
图6是根据一些实施例的包括荷重元(load cell)的卡钳的剖视图。
图7A及图7B分别是根据一些实施例的包括密封环的3DIC的剖视图及俯视图。
图8是根据一些实施例的包括间隔壁的3DIC的剖视图。
图9A及图9B是根据一些实施例的包括缓冲特征(relief feature)的3DIC的剖视图。
图10A至图16是根据一些实施例的包括在3DIC中的粘合剂及热界面材料(thermalinterface material,TIM)的替代性配置的各种图。
图17A及图17B是根据一些实施例的用以钳紧3DIC的夹具(jig)的透视图。
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本发明。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外,本发明可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
各种实施例提供用于形成三维集成电路器件(例如,衬底上晶片上芯片(CoWoS)器件)的改善的方法、用于执行所述方法的设备以及通过所述方法而形成的三维集成电路(3DIC)器件。所述方法包括在用于将粘合剂及热界面材料(TIM)固化的固化工艺期间对3DIC的盖及衬底施加钳紧力,这使得衬底及安置在所述衬底上的晶片上芯片(CoW)以热及机械的方式贴合到盖。在固化工艺期间钳紧3DIC有助于减小及控制粘合剂及TIM的厚度,这会使3DIC的厚度减小且使3DIC中的分层(delamination)及管芯开裂问题减少。这会改善3DIC的热稳定性及机械稳定性、减少3DIC中的缺陷、改善3DIC的热性能,进而增加3DIC的产量。
图1至图4是根据各种实施例的制造三维集成电路(3DIC)封装(例如,衬底上晶片上芯片(CoWoS)封装100)的中间阶段的剖视图。在各种实施例中,CoWoS封装100可包括芯片堆叠,例如叠层逻辑(logic-on-logic,LoL)、逻辑上存储器(memory-on-logic,MoL)等。图1绘示出接合到衬底104的晶片上芯片(CoW)封装102。CoW封装102可包括安置在两个低功耗管芯108之间的高功耗管芯106。高功耗管芯106及低功耗管芯108可为管芯堆叠且可称作芯片。高功耗管芯106消耗相对高的功率且因此与低功耗管芯108相比产生相对大的热量。举例来说,高功耗管芯106可消耗介于约100瓦(W)到约1,000W的功率,而低功耗管芯108可消耗介于约10W到约100W的功率。高功耗管芯106所消耗的功率对低功耗管芯108所消耗的功率的比率可介于约10到约30,例如约16。高功耗管芯106可为处理器,例如中央处理器(central processing unit,CPU)、图形处理单元(graphics processing unit,GPU)等。低功耗管芯108可为存储器管芯,例如高带宽存储器(high bandwidth memory,HBM)、存储器立方(memory cube)、存储器堆叠(memory stack)等。尽管图1绘示出CoW封装102具有一个高功耗管芯106及两个低功耗管芯108,然而其他实施例可包括任意数目的高功耗管芯106和/或低功耗管芯108。
高功耗管芯106及低功耗管芯108可被包括模制化合物的包封体120所环绕。可将高功耗管芯106、低功耗管芯108及包封体120平坦化,进而使得高功耗管芯106的顶表面、低功耗管芯108的顶表面及包封体120的顶表面齐平。由于包封体120中可不产生热,因此包封体120附近的区域的散热需求可较低。
将高功耗管芯106及低功耗管芯108接合到封装组件110的顶表面。可通过多个第一连接件112将高功耗管芯106及低功耗管芯108电耦合到且机械耦合到封装组件110,多个第一连接件112可为导电凸块、微凸块、金属柱等。尽管未单独绘示,然而可在高功耗管芯106及低功耗管芯108与封装组件110之间形成环绕第一连接件112的一种或多种底部填充材料(与底部填充材料118分隔开,如以下所论述)。
封装组件110可为中介板衬底,其可为例如硅衬底等半导体衬底。封装组件110也可由例如硅锗、硅碳等另一种半导体材料形成。根据一些实施例,在封装组件110的表面处形成例如晶体管(未单独绘示)等有源器件。也可在封装组件110中形成例如电阻器和/或电容器等无源器件(未单独绘示)。根据本发明的替代性实施例,封装组件110可为半导体衬底或介电质衬底,且各个封装组件110中可不包括有源器件。根据这些实施例,封装组件110可包括或可不包括形成在其中的无源器件。
可形成从封装组件110的顶表面延伸到封装组件110中的穿孔114。在其中封装组件110为硅衬底的实施例中,穿孔114可称作衬底穿孔或硅穿孔。在一些实施例中,封装组件110可包括形成在用于电性连接到集成电路器件(如果有的话)的衬底之上的内连线结构(未单独绘示)以及CoW封装102的穿孔114。内连线结构可包括多个介电层、形成在介电层中的金属线及形成在金属线之间并将金属线内连、上覆在金属线上且在金属线之下的通孔。根据一些实施例,介电层30可由氧化硅、氮化硅、碳化硅、氮氧化硅、其组合和/或其多层形成。作为另外一种选择,介电层可包括一种或多种具有低介电常数(k值)的低k介电层。举例来说,介电层中的低k介电材料的k值可低于约3.0或低于约2.5。
将CoW封装102的封装组件110接合到衬底104的顶表面。可通过多个第二连接件116将封装组件110电耦合到且机械耦合到衬底104,多个第二连接件116可为导电凸块、微凸块、金属柱等。可在封装组件110与衬底104之间形成环绕第二连接件116的底部填充材料118。底部填充材料118也可在高功耗管芯106及低功耗管芯108与封装组件110之间延伸而环绕第一连接件112。
衬底104可为封装衬底,其可为印刷电路板(PCB)等。衬底104可包括一个或多个介电层以及例如导电线及通孔等导电特征。在一些实施例中,衬底104可包括穿孔、有源器件、无源器件等。衬底104可进一步包括形成在衬底104的上表面及下表面处的导电接垫。可将第二连接件116耦合到位于衬底104的顶表面处的导电接垫。
在图2中,在衬底104上且在包封体120、高功耗管芯106及低功耗管芯108之上分别沉积粘合剂122及热界面材料(TIM)124。粘合剂122可为环氧树脂(epoxy)、硅树脂、胶水等。粘合剂122可具有比TIM 124好的粘合能力。粘合剂122可具有介于约1W/m·K到约3W/m·K、低于约0.5W/m·K等的导热系数(thermal conductivity)。可将粘合剂122定位成使得散热特征(例如,图3中所绘示的盖126)能够贴合在CoW封装102周围。因此,在一些实施例中,可将粘合剂122安置在CoW封装102的周界周围或者甚至将粘合剂122安置成包围CoW封装102。
TIM 124可为具有良好导热系数的聚合物,所述良好导热系数可介于约3W/m·K到约5W/m·K。在一些实施例中,TIM 124可包括具有导热填料的聚合物。导热填料可使TIM124的有效导热系数增大到介于约10W/m·K到约50W/m·K或50W/m·K以上。可应用的导热填料材料可包括氧化铝、氮化硼、氮化铝、铝、铜、银、铟、其组合等。在其他实施例中,TIM124可包括其他材料,例如包括银、铟膏体等的金属系材料或焊料系材料。在更进一步的实施例中,TIM 124可包括膜系材料或片材系材料,例如包括合成碳纳米管(synthesizedcarbon nanotube,CNT)的片材系材料或者具有垂直取向的石墨填料的导热片材。尽管TIM124被示为在高功耗管芯106及低功耗管芯108之上延伸的连续TIM,然而在其他实施例中,TIM 124可物理地断开。举例来说,可在邻近管芯(例如,高功耗管芯106和/或低功耗管芯108)之间的TIM 124中安置空气隙(air gap)以减少所述管芯之间的侧向热互作用。在一些实施例中,可在沉积粘合剂122之后沉积TIM 124;然而,也可在沉积粘合剂122之前沉积TIM124。
在图3中,将盖126贴合到衬底104及CoW封装102以形成CoWoS封装100。盖126可被贴合以保护CoW封装102及衬底104,并使从CoW封装102产生的热扩散到更大的区域,从而消散掉来自CoW封装102的热。盖126可由例如钢、不锈钢、铜、铝、其组合等具有高导热系数的材料形成。在一些实施例中,盖126可为涂布有另一种金属(例如金)的金属。盖126可由具有介于约100W/m·K到约400W/m·K(例如,约400W/m·K)的导热系数的材料形成。盖126覆盖且环绕CoW封装102。在一些实施例中,盖126为单一连续材料。在其他实施例中,盖126可包括多个片件(piece),其可为相同材料或不同材料。
粘合剂122具有比TIM 124大的粘合能力,但具有比TIM 124低的导热系数。因此,将粘合剂122安置在盖126与衬底104之间、CoW封装102的周边周围以将盖126粘合到衬底104。将TIM 124安置在高功耗管芯106与低功耗管芯108上、高功耗管芯106及低功耗管芯108与盖126之间以将来自高功耗管芯106及低功耗管芯108的热消散到盖126。
在图4中,使用卡钳130在盖126与衬底104之间施加钳紧力。卡钳130包括下部板132、上部板134、紧固件136及弹簧138。在用于将粘合剂122和/或TIM 124固化的钳紧固化工艺期间,可使用卡钳130施加介于约3千克力(kgf)到约100kgf、介于约3kgf到约20kgf、介于约20kgf到约50kgf或者大于50kgf的钳紧力。在盖126与衬底104被钳紧之后,粘合剂122可具有介于约100微米(μm)到约200μm、介于约200μm到约300μm或者小于约100μm的厚度T1,且TIM 124可具有介于约30μm到约60μm、介于约60μm到约150μm或者小于约200μm的厚度T2。
当盖126与衬底104被钳紧,可通过对粘合剂122及TIM 124施加热来固化粘合剂122及TIM 124。在一些实施例中,可通过将被钳紧的CoWoS封装100放置在固化烤箱中来固化粘合剂122及TIM 124。在卡钳130施加钳紧力时,可在介于100℃到约260℃的温度下、介于约100℃到约150℃的温度下、介于约150℃到约260℃的温度下或任何其他适合的温度下将粘合剂122及TIM124固化达介于约20秒到约2小时、介于约30分钟到约2小时或任何其他适合时间。
下部板132及上部板134可由例如铝、不锈钢、铜、镀镍铜、铜钨、碳化铝硅(aluminum silicon carbide)等材料形成。在一些实施例中,下部板132可由与上部板134相同的材料或与上部板134不同的材料形成。紧固件136可为螺钉型紧固件、推针型紧固件、磁性紧固件、弹簧锁紧固件或任何其他类型的紧固件。可使用紧固件136及弹簧138来控制施加在下部板132与上部板134之间的钳紧力。举例来说,可通过提供具有不同弹簧常量(spring constant)的弹簧来变更钳紧力,从而为螺钉型紧固件等提供不同的扭矩。在一些实施例中,可在下部板132与衬底104之间和/或上部板134与盖126之间安置分布板。分布板可由弹性材料、橡胶材料等形成且可用以将卡钳施加的力均匀地分布在衬底104的表面和/或盖126的表面。
在整个用于固化粘合剂122和/或TIM 124的钳紧固化工艺中使用卡钳130施加钳紧力会使粘合剂122及TIM 124的接合线厚度(bond line thickness,BLT)减小、改善粘合剂122及TIM 124的厚度均匀性并提高TIM 124的覆盖率。这些改善降低了盖126将从CoW封装102及衬底104分层的可能性。因此,根据上述方法而形成的半导体封装具有减小的厚度、改善的热性能、提高的可靠性及减少的缺陷。
图5A及图5B是根据其中紧固件136包括推针紧固件的实施例的卡钳130的剖视图。如图5A中所示,下部板132包括推针孔180,推针孔180具有第一宽度与大于第一宽度的第二宽度,第一宽度邻近下部板132的顶表面,而第二宽度邻近下部板132的底表面。推针孔180可完全延伸穿过下部板132,使得紧固件136可被移除。在实施例中,紧固件136包括推针紧固件,紧固件136包括具有梯形形状且中空的推针头182。如图5B中所示,推针头182的形状使得推针头182能够在被按压到推针孔180中时变形且在推针头182被推按到下部板132的具有第二宽度的部分中时紧固。紧固件136可接着通过一起推按推针头182的相对两侧并将推针头182经由推针孔180往回推按而被从下部板132移除。按压板(未单独绘示)可同时按压在若干个卡钳130的紧固件上,以同时钳紧若干个CoWoS封装100。
图6是根据其中上部板134包括一个或多个荷重元184的实施例的卡钳130的剖视图。在图6中所示的实施例中,荷重元184安置在上部板134中且检测上部板134与盖126之间的力;然而,在其他实施例中,荷重元184可安置在下部板132中且可检测下部板132与衬底104之间的力。在更进一步的实施例中,荷重元184可包括在上部板134及下部板132二者中。荷重元184可用于判断施加到CoWoS封装100的力是否处于期望范围内(例如,介于约2kgf到约20kgf或介于约20kgf到约100kgf)。荷重元184可与螺钉型紧固件136结合使用。如果荷重元184检测到力过低,则螺钉型紧固件136可被扭转以对CoWoS封装100施加额外的力,且如果荷重元184检测到力过高,则螺钉型紧固件136可被扭转以对CoWoS封装100施加更少的力。此外,螺钉型紧固件136可使用具有数字输出的扭矩驱动器(torque driver)来扭转,进而使得螺钉型紧固件136可扭转到一致的扭矩。荷重元184可检测介于约5kgf到约100kgf或介于约100kgf到约200kgf的力。在上部板134和/或下部板132中可安置有任意数目的荷重元184。荷重元184可被安置成邻近紧固件136以判断各别紧固件是否需要被扭转以对CoWoS封装100施加更多或更少的力。
图7A至图9B绘示为可包括在CoWoS封装100中的各种特征以防止缺陷并提高可靠性。所述各种特征可结合针对图4至图6所论述的钳紧固化工艺而在CoWoS封装100中使用。图7A及图7B分别是CoWoS封装100的其中密封环140被贴合到衬底104且粘合剂122被放置在密封环140内的实施例的剖视图及俯视图。如图7A及图7B中所示,密封环140可包括外部部分及内部部分,外部部分包围粘合剂122的外直径,而内部部分安置在粘合剂122与CoW封装102之间并环绕粘合剂122的内直径。密封环140的外部部分防止粘合剂溢出盖126的边缘,粘合剂溢出盖126的边缘可能会造成外观缺陷及其他缺陷。如图7A中所示,密封环140的内部部分可在侧向上安置在盖126的内侧边缘内。密封环140的内部部分的定位可使得粘合剂能够在盖126被钳紧时向上扩散到盖126的内边缘的垂直部分,这可增大盖126与衬底104之间的粘合。在一些实施例中,密封环140可仅包括外部部分。密封环140可由弹性材料、橡胶材料等形成。密封环140可具有介于约50μm到约400μm(例如,约100μm)的高度及介于约50μm到约200μm(例如,约100μm)的厚度。
图8是CoWoS封装100的其中在盖126与衬底104之间安置有间隔壁142的实施例。间隔壁142可在将盖126钳紧到衬底104之前贴合到衬底104、盖126和/或CoW封装102。在一些实施例中,间隔壁142可包括在粘合剂122和/或TIM 124中。间隔壁142可被构型为立方体、球体或任何其他适合的形状。间隔壁142可具有介于约0.5毫米(mm)到约2mm(例如,约1mm)的长度/直径。间隔壁142可由弹性材料、橡胶材料、焊料材料(例如,焊球、焊点或焊条)或者膜型材料或片材型材料(例如,多孔铜片材(perforated copper sheet)、多孔石墨片材(perforated graphite sheet)等)形成。
间隔壁142可用于控制粘合剂122及TIM 124的接合线厚度。将粘合剂122和/或TIM124形成得过薄可使粘合剂122及TIM 124出现例如开裂、分层等缺陷。间隔壁142防止粘合剂122及TIM 124在钳紧固化工艺期间变得过薄,藉此防止缺陷并提高包括间隔壁142的CoWoS封装100的可靠性。
图9A及图9B是CoWoS封装100的其中盖126中包括缓冲特征(relief featrue)144的实施例。如图9A中所示,缓冲特征144可为形成在盖126中的凹槽(groove)、沟槽(trench)等。缓冲特征144可被构型为条、同心正方形、同心圆,或者在俯视图中具有任何其他形状。由于盖126、衬底104及CoW封装102之间存在热膨胀系数(coefficient of thermalexpansion,CTE)不匹配,因此在钳紧固化工艺期间且在CoWoS封装100的整个使用寿命期间,盖126、衬底104及CoW封装102可存在翘曲(warping)。缓冲特征144可被设置成使得盖126能够变形且与由温度变化等所造成的CoW封装102和/或衬底104的任何翘曲共形。如此,通过包括缓冲特征144,可防止由翘曲所造成的缺陷且提高CoWoS封装100的可靠性。如在图9A及图9B中所进一步绘示,CoWoS封装100可包括缓冲特征144及密封环140二者。在又一些实施例中,CoWoS封装100可包括密封环140、间隔壁142及缓冲特征144的任意组合。
缓冲特征144可在盖126与TIM 124和/或粘合剂122之间进一步提供增大的接触面积。如图9B中所示,缓冲特征144可设置在CoW封装102的散热需求降低的区域上方(例如,包封体120上方)且粘合剂122可施加到CoW封装102的与缓冲特征144对应的区域。这可改善盖126与CoW封装102之间的粘合,而不会负面地影响CoW封装102的散热。在又一些实施例(未单独绘示)中,缓冲特征144可安置在CoW封装102的散热需求较高的区域上方(例如,高功耗管芯106上方和/或低功耗管芯108上方),且TIM 124可施加到CoW封装102的与缓冲特征144对应的部分,从而增大从CoW封装102到盖126的散热。因此,缓冲特征144可增大盖126对CoW封装102的粘合且可改善CoW封装102的散热,从而防止缺陷并提高包括缓冲特征144的CoWoS封装100的可靠性。
图9B进一步示出盖126可在不同的区域中具有不同的厚度。举例来说,盖126的安置在高功耗管芯106之上的部分所具有的厚度T3可大于盖126的安置在低功耗管芯108之上的部分的厚度T4。厚度T3可介于约0.5mm到约3mm(例如,约1mm),而厚度T4可介于约0.5mm到约3mm(例如,约0.5mm)。厚度T3对厚度T4的比率可介于约2到约6(例如,约2)。提供在不同区域中具有不同厚度的盖126可有助于改善盖126与衬底104及CoW封装102的可共形性,进一步防止缺陷并提高包括盖126的CoWoS封装100的可靠性。
图10A至图16是用于在CoW封装102之上提供粘合剂122及TIM 124的各种图案。所述各种图案可用于改善盖126与CoW封装102之间的粘合及散热。图10A至图16中所示的各种图案化方案可与图7A至图9B中所说明的特征及针对图4所论述的钳紧固化工艺结合使用。
图10A及图10B分别是将粘合剂122施加在安置有包封体120在其中的CoW封装102的部分之上并将TIM 124施加在安置有高功耗管芯106及低功耗管芯108在其中的CoW封装102的部分之上的实施例的剖视图及俯视图。如前面所论述,高功耗管芯106及低功耗管芯108可产生热,而包封体120可不产生热。如此,高功耗管芯106及低功耗管芯108附近的产热需求较大,且包封体120附近的产热需求较低。在包封体120之上提供粘合剂122并在高功耗管芯106及低功耗管芯108之上提供TIM 124会增大盖126与CoW封装102之间的粘合,同时为高功耗管芯106及低功耗管芯108提供散热。
图11至图13是其中粘合剂122及TIM 124(统称为盖贴合材料150)以从邻近CoW封装102的一个边缘延伸到邻近CoW封装102的相对边缘的蛇行图案而在CoW封装102之上进行分配的实施例。盖贴合材料150可以任意数目的行(例如,介于10行到30行,或者19行)进行分配。盖贴合材料150的奇数行可内连,且盖贴合材料150的偶数行断开。如图11至图13中所示,任意数目的偶数行(例如,5个中间偶数行(图11)、7个中间偶数行(图12)或9个中间偶数行(图13))可包括粘合剂122,而盖贴合材料的其余部分包括TIM124。粘合剂122也可在衬底104的周界周围进行分配。这些实施例可用于改善盖126与CoW封装102之间的粘合,同时为高功耗管芯106及低功耗管芯108提供散热。
图14至图16是其中粘合剂122及TIM 124(统称为盖贴合材料150)以若干个蛇行图案而在CoW封装102之上进行分配的实施例。盖贴合材料150可以从高功耗管芯106的边缘延伸到高功耗管芯106的相对边缘的第一蛇行图案152及从低功耗管芯108的边缘延伸到低功耗管芯108的相对边缘的第二蛇行图案154而在CoW封装102之上进行分配。盖贴合材料150可以任意数目的行(例如,介于10行到30行,或者19行)进行分配。盖贴合材料150的奇数行可内连,且盖贴合材料150的偶数行断开。如图14中所示,第二蛇行图案154可包括粘合剂122,而第一蛇行图案152包括TIM 124。因此,粘合剂122可在低功耗管芯108及包封体120之上进行分配,且TIM 124可在高功耗管芯106之上进行分配。在图15中,第二蛇行图案154可包括粘合剂122,且第一蛇行图案152可包括TIM 124,第一蛇行图案152中的一定数目的偶数行(例如,3个偶数行)包括粘合剂122。因此,粘合剂122可在低功耗管芯108、包封体120以及高功耗管芯106的中间部分之上进行分配,且TIM 124可在高功耗管芯106之上进行分配。在图16中,第一蛇行图案152及第二蛇行图案154可包括TIM 124,第一蛇行图案152及第二蛇行图案154的中间行及外侧行包括粘合剂122。因此,粘合剂122可在包封体120以及高功耗管芯106的中间部分及边缘部分之上进行分配,且TIM 124可在高功耗管芯106及低功耗管芯108之上进行分配。粘合剂122也可在衬底104的周界周围进行分配。可使用任何其他适合的图案在CoW封装102之上分配粘合剂122及TIM 124,以在CoW封装102及衬底104与盖126之间提供粘合,同时满足高功耗管芯106及低功耗管芯108的散热需求。这些实施例可用于改善盖126与CoW封装102之间的粘合,同时为高功耗管芯106及低功耗管芯108提供散热。
图17A及图17B是根据实施例的夹具160的分解透视图。夹具160可用于在钳紧固化工艺期间钳紧多个CoWoS封装100。如图17A及图17B中所示,夹具160包括下部板132、下部船式托盘(boat tray)164及上部板134。尽管上部板134被例示为对于每一CoWoS封装100来说为单独的板,然而上部板134中的每一者可用以钳紧多个CoWoS封装100。上部板134包括紧固件136。紧固件136可为螺钉型紧固件、推针型紧固件、磁性紧固件、弹簧锁紧固件或适合于在钳紧固化工艺期间将上部板134紧固到下部板132的任何其他类型的紧固件。紧固件136可安置在上部板134或下部板132上。紧固件136可使用按压板等而自动紧固(例如,通过机器人螺钉进给自动化(robotic screw feed automation))。
下部板包括卡钳导销162、紧固件接纳孔168及封装平台170。卡钳导销162可用于将上部板134及下部船式托盘164与下部板132对准。紧固件接纳孔168可用于接纳紧固件136且可为带螺纹的、可为磁性的或可包括其他特征以固定紧固件136。在钳紧固化工艺期间,CoWoS封装100可放置在封装平台170上。下部板132可由例如铝、不锈钢、铜、镀镍铜、铜钨、碳化铝硅等热传导材料形成。如图17A中所示,各种封装平台170可安置在单一下部板132上。下部板132上可安置有任意数目的封装平台170,所述任意数目的封装平台170以任意数目的行及列(例如2行×4列)进行排列。
下部船式托盘164可用于将CoWoS封装100与下部板132对准。举例来说,如图17A及图17B中所示,下部船式托盘164可包括封装导销166,封装导销166可用于将CoWoS封装100与封装平台170对准。下部船式托盘164可具有介于约1mm到约2mm(例如,约1.2mm)的厚度。在一些实施例中,下部船式托盘164可用作下部板132与上部板134之间的间隔壁。在一些实施例中,下部船式托盘164的特征可被集成到下部板132中,进而使得下部船式托盘164及下部板132包括单一集成材料。
在封装平台170上或在上部板134与CoWoS封装100之间可安置有一个或多个分布板(未单独绘示)。分布板可由弹性材料、橡胶材料等形成且可用以将在钳紧固化工艺期间施加的力均匀地分布在CoWoS封装100表面上。
图17B是根据实施例的夹具160的局部装配透视图。如图17B中所示,下部船式托盘164可使用卡钳导销162及封装平台170而与下部板132对准。封装导销166用于将CoWoS封装100与封装平台170对准。使用夹具160来钳紧CoWoS封装100使得多个CoWoS封装100能够同时被钳紧并经历钳紧固化工艺,这会使成品CoWoS封装100的产量增大。另外,使用夹具160而固化的CoWoS封装100可经历以上参照图4所论述的钳紧固化且具有减小的厚度、改善的热性能、提高的可靠性及减少的缺陷。
根据实施例,一种方法包括:将器件管芯接合到衬底的第一表面;在所述衬底的所述第一表面上沉积粘合剂;在所述器件管芯的与所述衬底相对的表面上沉积热界面材料;在所述器件管芯及所述衬底之上放置盖,所述盖接触所述粘合剂及所述热界面材料;对所述盖及所述衬底施加钳紧力;以及在施加所述钳紧力时,将所述粘合剂及所述热界面材料固化。在实施例中,在沉积所述热界面材料之前沉积所述粘合剂。在实施例中,将所述粘合剂及所述热界面材料固化20秒到2小时。在实施例中,在100℃到150℃的温度下,将所述粘合剂及所述热界面材料固化。在实施例中,所述钳紧力介于3kgf到100kgf。在实施例中,施加所述钳紧力包括:将所述盖、所述器件管芯及所述衬底放置在上部板与下部板之间;以及在所述上部板与所述下部板之间紧固多个紧固件。在实施例中,紧固所述多个紧固件包括扭转多个螺钉型紧固件。在实施例中,所述方法进一步包括在所述器件管芯的与所述衬底相对的所述表面上沉积所述粘合剂。
根据另一实施例,一种半导体器件包括:衬底;器件管芯,接合到所述衬底的第一表面,所述器件管芯被包封体环绕;第一粘合剂,安置在所述器件管芯的相对两侧上的所述衬底的所述第一表面上,所述第一粘合剂与所述器件管芯分隔开;第二粘合剂,安置在所述器件管芯的与所述衬底相对的表面上,所述第二粘合剂接触所述包封体;热界面材料,安置在所述器件管芯的与所述衬底相对的所述表面上,所述热界面材料接触所述器件管芯;盖,通过所述第一粘合剂而接合到所述衬底且通过所述热界面材料及所述第二粘合剂而接合到所述器件管芯;以及密封环,安置在所述第一粘合剂的相对两侧上且从所述盖延伸到所述衬底。在实施例中,所述第一粘合剂接触所述盖的底表面且所述盖的内侧壁与所述底表面垂直。在实施例中,所述半导体器件进一步包括将间隔壁安置在所述第一粘合剂及所述热界面材料中,所述间隔壁将所述盖与所述衬底及所述器件管芯分隔开。在实施例中,所述盖进一步包括缓冲特征用以使得所述盖能够变形,所述缓冲特征安置在所述包封体之上,所述第二粘合剂延伸到所述缓冲特征中。在实施例中,所述器件管芯包括高功耗管芯,所述半导体器件进一步包括邻近所述高功耗管芯的低功耗管芯,所述盖在所述高功耗管芯之上具有第一厚度且在所述低功耗管芯之上具有第二厚度,且所述第一厚度大于所述第二厚度。在实施例中,所述器件管芯包括高功耗管芯,所述半导体器件进一步包括邻近所述高功耗管芯的低功耗管芯,所述热界面材料安置在所述高功耗管芯与所述盖之间,且所述第二粘合剂安置在所述低功耗管芯与所述盖之间。
根据又一实施例,一种装置包括:下部板,所述下部板包括多个封装平台以及多个导销,所述多个封装平台用以固持多个半导体封装;船式托盘,安置在所述下部板上,所述船式托盘与所述多个封装平台及所述多个导销对准,所述船式托盘包括多个封装导销,所述多个封装导销用以将所述多个半导体封装与所述多个封装平台对准;多个上部板,所述多个上部板中的每一者利用所述导销而与所述多个封装平台中的每一者对准;以及多个紧固件,在所述下部板与所述多个上部板之间施加钳紧力。在实施例中,所述多个紧固件包括螺钉型紧固件。在实施例中,所述多个紧固件包括推针型紧固件。在实施例中,所述装置进一步包括安置在所述多个封装平台与所述多个上部板之间的多个分布板,所述多个分布板用以在所述多个半导体封装的表面上均匀地分布所述钳紧力。在实施例中,所述多个分布板包括弹性材料或橡胶材料。在实施例中,所述多个上部板及所述下部板包括铝、不锈钢、铜、镀镍铜、铜钨或碳化铝硅。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知,其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种形成封装结构的方法,其特征在于,包括:
将器件管芯接合到衬底的第一表面;
在所述衬底的所述第一表面上沉积粘合剂;
在所述器件管芯的与所述衬底相对的表面上沉积热界面材料;
在所述器件管芯及所述衬底之上放置盖,所述盖接触所述粘合剂及所述热界面材料;
对所述盖及所述衬底施加钳紧力;以及
在施加所述钳紧力时,将所述粘合剂及所述热界面材料固化。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962789853P | 2019-01-08 | 2019-01-08 | |
US62/789,853 | 2019-01-08 | ||
US16/371,769 | 2019-04-01 | ||
US16/371,769 US11062971B2 (en) | 2019-01-08 | 2019-04-01 | Package structure and method and equipment for forming the same |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111415872A true CN111415872A (zh) | 2020-07-14 |
Family
ID=71404451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910537740.1A Pending CN111415872A (zh) | 2019-01-08 | 2019-06-20 | 形成封装结构的方法 |
Country Status (3)
Country | Link |
---|---|
US (3) | US11062971B2 (zh) |
CN (1) | CN111415872A (zh) |
TW (1) | TW202027177A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI821083B (zh) * | 2022-12-23 | 2023-11-01 | 創意電子股份有限公司 | 半導體封裝裝置 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111106235B (zh) * | 2018-10-29 | 2023-07-11 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US11581239B2 (en) * | 2019-01-18 | 2023-02-14 | Indium Corporation | Lead-free solder paste as thermal interface material |
US20200373220A1 (en) * | 2019-05-22 | 2020-11-26 | Intel Corporation | Integrated circuit packages with thermal interface materials with different material compositions |
KR102574409B1 (ko) * | 2019-07-01 | 2023-09-04 | 삼성전기주식회사 | 반도체 패키지 |
CN113035801A (zh) * | 2019-12-25 | 2021-06-25 | 台湾积体电路制造股份有限公司 | 存储器装置及其制造方法 |
US10777483B1 (en) * | 2020-02-28 | 2020-09-15 | Arieca Inc. | Method, apparatus, and assembly for thermally connecting layers |
KR20210120355A (ko) * | 2020-03-26 | 2021-10-07 | 엘지마그나 이파워트레인 주식회사 | 양면 냉각형 파워 모듈 |
US11239136B1 (en) * | 2020-07-28 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adhesive and thermal interface material on a plurality of dies covered by a lid |
US20220052667A1 (en) * | 2020-08-14 | 2022-02-17 | Qorvo Us, Inc. | Electronic device with solder interconnect and multiple material encapsulant |
WO2022061682A1 (zh) * | 2020-09-25 | 2022-03-31 | 华为技术有限公司 | 一种封装结构及封装方法、电子装置及其制造方法 |
US11545444B2 (en) | 2020-12-31 | 2023-01-03 | International Business Machines Corporation | Mitigating cooldown peeling stress during chip package assembly |
US11824037B2 (en) | 2020-12-31 | 2023-11-21 | International Business Machines Corporation | Assembly of a chip to a substrate |
US11804468B2 (en) * | 2021-01-15 | 2023-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Manufacturing method of semiconductor package using jig |
US20220301970A1 (en) * | 2021-03-19 | 2022-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of manufacturing semiconductor package |
US11915991B2 (en) | 2021-03-26 | 2024-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having first heat spreader and second heat spreader and manufacturing method thereof |
KR20220151442A (ko) * | 2021-05-06 | 2022-11-15 | 삼성전자주식회사 | 반도체 패키지 |
US20220384304A1 (en) * | 2021-05-27 | 2022-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | High Efficiency Heat Dissipation Using Discrete Thermal Interface Material Films |
US11705381B2 (en) * | 2021-06-04 | 2023-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | High efficiency heat dissipation using thermal interface material film |
KR20230010079A (ko) * | 2021-07-08 | 2023-01-18 | 삼성전자주식회사 | 반도체 패키지 |
US11869822B2 (en) * | 2021-07-23 | 2024-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055909A (en) * | 1990-05-14 | 1991-10-08 | Vlsi Technology, Inc | System for achieving desired bondlength of adhesive between a semiconductor chip package and a heatsink |
US5109320A (en) * | 1990-12-24 | 1992-04-28 | Westinghouse Electric Corp. | System for connecting integrated circuit dies to a printed wiring board |
US5839641A (en) * | 1995-08-30 | 1998-11-24 | Industrial Technology Research Institute | Apparatus for placing and aligning solder balls onto solder pads on a substrate for manufacturing IC devices |
US5745344A (en) * | 1995-11-06 | 1998-04-28 | International Business Machines Corporation | Heat dissipation apparatus and method for attaching a heat dissipation apparatus to an electronic device |
JP3386986B2 (ja) * | 1997-10-16 | 2003-03-17 | シャープ株式会社 | プラズマ処理装置 |
US6130821A (en) * | 1998-12-03 | 2000-10-10 | Motorola, Inc. | Multi-chip assembly having a heat sink and method thereof |
US6292367B1 (en) * | 2000-06-22 | 2001-09-18 | International Business Machines Corporation | Thermally efficient semiconductor chip |
US6853064B2 (en) * | 2003-05-12 | 2005-02-08 | Micron Technology, Inc. | Semiconductor component having stacked, encapsulated dice |
US20040238947A1 (en) * | 2003-05-28 | 2004-12-02 | Intel Corporation | Package and method for attaching an integrated heat spreader |
US6870258B1 (en) * | 2003-06-16 | 2005-03-22 | Advanced Micro Devices | Fixture suitable for use in coupling a lid to a substrate and method |
US7168484B2 (en) * | 2003-06-30 | 2007-01-30 | Intel Corporation | Thermal interface apparatus, systems, and methods |
US7193318B2 (en) * | 2004-08-18 | 2007-03-20 | International Business Machines Corporation | Multiple power density chip structure |
US7609523B1 (en) * | 2004-09-29 | 2009-10-27 | Super Talent Electronics, Inc. | Memory module assembly including heat sink attached to integrated circuits by adhesive and clips |
US20070108583A1 (en) * | 2005-08-08 | 2007-05-17 | Stats Chippac Ltd. | Integrated circuit package-on-package stacking system |
US7256067B1 (en) * | 2006-05-01 | 2007-08-14 | Advanced Micro Devices, Inc. | LGA fixture for indium assembly process |
US7892883B2 (en) * | 2008-05-30 | 2011-02-22 | Intel Corporation | Clipless integrated heat spreader process and materials |
US7733655B2 (en) * | 2008-07-22 | 2010-06-08 | International Business Machines Corporation | Lid edge capping load |
US7781883B2 (en) * | 2008-08-19 | 2010-08-24 | International Business Machines Corporation | Electronic package with a thermal interposer and method of manufacturing the same |
US8202765B2 (en) * | 2009-01-22 | 2012-06-19 | International Business Machines Corporation | Achieving mechanical and thermal stability in a multi-chip package |
US8373269B1 (en) * | 2011-09-08 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jigs with controlled spacing for bonding dies onto package substrates |
KR101332866B1 (ko) * | 2012-02-16 | 2013-11-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 장치 |
US20140091461A1 (en) * | 2012-09-30 | 2014-04-03 | Yuci Shen | Die cap for use with flip chip package |
US20140167243A1 (en) * | 2012-12-13 | 2014-06-19 | Yuci Shen | Semiconductor packages using a chip constraint means |
US8907472B2 (en) * | 2013-02-07 | 2014-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC package comprising perforated foil sheet |
US9089051B2 (en) * | 2013-06-27 | 2015-07-21 | International Business Machines Corporation | Multichip module with stiffening frame and associated covers |
US9583415B2 (en) * | 2013-08-02 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with thermal interface material on the sidewalls of stacked dies |
US9082743B2 (en) * | 2013-08-02 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packages with heat dissipation structures |
US9269694B2 (en) * | 2013-12-11 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with thermal management features for reduced thermal crosstalk and methods of forming same |
KR101579673B1 (ko) * | 2014-03-04 | 2015-12-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지 |
KR102254104B1 (ko) * | 2014-09-29 | 2021-05-20 | 삼성전자주식회사 | 반도체 패키지 |
US10269682B2 (en) * | 2015-10-09 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices |
US9806002B2 (en) * | 2015-12-23 | 2017-10-31 | Intel Corporation | Multi-reference integrated heat spreader (IHS) solution |
US10236229B2 (en) * | 2016-06-24 | 2019-03-19 | Xilinx, Inc. | Stacked silicon package assembly having conformal lid |
US10269669B2 (en) * | 2016-12-14 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of forming the same |
US10529645B2 (en) * | 2017-06-08 | 2020-01-07 | Xilinx, Inc. | Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management |
US11101236B2 (en) * | 2018-08-31 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
TWI764340B (zh) * | 2020-10-23 | 2022-05-11 | 美商第一檢測有限公司 | 抵壓組件及晶片測試設備 |
-
2019
- 2019-04-01 US US16/371,769 patent/US11062971B2/en active Active
- 2019-06-20 CN CN201910537740.1A patent/CN111415872A/zh active Pending
- 2019-07-09 TW TW108124122A patent/TW202027177A/zh unknown
-
2021
- 2021-07-12 US US17/373,250 patent/US11810833B2/en active Active
-
2023
- 2023-07-28 US US18/361,332 patent/US12021006B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI821083B (zh) * | 2022-12-23 | 2023-11-01 | 創意電子股份有限公司 | 半導體封裝裝置 |
Also Published As
Publication number | Publication date |
---|---|
US12021006B2 (en) | 2024-06-25 |
TW202027177A (zh) | 2020-07-16 |
US11810833B2 (en) | 2023-11-07 |
US11062971B2 (en) | 2021-07-13 |
US20200219786A1 (en) | 2020-07-09 |
US20210343619A1 (en) | 2021-11-04 |
US20230369162A1 (en) | 2023-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11810833B2 (en) | Package structure and method and equipment for forming the same | |
CN108987358B (zh) | 封装件中具有不同厚度的热界面材料 | |
US8772927B2 (en) | Semiconductor package structures having liquid cooler integrated with first level chip package modules | |
TWI224846B (en) | Semiconductor package with heat dissipating structure | |
US20040095727A1 (en) | Thermal heat spreaders designed for lower cost manufacturability, lower mass and increased thermal performance | |
US20130069218A1 (en) | High density package interconnect with copper heat spreader and method of making the same | |
US10811384B2 (en) | Semiconductor package and method of manufacturing the same | |
US20110079902A1 (en) | Semiconductor device | |
CN113035786A (zh) | 半导体结构及其制造方法 | |
US20240136247A1 (en) | Structure and method related to a power module using a hybrid spacer | |
US11587887B2 (en) | Semiconductor device and manufacturing method thereof | |
US20220102288A1 (en) | Semiconductor device and manufacturing method thereof | |
TW202303872A (zh) | 封裝組件 | |
US20230071542A1 (en) | Semiconductor device | |
TW202244990A (zh) | 半導體封裝及其形成方法 | |
TWI721898B (zh) | 半導體封裝結構 | |
CN115064508A (zh) | 多tim封装及其形成方法 | |
US20230024043A1 (en) | Semiconductor Packages with Thermal Lid and Methods of Forming the Same | |
CN219832631U (zh) | 芯片封装结构 | |
TWI779512B (zh) | 用於製造半導體封裝件的治具及半導體封裝件的製造方法 | |
JP2011243800A (ja) | 半導体装置の製造方法 | |
US20240047292A1 (en) | Semiconductor package | |
US20240038617A1 (en) | Package structure and manufacturing method thereof | |
TW202347674A (zh) | 晶片封裝結構及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200714 |
|
WD01 | Invention patent application deemed withdrawn after publication |