TW202018772A - 半導體裝置的製造方法及半導體裝置 - Google Patents

半導體裝置的製造方法及半導體裝置 Download PDF

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TW202018772A
TW202018772A TW108127783A TW108127783A TW202018772A TW 202018772 A TW202018772 A TW 202018772A TW 108127783 A TW108127783 A TW 108127783A TW 108127783 A TW108127783 A TW 108127783A TW 202018772 A TW202018772 A TW 202018772A
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layer
source
epitaxial layer
drain epitaxial
dummy gate
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TWI711073B (zh
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布萊戴恩杜瑞茲
喬治凡利亞尼提斯
朵爾伯斯 荷爾本
范達爾 馬庫斯瓊斯亨利庫斯
馬汀克里斯多福荷蘭
文森 堤姆斯
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台灣積體電路製造股份有限公司
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Abstract

在半導體裝置的製造方法，虛設閘極結構係形成在半導體層之通道區域上，源極/汲極磊晶層係被形成虛設閘極結構之相對側上，平坦化操作係對源極/汲極磊晶層進行，被平坦化之源極/汲極磊晶層係圖案化，虛設閘極結構係被移除，以形成閘極空間，以及金屬閘極結構係形成在閘極空間內。

Description

半導體裝置的製造方法及半導體裝置
習知的互補式金屬氧化物半導體(complementary-metal-oxide-semiconductor，CMOS)技術常用以製作大量的半導體裝置在單一積體電路(integrated-circuit，IC)晶片之幾乎相同的高度上，例如金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistors，MOSFETs)及雙極性接面型電晶體(bipolar junction transistors，BJTs)。在進階的積體電路晶片中，電晶體係設置在多層上。
10‧‧‧半導體層
20‧‧‧半導體層
22‧‧‧半導體層
30‧‧‧介電層
32‧‧‧絕緣層
35‧‧‧絕緣層
40‧‧‧虛設閘極電極層
42‧‧‧硬罩幕層
45‧‧‧閘極空間
46‧‧‧第一閘極側壁間隙壁
46’‧‧‧側壁
48‧‧‧第二閘極側壁間隙壁
50‧‧‧第一層間介電層
60‧‧‧磊晶層
70‧‧‧第二層間介電層
80‧‧‧源極/汲極接觸窗
82‧‧‧閘極介電層
85‧‧‧閘極電極層
100‧‧‧下層裝置
200‧‧‧上層裝置
DG‧‧‧虛設閘極結構
根據以下詳細說明並配合附圖閱讀，使本揭露的態樣獲致較佳的理解。需強調的是，如同業界的標準作法，許多特徵並不是按照比例繪示的。事實上，為了進行清楚討論，許多特徵的尺寸可以經過任意縮放。
[圖1]係繪示根據本揭露一實施例之半導體場效電晶體裝置的剖面視圖。
[圖2]係繪示根據本揭露另一實施例之半導體場效電晶體裝置的剖面視圖。
[圖3]係繪示根據本揭露另一實施例之半導體場效電晶體裝置的剖面視圖。
[圖4A]及[圖4B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖5A]及[圖5B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖6A]及[圖6B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖7A]及[圖7B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖8A]及[圖8B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖9A]及[圖9B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖10A]及[圖10B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖11A]及[圖11B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖12A]及[圖12B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖13A]及[圖13B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖14A]及[圖14B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖15A]及[圖15B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖16A]及[圖16B]係繪示根據本揭露一實施例之製造半導體場效電晶體裝置之各步驟之一者。
[圖17]係繪示根據本揭露一實施例之半導體場效電晶體裝置的剖面視圖。
以下揭露提供許多不同實施例或例示，以實施發明的不同特徵。以下敘述之成份和排列方式的特定例示是為了簡化本揭露。這些當然僅是做為例示，其目的不在構成限制。舉例而言，元件的尺寸係不限於所揭露之範圍或數值，但可取決於製程條件及/或裝置所要求的性質。再者，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵沒有直接接觸的實施例。許多特徵的尺寸可以不同比例繪示，以使其簡化且清晰。
再者，空間相對性用語，例如「下方(beneath)」、「在...之下(below)」、「低於(lower)」、「在...之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關 係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。除此之外，用語「由...所製成(being made of)」可表示為「包含(comprising)」或「由...所組成(consisting of)」。在本揭露中，用語「A、B及C」表示「A、B及/或C」(A、B、C、A及B、A及C、B及C、或A、B及C)，且並不代表來自A的一種元件、來自B的一種元件及來自C的一種元件，除非有另外說明。
對於電晶體製程的後段製程(back-end of line)而言，必須選擇性地形成源極/汲極磊晶層。然而，選擇性的源極/汲極磊晶成長方法並不適合用於後段製程，其係由於熱預算(thermal budget)(例如低於450℃)的限制。導入高濃度的摻質至源極/汲極磊晶層常導致選擇性的磊晶成長變成非選擇性。HCl氣體有助於恢復選擇性但會減少摻質效率及成長速度。對於奈米尺度結構而言，特別是在使用鍺或矽鍺時，低熱預算是必要的。然而，對Si：P進行低溫(<500℃)的選擇性磊晶成長往往是具有挑戰性的。雖然對Ge：P進行低溫(<500℃)的選擇性磊晶成長是可行的，Ge：P僅能選擇高密度的氧化物。對於氮化物或物理氣相沉積的氧化物而言，選擇性又是一個問題。除此之外，取代閘極(replacement gate，RPG)技術通常須要接觸式開放罩幕(contact opening mask)，以在取代閘極製程之後接觸源極及汲極(S/D)。
本揭露提供一種新穎的取代閘極技術，其係藉由減少一個罩幕(不需要接觸式開放罩幕)以及非選擇性的源極/汲極磊晶製程。
在以下實施例中，一實施例的材料、配置、尺寸及/或製程可用於另一實施例中，除非有另外說明，否則其中的細節說明係可省略的。
圖1係繪示根據本揭露一實施例之半導體場效電晶體裝置的剖面視圖。在一些實施例中，半導體裝置包含半導體層20，其中半導體層20具有通道區域、設置在半導體層10上或做為半導體層10之一部分的源極區域及汲極區域、設置在半導體層20之通道區域上的閘極介電層82(例如高介電常數介電材料)、設置在閘極介電層82上的金屬閘極電極層85、設置在閘極電極層85之相對側面上的第一閘極側壁間隙壁46、及設置在半導體層20之源極及汲極區域上的源極/汲極磊晶層60。在一些實施例中，半導體層20為晶體型半導體，例如矽、矽鍺、鍺或III-V族半導體。
在一些實施例中，磊晶層60之最上方部分及閘極電極層85之最上方部分之間的高度差係小於5nm(±5nm)。在另一些實施例中，高度差係小於2nm。在特定實施例中，高度差為0(彼此完全齊平)。
在一些實施例中，源極/汲極磊晶層60係側向地設置在半導體層20之源極及汲極區域之外，且係設置在介電層30之上。在一些實施例中，介電層30為隔離絕緣層，例如淺溝渠隔離(shallow trench isolation，STI)。在一 些實施例中，源極/汲極磊晶層60包含一或多個SiP及SiCP。在另一些實施例中，源極/汲極磊晶層60包含一或多個SiGe及Ge。在一些實施例中，第一閘極側壁間隙壁46之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。在一些實施例中，第二閘極側壁間隙壁48之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。再者，如圖1所示，第一層間介電(interlayer dieletric，ILD)層50係設置在閘極結構之面上，且第二層間介電層70係設置在第一層間介電層50上。源極/汲極接觸窗80係設置在源極/汲極磊晶層60上，並穿透過第二層間介電層70。
圖2係繪示根據本揭露另一實施例之半導體場效電晶體裝置的剖面視圖。
在一些實施例中，半導體裝置包含半導體層20，其中半導體層20具有通道區域、設置在半導體層10上或做為半導體層10之一部分的源極區域及汲極區域、設置在半導體層20之通道區域上的閘極介電層82(例如高介電常數介電材料)、設置在閘極介電層82上的金屬閘極電極層85、設置在閘極電極層85之相對側面上的第一閘極側壁間隙壁46、設置在第一閘極側壁間隙壁46及閘極電極層85之間的第二閘極側壁間隙壁48、及設置在半導體層20之源極及汲極區域上的源極/汲極磊晶層60。在一些實施例中，半導體層20為晶體型半導體，例如矽、矽鍺、鍺或III-V族半 導體。
在一些實施例中，磊晶層60之最上方部分及閘極電極層85之最上方部分之間的高度差係小於5nm(±5nm)。在另一些實施例中，高度差係小於2nm。在特定實施例中，高度差為0(彼此完全齊平)。在一些實施例中，由半導體層20或22開始測量的磊晶層60之最上方部分之高度H1相對於閘極電極層85之最上方部分之高度H2的比值H1/H2的範圍為約0.90至約1.10，且在另一些實施例中，其範圍為約0.95至約1.05。
在一些實施例中，源極/汲極磊晶層60係側向地設置在半導體層20之源極及汲極區域之外，且係設置在介電層30之上。在一些實施例中，介電層30為隔離絕緣層，例如淺溝渠隔離(shallow trench isolation，STI)。在一些實施例中，源極/汲極磊晶層60包含一或多個SiP及SiCP。在另一些實施例中，源極/汲極磊晶層60包含一或多個SiGe及Ge。在一些實施例中，第一閘極側壁間隙壁46之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。在一些實施例中，第二閘極側壁間隙壁48之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。再者，如圖1所示，第一層間介電層50係設置在閘極結構之面上，且第二層間介電層70係設置在第一層間介電層50上。源極/汲極接觸窗80係設置在源極/汲極磊晶層60上，並穿透過第二層間介電層70。
在此實施例中，閘極側壁間隙壁包含第一閘極側壁間隙壁46以及比第一閘極側壁間隙壁46更靠近閘極電極85的第二閘極側壁間隙壁48。第一閘極側壁間隙壁46之彎曲表面朝向源極/汲極磊晶層60，且第二閘極側壁間隙壁48之彎曲表面朝向閘極電極層85。在一些實施例中，第二側壁間隙壁48係與閘極介電層82接觸。
在一些實施例中，一塊虛設閘極介電層(未繪示於圖1至圖3中)係設置在第一側壁間隙壁46及半導體層20之間。在一些實施例中，虛設閘極介電層並未設置在第二側壁間隙壁48及半導體層20之間。
圖3係繪示根據本揭露另一實施例之半導體場效電晶體裝置的剖面視圖。在此實施例中，做為通道區域及源/汲極區域的半導體層22係設置在絕緣層32上。在一些實施例中，絕緣層32為絕緣層上覆矽(silicon-on-insulator，SOI)晶圓的絕緣層，而在另一些實施例中，絕緣層32為設置在下方裝置(例如：電晶體)上方的層間介電層。在一些實施例中，半導體層22為晶體型半導體，例如矽、矽鍺、鍺或III-V族半導體。在一些實施例中，側壁46’係形成在半導體層22的側面上。
在一些實施例中，半導體裝置包含半導體層22，其中半導體層22具有通道區域、形成在絕緣層35上的源極區域及汲極區域、設置在半導體層22之通道區域上的閘極介電層82(例如高介電常數介電材料)、設置在閘極介電層82上的金屬閘極電極層85、設置在閘極電極層85之相對 側面上的第一閘極側壁間隙壁46、設置在第一閘極側壁間隙壁46及閘極電極層85之間的第二閘極側壁間隙壁48、及設置在半導體層22之源極及汲極區域上的源極/汲極磊晶層60。
在一些實施例中，磊晶層60之最上方部分及閘極電極層85之最上方部分之間的高度差係小於5nm(±5nm)。在另一些實施例中，高度差係小於2nm。在特定實施例中，高度差為0(彼此完全齊平)。
在一些實施例中，源極/汲極磊晶層60係側向地設置在半導體層22之源極及汲極區域之外，且係設置在絕緣層32之上。在一些實施例中，源極/汲極磊晶層60包含一或多個SiP及SiCP。在另一些實施例中，源極/汲極磊晶層60包含一或多個SiGe及Ge。在一些實施例中，第一閘極側壁間隙壁46之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。在一些實施例中，第二閘極側壁間隙壁48之最上方部分及源極/汲極磊晶層60之最上方部分或閘極電極層85之最上方部分之間的高度差係小於5nm。再者，如圖1所示，第一層間介電層50係設置在閘極結構之面上，且第二層間介電層70係設置在第一層間介電層50上。源極/汲極接觸窗80係設置在源極/汲極磊晶層60上，並穿透過第二層間介電層70。
在此實施例中，閘極側壁間隙壁包含第一閘極側壁間隙壁46以及比第一閘極側壁間隙壁46更靠近閘極電 極85的第二閘極側壁間隙壁48。第一閘極側壁間隙壁46之彎曲表面朝向源極/汲極磊晶層60，且第二閘極側壁間隙壁48之彎曲表面朝向閘極電極層85。在一些實施例中，第二側壁間隙壁48係與閘極介電層82接觸。
在一些實施例中，一塊虛設閘極介電層(未繪示於圖1至圖3中)係設置在第一側壁間隙壁46及半導體層22之間。在一些實施例中，虛設閘極介電層並未設置在第二側壁間隙壁48及半導體層22之間。
在一些實施例中，源極/汲極磊晶層60係側向地設置在半導體層22之源極及汲極區域之外，且係設置在絕緣層32之上。
再者，在一些實施例中，一或多個虛設閘極結構DG係設置在基材10上。在一些實施例中，虛設閘極結構DG具有與做為功能型電晶體之閘極結構實質上相同的結構，且並非設置在半導體層上，而是設置在絕緣層35上。源極/汲極磊晶層並未設置在虛設閘極結構DG的側面上。
在一些實施例中，如上所述之高度差不為0，且源極/汲極磊晶層60係較其他特徵高或低至少0.5nm。
圖4A至圖16B係繪示根據本揭露一實施例之製造半導體場效電晶體裝置的各步驟。須理解的是，在圖4A至圖16B所示之操作之前、之間及之後可提供其他的操作，且對於本方法的其他實施例而言，以下所述之一些操作係可被取代或去除的。操作/製程的順序係可交換的。再者，在本揭露中，源極及汲極係被交換地使用，且源極/汲極係指 源極及汲極之至少一者。在圖4A至圖16B中，「A」的圖式為透視圖，且「B」的圖式為對應圖4A之A-A’線的剖面視圖。
如圖4A及圖4B所示，提供基材10。在一些實施例中，基材為絕緣層上覆矽(SOI)基材。在另一些實施例中，基材10包含單晶半導體層在至少其表層部分上。基材10可包含單晶半導體材料，例如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在特定實施例中，基材10係由晶體Si、SíGe或Ge所形成。在一些實施例中，基材10可包含一或多個緩衝層(圖未繪示)在其表面區域內。緩衝層可用以自基材之緩衝層至源/汲極區域之緩衝層逐漸改變晶格常數。緩衝層可藉由磊晶成長單晶半導體材料而形成，例如但不限於Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP及InP。在特別的實施例中，基材10包含矽鍺(SiGe)緩衝層磊晶成長在矽基材10上。SiGe緩衝層的鍺濃度可由最底部緩衝層的30原子%鍺增加至最頂部緩衝層的70原子%鍺。
如圖4A及圖4B所示，絕緣層35係設置在基材10上，且半導體層22係設置在絕緣層35上。當使用絕緣層上覆矽基材時，半導體層22為矽層，且絕緣層35為絕緣層上覆矽基材的絕緣層。在一些實施例中，半導體層22係藉由非晶相半導體層的再結晶所形成，或形成在絕緣層35上的多晶半導體層。在一些實施例中，半導體層22為晶體型 半導體，例如矽、矽鍺、鍺或III-V族半導體。在一些實施例中，半導體層22之厚度範圍為約10nm至約10μm。
如圖5A及圖5B所示，半導體層22係被圖案化以形成主動層(通道及源/汲極區域)。
接著，形成用於閘極取代技術的虛設閘極結構，如圖6A及圖6B所示。在一些實施例中，虛設閘極結構包含虛設閘極介電層(圖未繪示)，例如氧化矽，以及虛設閘極電極層40。在一些實施例中，虛設閘極電極層40為多晶型或非晶形矽鍺或鍺。在特定實施例中，虛設閘極電極層40為非晶形或多晶型鍺。虛設閘極電極層40係藉由化學氣相沉積或任何其他合適的薄膜形成方法。在一些實施例中，在450℃或低於450℃的溫度下進行化學氣相沉積。在一些實施例中，溫度係高於200℃。
再者，硬罩幕層42係形成在虛設閘極電極層40上。在一些實施例中，硬罩幕層42係由氮化矽基材料所形成，例如氮化矽、SiON或SiCN。在硬罩幕層42形成之後，藉由一個或多個微影及蝕刻操作，以圖案化硬罩幕層42。接著，藉由利用被圖案化的硬罩幕層42為蝕刻罩幕，以圖案化被沉積的虛設閘極電極層40。在一些實施例中，形成一或多個虛設結構DG環繞功能性電晶體的虛設閘極結構，其中虛設結構DG係用以抑制製程變化及/或優化圖案的精確度。
在一些實施例中，用在功能性電晶體的虛設閘極電極40包含設置在半導體層20上的閘極部分以及設置在 絕緣層35上之做為閘極接觸的襯墊部分。虛設閘極電極40的末端係設置在絕緣層35上。虛設結構DG係形成在介電層上。在一些實施例中，虛設閘極電極40之厚度範圍為約20nm至約500nm，而在另一些實施例中，其厚度範圍為約50nm至約200nm。在一些實施例中，硬罩幕層42之厚度範圍為約20nm至約100nm。
接著，圖7A及圖7B所示，第一側壁間隙壁46係形成在虛設閘極電極40之側面上。第一側壁間隙壁之絕緣材料的毯覆層係藉由化學氣相沉積或其他合適的方法而共形地形成。毯覆層係以共形的方式沉積，故其係形成以具有實質相等的厚度在鉛直表面(例如側壁)、水平表面以及虛設閘極結構之頂部上。在一些實施例中，毯覆層係沉積至約2nm至約30nm的厚度。在一實施例中，毯覆層之絕緣材料係不於於虛設閘極結構之材料，且係由氮化矽基材料所形成，例如氮化矽、SiON、SiOCN或SiCN及上述的組合。在一些實施例中，毯覆層係由氮化矽所形成。側壁間隙壁係藉由非等向性蝕刻而形成在虛設閘極結構之相對側面上。如圖7A及圖7B所示，側壁46’係形成在半導體層22之側面上，且側壁間隙壁亦係形成在虛設結構DG上。
然後，如圖8A及圖8B所示，形成源極/汲極磊晶層60。源極/汲極磊晶層60包含一層或多層做為n型通道場效電晶體的Si、SiP、SiC及SiCP或做為p型通道場效電晶體的SiGe、Ge。對於p型通道場效電晶體而言，硼可被包含於源極/汲極區域中。在一些實施例中，源極/汲極磊晶 層係藉由磊晶成長方法所形成，其係在低於500℃的溫度下利用化學氣相沉積法、原子層沉積法或分子束磊晶法(molecular beam epitaxy，MBE)。在另一些實施例中，溫度係在約250℃至約450℃的範圍，而在特定實施例中，溫度係在約250℃至約350℃的範圍。在一些實施例中，源極/汲極磊晶層係非選擇性地不僅形成在半導體層22之源極/汲極區域上，且形成在絕緣層35上。在一些實施例中，在源極/汲極磊晶層60形成之前，半導體層22之源極/汲極區域係被凹陷，且源極/汲極磊晶層60係形成在凹陷的源極/汲極區域上。在一些實施例中，源極/汲極磊晶層60係形成為使源極/汲極磊晶層60之頂部位於虛設閘極結構之下，其中虛設閘極結構係包含虛設閘極電極40及硬罩幕層42。在另一些實施例中，源極/汲極磊晶層60係形成為使源極/汲極磊晶層60完全地覆蓋虛設閘極結構。
接著，如圖9A及圖9B所示，進行平坦化操作(例如化學機械研磨製程)，以平坦化源極/汲極磊晶層60。在一些實施例中，進行化學機械研磨製程，以使硬罩幕層42被暴露出。
然後，如圖10A及圖10B所示，藉由一或多次微影及蝕刻操作，圖案化被平坦化的源極/汲極磊晶層60，以使源極/汲極磊晶層保持實質地在半導體層20之源極/汲極區域上。
在一些實施例中，源極/汲極磊晶層60包含形成在半導體層22之源極/汲極區域上的結晶部分以及形成在絕 緣層35上的非結晶部分。在一些實施例中，被平坦化的源極/汲極磊晶層60之非結晶部分可藉由合的溼式及/或乾式蝕刻而選擇性地被移除，而不使用微影操作[無罩幕(光阻)圖案]。在一些實施例中，氨水-過氧化氫-水混合物(ammonia hydroxide-hydrogen peroxide-water mixture，APM)係做為溼式蝕刻劑。
接著，第一層間介電層50係形成在源極/汲極磊晶層60及虛設閘極結構上，如圖11A及圖11B所示。做為第一層間介電層50的材料包括含有矽、氧、碳及/或氫的化合物，例如氧化矽、SiCOH及SiOC。有機材料(例如聚合物)可用以做為第一層間介電層50。在第一層間介電層50形成之後，進行平坦化操作(例如化學機械研磨製程)，以使源極/汲極磊晶層60及虛設閘極電極層40之頂部部分被暴露出，如圖12A及圖12B所示。在一些實施例中，源極/汲極磊晶層60及虛設閘極電極層40係做為化學機械研磨中止層。在一些實施例中，在第一層間介電層50被形成之前，形成接觸蝕刻中止層，例如氮化矽層或氮氧化矽層。
然後，虛設閘極電極層40及虛設閘極介電層被移除，藉以形成閘極空間45，如圖13A及圖13B所示。虛設閘極結構可利用電漿乾式蝕刻及/或溼式蝕刻而被移除。在一些實施例中，當虛設閘極電極層40係由多晶型或非晶型鍺所形成，氨水-過氧化氫-水混合物係做為溼式蝕刻劑。在一些實施例中，當虛設閘極電極層40係由多晶型或非晶型矽所形成，四甲基氫氧化銨(tetramethylammonium hydroxide，TMAH)水溶液係做為溼式蝕刻劑。虛設閘極介電層也可藉由合適的溼式/乾式蝕刻而移除。
在虛設閘極結構被移除之後，在一些實施例中，第二閘極側壁間隙壁40係選擇性地形成在閘極空間45內的第一閘極側壁間隙壁46上，如圖14A及圖14B所示。做為第二閘極側壁間隙壁48的介電材料可與第一側壁間隙壁46的介電材料相同或不同。藉由形成第二閘極側壁間隙壁48，閘極空間45的寬度被減少，且後續形成之金屬閘極電極的閘極長度可被減少。
接著，如圖15A及圖15B所示，閘極介電層及閘極電極85係形成在閘極空間內。在一些實施例中，閘極介電層82包含一或多層介電材料，例如氧化矽、氮化矽或高介電常數(高k)介電材料、其他合適的介電材料及/或前述的組合。高k介電材料包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料及/或前述的組合。在一些實施例中，閘極介電層82包含藉由化學氧化法形成在道通層及介電材料之間的界面層。閘極介電層82可藉由化學氣相沉積法、原子層沉積法或任意合適的方法而形成。在一實施例中，閘極介電層82係利用例如原子層沉積的高度共形沉積製程而形成，以確保形成在圍繞每一個通道層之閘極介電層具有一致的厚度。在一實施例中，閘極介電層82之厚度範圍為約1nm至約10nm。
閘極電極層82包含一層或多層導電材料，例如 多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適的材料及/或前述之組合。閘極電極層85可藉由化學氣相沉積、原子層沉積、電鍍或其他合適的方法所製成。做為閘極介電層82及閘極電極層85的金屬亦係被沉積在第一層間介電層50之上表面。形成在第一層間介電層50上之做為閘極電極層85的材料係接著藉由例如化學機械研磨而被平坦化，直至第一層間介電層50之頂表面被暴露出，如圖16A及圖16B所示。在一些實施例中，在平坦化操作之後，金屬閘極電極層係被凹陷，且頂蓋絕緣層(圖未繪示)係形成在凹陷的閘極電極層上。頂蓋絕緣層包含一層或多層的氮化矽基材料，例如氮化矽。頂蓋絕緣層可藉由沉積絕緣材料並接續平坦化操作而形成。
在本揭露的特定實施例中，一或多個功函數調整層(圖未繪示)係介於閘極介電層82及閘極電極層85之間。功函數調整層係由導電材料所形成，例如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或多層二種或多種上述材料。對於n型通道場效電晶體，一或多個TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi係用作功函數調整層，而對於p型通道場效電晶體，一或多個TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及鈷係用作功函數調整層。功函數調整層可藉由原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍或其他合適的製程所形成。再者，功函數調整層可分別形成給使用不 同金屬層的n型通道場效電晶體及p型通道場效電晶體。
再者，第二層間介電層70係形成在第一層間介電層50上(參閱圖1至圖3)，且穿透第二層間介電層70或第二層間介電層及第一層間介電層的導電接觸窗80係形成以接觸閘極電極85及源極/汲極磊晶層60。接觸窗開口係形成在第一層間介電層50及/或第二層間介電層70內。一層或多層導電材料係形成在接觸窗開口內及其上，接著進行平坦化操作(例如化學機械研磨)以形成導電接觸窗80。在一些實施例中，導電接觸窗80包含襯層及主體層。襯層為阻障層及/或黏著(附著)層。在一些實施例中，鈦層係形成在源極/汲極磊晶層上，而TiN或TaN層係形成在鈦層上，做為襯層。主體層包含一層或多層Co、Ni、W、Ti、Ta、Cu及鋁，或任意其他合適的材料。
須理解的是，場效電晶體經過進一步的互補式金氧半製程(CMOS process)，以形成各種特徵，例如接觸窗/介層窗、內連接金屬層、介電層、鈍化層等。
圖17係繪示根據本揭露一實施例之半導體裝置的剖面視圖。如圖17所示，下層裝置100係形成在基材上。下層裝置100包含一或多個鰭式場效電晶體(fin field effect transistors，FinFETs)、環繞式閘極場效電晶體(gate-all-around FET，GAA FET)、平面式場效電晶體、直立式場效電晶體或任意其他的電子裝置。圖17亦繪示設置在下層裝置100上的上層裝置200。在一些實施例中，一或多層層間介電層、金屬電線層及/或介層接觸窗係設置在 下層裝置100及上層裝置200之間。在一些實施例中，上層裝置200包含一或多個藉由本揭露之前述實施例所製造的場效電晶體。
在前述實施例中，在不增加微影製程數下，甚至在閘極替換製程中減少一次微影製程下，形成源極/汲極結構係可達成的。在閘極替換製程中減少閘極長度亦是可達成的。再者，獲得大量源極/汲極磊晶層係可達成的，且亦可增加接觸面積。除此之外，由於低溫製程係可形成源極/汲極磊晶層，前述製程對於後段製程係有益的。
須理解的是，並非所有優點都有必要在此討論，沒有特定優點係適用於所有實施例或具體例的，且其他實施例或具體例可提供不同的優點。
根據本揭露之一態樣，在半導體裝置的製造方法中，虛設閘極結構係形成在半導體層之通道區域上，源極/汲極磊晶層係被形成，平坦化操作係對源極/汲極磊晶層進行，被平坦化之源極/汲極磊晶層係圖案化，虛設閘極結構係被移除，以形成閘極空間，以及金屬閘極結構係形成在閘極空間內。在一或多個上述或以下實施例中，在形成源極/汲極磊晶層之前，第一閘極側壁間隙壁係形成在虛設閘極結構之相對側面上。在一或多個上述或以下實施例中，第二閘極側壁間隙壁係形成在閘極空間內之第一閘極側壁間隙壁上。在一或多個上述或以下實施例中，虛設閘極結構包含虛設閘極電極層，且虛設閘極電極層係由多晶體或非晶形的矽鍺或鍺所形成。在一或多個上述或以下實施例中，源極/汲 極磊晶層係形成為使源極/汲極磊晶層之頂部位於虛設閘極結構之上。在一或多個上述或以下實施例中，源極/汲極磊晶層係形成為使源極/汲極磊晶層完全地覆蓋虛設閘極結構。在一或多個上述或以下實施例中，源極/汲極磊晶層係在250℃至450℃之溫度下形成。在一或多個上述或以下實施例中，第一層間介電層係形成在被平坦化之源極/汲極磊晶層及虛設閘極結構上，且平坦化操作係對第一層間介電層進行，以使被平坦化之源極/汲極磊晶層及虛設閘極結構之上表面被暴露。在一或多個上述或以下實施例中，第二層間介電層係形成在金屬閘極結構上，且源極/汲極接觸係被形成。在一或多個上述或以下實施例中，半導體裝置係形成在絕緣層上覆矽基材上，且半導體層為絕緣層上覆矽基材之矽層。
根據本揭露之一態樣，在半導體裝置的製造方法中，半導體層係形成在設置在基材上之介電層上方，虛設閘極結構係形成在半導體層之通道區域上，源極/汲極磊晶層係被形成，平坦化操作係對源極/汲極磊晶層進行，被平坦化之源極/汲極磊晶層係圖案化，虛設閘極結構係被移除，以形成閘極空間，以及金屬閘極結構係形成在閘極空間內。在一或多個上述或以下實施例中，在形成源極/汲極磊晶層之前，第一閘極側壁間隙壁係形成在虛設閘極結構之相對側面上。在一或多個上述或以下實施例中，第二閘極側壁間隙壁係形成在閘極空間內之第一閘極側壁間隙壁上。在一或多個上述或以下實施例中，虛設閘極結構包含虛設閘極電 極層，且虛設閘極電極層係由多晶體或非晶形的矽鍺或鍺所形成。在一或多個上述或以下實施例中，源極/汲極磊晶層係形成為使源極/汲極磊晶層之頂部位於虛設閘極結構之上。在一或多個上述或以下實施例中，源極/汲極磊晶層係形成為使源極/汲極磊晶層完全地覆蓋虛設閘極結構。在一或多個上述或以下實施例中，源極/汲極磊晶層係在250℃至450℃之溫度下形成。在一或多個上述或以下實施例中，第一層間介電層係形成在被平坦化之源極/汲極磊晶層及虛設閘極結構上，且平坦化操作係對第一層間介電層進行，以使被平坦化之源極/汲極磊晶層及虛設閘極結構之上表面被暴露。在一或多個上述或以下實施例中，場效電晶體係形成在基材上，且介電層係形成以覆蓋場效電晶體。
根據本揭露之一態樣，在半導體裝置的製造方法，虛設閘極結構係形成在半導體層之通道區域上，源極/汲極磊晶層係被形成。源極/汲極磊晶層包含形成在半導體層之源極/汲極區域之上的晶體部分，以及形成在介電層上的非晶體部分。平坦化操作係對源極/汲極磊晶層進行，被平坦化之源極/汲極磊晶層的非晶體部分係被選擇性地移除，虛設閘極結構係被移除，以形成閘極空間，且金屬閘極結構係形成在閘極空間內。在一或多個上述或以下實施例中，源極/汲極磊晶層包含SiP。在一或多個上述或以下實施例中，在形成源極/汲極磊晶層之前，第一閘極側壁間隙壁係形成在虛設閘極結構之相對側面上。在一或多個上述或以下實施例中，第二閘極側壁間隙壁係形成在閘極空間內之第 一閘極側壁間隙壁上。在一或多個上述或以下實施例中，虛設閘極結構包含虛設閘極電極層，且虛設閘極電極層係由多晶體或非晶形的矽鍺或鍺所形成。在一或多個上述或以下實施例中，源極/汲極磊晶層係形成為使源極/汲極磊晶層之頂部位於虛設閘極結構之上。在一或多個上述或以下實施例中，源極/汲極磊晶層係形成為使源極/汲極磊晶層完全地覆蓋虛設閘極結構。在一或多個上述或以下實施例中，源極/汲極磊晶層係在250℃至450℃之溫度下形成。在一或多個上述或以下實施例中，第一層間介電層係形成在被平坦化之源極/汲極磊晶層及虛設閘極結構上，且平坦化操作係對第一層間介電層進行，以暴露出被平坦化之源極/汲極磊晶層及虛設閘極結構之上表面。在一或多個上述或以下實施例中，場效電晶體係形成在基材上，且介電層係形成以覆蓋場效電晶體。在一或多個上述或以下實施例中，在源極/汲極磊晶層被形成之前，半導體層之源極/汲極區域係被凹陷。
根據本揭露之一態樣，半導體裝置包含形成為半導體層之部分的通道、設置在通道上的閘極介電層、設置在閘極介電層上的閘極電極層、設置在閘極電極層之相對側面上的閘極側壁間隙壁、源極及汲極，源極和汲極之每一者包含磊晶層，其中半導體層係設置在介電層上。在一或多個上述或以下實施例中，磊晶層之最上方部分及閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，高度差為0。在一或多個上述或以下實施例中，源極/汲極磊晶層係側向地設置在半導體層之源極及汲 極區域之外，且係設置在絕緣層之上。在一或多個上述或以下實施例中，介電層為隔離絕緣層。在一或多個上述或以下實施例中，源極/汲極磊晶層包含一或多個SiP及SiCP。在一或多個上述或以下實施例中，閘極側壁間隙壁之最上方部分及磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，閘極側壁間隙壁包含第一閘極側壁間隙壁以及第二閘極側壁間隙壁，且第一閘極側壁間隙壁之彎曲表面係與源極/汲極磊晶層接觸，第二閘極側壁間隙壁之彎曲表面係與閘極介電層接觸。在一或多個上述或以下實施例中，一或多個虛設閘極結構係設置在介電層上。在一或多個上述或以下實施例中，一或多個虛設閘極結構之最上方部分及源極/汲極磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，場效電晶體係被介電層所覆蓋。
根據本揭露之一態樣，半導體裝置包含設置在基材上的電子裝置、設置在電子裝置上的一或多層介電層，以及設置在一或多層介電層之最上層上的薄膜電晶體。每一個薄膜電晶體包含形成為半導體層之部分的通道、設置在通道上的閘極介電層、設置在閘極介電層上的閘極電極層、設置在閘極電極層之相對側面上的閘極側壁間隙壁、源極及汲極，源極和汲極之每一者包含磊晶層，其中半導體層係設置在介電層上。由半導體層開始測量的磊晶層之最上方部分之高度相對於閘極電極層之最上方部分之高度的比值H1/H2 的範圍為約0.90至約1.10。在一或多個上述或以下實施例中，磊晶層之最上方部分及閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，電子元件為電晶體。在一或多個上述或以下實施例中，電晶體為鰭式場效電晶體及環繞式閘極場效電晶體其中之一者。在一或多個上述或以下實施例中，高度差為0。在一或多個上述或以下實施例中，源極/汲極磊晶層係側向地設置在半導體層之源極及汲極區域之外，且係設置在絕緣層之上。在一或多個上述或以下實施例中，介電層為隔離絕緣層。在一或多個上述或以下實施例中，源極/汲極磊晶層包含一或多個SiP及SiCP。在一或多個上述或以下實施例中，閘極側壁間隙壁之最上方部分及磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，閘極側壁間隙壁包含第一閘極側壁間隙壁以及第二閘極側壁間隙壁，且第一閘極側壁間隙壁之彎曲表面係與源極/汲極磊晶層接觸，第二閘極側壁間隙壁之彎曲表面係與閘極介電層接觸。在一或多個上述或以下實施例中，一或多個虛設閘極結構係設置在介電層上。在一或多個上述或以下實施例中，一或多個虛設閘極結構之最上方部分及源極/汲極磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。
根據本揭露之一態樣，半導體裝置包含由半導體材料所形成的通道、設置在通道上的閘極介電層、設置在閘極介電層上的閘極電極層、設置在閘極電極層之相對側面 上的閘極側壁間隙壁、源極及汲極，源極和汲極之每一者包含磊晶層。磊晶層之最上方部分及閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，高度差為0。在一或多個上述或以下實施例中，源極/汲極磊晶層係側向地設置在半導體層之源極及汲極區域之外，且係設置在絕緣層之上。在一或多個上述或以下實施例中，介電層為隔離絕緣層(淺溝渠隔離)。在一或多個上述或以下實施例中，源極/汲極磊晶層包含一或多個SiP及SiCP。在一或多個上述或以下實施例中，閘極側壁間隙壁之最上方部分及磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。在一或多個上述或以下實施例中，閘極側壁間隙壁包含第一閘極側壁間隙壁以及第二閘極側壁間隙壁，且第一閘極側壁間隙壁之彎曲表面係與源極/汲極磊晶層接觸，第二閘極側壁間隙壁之彎曲表面係與閘極介電層接觸。在一或多個上述或以下實施例中，一或多個虛設閘極結構係設置在介電層上。在一或多個上述或以下實施例中，一或多個虛設閘極結構之最上方部分及源極/汲極磊晶層之最上方部分或閘極電極層之最上方部分之間的高度差係小於5nm。
上述摘要許多實施例的特徵，因此本領域具有通常知識者可更了解本揭露的態樣。本領域具有通常知識者應理解利用本揭露為基礎可以設計或修飾其他製程和結構以實現和所述實施例相同的目的及/或達成相同優勢。本領域具有通常知識者也應了解與此同等的架構並沒有偏離本 揭露的精神和範圍，且可以在不偏離本揭露的精神和範圍下做出各種變化、交換和取代。
10‧‧‧半導體層
20‧‧‧半導體層
30‧‧‧介電層
46‧‧‧第一閘極側壁間隙壁
48‧‧‧第二閘極側壁間隙壁
50‧‧‧第一層間介電層
60‧‧‧磊晶層
70‧‧‧第二層間介電層
80‧‧‧源極/汲極接觸窗
82‧‧‧閘極介電層
85‧‧‧閘極電極層

Claims (20)

  1. 一種半導體裝置的製造方法，包含：形成一虛設閘極結構在一半導體層之一通道區域上；形成一源極/汲極磊晶層在該虛設閘極結構之複數個相對側上；對該源極/汲極磊晶層進行一平坦化操作；圖案化被平坦化之該源極/汲極磊晶層；移除該虛設閘極結構，以形成一閘極空間；以及形成一金屬閘極結構在該閘極空間內。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包含：在形成該源極/汲極磊晶層之前，形成複數個第一閘極側壁間隙壁在該虛設閘極結構之複數個相對側面上。
  3. 如申請專利範圍第2項所述之半導體裝置的製造方法，更包含：在形成該閘極空間之後，形成複數個第二閘極側壁間隙壁在該閘極空間內之該第一閘極側壁間隙壁上。
  4. 如申請專利範圍第3項所述之半導體裝置的製造方法，其中該虛設閘極結構包含一虛設閘極電極層，且該虛設閘極電極層係由多晶體或非晶形的矽鍺或鍺所形成。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係形成為使該源極/汲極磊晶層之一頂部位於該虛設閘極結構之上。
  6. 如申請專利範圍第5項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係形成為使該源極/汲極磊晶層完全地覆蓋該虛設閘極結構。
  7. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係在250℃至450℃之一溫度下形成。
  8. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包含：形成一第一層間介電(interlayer dieletric，ILD)層在被平坦化之該源極/汲極磊晶層及該虛設閘極結構上；以及對該第一層間介電層進行一平坦化操作，以使被平坦化之該源極/汲極磊晶層及該虛設閘極結構之複數個上表面被暴露。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，更包含：形成一第二層間介電層在該金屬閘極結構上；以及形成一源極/汲極接觸。
  10. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該半導體裝置係形成在一絕緣層上覆矽(silicon-on-insulator，SOI)基材上，且該半導體層為該絕緣層上覆矽基材之一矽層。
  11. 一種半導體裝置的製造方法，包含：形成一半導體層在一介電層上，其中該介電層係設置在一基材上；形成一虛設閘極結構在該半導體層之一通道區域上；形成一源極/汲極磊晶層在該虛設閘極結構之複數個相對側上；對該源極/汲極磊晶層進行一平坦化操作；圖案化被平坦化之該源極/汲極磊晶層；移除該虛設閘極結構，以形成一閘極空間；以及形成一金屬閘極結構在該閘極空間內。
  12. 如申請專利範圍第11項所述之半導體裝置的製造方法，更包含：在形成該源極/汲極磊晶層之前，形成複數個第一閘極側壁間隙壁在該虛設閘極結構之複數個相對側面上。
  13. 如申請專利範圍第12項所述之半導體裝置的製造方法，更包含：形成第二閘極側壁間隙壁在該閘極空間內之該第一閘 極側壁間隙壁上。
  14. 如申請專利範圍第13項所述之半導體裝置的製造方法，其中該虛設閘極結構包含一虛設閘極電極層，且該虛設閘極電極層係由多晶體或非晶形的矽鍺或鍺所形成。
  15. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係形成為使該源極/汲極磊晶層之一頂部位於該虛設閘極結構之上。
  16. 如申請專利範圍第15項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係形成為使該源極/汲極磊晶層完全地覆蓋該虛設閘極結構。
  17. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該源極/汲極磊晶層係在250℃至450℃之一溫度下形成。
  18. 如申請專利範圍第11項所述之半導體裝置的製造方法，更包含：形成一第一層間介電層在被平坦化之該源極/汲極磊晶層及該虛設閘極結構上；以及對該第一層間介電層進行一平坦化操作，以暴露出被平坦化之該源極/汲極磊晶層及該虛設閘極結構之複數個 上表面。
  19. 如申請專利範圍第18項所述之半導體裝置的製造方法，包含：形成一場效電晶體在該基材上；以及形成該介電層，以覆蓋該場效電晶體。
  20. 一種半導體裝置，包含：一通道，形成為一半導體層之一部分，其中該半導體層係設置在一介電層上；一閘極介電層，設置在該通道上；一閘極電極層，設置在該閘極介電層上；複數個閘極側壁間隙壁，設置在該閘極電極層之複數個相對側面上；以及一源極及一汲極，該源極和該汲極之每一者包含一磊晶層，其中該磊晶層之一最上方部分及該閘極電極層之一最上方部分之間的一高度差係小於5nm。
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TWI711073B (zh) 2020-11-21
US20200135897A1 (en) 2020-04-30
US20210265490A1 (en) 2021-08-26
CN111128734B (zh) 2023-12-19
CN111128734A (zh) 2020-05-08
US11764289B2 (en) 2023-09-19
KR20200050327A (ko) 2020-05-11
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US11004958B2 (en) 2021-05-11
US20230361202A1 (en) 2023-11-09

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