TW202017119A - 半導體裝置封裝及其製造方法 - Google Patents
半導體裝置封裝及其製造方法 Download PDFInfo
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Abstract
一種封裝基板包括一第一介電層、一第一圖案化導電層及一第一組對準標記。該第一圖案化導電層安置在該第一介電層上。該第一組對準標記安置在該第一介電層上且鄰近該第一介電層之一第一邊緣。該第一組對準標記包括複數個對準標記。該第一組對準標記中之該等對準標記與該第一邊緣之間的距離彼此不同。
Description
本發明係關於一種半導體裝置封裝及其製造方法,且係關於一種包括多層基板之半導體裝置封裝及其製造方法。
多層基板廣泛用於許多半導體裝置封裝中。多層基板可包括多個層(例如,介電層)。該等層中之每一者具有圖案化導電層。基板之任何兩個層之間的對準對於獲得更好的可為重要的。
根據本發明之一些實施例,一種封裝基板包括一第一介電層、一第一圖案化導電層及一第一組對準標記。該第一圖案化導電層安置在該第一介電層上。該第一組對準標記安置在該第一介電層上且鄰近該第一介電層之一第一邊緣。該第一組對準標記包括複數個對準標記。該第一組對準標記中之該等對準標記與該第一邊緣之間的距離彼此不同。
根據本發明之一些實施例,一種用於製造一半導體裝置封裝之方法包括:(a)提供一基板;(b)將一電子組件安置在該基板上;及(c)在該基板上形成一封裝本體以覆蓋該電子組件。該基板包括一第一介電層、一第一圖案化導電層及一第一組對準標記。該第一圖案化導電層安置在該第一介電層上。該第一組對準標記安置在該第一介電層上且鄰近該第一介電層之一第一邊緣。該第一組對準標記包括複數個對準標記。該第一組對準標記中之該等對準標記之長度彼此不同。
根據本發明之一些實施例,一種用於製造一半導體裝置封裝之方法包括:(a)提供一基板;(b)將一電子組件安置在該基板上;及(c)在該基板上形成一封裝本體以覆蓋該電子組件。該基板具有一第一介電層、一第一圖案化導電層及一第一組對準標記。該第一圖案化導電層安置在該第一介電層上。該第一組對準標記安置在該第一介電層上且鄰近該第一介電層之一第一邊緣。該第一組對準標記包括複數個對準標記。該第一組對準標記中之該等對準標記與該第一邊緣之間的距離彼此不同。
相關申請案之交叉參考
本申請案主張2018年10月19日申請之美國臨時申請案第62/748,172號之權益及優先權,該臨時申請案之內容以全文引用之方式併入本文中。
圖1A說明根據某些比較技術之基板封裝之橫截面視圖。基板封裝包括基板10及安置於基板10內之圖案化導電層(例如,重佈層(RDL)或天線場型)。基板10可為多層基板,其包括核心結構10a、介電層10b、10c及保護層10d、10e (例如,包括阻焊劑或防焊劑之層)。核心結構10a可例如選自但不限於矽基板、塑膠基板或陶瓷基板。介電層10b及10c分別安置在核心結構10a之頂面及底面上。介電層10b及10c中之每一者可包括諸如聚丙烯(PP)、雙馬來醯亞胺三嗪(BT)樹脂、環氧樹脂、聚醯亞胺(PI)或其他介電材料之材料。介電層10b及10c可包括彼此相同的材料或可包括不同材料。在其他實施例中,基板10可為無核心多層基板,其省略核心結構並包括複數個介電層(或子層)。
基板10之一或多個層包括圖案化導電層。舉例而言,如圖1A中所展示,圖案化導電層可安置於核心結構10a及介電層10b以及10c上。舉例而言,圖案化導電層可安置於核心結構10a之兩個表面上。舉例而言,圖案化導電層可安置於介電層10b之頂面上並由保護層10d覆蓋。舉例而言,圖案化導電層可安置於介電層10c之底面上並由保護層10e覆蓋。
基板10包括一或多組對準標記(例如,基板10之層之側向表面上的第一組對準標記10m1、第二組對準標記10m2、第三組對準標記10m3及第四組對準標記10m4),且該等若干組對準標記中之每一者具有相同數目的對準標記。對準標記之間距實質上相同。舉例而言,任何兩個鄰近對準標記之間的距離實質上相同。對準標記之寬度實質上相同。在一些實施例中,每一對準標記之寬度為約20微米(μm)。
若干組對準標記10m1、10m2、10m3及10m4可用於判定基板10之層(及基板10內之圖案化導電層)是否彼此對準。舉例而言,如圖1A中所展示,基板10之對準標記10m1、10m2、10m3及10m4彼此對準,且因此判定基板10之層(及基板10內之圖案化導電層)彼此對準。換言之,在基板10之層中最小化或縮減移位、偏差或漂移。
如圖1B中所展示,該組對準標記10m2 (自頂部起第二組)與其他組對準標記10m1、10m3及10m4未對準,且因此判定其上安置有該組對準標記10m2之核心結構10a具有移位、偏差或漂移。可基於該組對準標記10m2之位置相對於該組對準標記10m1或10m3之位置而判定層10b之移位、偏差或漂移的距離或量。
由於製造對準標記之限制,對準標記之間距可受限制(例如,對準標記之最小間距為約20 μm至約25 μm),從而縮減了用於判定移位、偏差或漂移之準確度。另外,如圖1C中所展示,可能難以量測對準標記之移位距離,圖1C為展示包括對準標記之基板的影像。
圖2說明根據本發明之一些實施例的多層基板(例如,如圖3A或圖3B中所展示之基板20)之一個層的一部分(例如,該層之四分之一)之俯視圖。圖2中所說明之基板20類似於圖1A中所說明之基板10,且基板10之一些描述可適用於圖2中之基板20。基板20之經描繪層包括電路區22 (其可延伸超出圖2中所展示之層之右下角)。在一些實施例中,電路區22可為或可包括RDL、天線場型及/或晶片結合區。電路區22與基板20之層之邊緣間隔開。舉例而言,基板20之層之邊緣中之每一者與電路區22之間存在一距離。在一些實施例中,基板20之層之邊緣中之每一者與電路區22之間的距離為約100 μm至約150 μm。
基板20之層包括若干組對準標記20m1、20m2,且每一組對準標記包括多個對準標記。應注意,在一些其他實施例中,基板或基板之層可包括單組(僅一組)對準標記。若干組對準標記20m1及20m2位於基板20之層之邊緣與電路區22之間的空間(例如,側軌)處。該組對準標記20m1沿著邊緣201安置。該組對準標記20m2沿著邊緣202安置。如圖2中所展示,若干組對準標記20m1及20m2中之對準標記的長度彼此不同。舉例而言,該組對準標記20m1中之對準標記之長度自邊緣202至電路區22逐漸增加(例如,單調地增加)(例如,在自外部邊緣朝向中心部分之方向上)。在一些實施例中,兩個鄰近對準標記之間的長度差D21為約2 μm至約5 μm。任何兩個鄰近對準標記藉由實質上相同距離彼此間隔開。在一些實施例中,對準標記具有實質上相同寬度(例如,約30 μm至約50 μm)。替代地,對準標記之寬度可取決於設計規格來調整。舉例而言,一組對準標記可包括九個對準標記,其中第一對準標記具有第一寬度(例如,約50 μm),第二對準標記至第四對準標記具有第二寬度(例如,約30 μm),第五對準標記具有第一寬度(例如,約50 μm),且第六對準標記至第九對準標記具有第二寬度(例如,約30 μm)。在一些實施例中,最後一個對準標記(例如,最長對準標記)可具有不同於任何其他對準標記之寬度的寬度以指示端點。在一些實施例中,一組對準標記中之兩個鄰近對準標記之長度的差實質上等於該組對準標記中之任何其他兩個鄰近對準標記之長度的差。
基板20可包括多個層,其各自具有與圖2中所展示之圖案化導電層及對準標記相同及/或類似之圖案化導電層及對準標記。多個層經堆疊在一起以形成多層基板20,如圖3A或圖3B中所展示。基板20之層之電路區22及若干組對準標記20m1、20m2彼此對準。若基板20之層中之任一者中存在極小或不存在移位、偏差或漂移,則基板20之每一層應在其如圖3A或圖3B中所展示之側向表面上具有相同數目的對準標記(例如,20m1、20m1'、20m1''及20m1'''應具有相同數目的對準標記)。舉例而言,如圖3A中所展示,基板20之層中之每一者在其側向表面上具有一個對準標記,且因此判定基板20之層中之任一者中不存在移位、偏差或漂移。類似地,如圖3B中所展示,基板20之層中之每一者在其側向表面上具有三個對準標記,且因此判定基板20之層中之任一者中不存在移位、偏差或漂移。
圖3A中之結構與圖3B中之結構之間的差異中之一者為在基板20之每一層之側向表面上展示的對準標記之數目。對準標記之數目自圖3A及圖3B中所說明之基板20之每一層的側向表面曝露的原因中之一者為當對基板條帶執行單體化操作時,用於圖3B中所說明之基板20的切割裝置相對較寬。
圖4A及圖4B說明根據本發明之一些實施例的基板20在基板20之層中之一者存在移位、偏差或漂移之狀況下的透視圖。如圖4A及圖4B中所展示,基板20之一個層之側向表面上的一組對準標記中之對準標記的數目不同於基板20之其他層之側向表面上之其他組對準標記中之對準標記的數目。舉例而言,如圖4A中所展示,基板20之層之側向表面上的該組對準標記20m1'中之對準標記的數目不同於(大於)基板20之其他層之側向表面上的其他組對準標記20m1、20m1''及20m1'''中之對準標記的數目,且因此判定其上定位有該組對準標記20m1'之層存在移位、偏差或漂移。類似地,如圖4B中所展示,基板20之層之側向表面上的該組對準標記20m1''中之對準標記的數目不同於(大於)基板20之其他層之側向表面上的其他組對準標記20m1、20m1'及20m1'''中之對準標記的數目,且因此判定其上定位有該組對準標記20m1''之層存在移位、偏差或漂移。換言之,可基於基板20之層之側向表面上所展示的對準標記之數目而判定基板20之層是否存在移位、偏差或漂移。
另外,可基於經移位層之對準標記之數目相對於任何其他未經移位層之對準標記之數目而判定基板20之層之移位、偏差或漂移的距離。舉例而言,如圖4A中所展示,其上定位有該組對準標記20m1'之層在其側向表面上的對準標記比其他層之側向表面上之其他組對準標記20m1、20m1''及20m1'''中之對準標記的數目多兩個。因此,經移位層相對於其他未經移位層之移位距離為2×N,其中N為兩個鄰近對準標記之間的長度差。舉例而言,若N為5 μm,則第二層之移位距離為約10 μm。類似地,如圖4B中所展示,其上定位有該組對準標記20m1''之層在其側向表面上的對準標記比其他層之側向表面上之其他組對準標記20m1'、20m1'及20m1'''中之對準標記的數目多四個。因此,第三層相對於其他層之移位距離為4×N,其中N為兩個鄰近對準標記之間的長度差。
在一些實施例中,對準標記可經展示在基板20之每一層之兩個鄰近側向表面上,如圖5中所展示,以在x方向及y方向兩者上量測層之移位、偏差或漂移。
圖6A說明根據本發明之一些實施例的多層基板之一個層之一部分(例如,層之四分之一)之俯視圖。圖6A中所說明之結構類似於圖2中之結構,且其間之差異中之一者為圖6A中所說明之若干組對準標記60m1及60m2中之對準標記以經描繪方式分別與基板之層之邊緣201及202對準。因此,如圖6B中所展示,若基板之一個層存在移位、偏差或漂移,則基板之經移位層(例如,其上定位有該組對準標記60m1'之層)之側向表面上的對準標記之數目小於基板之其他未經移位層之側向表面上的若干組對準標記60m1、60m1''及60m1'''中之對準標記的數目。
根據圖2、圖3A、圖3B、圖4A、圖4B、圖5、圖6A及圖6B之實施例,由於移位距離係藉由經移位層之側向表面上展示之對準標記之數目相對於未經移位層之側向表面上展示之對準標記之數目來判定,因此有可能容易地並且準確地量測移位距離。另外,用於判定移位距離之構件係藉由兩個鄰近對準標記之間的長度差—而非藉由如圖1A及圖1B中所展示之對準標記之寬度—來判定,其可在判定移位距離時提供較大準確度。
圖7A、圖7B、圖7C及圖7D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。
參考圖7A,提供包括複數個多層基板(例如,基板20)之基板條帶70。如圖7中所展示,對準標記可安置於對應於每一列及每一行基板之位置處。在其他實施例中,對準標記可經選擇性地安置(例如,在基板條帶70之四個拐角或邊緣處)。在一些實施例中,基板條帶70之每一基板亦可包括對準標記。因此,較易於判定基板之哪一行或哪一列包括移位、偏差或漂移。另外,若判定基板之一行或一列包括移位、偏差或漂移,則較易於判定基板之該行或該列中之哪一基板包括移位、偏差或漂移。
參考圖7B,電子組件71 (例如,晶粒或晶片)結合至該等基板中之每一者。
參考圖7C,封裝本體72形成於基板條帶70上以覆蓋或囊封電子組件71。在一些實施例中,封裝本體72可藉由例如轉移模製、壓縮模製或任何其他模製技術形成。
參考圖7D,可執行單體化以分離出個別半導體封裝裝置。亦即,貫穿封裝本體72及包括複數個多層基板(例如,基板20)之基板條帶70執行單體化。舉例而言,可藉由使用劃片機、雷射或其他恰當之切割技術執行單體化。
圖8說明根據本發明之一些實施例的半導體裝置封裝8。半導體裝置封裝8包括基板80、電子組件81a、81b,封裝本體82及電接點83。在一些實施例中,半導體裝置封裝8可使用圖7A、圖7B、圖7C及圖7D中所展示之操作或任何其他適當製造製程形成。
在一些實施例中,基板80為多層基板。舉例而言,基板80可為或可包括圖1A、圖1B、圖2、圖3A、圖3B、圖4A、圖4B、圖5、圖6A及圖6B中之任一者中所說明之基板10或20。基板80具有表面801及與表面801相對之表面802。
電氣組件81a及81b安置在基板80之頂面801上。電氣組件81a可為主動組件,諸如積體電路(IC)晶片或晶粒。電氣組件81b可為被動電氣組件,諸如電容器、電阻器或電感器。每一電氣組件81a及81b可電連接至另一電氣組件81a及81b中之一或多者及/或電連接至基板80 (例如,電連接至RDL),且電氣連接可藉助於覆晶或導線接合技術獲得。
封裝本體82安置在基板80之表面801上並囊封基板80之表面801及電氣組件81a及81b的一部分。在一些實施例中,封裝本體82包括具有分散其中之填充劑之環氧樹脂。
電接點83 (例如,焊球)安置在基板80之表面802上且可在半導體裝置封裝8與外部組件(例如,外部電路或電路板)之間提供電氣連接。在一些實施例中,電接點83包括控制崩潰晶片連接(C4)凸塊、球狀柵格陣列(BGA)或平台柵格陣列(LGA)。
在一些實施例中,半導體裝置封裝8可藉由包括以下各者之製程形成:(i)提供基板80;(ii)將電子組件81a及81b安置在基板80之表面801上;(iii)在基板80之表面801上形成封裝本體82以覆蓋電子組件81a及81b;及(iv)在基板80之表面802上形成電子組件83。
如本文中所使用,術語「實質上」、「實質的」、「大約」及「約」用以表示及考慮小的變化。舉例而言,當結合數值使用時,術語可指小於或等於彼數值之±10%的變化範圍,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%之變化範圍。作為另一實例,膜或層之厚度「實質上均勻」可指膜或層之平均厚度的小於或等於±10%之標準偏差,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%的標準偏差。術語「實質上共面」可指沿著同一平面處於微米內之兩個表面,諸如沿著同一平面處於40 μm內、30 μm內、20 μm內、10 μm內或1 μm內。若兩個表面或組件之間的角度為(例如) 90°±10°(諸如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°),則兩個表面或組件可視為「實質上垂直」。當結合事件或情形使用時,術語「實質上」、「實質的」、「大約」及「約」可指事件或情形精確發生之情況以及事件或情形近似發生之情況。
除非上下文另外明確規定,否則如本文中所用,單數術語「一」及「該」可包括複數個指示物。在對一些實施例之描述中,設置「在」另一組件「上」或「上方」之組件可涵蓋前一組件直接在後一組件上(例如,與後一組件實體接觸)之狀況以及一或多個介入組件位於前一組件與後一組件之間的狀況。
如本文中所使用,術語「導電(conductive)」、「導電性(electrically conductive)」及「導電率」指代輸送電流之能力。導電材料通常指示展現對於電流流動之極小或零阻力之彼等材料。導電率之一個量度為西門子/公尺(S/m)。通常,導電材料係具有大於約104
S/m (諸如至少105
S/m或至少106
S/m)之導電率的一種材料。材料之導電率有時可隨溫度而變化。除非另外規定,否則材料之導電率係在室溫下量測。
另外,有時在本文中按範圍格式呈現量、比率及其他數值。可理解,此類範圍格式用於便利及簡潔起見,且應靈活地理解為不僅包括明確地指定為範圍限制之數值,而且亦包括涵蓋於該範圍內之所有個別數值或子範圍,如同明確地指定每一數值及子範圍一般。
儘管已參考本發明之具體實施例描述並說明本發明,但此等描述及說明並不限制本發明。熟習此項技術者可清楚地理解,可進行各種改變,且可在實施例內替代等效元件而不會脫離如由所附申請專利範圍所界定之本發明之真實精神及範疇。說明可能未必按比例繪製。由於在製造製程中之變數等等,在本發明中之工藝再現與實際設備之間可存在區別。可存在並未具體說明的本發明的其他實施例。說明書及圖式應被視為說明性,而非限制性。可作出修改,以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改意欲在此隨附之申請專利範圍之範疇內。雖然已參考按特定次序執行之特定操作來描述本文中所揭示之方法,但可理解,在不脫離本發明之教示的情況下,可組合、再細分或重新定序此等操作以形成等效方法。因此,除非在本文中具體指示,否則操作之次序及分組並非對本發明之限制。
8:半導體裝置封裝
10:基板
10a:核心結構
10b:介電層
10c:介電層
10d:保護層
10e:保護層
10m1:對準標記
10m2:對準標記
10m3:對準標記
10m4:對準標記
20:基板
20m1:對準標記
20m1':對準標記
20m1'':對準標記
20m1''':對準標記
20m2:對準標記
22:電路區
60m1:對準標記
60m1':對準標記
60m1'':對準標記
60m2:對準標記
70:基板條帶
71:電子組件
72:封裝本體
80:基板
81a:電子組件
81b:電子組件
82:封裝本體
83:電接點/電子組件
201:邊緣
202:邊緣
801:表面
802:表面
D21:長度差
圖1A說明根據某些比較技術之基板之透視圖。
圖1B說明根據某些比較技術之基板之透視圖。
圖1C為根據某些比較技術之展示基板之橫截面視圖的影像。
圖2說明根據本發明之一些實施例的基板之一個層之俯視圖。
圖3A說明根據本發明之一些實施例的基板之透視圖。
圖3B說明根據本發明之一些實施例的基板之透視圖。
圖4A說明根據本發明之一些實施例的基板之透視圖。
圖4B說明根據本發明之一些實施例的基板之透視圖。
圖5說明根據本發明之一些實施例的基板之透視圖。
圖6A說明根據本發明之一些實施例的基板之一個層之俯視圖。
圖6B說明根據本發明之一些實施例的基板之透視圖。
圖7A、圖7B、圖7C及圖7D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。
圖8說明根據本發明之一些實施例的半導體裝置封裝之橫截面視圖。
貫穿該等圖式及實施方式使用共同參考數字以指示相同或類似組件。結合隨附圖式,自以下實施方式,將容易理解本發明。
20:基板
20m1:對準標記
20m2:對準標記
22:電路區
201:邊緣
202:邊緣
D21:長度差
Claims (21)
- 一種封裝基板,其包含: 一第一介電層; 一第一圖案化導電層,其安置在該第一介電層上;及 一第一組對準標記,其安置在該第一介電層上且鄰近該第一介電層之一第一邊緣,該第一組對準標記包括複數個對準標記, 其中該第一組對準標記中之該等對準標記與該第一邊緣之間的距離彼此不同。
- 如請求項1之封裝基板,其進一步包含: 一第二介電層,其安置在該第一介電層上且覆蓋該第一圖案化導電層; 一第二圖案化導電層,其安置在該第二介電層上;及 一第二組對準標記,其安置在該第二介電層上且鄰近該第二介電層之一邊緣,該第二組對準標記包括複數個對準標記, 其中該第二組對準標記中之該等對準標記與該第二介電層之該邊緣之間的距離彼此不同。
- 如請求項2之封裝基板,其中該第一組對準標記與該第二組對準標記實質上對準。
- 如請求項2之封裝基板,其中自該第一介電層曝露之該第一組對準標記中之該等對準標記之一數目與自該第二介電層曝露之該第二組對準標記中之該等對準標記之一數目相同。
- 如請求項1之封裝基板,其中該第一介電層具有一中心部分及鄰近該第一介電層之該第一邊緣之一第二邊緣,且該第一組對準標記中之該等對準標記之長度在自該第一介電層之該第二邊緣朝向該第一介電層之該中心部分之一方向上逐漸增加。
- 一種用於製造一半導體裝置封裝之方法,其包含: (a)提供一基板,該基板具有一第一介電層、安置在該第一介電層上之一第一圖案化導電層及安置在該第一介電層上且鄰近該第一介電層之一第一邊緣的一第一組對準標記,該第一組對準標記包括複數個對準標記,其中該第一組對準標記中之該等對準標記之長度彼此不同; (b)將一電子組件安置在該基板上;及 (c)在該基板上形成一封裝本體以覆蓋該電子組件。
- 如請求項6之方法,其中該第一組對準標記中之至少一個對準標記自該第一介電層之一側向表面曝露。
- 如請求項7之封裝基板,其中該基板進一步包含: 一第二介電層,其安置在該第一介電層上且覆蓋該第一圖案化導電層; 一第二圖案化導電層,其安置在該第二介電層上;及 一第二組對準標記,其安置在該第二介電層上且鄰近該第二介電層之一第一邊緣,該第二組對準標記包括複數個對準標記, 其中該第二組對準標記中之該等對準標記之長度彼此不同。
- 如請求項8之方法,其中該第一組對準標記與該第二組對準標記實質上對準。
- 如請求項9之方法,其中自該第一介電層曝露之該第一組對準標記中之該等對準標記之一數目與自該第二介電層曝露之該第二組對準標記中之該等對準標記之一數目相同。
- 如請求項6之方法,其中該第一介電層具有一中心部分及鄰近該第一介電層之該第一邊緣之一第二邊緣,且該第一組對準標記中之該等對準標記之該等長度在自該第一介電層之該第二邊緣朝向該第一介電層之該中心部分之一方向上逐漸增加。
- 如請求項6之方法,其中該第一組對準標記中之兩個鄰近對準標記之該等長度之一差實質上等於該第一組對準標記中之任何其他兩個鄰近對準標記之該等長度之一差。
- 如請求項6之方法,操作(a)進一步包含: 提供包括該基板之一基板條帶, 其中該基板包括一側軌及一晶片結合區域,且 該第一組對準標記安置在該基板之該側軌上。
- 一種用於製造一半導體裝置封裝之方法,其包含: (a)提供一基板,該基板具有一第一介電層、安置在該第一介電層上之一第一圖案化導電層及安置在該第一介電層上且鄰近該第一介電層之一第一邊緣的一第一組對準標記,該第一組對準標記包括複數個對準標記,其中該第一組對準標記中之該等對準標記與該第一邊緣之間的距離彼此不同; (b)將一電子組件安置在該基板上;及 (c)在該基板上形成一封裝本體以覆蓋該電子組件。
- 如請求項14之方法,其中該第一組對準標記中之至少一個對準標記自該第一介電層之一側向表面曝露。
- 如請求項15之封裝基板,其中該基板進一步包含: 一第二介電層,其安置在該第一介電層上且覆蓋該第一圖案化導電層; 一第二圖案化導電層,其安置在該第二介電層上;及 一第二組對準標記,其安置在該第二介電層上且鄰近該第二介電層之一第一邊緣,該第二組對準標記包括複數個對準標記, 其中該第二組對準標記中之該等對準標記之長度彼此不同。
- 如請求項16之方法,其中該第一組對準標記與該第二組對準標記實質上對準。
- 如請求項17之方法,其中自該第一介電層曝露之該第一組對準標記中之該等對準標記之一數目與自該第二介電層曝露之該第二組對準標記中之該等對準標記之一數目相同。
- 如請求項14之方法,其中該第一介電層具有一中心部分及鄰近該第一介電層之該第一邊緣之一第二邊緣,且該第一組對準標記中之該等對準標記之該等長度在自該第一介電層之該第二邊緣朝向該第一介電層之該中心部分之一方向上逐漸增加。
- 如請求項14之方法,其中該第一組對準標記中之兩個鄰近對準標記之該等長度之一差實質上等於該第一組對準標記中之任何其他兩個鄰近對準標記之該等長度之一差。
- 如請求項14之方法,操作(a)進一步包含: 提供包括該基板之一基板條帶,其中 該基板包括一側軌及一晶片結合區域,且 該第一組對準標記安置在該基板之該側軌上。
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US5266380A (en) * | 1992-09-08 | 1993-11-30 | Motorola, Inc. | Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board |
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