TW202008428A - 半導體元件 - Google Patents

半導體元件 Download PDF

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TW202008428A
TW202008428A TW108116975A TW108116975A TW202008428A TW 202008428 A TW202008428 A TW 202008428A TW 108116975 A TW108116975 A TW 108116975A TW 108116975 A TW108116975 A TW 108116975A TW 202008428 A TW202008428 A TW 202008428A
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layer
alloy
metal
fin
layers
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TW108116975A
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王菘豊
姆魯尼爾Ａ 卡迪爾巴德
奧野泰利
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台灣積體電路製造股份有限公司
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Publication of TW202008428A publication Critical patent/TW202008428A/zh

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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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Abstract

一種半導體元件包含第一半導體鰭片、第一磊晶層、第一合金層以及接觸栓塞。第一半導體鰭片位於基材上。第一磊晶層位於第一半導體鰭片上。第一合金層位於第一磊晶層上方。第一合金層的材質包含一或多個IV族元素以及一或多個金屬元素，且第一合金層包含第一側壁及第二側壁，第二側壁自第一側壁之底部沿著不平行於第一側壁之方向向下延伸。接觸栓塞接觸於第一合金層之第一側壁以及第二側壁。

Description

半導體元件
本揭露係關於一種半導體元件，特別係關於一種半導體元件的形成方法。
隨著半導體工業已發展到奈米技術製程節點以追求更高之元件密度、更高效能及更低成本，來自製造及設計問題兩者之挑戰已導致了三維設計之發展，諸如，鰭式場效應電晶體(fin-type field effect transistor,FinFET)以及具有高介電常數(high dielectric constant,high-k)材料之金屬閘極結構的使用。通常藉由使用閘極替換技術來製造金屬閘極結構，且藉由使用磊晶生長方法形成源極及汲極。源極/汲極接觸栓塞亦形成於源極/汲極區域上。
於一些實施方式中，一種半導體元件包含第一半導體鰭片、第一磊晶層、第一合金層以及接觸栓塞。第一半導體鰭片位於基材上。第一磊晶層位於第一半導體鰭片上。第一合金層位於第一磊晶層上方。第一合金層的材質包含一或多個IV族元素以及一或多個金屬元素，且第一合金 層包含第一側壁及第二側壁，第二側壁自第一側壁之底部沿著不平行於第一側壁之方向向下延伸。接觸栓塞接觸於第一合金層之第一側壁以及第二側壁。
10‧‧‧遮罩層
11‧‧‧襯墊氧化物層
12‧‧‧氮化矽遮罩層
15‧‧‧第一保護層
17‧‧‧第二保護層
20‧‧‧虛設閘極介電層
22‧‧‧虛設閘電極層
24‧‧‧側壁間隔件
50‧‧‧基材
52、54‧‧‧鰭狀結構
58‧‧‧隔離絕緣層
60‧‧‧用於n型FET之源極/汲極磊晶層
62‧‧‧用於p型FET之源極/汲極磊晶層
65‧‧‧介電質覆蓋層
67‧‧‧第一層間介電質(層間介電質)層
72‧‧‧閘極介電層
73‧‧‧功函數調整層
74‧‧‧金屬閘電極層
78‧‧‧絕緣材料
80、81‧‧‧金屬合金層
110‧‧‧間隔件殘留物
132‧‧‧第一n型磊晶層
134‧‧‧第二n型磊晶層
136‧‧‧第一p型磊晶層
138‧‧‧第二p型磊晶層
150‧‧‧接觸蝕刻終止層
160‧‧‧第二層間介電質層
200、200a、200b、201、201a、201b、203‧‧‧接觸栓塞
215、216‧‧‧氮化合金覆蓋結構
220、222‧‧‧合金層
224、226、263‧‧‧孔隙
225‧‧‧過渡金屬層
241、242、243、244、245‧‧‧介面層
251、252、253、254、255‧‧‧貴金屬結構
261、262‧‧‧接縫
271、272‧‧‧種晶層
281、282‧‧‧金屬結構
2001、2011、2012‧‧‧錐形部分
2002‧‧‧延伸部分
O1、O2‧‧‧接觸開口
O11、O21‧‧‧錐形開口
O12、O22‧‧‧縫隙
S11~S18‧‧‧步驟
SW1、SW3、SW5、SW6‧‧‧上傾側壁
SW2、SW4‧‧‧垂直側壁
當結合附圖閱讀時得以自以下詳細描述最佳地理解本揭露之態樣。應注意，根據工業上之標準實務，各種特徵未按比例繪製。實際上，為了論述清楚可任意地增大或減小各種特徵之尺寸。
第1圖為說明根據一些實施方式之形成源極/汲極接觸件之方法的流程圖。
第2圖至第16圖展示根據本揭露之一些實施方式的用於製造鰭式場效應電晶體(fin-type field effect transistor,FinFET)之各種階段的例示性橫截面圖。
第17A圖、第18A圖、第19A圖及第20A圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段對應於第16圖中所說明之線段A-A的例示性橫截面圖。
第17B圖、第18B圖、第19B圖及第20B圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段對應於第16圖中所說明之線段B-B的例示性橫截面圖。
第21A圖、第22A圖及第23A圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段對應於第16圖中所說明之線段A-A的例示性橫截面圖。
第21B圖、第22B圖及第23B圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段對應於第16圖中所說明之線段B-B的例示性橫截面圖。
第24A圖為根據本揭露之一些實施方式的對應於半導體元件的第16圖中之線段A-A的例示性橫截面圖。
第24B圖為根據本揭露之一些實施方式的對應於半導體元件的第16圖中之線段B-B的例示性橫截面圖。
第25圖及第26圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段對應於第16圖中所說明之線段A-A的例示性橫截面圖。
第27圖說明根據本揭露之一些實施方式的使用化學氣相沉積(chemical vapor deposition,CVD)製程在各種材料上沉積釕之實驗結果。
第28圖說明根據本揭露之一些實施方式的使用化學氣相沉積製程在各種材料上沉積釕之實驗結果。
以下揭示內容提供用於實施所提供標的物之不同特徵的許多不同實施方式或實例。以下描述部件及佈置之特定實例以簡化本揭露。當然，此等僅為實例且並不意欲為限定性的。舉例而言，在如下描述中第一特徵在第二特徵之上或在第二特徵上形成可包含其中第一及第二特徵直接接觸形成之實施方式，且亦可包含其中額外特徵可在第一及第二特徵之間形成而使得第一及第二特徵可不直接接觸的實 施方式。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複是出於簡化及清楚目的，且其本身並不指示所論述之一些實施方式及/或配置之間的關係。
另外，為了描述簡單起見，可在本文中使用諸如「在......之下」、「在......下方」、「下方」、「在......上方」、「上方」以及其類似術語的空間相對術語，以描述如諸圖中所說明之一個部件或特徵相對於另一(其他)部件或特徵的關係。所述空間相對術語意欲涵蓋除了諸圖中所描繪之定向以外元件在使用或操作中之不同定向。裝置可以其他方式定向(旋轉90度或在其他定向上)，且可同樣相應地解釋本文中所使用之空間相對描述詞。
可藉由任何合適方法來圖案化鰭式場效應電晶體(fin-type field effect transistor,FinFET)之鰭片結構。舉例而言，可使用一或多個光微影製程(包含雙圖案化或多圖案化製程)來圖案化鰭。大體而言，雙圖案化或多圖案化製程組合了光微影及自對準製程，從而允許產生具有(例如)小於可使用單一、直接光微影製程另外獲得之間距的間距之圖案。舉例而言，在一個實施方式中，犧牲層形成於基材之上且使用光微影製程圖案化。使用自對準製程並靠著經圖案化之犧牲層形成間隔件。接著移除犧牲層，且剩餘間隔物可接著用以圖案化鰭。
第1圖說明根據一些實施方式之形成半導體元件之方法。所述方法可實施在平面元件或多閘極元件上，諸如，鰭式場效應電晶體、全閘極(gate-all-around GAA) 元件、歐米伽閘極(Ω閘極)元件或Pi閘極(Π閘極)元件，以及應變半導體元件、絕緣體覆矽(silicon-on-insulator,SOI)元件、部分耗盡之絕緣體覆矽元件、完全耗盡之絕緣體覆矽元件或其他元件。第2圖至第16圖展示根據本揭露之一些實施方式的用於製造鰭式場效應電晶體之各種階段的例示性橫截面圖。在隨後論述中，參考第1圖中之製程步驟來論述第2圖至第16圖中所展示之製程步驟。應理解，可在第2圖至第16圖所展示之製程之前、在其期間以及在其之後提供額外操作，且以下所述之操作中的一些可被替代或消除而獲得方法之額外實施方式。操作/製程之次序可互換。
在鰭式場效應電晶體之製造方法中，形成鰭狀結構。遮罩層10形成於基材50上，如第2圖中所展示。藉由(例如)熱氧化製程及/或化學氣相沉積(chemical vapor deposition,CVD)製程來形成遮罩層10。基材50為(例如)具有在自約1×1015cm-3至約1×1016cm-3之範圍中之雜質濃度的p型矽基材。在其他實施方式中，基材為具有在自約1×1015cm-3至約1×1016cm-3之範圍中之雜質濃度的n型矽或鍺基材。
或者，基材50可包含另一元素半導體，諸如，鍺；化合物半導體，包含諸如SiC及SiGe之IV-IV族化合物半導體，諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP之III-V族化合物半導體；或其組合。基材50可包含已適當地摻雜有雜質(例如，p型或n型電導率)之各種區域。
在一些實施方式中，遮罩層10包含(例如)襯墊氧化物(例如，氧化矽)層11及氮化矽遮罩層12，如第2圖中所展示。可藉由使用熱氧化或化學氣相沉積製程來形成襯墊氧化物層11。可藉由以下來形成氮化矽遮罩層12：諸如濺鍍方法之物理氣相沉積(physical vapor deposition,PVD)；化學氣相沉積；電漿增強化學氣相沉積(Plasma enhanced chemical vapor deposition,PECVD)；大氣壓化學氣相沉積(atmospheric pressure chemical vapor deposition,APCVD)；低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)；高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDPCVD)；原子層沉積(atomic layer deposition,ALD)；及/或其他製程。襯墊氧化物層11之厚度在約2nm至約15nm之範圍中，且在一些實施方式中氮化矽遮罩層12之厚度在約2nm至約50nm之範圍中。
遮罩圖案進一步形成於遮罩層上。舉例而言，遮罩圖案為藉由微影操作形成之抗蝕劑圖案。藉由使用遮罩圖案作為蝕刻遮罩，形成襯墊氧化物層11及氮化矽遮罩層12之硬遮罩圖案，如第3圖中所展示。
接著，如第4圖中所展示，藉由使用硬遮罩圖案作為蝕刻遮罩，藉由使用乾式蝕刻方法及/或濕式蝕刻方法之溝槽蝕刻將基材50圖案化為用於n型場效應電晶體之鰭狀結構52以及用於p型場效應電晶體的鰭狀結構54。用於n 型場效應電晶體之鰭狀結構52的尺寸可與用於p型場效應電晶體之鰭狀結構54的尺寸相同或不同。
在第4圖中，兩個鰭狀結構52及兩個鰭狀結構54被安置在基材50上。然而，鰭狀結構之數目並不限於兩個。數目可小至一個或多於三個。另外，一或多個虛設鰭狀結構可鄰近鰭狀結構52及/或鰭狀結構54之兩側安置，以改良圖案化製程中之圖案保真度。
鰭狀結構52、54可由與基材50相同之材料製成，且可自基材50連續延伸或突出。在此實施方式中，鰭狀結構由Si製成。鰭狀結構52、54之矽層可為本征的，或適當地摻雜有n型雜質或p型雜質。
在一些實施方式中鰭狀結構52、54之寬度W1在自約5nm至約40nm之範圍中，且在其他實施方式中在自約7nm至約12nm之範圍中。在一些實施方式中，兩個鰭狀結構之間的空間S1在自約10nm至約40nm之範圍中。在一些實施方式中鰭狀結構52、54之高度H1(沿Z方向)在自約100nm至約300nm之範圍中，且在其他實施方式中在自約50nm至100nm之範圍中。
鰭狀結構52、54之下部部分可稱作井區，且被閘電極覆蓋的鰭狀結構52、54之上部部分可稱作通道或通道區域，且未被閘電極覆蓋的鰭狀結構52、54之上部部分可稱作源極及汲極，或源極區域及汲極區域。在本揭露中，「源極」及「汲極」可共同地稱作「源極/汲極」。在一些實施方式中井區域之高度在自約60nm至100nm之範圍 中，且通道區域之高度在自約40nm至120nm之範圍中，且在其他實施方式中在自約38nm至約60nm之範圍中。
在形成鰭狀結構52、54之後，形成第一保護層15以覆蓋結構52、54，如第5圖中所展示。於一些實施方式中，覆蓋結構也可稱之為覆蓋層。第一保護層15由(例如)氧化矽、氮化矽(SiN)或氮氧化矽(SiON)製成。在實施方式中，第一保護層15由SiN製成。可藉由化學氣相沉積形成第一保護層15。在一些實施方式中，第一保護層15之厚度在自約1nm至約20nm之範圍中。
在形成第一保護層15之後，如第6圖中所展示，形成第二保護層17。第二保護層17由(例如)氧化矽、氮化矽(SiN)或氮氧化矽(SiON)製成，且不同於第一保護層15。在一些實施方式中，第二保護層17由氧化矽製成。可藉由化學氣相沉積形成第二保護層17。在一些實施方式中，第二保護層17之厚度在自約1nm至約20nm之範圍中。
另外，隔離絕緣層58形成於鰭狀結構之間的空間中及/或一個鰭狀結構與形成於基材50上之另一部件之間的空間中，如第7圖中所展示。隔離絕緣層58亦可稱為「淺溝槽隔離(shallow trench isolation,STI)」層。用於隔離絕緣層58之絕緣材料可包含氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、摻氟矽酸鹽玻璃(fluorine-doped silicate glass,FSG)或低k介電材料之一或多個層。藉由低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿化學氣相沉積或可流動化學氣 相沉積形成隔離絕緣層。在可流動化學氣相沉積中，可沉積可流動介電材料而不是氧化矽。顧名思義，可流動介電材料可在沉積期間「流動」以填充具有高的深寬比之縫隙或空間。視情況將各種化學物質添加至含矽前驅物以允許已沉積之膜流動。在一些實施方式中，添加氮氫鍵。可流動之介電前驅物(尤其是可流動之氧化矽前驅物)的實例包含矽酸鹽、矽氧烷、甲基倍半矽氧烷(methyl silsesquioxane,MSQ)、氫倍半矽氧烷(hydrogen silsesquioxane,HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane,TCPS)、全氫-聚矽氮烷(perhydro-polysilazane,PSZ)、正矽酸四乙酯(tetraethyl orthosilicate,TEOS)，或甲矽烷基胺(silyl-amine)，諸如，三甲矽烷基胺(trisilylamine,TSA)。在多操作製程中形成此等可流動氧化矽材料。在沉積了可流動膜之後，使其固化並接著退火以移除不需要之(若干)元素從而形成氧化矽。當移除不需要之(若干)元素時，可流動膜緻密化並收縮。在一些實施方式中，進行多個退火製程。不止一次地使可流動膜固化並退火。可流動膜可摻雜有硼及/或磷。
如第7圖中所展示，首先在厚層中形成絕緣層58，使得鰭狀結構52及54嵌入厚層中，且厚層凹陷以便暴露鰭狀結構52及54之上部部分，如第8圖中所展示。將所述各別步驟展示為第1圖之製程流程中之步驟S11。可藉由使用乾式及/或濕式蝕刻使絕緣層58凹陷。在一些實施方式 中，亦自結構52、54之已暴露部分移除遮罩層11及12以及第一保護層15及第二保護層17。
在一些實施方式中，來自隔離絕緣層58之上表面的鰭狀結構之高度H2在自約20nm至約100nm之範圍中，且在其他實施方式中在自約30nm至約50nm之範圍中。在使隔離絕緣層58凹陷之後或之前，可執行例如退火製程之熱處理以改良隔離絕緣層58之品質。在某些實施方式中，藉由在惰性氣體環境(諸如，N2、Ar或He環境)中在自約900℃至約1050℃之範圍中的溫度下使用快速熱退火(RTA)歷時約1.5秒至約10秒來執行熱處理。
在一些實施方式中，採用閘極替換技術。在形成(並凹陷)絕緣層58之後，如第9圖中所展示，在鰭狀結構52、54上形成一或多個虛設閘極結構，其各自包含虛設閘極介電層20及虛設閘電極層22。將所述各別步驟展示為第1圖之製程流程中之步驟S12。如第9圖中所展示，閘極結構在X方向上延伸，而鰭狀結構在Y方向上延伸。
為了製造虛設閘極結構，在隔離絕緣層58及已暴露之鰭狀結構52、54上形成介電層及多晶矽層，且接著執行圖案化操作以便獲得包含由多晶矽製成之虛設閘電極層22以及虛設閘極介電層20的虛設閘極結構。在一些實施方式中，藉由使用硬遮罩來圖案化多晶矽層，且硬遮罩保留在虛設閘電極層22上作為覆蓋絕緣層。硬遮罩(覆蓋絕緣層)包含絕緣材料之一或多個層。在一些實施方式中，覆蓋絕緣層包含形成在氧化矽層之上的氮化矽層。在其他實施方 式中，覆蓋絕緣層包含形成在氮化矽層之上的氧化矽層。可藉由化學氣相沉積、PVD、ALD、電子束蒸發或其他合適製程形成用於覆蓋絕緣層之絕緣材料。在一些實施方式中，虛設閘極介電層20可包含氧化矽、氮化矽、氮氧化矽或高介電常數介電質之一或多個層。在一些實施方式中，虛設閘極介電層20之厚度在自約2nm至約20nm之範圍中，且在其他實施方式中在自約2nm至約10nm之範圍中。在一些實施方式中虛設閘極結構之高度在自約50nm至約400nm之範圍中，且在其他實施方式中在自約100nm至200nm之範圍中。
若採用先閘極技術，則將虛設閘電極層22及虛設閘極介電層20用作閘電極及閘極介電層。
其後，側壁間隔件24形成在虛設閘電極層22之相對側壁上，如第10圖中所展示。接著，如第11圖中所展示，例如藉由使用各向異性乾式蝕刻來移除形成於鰭狀結構52、54上之側壁間隔件24，以便暴露結構52、54之源極/汲極區域。將所述各別步驟展示為第1圖之製程流程中之步驟S13。側壁間隔件24包含絕緣材料之一或多個層，諸如，SiO2、SiN、SiON、SiOCN或SiCN，其是藉由化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、電子束蒸發製程或其他合適製程形成。可將低k介電材料用作側壁間隔件。藉由形成絕緣材料之毯覆層並執行各向異性蝕刻來形成側壁間隔件24。在實施方式中，側壁間隔件層由氮化矽基材料製成，諸如，SiN、SiON、SiOCN或SiCN。在一些 實施方式中，側壁間隔件24之厚度在自約2nm至約10nm之範圍中。
在暴露鰭狀結構52、54之源極/汲極區域之後，形成源極/汲極磊晶層，如第12圖中所展示。將所述各別步驟展示為第1圖之製程流程中之步驟S14。在一些實施方式中，用於n型場效應電晶體之源極/汲極磊晶層60包含半導體材料之一或多個層，諸如，SiC、SiP及SiCP，其為n型場效應電晶體之通道提供適當應力。當將SiP或SiCP用作多個磊晶層時，層具有不同的P及/或C濃度。因為鰭狀結構52為結晶Si，所以磊晶層60亦為結晶的。在一些實施方式中，用於p型場效應電晶體之源極/汲極磊晶層62包含一或多個半導體材料，諸如，Ge及SixGe1-x，其中0<x<1，其為p型場效應電晶體之通道提供適當應力。當將SiGe用作多個磊晶層時，多層具有不同的Ge濃度。因為鰭狀結構52、54為結晶Si，所以磊晶層60、62亦為結晶的。在某些實施方式中，將向通道提供適當應力之III-V族材料用作源極/汲極磊晶層60及/或62。在一些實施方式中，源極/汲極磊晶層60及/或62包含磊晶形成之半導體材料的多個層。
藉由使用以下氣體可在約80至150托之壓力下在約400至800℃的溫度下生長源極/汲極磊晶層60、62：諸如SiH4、Si2H6或SiCl2H2之含Si氣體；諸如GeH4、Ge2H6或GeCl2H2之含Ge氣體；諸如CH4或C2H6之含C氣體；及/或例如PH3之摻雜氣體。可藉由單獨的磊晶製程形成用於n 型場效應電晶體之源極/汲極結構以及用於p型場效應電晶體之源極/汲極結構。
在本揭露中，在形成源極/汲極磊晶層60、62之後，形成於一個鰭狀結構52上之源極/汲極磊晶層60不與形成於鄰近鰭狀結構52上之源極/汲極磊晶層60接觸(亦即，物理地分離)，如第12圖中所展示。類似地，形成於一個鰭狀結構54上之源極/汲極磊晶層62不與形成於鄰近鰭狀結構54上之源極/汲極磊晶層62接觸(亦即，物理地分離)。在一些實施方式中，源極/汲極磊晶層60(或62)之間的空間S2在自約5nm至15nm之範圍中。視兩個鰭狀結構之間的空間S1(參見第4圖)而定，調整源極/汲極磊晶層60及62之厚度以確保所需空間S2。
在形成源極/汲極磊晶層60及62之後，介電質覆蓋層65形成於源極/汲極磊晶層60及62上，且第一層間介電質(interlayer dielectric,ILD)層67形成於介電質覆蓋層65上，如第13圖中所展示。將所述各別步驟展示為第1圖之製程流程中之步驟S15。介電質覆蓋層65(例如)由SiN或SiON製成，且在一些實施方式中具有在自約2nm至約20nm之範圍中的厚度。第一層間介電質67由與介電質覆蓋層65不同之材料製成，且由(例如)氧化矽、SiCN、SiOCN或低k材料之一或多個層製成。
在形成層間介電質層67之後，形成一或多個金屬閘極結構。移除虛設閘極結構(虛設閘電極層22及虛設閘極介電層20)，且以金屬閘極結構來替換。在某些實施 方式中，在虛設閘極結構之上形成第一層間介電質層67，且執行諸如化學機械研磨(chemical mechanical polishing,CMP)製程或回蝕製程之平坦化操作以暴露虛設閘電極層22之上表面。接著，分別藉由適當蝕刻製程來移除虛設閘電極層22及虛設閘極介電層20，以形成閘極開口。在閘極開口中形成包含閘極介電層72、一或多個功函數調整層73及金屬閘電極層74之金屬閘極結構。將所述各別步驟展示為第1圖之製程流程中之步驟S16。
閘極介電層72可形成於安置在鰭狀結構52、54之通道層上的介面層(未繪示)上。在一些實施方式中，介面層可包含具有0.2nm至1.5nm之厚度的氧化矽或氧化鍺。在其他實施方式中，介面層之厚度在約0.5nm至約1.0nm之範圍中。
閘極介電層72包含介電材料之一或多個層，諸如，氧化矽、氮化矽或高介電常數介電材料、其他合適介電材料，及/或其組合。高介電常數介電材料之實例包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高介電常數介電材料，及/或其組合。藉由(例如)化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積或其他合適方法及/或其組合來形成閘極介電層72。在一些實施方式中閘極介電層之厚度在自約1nm至約10nm之範圍中，且在其他實施方式中可在自約2nm至約7nm之範圍中。
一或多個功函數調整層73形成在閘極介電層72上，如第14圖中所展示。功函數調整層73由導電材料製成，諸如，TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC之單個層，或此等材料中之兩者或兩者以上的多層。對於n通道鰭式場效應電晶體而言，將TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi中之一或多者用作功函數調整層，且對於p通道鰭式場效應電晶體而言，將TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調整層。
金屬閘電極層74形成在一或多個功函數調整層73上。金屬閘電極74包含任何合適金屬材料之一或多個層，諸如，鋁、銅、鈦、鉭、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適材料，及/或其組合。
在沉積了用於金屬閘極結構之適當材料之後，執行諸如化學機械研磨之平坦化操作。另外，在一些實施方式中，使金屬閘極結構凹陷以形成覆蓋空間，且以絕緣材料78填充覆蓋空間，如第14圖中所展示。
在形成金屬閘極結構之後，移除第一層間介電質層67及介電質覆蓋層65。在一些實施方式中完全移除第一層間介電質層67及介電質覆蓋層65，且在其他實施方式中，自圍繞源極/汲極結構之區域部分地移除第一層間介電質層67及介電質覆蓋層65。
在至少部分地移除了第一層間介電質層67之後，金屬合金層80及81分別形成於源極/汲極磊晶層60及62上，如第15圖中所展示。將所述各別步驟展示為第1圖之製程流程中之步驟S17。
金屬合金層80及81是由一或多個IV族元素及一或多個過渡金屬元素製成之合金。當由矽形成源極/汲極磊晶層60及62時，金屬合金層80及81為矽化物層。當由鍺形成源極/汲極磊晶層60及62時，金屬合金層80及81為鍺化物層。當由SiGe形成源極/汲極磊晶層60及62時，金屬合金層80及81為鍺化矽層。
過渡金屬包含Ti、Ta、Ru、Pt、Ni及Co中之一或多者。合金層80或81為TiSi、TaSi、RuSi、PtSi、NiSi、CoSi、TiSiGe、TaSiGe、NiSiGe及CoSiGe中之一或多者。
在移除了第一層間介電質層67之後，藉由(例如)化學氣相沉積製程、原子層沉積製程或物理氣相沉積製程將過渡金屬沉積在源極/汲極磊晶層60及62上。在沉積期間，已沉積之過渡金屬與源極/汲極磊晶層60及62中之Si及/或Ge反應，藉以在一些實施方式中形成合金層80及81。在一些實施方式中，可藉由電漿增強化學氣相沉積、化學氣相沉積、電漿增強原子層沉積(plasma-enhanced atomic layer deposition,PEALD)或原子層沉積金屬沉積在約250℃至700℃之溫度範圍內形成矽化物(合金)層，且接著應用使用Cl基或F基氣體之原位乾式蝕刻或異位濕式選 擇性蝕刻以移除間隔件及隔離絕緣層上之剩餘金屬。在其他實施方式中，可藉由電漿增強化學氣相沉積、化學氣相沉積、電漿增強原子層沉積或原子層沉積金屬沉積在約350℃至650℃之溫度範圍內形成矽化物(合金)層。在一些實施方式中，稍後執行氮化處理以鈍化矽化物表面用於隨後之矽化物形成退火。在其他實施方式中，經由藉由自組裝分子(self-assembly molecular,SAMs)之表面阻擋，或自適當金屬及矽前驅物進行固有的選擇性形成，執行選擇性矽化物沉積製程。可利用其他合適之矽化物形成製程。
在本揭露實施方式中，在形成合金層80之前，在鰭狀結構52中之一者上的源極/汲極磊晶層60與鄰近鰭狀結構52上之源極/汲極磊晶層60分離，且在鰭狀結構54中之一者上的源極/汲極磊晶層62與鄰近鰭狀結構54上之源極/汲極磊晶層62分離。形成合金層80及81，使得分離之源極/汲極磊晶層60上之所得合金層80被分離，且亦被分離分離之源極/汲極磊晶層62上之所得合金層81。
在一些實施方式中，在過渡金屬層形成於源極/汲極磊晶層60及62上之後，執行退火操作以形成合金層80及81。退火操作是在約250℃至約850℃之溫度下執行。
在形成合金層80及81之後，形成接觸蝕刻終止層(contact-etch stop layer,CESL)150以覆蓋合金層80、81，且第二層間介電質層160形成於接觸蝕刻終止層150上，如第16圖中所展示。接觸蝕刻終止層150由諸如SiN及SiON之氮化矽基材料製成，且在一些實施方式中具有在 自約2nm至約20nm之範圍中的厚度。第二層間介電質160由與接觸蝕刻終止層150不同之材料製成，且由(例如)氧化矽、SiCN、SiOCN或低k材料之一或多個層製成。
隨後，執行圖案化操作以在源極/汲極結構之合金層80及81上形成接觸開口，且以導電材料填充開口，藉以形成接觸栓塞(contact plug)200及201，如第16圖中所展示。將所述各別步驟展示為第1圖之製程流程中之步驟S18。使用選擇性自底向上之沉積技術形成接觸栓塞200及201，以填充相鄰合金層之間的縫隙，此將在下文中得到進一步描述。
第17A圖至第20B圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段的例示性橫截面圖。在第17A圖至第20B圖中，「A」圖(例如，第17A圖)說明沿著對應於第16圖中所說明之線段A-A之X方向的橫截面圖，且「B」圖(例如，第17B圖)說明沿著對應於第16圖中所說明之線段B-B之Y方向的橫截面圖。在第17A圖至20B中，將各自包含兩個鰭狀結構52、54之n通道鰭式場效應電晶體(NFET)及p通道鰭式場效應電晶體(PFET)說明為彼此鄰近。然而，配置並不限於此。鰭狀結構之數目可為三個或三個以上，且一或多個額外結構可安置在n通道鰭式場效應電晶體與p通道鰭式場效應電晶體之間。
在第17A圖及第17B圖中，在n通道FET中，第一n型磊晶層132形成於鰭狀結構52上，且第二n型磊晶層134形成於第一n型磊晶層132上。第一及第二n型磊晶層為 具有彼此不同且不同於鰭狀結構之晶格常數的結晶半導體層，諸如，Si、SiC、SiCP、SiP、Ge及SiGe。當使用SiC、SiP及/或SiCP時，第二n型磊晶層134之C或P濃度高於第一n型磊晶層132之C或P濃度。在一些實施方式中，將III-V族半導體層用於第一及第二n型磊晶層中之至少一者。第一n型磊晶層132及第二n型磊晶層134之組合對應於第16圖中所展示之源極/汲極磊晶層60。在其他實施方式中，僅形成第一n型磊晶層132及第二n型磊晶層134中之一者，且在某些實施方式中，形成三個或三個以上n型磊晶層。
另外，對應於第16圖中所展示之合金層80的合金層222(例如，矽化物層)分別形成於第二n型磊晶層134上。藉由第二n型磊晶層134之材料與形成於其上之過渡金屬層之間的反應形成合金層222。如第17A圖中所展示，鄰近兩個鰭狀結構52中之一者的第二n型磊晶層134不觸碰鄰近兩個鰭狀結構52中之另一者的第二n型磊晶層134。形成於各別第二n型磊晶層134上之合金層222未合並且因此分離。
在一些實施方式中，藉由在一些實施方式中藉由使用NH3或N2+H2電漿進行之氮化操作，合金層222之表面層可轉化成氮化合金覆蓋結構215。氮化合金覆蓋結構215覆蓋合金層222之表面以保護合金層222免於受由後續製程引起之損壞，諸如，來自隨後形成之接觸栓塞200之金屬擴散。相鄰鰭狀結構52上之氮化合金覆蓋結構215各自包含上傾側壁SW1及垂直側壁SW2，垂直側壁SW2自上傾斜 側壁SW1之底部沿不平行於上傾側壁SW1的方向向下延伸。此是歸因於氮化合金覆蓋結構215環繞沿不同晶面延伸(亦即，具有不同晶體定向)之磊晶層134之刻面的事實。
過渡金屬層225保留在由合金層222及隔離絕緣層58形成之孔隙224的底部。過渡金屬層225之體積足夠小，以便不影響n通道鰭式場效應電晶體之電性質。另外，間隔件殘留物110存在，其為側壁間隔件24之未在第11圖之操作中被蝕刻的剩餘部分。
第17A圖中所展示之p通道鰭式場效應電晶體具有與n通道鰭式場效應電晶體相同或類似之結構，且可省略對共用配置之解釋。第一p型磊晶層136形成於鰭狀結構54上，且第二p型磊晶層138形成於第一p型磊晶層136上。第一及第二p型磊晶層為具有彼此不同且不同於鰭狀結構之晶格常數的結晶半導體層，諸如，Si、SiC、SiCP、SiP、Ge及SiGe。當使用SiGe時，第二p型磊晶層138之Ge濃度高於第一p型磊晶層136之Ge濃度。在一些實施方式中，將III-V族半導體層用於第一及第二p型磊晶層中之至少一者。第一p型磊晶層136及第二p型磊晶層138之組合對應於第16圖中所展示之源極/汲極磊晶層62。在其他實施方式中，僅形成第一p型磊晶層136及第二p型磊晶層138中之一者，且在某些實施方式中，形成三個或三個以上p型磊晶層。
另外，對應於第16圖中所展示之合金層81的合金層220(例如，矽化物層)形成於各別第二p型磊晶層138上。藉由第二p型磊晶層138之材料與形成於其上之過渡金 屬層之間的反應形成合金層220。如第17A圖中所展示，鄰近兩個鰭狀結構54中之一者的第二p型磊晶層138不觸碰鄰近兩個鰭狀結構54中之另一者的第二p型磊晶層138。形成於各別第二p型磊晶層138上之合金層220未合並且因此分離。
在一些實施方式中，藉由如先前關於氮化合金覆蓋結構215之形成所論述的氮化操作，合金層222之表面層可轉化成氮化合金覆蓋結構216。氮化合金覆蓋結構216覆蓋合金層222之表面以保護合金層222免於受由後續製程引起之損壞，諸如，來自接觸栓塞201之金屬擴散。相鄰鰭狀結構54上之氮化合金覆蓋結構216各自包含上傾側壁SW3及垂直側壁SW4，垂直側壁SW4自上傾斜側壁SW3之底部沿不平行於上傾側壁SW3的方向向下延伸。此是歸因於氮化合金覆蓋結構216環繞沿不同晶面延伸之磊晶層138之刻面的事實。
過渡金屬層225保留在由合金層220及隔離絕緣層58形成之孔隙226的底部。過渡金屬層225之體積足夠小，以便不影響p通道鰭式場效應電晶體之電性質。另外，間隔件殘留物110存在，其為側壁間隔件24之未在第11圖之操作中被蝕刻的剩餘部分。
接觸蝕刻終止層150經形成作為毯覆層以覆蓋整個n通道鰭式場效應電晶體及p通道鰭式場效應電晶體，且第二層間介電質層160經形成以覆蓋整個接觸蝕刻終止層150。接著在第二層間介電質層160中蝕刻接觸開口O1及 O2且其穿過接觸蝕刻終止層150以分別暴露氮化合金覆蓋結構215及216。在第18A圖及第18B圖中說明所得結構。接觸開口O1包含錐形開口O11及自錐形開口O11之底部向下延伸的縫隙O12。縫隙O12由氮化合金覆蓋結構215之垂直側壁SW2限定，且錐形開口O11由氮化合金覆蓋結構215之上傾側壁SW1及第二層間介電質層160之上傾側壁SW5限定，第二層間介電質層160之上傾側壁SW5具有與氮化合金覆蓋結構215之上傾側壁SW1不同的坡度。類似地，接觸開口O2包含錐形開口O21及自錐形開口O21之底部向下延伸的縫隙O22。縫隙O22由氮化合金覆蓋結構216之垂直側壁SW4限定，且錐形開口O21由氮化合金覆蓋結構216之上傾側壁SW3及第二層間介電質層160之上傾側壁SW6限定，第二層間介電質層160之上傾側壁SW6具有與上傾側壁SW3不同的坡度。在一些實施方式中，縫隙O21或O22之寬度在自約3nm至約15nm之範圍中。控制縫隙O21或O22之寬度以使用毛細管冷凝機制促進隨後的自底向上之沉積，此將在下文得到進一步論述。若縫隙O21或O22之寬度大於約15nm或小於約3nm，則其可能不利地影響隨後的自底向上之沉積製程。
接觸栓塞200及201接著形成於各別接觸開口O1及O2中，如第19A圖及第19B圖中所說明。使用自底向上之方法來沉積接觸栓塞200及201，使得可大體上以接觸栓塞200及201填充窄縫隙O12及O22(如第18A圖中所展示)。在某些實施方式中，自底向上之沉積為涉及毛細管冷 凝機制之化學氣相沉積的沉積製程，且因此在後文中等效地稱作毛細管冷凝化學氣相沉積的製程。
毛細管冷凝化學氣相沉積製程選擇性地將金屬沉積在基材上之最窄的受限空間中，諸如，接觸開口O1及O2之縫隙O12及O22。毛細管冷凝化學氣相沉積製程之前驅物最初是在低於其飽和壓力之分壓(例如，自0.01mT至約0.1mT)下以氣相提供。若前驅物之分壓大於約0.1mT或小於約0.01mT，則毛細管冷凝機制可能不令人滿意。歸因於毛細管冷凝機制，即使前驅物蒸汽之分壓低於其飽和壓力，前驅物蒸汽亦在最窄縫隙(亦即，縫隙O12及O22)中冷凝為液體。此歸因於毛細管之受限空間(亦即，縫隙O12及O22)內之氣相分子之間的范德華相互作用的數目增加。此傾向用以選擇性地填充未合併之合金層與前驅物液體之間的窄縫隙O12及O22。在前驅物液體選擇性地被限制在最窄縫隙的情況下，前驅物液體被轉化成固相已沉積金屬。可以物理方式達成此轉化(例如，藉由固化)，或以化學方式藉由使前驅物液體與另一材料反應以產生固體材料或藉由分解前驅物達成。
使用毛細管冷凝化學氣相沉積之金屬沉積自最窄受限空間開始，此又導致「自底向上」填充現象而非「共形」沉積現象，因此以接觸栓塞200及201大體上填充縫隙O12及O22。以此方式，氮化合金覆蓋結構之垂直側壁之間的窄縫隙可由金屬填充，而不是由矽化物、鍺化物或金屬氮化物填充，此又將達成減小接觸電阻，因為金屬具有比矽化 物、鍺化物或金屬氮化物低之電阻。在一些實施方式中，執行毛細管冷凝化學氣相沉積製程直至接觸開口O1及O2被充滿金屬為止，如第19A圖及第19B圖中所說明。
在一些實施方式中，毛細管冷凝化學氣相沉積之前驅物可為(例如)金屬羰基、金屬鹵化物、其類似者或其組合，且載氣可包含(例如)氬氣、氫氣、其類似者或其組合。在一些實施方式中，在毛細管冷凝化學氣相沉積製程期間採用額外抑制氣體。抑制氣體可改良「自底向上」填充現象，因為其抑制了介電質上之金屬成核(例如，在層間介電質層160中之錐形開口O11及O21的側壁上)。在前驅物包含金屬羰基之一些實施方式中，抑制氣體包含(例如)一氧化碳(CO)。在前驅物包含金屬鹵化物之一些實施方式中，抑制氣體包含(例如)鹵化氫。
在一些實施方式中，相比於諸如銅的之非貴金屬，貴金屬(例如，釕)是接觸栓塞200及201之有希望的候選者。此至少歸因於貴金屬表現出比非貴金屬(例如，銅)低的金屬擴散。因此，若接觸栓塞200及201包含貴金屬(例如，釕)，則可省略在接觸栓塞200及201之形成之前沉積擴散阻障層。擴散阻障層之省略將有助於改良用於將接觸栓塞200及201沉積至窄縫隙O12及O22中的製程視窗。
在沉積的初始階段，貴金屬(例如，釕)可與已暴露區域中之矽及/或鍺(例如，在含矽及/或含鍺氮化合金覆蓋結構215及216中以及在含矽層間介電質層160中之接觸開口O1及O2之側壁中的矽及/或鍺)反應，藉以形成含 有貴金屬元素及IV族元素(例如，矽及/或鍺)的介面層241及242。在沉積之隨後階段，貴金屬不與矽及/或鍺反應，此又導致在各別介面層241及242上形成無矽及/或無鍺之貴金屬結構251及252。以此方式，介面層241改良了無矽及/或無鍺之貴金屬結構251與氮化合金覆蓋結構215及層間介電質層160之黏合。類似地，介面層242改良了無矽及/或無鍺之釕結構252與氮化合金覆蓋結構215及層間介電質層160之黏合。
在一些實施方式中，在毛細管冷凝化學氣相沉積製程之前執行預清潔製程。預清潔包含使用氫氣(H2)、氬氣、氦氣、氮氣(N2)、其類似者或其組合之離子轟擊。作為轟擊之結果，由接觸開口O1及O2暴露之介電材料(諸如，氧化矽和/或氮化矽)的鍵可能斷裂或鬆散，此將促進藉由使貴金屬與由介電材料中之斷裂鍵引起之矽反應而形成介面層241及242。
在貴金屬為釕之一些實施方式中，前驅物可為(例如)羰基釕、三羰基釕、鹵化釕、其類似者或其組合，且載氣可包含(例如)氬氣、氫氣、其類似者或其組合。
在前驅物為三羰基釕之一些實施方式中，接觸栓塞200及201之形成可為包含沉積循環及清潔循環之一或多次重複的循環製程。舉例而言，其可執行沉積循環繼之以清潔循環，且重複沉積及清潔循環。在一些實施方式中，沉積循環涉及如先前所論述之毛細管冷凝化學氣相沉積製程。在沉積循環中，三羰基釕前驅物最初是在低於其飽和壓 力之分壓(例如，自0.01mT至約0.1mT)下以氣相提供。若三羰基釕之分壓大於約0.1mT或小於約0.01mT，則毛細管冷凝機制可能不令人滿意。清潔循環涉及藉由使用包含氫氣(H2)、氬氣、氦氣、氮氣(N2)、其類似者或其組合之氣體執行的離子轟擊來處理接觸開口O1及O2。如先前所論述，離子轟擊有利於在接觸開口O1及O2之側壁上形成介面層241及242。在一些實施方式中，沉積循環及/或清潔循環是在自約160℃至約250℃之範圍中的溫度下執行。若沉積循環及/或清潔循環之溫度在自約160℃至約250℃的範圍之外，則自底向上之填充現象可能降級，因此導致所得導電插座200及201中之孔隙。
在前驅物為羰基釕之一些實施方式中，接觸栓塞200及201之形成可為涉及如上所述之毛細管冷凝機制的單步化學氣相沉積製程。化學氣相沉積製程是在自約130℃至約250℃之範圍中的溫度下執行。若熱化學氣相沉積製程之溫度在自約130℃至約250℃的範圍之外，則自底向上之填充現象可能降級，因此導致所得導電插座200及201中產生孔隙。羰基釕最初是在低於其飽和壓力之分壓(例如，自0.01mT至約0.1mT)下以氣相提供。若羰基釕之分壓大於約0.1mT或小於約0.01mT，則毛細管冷凝機制可能不令人滿意。
如上所述之含釕前驅物不僅適合於實施毛細管冷凝機制，而且若沉積製程在低於約250℃之溫度下執行，則金屬與氧化物之間亦具有固有的沉積選擇性，如下所述。
第27圖說明使用化學氣相沉積製程在各種材料上沉積釕之實驗結果，所述化學氣相沉積製程是在範圍為自約195℃至約205℃之溫度下執行，其中三羰基釕作為前驅物。第27圖為展示作為時間之函數之釕層厚度的圖表，其中使用X射線螢光(X-ray fluorescence,XRF)來量測釕層之厚度並表示為X射線螢光強度。在條件#1下，執行化學氣相沉積製程以將釕沉積在鉑上。在條件#2下，執行化學氣相沉積製程以將釕沉積在氧化矽上。當在範圍為自約195℃至約205℃之溫度下執行使用三羰基釕作為前驅物之化學氣相沉積製程時，沉積在鉑上之釕層的厚度大於沉積在氧化矽上之釕層的厚度(比較條件# 1與條件# 2)，此意謂若沉積溫度在自約195℃至約205℃之範圍中的溫度下，則三羰基釕在金屬與氧化物之間具有沉積選擇性。
第28圖說明使用化學氣相沉積製程在各種材料上沉積釕之實驗結果，所述化學氣相沉積製程是在範圍為自約250℃至約260℃之溫度下執行，其中三羰基釕作為前驅物。第28圖為展示作為時間之函數之釕層厚度的圖表，其中使用掃描電子顯微鏡(scanning electron microscope,SEM)來量測釕層之厚度。在條件#3下，執行化學氣相沉積製程以將釕沉積在氧化矽上。在條件#4下，執行化學氣相沉積製程以將釕沉積在釕上。在條件#5下，執行化學氣相沉積製程以將釕沉積在鉑上。當在範圍為自約250℃至約260℃之溫度下執行使用三羰基釕作為前驅物之化學氣相沉積製程時，沉積在氧化矽上之釕層的厚度與沉積 在鉑及釕上之釕層的厚度大體上相同或略微大於沉積在鉑及釕上之釕層的厚度(比較條件# 3與條件# 4及# 5)，此意謂若沉積溫度等於或大於約250℃，則三羰基釕在金屬與氧化物之間具有不令人滿意之選擇性。由於來自第27圖及第28圖之實驗結果，形成接觸栓塞200及201之沉積溫度可不高於約250℃，使得可選擇性地將接觸栓塞200及201沉積在各別合金覆蓋結構215及216上，此又將導致改良的自底向上之沉積。
參考第19A圖及第19B圖，在沉積了接觸栓塞200及201之後，執行可選之退火製程以減少貴金屬結果251及252之間的接縫261及262，且執行可選之CMP製程以移除接觸開口O1及O2外部的貴金屬結構251、252以及介面層241、242之過量材料。在第20A圖及第20B圖中展示所得結構。在一些實施方式中，退火製程是在約350℃至約500℃之溫度下執行歷時約2分鐘至45分鐘之持續時間。若溫度大於500℃及/或持續時間大於45分鐘，則可能導致對金屬閘極之功函數(例如，功函數調整層73及金屬閘電極層74之功函數)的不利影響。若溫度低於350℃及/或持續時間大於2分鐘，則在退火製程之後，接縫261及262可能保留在貴金屬結構251及252中。
如第20A圖中所說明，接觸栓塞200與氮化合金覆蓋結構215之上傾側壁SW1及垂直側壁SW2接觸。在一些實施方式中，接觸栓塞200包含朝向基材50逐漸變細之錐形部分2001以及自錐形部分2001之底部向下延伸之延伸 部分2002。錐形部分2001及延伸部分2002分別與氮化合金覆蓋結構215之上傾側壁SW1及垂直側壁SW2接觸。分別以錐形部分2001及延伸部分2002填充錐形開口O11及縫隙O12。因此，錐形部分2001及延伸部分2002分別具有與錐形開口O11及縫隙O12相同之輪廓。具體而言，錐形部分2001之寬度變化大於延伸部分2002之寬度變化。舉例而言，隨著與基材50之距離減小，錐形部分2001之寬度減小，且隨著與基材50之距離減小，延伸部分2002之寬度保持大體恆定。
類似地，接觸栓塞201與氮化合金覆蓋結構216之上傾側壁SW3及垂直側壁SW4接觸。在一些實施方式中，接觸栓塞201包含朝向基材50逐漸變細之錐形部分2012以及自錐形部分2011之底部向下延伸之延伸部分2011。錐形部分2011及延伸部分2012分別與氮化合金覆蓋結構216之上傾側壁SW3及垂直側壁SW4接觸。分別以錐形部分2011及延伸部分2012填充錐形開口O21及縫隙O22。因此，錐形部分2011及延伸部分2012分別具有與錐形開口O21及縫隙O22相同之輪廓。
第21A圖至第23B圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段的例示性橫截面圖。在第21A圖至第23B圖中，「A」圖(例如，第21A圖)說明沿著對應於第16圖中所說明之線段A-A之X方向的橫截面圖，且「B」圖(例如，第21B圖)說明沿著對應於第16圖中所說明之線段B-B之Y方向的橫截面圖。第21A圖至第 23B圖展示大體上與第17A圖至第20B圖相同之結構，不同之處在於接觸栓塞。如第21A圖及21B中所說明，貴金屬結構251及252分別沉積在接觸開口O1及O2之下部部分中，且接觸開口O1及O2之上部部分無貴金屬結構251及252且保持未填充。
其後，分別在接觸開口O1及O2之上部部分中以及在貴金屬結構251及252上形成種晶層271及272，繼之以在各別種晶層271及272上沉積諸如金屬結構281及282之導電結構，以形成接觸栓塞200a及201a，如第22A圖及第22B圖中所說明。在一些實施方式中，種晶層271及272為共形地沉積在基材50上之毯覆種晶層的不同部分，且金屬結構281及282為沉積在毯覆種晶層上之金屬層的不同部分。其後，可執行可選之退火製程以減少貴金屬結構251及252中之接縫261及262，並執行CMP以移除在接觸開口O1、O2外部之金屬結構281、282及種晶層271、272的過量材料。在第23A圖及第23B圖中展示所得結構。
如圖23中所說明，種晶層271及272共形地沉積在錐形開口O11及O21之上部部分中，且因此具有大體上U形之輪廓。以各別金屬結構281及282填充錐形開口O11及O21之剩餘上部部分。因此，金屬結構281及282具有對應於錐形開口O11及O21之錐形輪廓，並且可以等效地稱作接觸栓塞200a及201a之錐形部分。
選擇種晶層271、272及金屬結構281、282之材料以使得金屬結構281及282以比毛細管冷凝化學氣相沉 積之沉積速率快的沉積速率沉積，用於沉積貴金屬結構251及252。以此方式，可以縮短之持續時間形成接觸栓塞200a及201a。在一些實施方式中，種晶層271及272由TiN、TaN、其類似者或其組合製成，且金屬結構281及282由與貴金屬結構251及252不同的(例如)Co、W、Ti、Ta、Cu、Rh、Ir、Al及/或Ni製成。種晶層271及272之此等材料不僅導致沉積金屬結構281及282的改良之沉積速率，而且亦充當擴散阻障層以抑制金屬結構281及282之金屬向外擴散至第二層間介電質層160中。因此，在一些實施方式中，種晶層217及272可等效地稱作擴散阻障層。
如圖23中所展示，擴散阻障層271在接觸開口O1中延伸並在到達合金覆蓋結構215之前終止，且擴散阻障層272在接觸開口O2中延伸並在到達合金覆蓋結構216之前終止。換言之，貴金屬結構251之上的擴散阻障層271與合金覆蓋結構215分離，且貴金屬結構252之上的擴散阻障層層272與合金覆蓋結構216分離。因此，擴散阻障層271不延伸至由氮化合金覆蓋結構215之垂直側壁SW2限定的窄縫隙中，且擴散阻障層272不延伸至由氮化合金覆蓋結構216之垂直側壁SW4限定的窄縫隙中。
第24A圖及第24B圖為根據本揭露之一些實施方式之半導體元件的例示性橫截面圖。第24A圖說明沿著對應於第16圖中所說明之線段A-A之X方向的橫截面圖，且第24B圖說明沿著對應於第16圖中所說明之線段B-B之Y方向的橫截面圖。第24A圖至第24B圖展示大體上與第20A圖 至第20B圖相同之結構，不同之處在於存在落於單個合金覆蓋結構215上之接觸栓塞203。在一些實施方式中，接觸栓塞203包含介面層243及在介面層243上之貴金屬結構253，其分別大體上與介面層241及貴金屬結構251相同，如先前所述。此外，孔隙263形成於接觸栓塞203與第二層間介電質層160之間。此歸因於毛細管冷凝化學氣相沉積製程在第二層間介電質層160之氧化物上表現出比在合金覆蓋結構215之金屬上低的成核。
第25圖及第26圖為根據本揭露之一些實施方式的在形成接觸栓塞之各種階段的示意性橫截面圖。第25圖展示大體上與第15圖相同之結構，不同之處在於介面層244及245形成於各別合金覆蓋結構215及216上且貴金屬結構254及255形成於各別介面層244及245上。
如第25圖中所說明，介面層244分別環繞相鄰鰭狀結構52上之單獨合金覆蓋結構215，且貴金屬結構254環繞介面層244。介面層244及貴金屬結構254大體上與使用毛細管冷凝化學氣相沉積形成之介面層241及貴金屬結構251相同，如先前所述。類似地，介面層245分別環繞相鄰鰭狀結構54上之單獨合金覆蓋結構216，且貴金屬結構255環繞介面層245。介面層245及貴金屬結構255大體上與使用毛細管冷凝化學氣相沉積形成之介面層242及貴金屬結構252相同，如先前所述。
其後，在貴金屬結構254及255上形成第二層間介電質層160，如第26圖中所說明。在一些實施方式中，貴 金屬結構254及貴金屬結構254中之介面層244可組合充當用於相鄰半導體鰭52之接觸栓塞200b，且在其他實施方式中，在層間介電質層160中以及在貴金屬結構254上形成額外金屬結構以完成用於半導體鰭52之接觸栓塞200b的形成。類似地，在一些實施方式中，貴金屬結構255及貴金屬結構255中之介面層245可組合充當用於相鄰半導體鰭54之接觸栓塞201b，且在其他實施方式中，在層間介電質層160中以及在貴金屬結構255上形成額外金屬結構以完成接觸栓塞201b的形成。
基於以上論述，可見本揭露提供了優勢。然而，應理解，其他實施方式可提供額外優勢，且本文中不一定揭示所有優勢，且無特定優勢對所有實施方式而言為必需。一個優勢在於，藉由在相鄰半導體鰭上之合金層(例如，矽化物層)之間的窄縫隙中形成金屬來達成減小源極/汲極接觸電阻並因此改良了元件效能。另一優勢在於，可藉由使用毛細管冷凝化學氣相沉積製程實現自底向上之沉積以填充合金層之間的窄縫隙。另一優勢在於，藉由在毛細管冷凝化學氣相沉積期間使用抑制氣體來抑制介電材料上之金屬成核，可達成增強的自底向上之沉積並因此達成減小接縫體積。另一優勢在於，可藉由氮化之矽化物覆蓋結構來抑制接觸栓塞之金屬的向外擴散。另一優勢在於，藉由使用貴金屬形成接觸栓塞，可達成減少金屬擴散並因此達成擴散阻障層金屬之省去。
在一些實施方式中，一種半導體元件包含第一半導體鰭片、第一磊晶層、第一合金層以及接觸栓塞。第一半導體鰭片位於基材上。第一磊晶層位於第一半導體鰭片上。第一合金層位於第一磊晶層上方。第一合金層的材質包含一或多個IV族元素以及一或多個金屬元素，且第一合金層包含第一側壁及第二側壁，第二側壁自第一側壁之底部沿著不平行於第一側壁之方向向下延伸。接觸栓塞接觸於第一合金層之第一側壁以及第二側壁。
於一些實施方式中，接觸栓塞包含第一錐形部分及延伸部分。第一錐形部分朝向基材逐漸變細。延伸部分自第一錐形部分之底部向下延伸。第一錐形部分之寬度變化，係大於延伸部分之寬度變化。
於一些實施方式中，接觸栓塞之第一錐形部分接觸於第一合金覆蓋結構之第一側壁。
於一些實施方式中，延伸部分接觸於第一合金覆蓋結構之第二側壁。
於一些實施方式中，接觸栓塞進一步包含第二錐形部分。第二錐形部分位於第一錐形部分上方。第一錐形部分的材料與第二錐形部分的材料包含是由不同的金屬材料所製成的。
於一些實施方式中，接觸栓塞進一步包含擴散阻障層。擴散阻障層位於第一錐形部分與第二錐形部分之間。
於一些實施方式中，擴散阻障層分離於第一合金覆蓋結構。
於一些實施方式中，半導體元件進一步包含一層間介電質層。層間介電質層圍繞第一合金覆蓋結構。層間介電質層與接觸栓塞之間定義孔隙。
於一些實施方式中，接觸栓塞環繞第一合金覆蓋結構。
於一些實施方式中，半導體元件進一步包含第二半導體鰭片、第二磊晶層以及第二合金覆蓋結構。第二半導體鰭片位於基材上。第二磊晶層位於第二半導體鰭片上。第二合金覆蓋結構位於第二磊晶層上方。第二合金覆蓋結構的材質包含一或多個IV族元素以及一或多個金屬元素。第二合金覆蓋結構分離於第一合金覆蓋結構，且接觸於接觸栓塞
於一些實施方式中，第二合金覆蓋結構包含第三側壁以及第四側壁。第四側壁自第三側壁之底部沿著不平行於第三側壁之方向向下延伸。接觸栓塞接觸於第二合金覆蓋結構之第三側壁以及第四側壁。
於一些實施方式中，接觸栓塞環繞第一合金覆蓋結構以及第二合金覆蓋結構。
在一些實施方式中，一種半導體元件包含第一半導體鰭、第一磊晶層、第一合金覆蓋結構以及接觸栓塞。第一半導體鰭位於基材上。第一磊晶層位於第一半導體鰭上。第一合金覆蓋結構位於第一磊晶層上方。第一合金覆蓋 結構的材質包含一或多個IV族元素以及一或多個金屬元素製成。接觸栓塞包含介面層以及貴金屬結構。介面層接觸於第一合金覆蓋結構，且貴金屬結構接觸於介面層。介面層包含一或多個IV族元素，且包含貴金屬結構所包含之一貴金屬元素。
於一些實施方式中，半導體元件進一步包含層間介電質層。層間介電質層圍繞接觸栓塞。介面層進一步接觸於層間介電質層。
於一些實施方式中，接觸栓塞進一步包含導電結構。導電結構位於貴金屬結構上方。導電結構的材質不包含貴金屬結構所包含之貴金屬元素。
於一些實施方式中，接觸栓塞進一步包含擴散阻障層。擴散阻障層位於貴金屬結構與導電層之間。
於一些實施方式中，半導體元件進一步包含第二半導體鰭片、第二磊晶層、第二合金覆蓋結構以及接觸蝕刻終止層。第二半導體鰭片位於基材上。第二磊晶層位於第二半導體鰭片上。第二合金覆蓋結構位於第二磊晶層上方。第二合金覆蓋結構的材質包含一或多個IV族元素以及一或多個金屬元素。接觸栓塞包含介面層以及貴金屬結構。介面層接觸於第一合金覆蓋結構。貴金屬結構接觸於介面層。介面層包含一或多個IV族元素，且包含貴金屬結構所包含之貴金屬元素。
在一些實施方式中，一種用於形成半導體元件之方法包含：在半導體鰭上形成磊晶層；藉由此磊晶層與金 屬反應而在磊晶層上形成合金層；以及使用沉積製程在合金層上形成第一金屬結構。沉積製程包含以氣相提供前驅物，且包含保持前驅物之分壓低於前驅物之飽和壓力以使得前驅物在合金層上冷凝為液體。
於一些實施方式中，半導體元件之方法進一步包含：在提供前驅物之前氮化合金層之表面層。
於一些實施方式中，半導體元件之方法進一步包含：在形成第一金屬結構之前形成具有暴露合金層之接觸開口的一層間介電質層，其中形成第一金屬結構的步驟，係使得接觸開口之底部部分被沉積，而使得接觸開口之頂部部分未被填充；在接觸開口之頂部部分中形成種晶層；以及藉由比形成第一金屬結構之沉積速率快的沉積速率將第二金屬結構沉積在種晶層上。
前文概述了若干實施方式之特徵，使得熟習此項技術者可較佳理解本揭露之態樣。熟習此項技術者應瞭解，其可容易地使用本揭露作為設計或修改用於實現相同目的及/或達成本文中所介紹之實施方式之相同優勢的其他製程及結構的基礎。熟習此項技術者亦應認識到，此等等效構造不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇的情況下於本文中進行各種改變、代替及替換。
S11~S18‧‧‧步驟

Claims (1)

  1. 一種半導體元件，包含：一第一半導體鰭片，位於一基材上；一第一磊晶層，位於該第一半導體鰭片上；一第一合金覆蓋結構，位於該第一磊晶層上方，其中該第一合金覆蓋結構的材質包含一或多個IV族元素以及一或多個金屬元素，且該第一合金覆蓋結構包含一第一側壁以及一第二側壁，該第二側壁自該第一側壁之一底部沿著不平行於該第一側壁之一方向向下延伸；以及一接觸栓塞，接觸於該第一合金覆蓋結構之該第一側壁以及該第二側壁接觸栓塞。
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