TW201946120A - 主動閘極接觸及其製造方法 - Google Patents
主動閘極接觸及其製造方法 Download PDFInfo
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- TW201946120A TW201946120A TW108110301A TW108110301A TW201946120A TW 201946120 A TW201946120 A TW 201946120A TW 108110301 A TW108110301 A TW 108110301A TW 108110301 A TW108110301 A TW 108110301A TW 201946120 A TW201946120 A TW 201946120A
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- 238000004519 manufacturing process Methods 0.000 title description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 44
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 207
- 125000006850 spacer group Chemical group 0.000 claims description 81
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229910052721 tungsten Inorganic materials 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 229910052707 ruthenium Inorganic materials 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- 238000000581 reactive spray deposition Methods 0.000 claims description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- NCZAACDHEJVCBX-UHFFFAOYSA-N [Si]=O.[C] Chemical compound [Si]=O.[C] NCZAACDHEJVCBX-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 238000005253 cladding Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- -1 SiOC Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910004140 HfO Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Abstract
所提供的是一種在主動閘極上方形成接觸之方法。具體實施例包括在鰭片之一部分上方形成第一與第二閘極結構;分別在該等第一閘極結構之間、及該第一閘極結構與該第二閘極結構之間的該鰭片之一部分中形成第一與第二RSD;在該等第一與第二RSD上方形成TS結構;在該等第一與第二閘極結構上方、或在該等TS結構上方形成第一覆蓋層;在該基板上方形成金屬氧化物襯墊,溝槽從而形成;用第二覆蓋層填充該等溝槽;在該基板上方形成ILD層;穿過該ILD之第一部分、及金屬氧化物層向下形成連至該第二RSD上方的該等TS結構之CA;以及穿過該ILD之第二部分、及金屬氧化物層向下形成連至該等第一閘極結構之CB。
Description
本揭露係關於諸如積體電路(IC)等半導體裝置之製造。本揭露尤其適用於透過7奈米(nm)及更先進的技術節點形成IC之主動閘極上方接觸(contacts over active gates;COAG)。
對於記憶體增加、運算能力增強且速度更快之較小的半導體裝置,需求日益增加。半導體裝置持續按比例縮小尺寸而使密度增加。然而,習知的製造技術涉及接觸隔離區上方的閘極電極之一部分,不僅浪費布局空間,還對密度造成不利影響。因此,在閘極之功能性部分上方直接形成接觸來提升裝置密度。
因此,有效率的實現方法需要具有COAG之比例縮小裝置。
本揭露之一態樣是一種具有COAG之比例縮小的半導體裝置,該COAG形成源極/汲極接觸(CA)及閘極接觸(CB)。
本揭露之另一態樣是一種製作具有COAG之比例縮小的半導體裝置的方法。
本揭露之附加態樣及其它特徵將會在以下說明中提出,並且對於審查以下內容之所屬技術領域中具有通常知識者部分將會顯而易見, 或可經由實踐本揭露來學習。可如隨附申請專利範圍中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露,有一些功效可藉由一種方法來部分達成,該方法包括形成位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之淺溝槽隔離(STI)層上方;形成位在該等第一閘極結構之間的該鰭片之一部分中之第一隆起源極/汲極(RSD)、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;形成位在該第一RSD及各該第二RSD上方之溝槽矽化物(TS)結構;形成位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上方之第一覆蓋層;採保形方式形成位在該基板上方之金屬氧化物襯墊,複數個溝槽從而形成;用第二覆蓋層填充該複數個溝槽;形成位在該基板上方之層間介電(ILD)層;形成向下穿過該ILD層之第一部分、及該金屬氧化物層連至該第二RSD上方的該等TS結構之CA;以及形成向下穿過該ILD層之第二部分、及該金屬氧化物層連至該等第一閘極結構之CB。
本揭露之態樣包括藉由以下步驟形成該等第一閘極結構及該等第二閘極結構:形成在該基板之該鰭片上方側向分開之第一虛設閘極、及各在該鰭片之該外部分及相鄰於該鰭片之該STI層上方側向分開之第二虛設閘極;形成位在該等第一虛設閘極及該等第二虛設閘極之各側壁上之側壁間隔物;繼該第一RSD及該第二RSD之該形成後,形成位在該基板上方之第二ILD層;將該第二ILD層向下平坦化至該等側壁間隔物;移除該等第一虛設閘極及該等第二虛設閘極;形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之一部分的高k/金屬閘極(HKMG)層;以及形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等 側壁間隔物之剩餘部分的該HKMG層上方之金屬層。進一步態樣包括藉由以下步驟形成該等TS結構:分別移除該第一RSD與該第二RSD上方介於該等側壁間隔物之間的該第二ILD層,第一溝槽與第二溝槽從而形成;用鈷(Co)、鎢(W)或釕(Ru)填充該第一溝槽與該第二溝槽;以及將該Co、W或Ru向下平坦化至該等側壁間隔物。另一態樣包括沿著該等側壁間隔物之該第二部分所形成之該金屬層,該方法包括:形成位在該基板上方之該第一覆蓋層;以及將該第一覆蓋層向下平坦化至該等側壁間隔物。
附加態樣包括在形成該金屬氧化物層前,先使該等TS結構及相鄰側壁間隔物凹陷。進一步態樣包括形成穿過該第二RSD上方的該第二覆蓋層之該CA;以及形成穿過該等第一閘極結構上方的該第一覆蓋層、及該等第一閘極結構之間的該第二覆蓋層之該CB。另一態樣包括沿著該等側壁間隔物之剩餘部分所形成之該金屬層,該方法包括:使該等TS結構凹陷;形成位在該基板上方之該第一覆蓋層;以及將該第一覆蓋層向下平坦化至該金屬層。附加態樣包括在形成該金屬氧化物層前,先使該金屬層及相鄰側壁間隔物凹陷。進一步態樣包括形成穿過該第二RSD上方的該第一覆蓋層之該CA;以及形成穿過該等第一閘極結構上方的該第二覆蓋層之該CB。另一態樣包括藉由原子層沉積(ALD)形成由氧化鋁(Al2O3)、二氧化鈦(TiO2)或氧化鉿(HfO2)構成之該金屬氧化物襯墊。
本揭露之另一態樣是一種裝置,其包括位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之STI層上方;位在該等第一閘極結構之間的該鰭片之一部分中之第一RSD、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;位在該第一RSD及各該第二RSD上方之TS結構;位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上 方之第一覆蓋層;位在該基板上方之金屬氧化物襯墊,複數個溝槽從而形成;用第二覆蓋層填充之該複數個溝槽;位在該基板上方之ILD層;向下穿過該ILD層之第一部分、及該金屬氧化物層連至該第二RSD上方的該等TS結構之CA;以及向下穿過該ILD層之第二部分、及該金屬氧化物層連至該等第一閘極結構之CB。
該裝置之態樣包括該第一閘極結構及該第二閘極結構,其包括:介於側壁間隔物之間、及沿著該等側壁間隔物之一部分的HKMG層;以及介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等側壁間隔物之剩餘部分的該HKMG層上方之金屬層。另一態樣包括穿過該第二RSD上方的該第二覆蓋層之該CA;以及穿過該等第一閘極結構上方的該第一覆蓋層、及該等第一閘極結構之間該第二覆蓋層之該CB。其它態樣包括穿過該第二RSD上方的該第一覆蓋層之該CA;以及穿過該等第一閘極結構上方的該第二覆蓋層之該CB。再一態樣包括含有Co、W或Ru之該等TS結構。附加態樣包括形成之該等TS結構厚度為50nm至200nm。另一態樣包括形成之該金屬氧化物襯墊厚度為2nm至10nm。
本揭露之態樣包括形成位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之STI層上方;形成位在該等第一閘極結構之間的該鰭片之一部分中之第一RSD、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;形成位在該第一RSD及各該第二RSD上方之由Co、W或Ru構成之TS結構;形成位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上方之由氮化矽(SiN)、碳氮化矽(SiCN)、矽氧碳氮化物(SiOCN)或碳氧化矽(SiOC)構成之第一覆蓋層;在該基板上方藉由ALD採保形方式形成由Al2O3、TiO2或HfO2構成之金屬氧化物襯墊, 複數個溝槽從而形成;用包括SiO2、SiOC或SiN之第二覆蓋層填充該複數個溝槽;形成位在該基板上方之由二氧化矽(SiO2)、SiOC或SiN構成之ILD層;形成向下穿過該ILD層之第一部分、及該金屬氧化物層連至該第二RSD上方的該等TS結構之CA;以及形成向下穿過該ILD層之第二部分、及該金屬氧化物層連至該等第一閘極結構之CB。
另一態樣包括藉由以下步驟形成該等第一閘極結構及該等第二閘極結構:形成在該基板之該鰭片上方側向分開之第一虛設閘極、及各在該鰭片之該外部分及相鄰於該鰭片之該STI層上方側向分開之第二虛設閘極;形成位在該等第一虛設閘極及該等第二虛設閘極之各側壁上之側壁間隔物;繼該第一RSD及該第二RSD之該形成後,形成位在該基板上方之第二ILD層;將該第二ILD層向下平坦化至該等側壁間隔物;移除該等第一虛設閘極及該等第二虛設閘極;形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之一部分的HKMG層;以及形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等側壁間隔物之剩餘部分的該HKMG層上方之金屬層。再一態樣包括藉由以下步驟形成該等TS結構:分別移除該第一RSD與該第二RSD上方介於該等側壁間隔物之間的該第二ILD層,第一溝槽與第二溝槽從而形成;用Co、W或Ru填充該第一溝槽與該第二溝槽;以及將該Co、W或Ru向下平坦化至該等側壁間隔物。
本揭露之附加態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變為顯而易見,其中本揭露之具體實施例單純地藉由經深思用以實行本揭露之最佳模式的說明來描述。如將會瞭解的是,本揭露能夠是其它及不同的具體實施例,而且其數項細節能夠在各種明顯方面進行修改,全都不會脫離本揭露。因此,圖式及說明本 質上要視為說明性,而不是作為限制。
101、1201‧‧‧鰭片
103、1203‧‧‧基板
105、1205‧‧‧STI層
107、107'、1207、1207'‧‧‧側壁間隔物
109、111、113、1209~1213‧‧‧RSD
115、701、701'、701"、1215、2001、2001'、2001"‧‧‧ILD層
117、1217‧‧‧HKMG層
119、1001、1101、1219、1219'、2301、2401‧‧‧金屬層
121、123、1221、1221'、1223、1223'‧‧‧閘極結構
125、601、601'、1601、1601'、1901‧‧‧覆蓋層
201~205、401~405、503~507、801、901、1301~1305、1501~1503、1701~1707、1803~1809、2101、2201‧‧‧溝槽
301、303、305、301'、303'、305'、1401~1405、1401'~1405'‧‧‧TS結構
501、501'、501"、1801、1801'、1801"‧‧‧金屬氧化物襯墊、金屬氧化物層
本揭露是在隨附圖式的附圖中舉例來說明,但非作為限制,圖中相同的參考元件符號係指類似的元件,並且其中:第1至11圖根據一例示性具體實施例,示意性繪示用於形成CA及CB之程序流程的截面圖;以及第12至24圖根據一例示性具體實施例,示意性繪示用於形成CA及CB之程序流程的截面圖。
在底下的說明中,為了解釋,提出許多特定細節以便透徹理解例示性具體實施例。然而,應顯而易知的是,沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中,眾所周知的結構及裝置是以方塊圖形式來展示,為的是要避免不必要地混淆例示性具體實施例。另外,除非另有所指,本說明書及申請專利範圍中用來表達成分、反應條件等等之量、比率、及數值特性的所有數字都要了解為在所有實例中是以「約」一字來修飾。
本揭露藉由在隔離區上方對閘極電極之一部分施作接觸來因應並解決目前形成接觸時伴隨而來之密度降低的問題。該問題特別是藉由形成CA及CB來解決。
根據本揭露之具體實施例之方法包括形成位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各個閘極結構位在該鰭片之外部分、及相鄰於該鰭片之STI層上方。在介於該等第一閘極結構之間的該鰭片之一部分中形成第一RSD、以及在介於該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中形成第二RSD。然後,在該第一RSD及 各該第二RSD上方形成TS結構。在該等第一閘極結構及該等第二閘極結構上方、或在該等TS結構上方形成第一覆蓋層。在該基板上方採保形方式形成金屬氧化物襯墊,複數個溝槽從而形成。用第二覆蓋層填充該複數個溝槽。在該基板上方形成ILD層。穿過該ILD層之第一部分、及該金屬氧化物層向下至該第二RSD上方的該等TS結構而形成源極/汲極接觸(CA),以及穿過該ILD層之第二部分、及該金屬氧化物層向下至該等第一閘極結構而形成閘極接觸(CB)。
單純地藉由所思最佳模式的描述,還有其它態樣、特徵、以及技術功效經由下文的實施方式對於所屬技術領域中具有通常知識者將顯而易知,其中所示及所述為較佳具體實施例。本揭露能夠有其它及不同具體實施例,並且其數項細節能夠用各種明顯觀點來修改。因此,圖式及說明本質上要視為說明性,而不是作為限制。
第1至11圖根據一例示性具體實施例,示意性繪示用於形成CA及CB之程序流程的截面圖。請參閱第1圖,在基板103之鰭片101之一部分上方形成側向分開之第一虛設閘極(為便於說明而未展示),並且在鰭片101之外部分、及相鄰於鰭片101之STI層105上方形成側向分開之第二虛設閘極(為便於說明而未展示)。在一項實例中,STI層105包括SiO2或類似材料。之後,側壁間隔物107係藉由化學氣相沉積(CVD)在第一虛設閘極及第二虛設閘極之側壁上由例如SiOCN、SiO2、SiN、SiCN、SiOC或類似材料所構成,寬度例如為2nm至10nm。接著,在該等第一虛設閘極之間的鰭片101之一部分中形成RSD 109,以及在該等第一虛設閘極及該等第二虛設閘極之間的鰭片101之一部分中形成RSD 111與113。在一項實例中,RSD 109、111及113包括磊晶(EPI)材料,其中用於NFET RSD之EPI材料為經過P型摻雜之矽-磷(SiP),而用於PFET RSD之EPI材料 為經過B型摻雜之矽鍺(SiGe)。隨後,ILD層115係在基板103上方由例如SiO2、SiOC、SiN或類似材料所構成,並且予以向下平坦化至側壁間隔物107。然後,移除該等第一虛設閘極及該等第二虛設閘極。之後,在諸側壁間隔物107之間及沿著其一部分形成厚度例如為2nm至10nm之HKMG層117。據此,金屬層119係在HKMG層117上方、以及在諸側壁間隔物107之間、及沿著側壁間隔物107之第二部分由例如Co、W或Ru所構成且厚度例如為10nm至100nm,分別形成閘極結構121與123。隨後,覆蓋層係在ILD層115、側壁間隔物107及閘極結構121與123上方由例如SiN、SiCN、SiOCN、SiOC或類似材料所構成,厚度例如為10nm至100nm。然後,將該覆蓋層平坦化至側壁間隔物107,形成覆蓋層125。
如第2圖所示,藉由反應性離子蝕刻(RIE)來移除諸側壁間隔物107之間、及RSD 109、111及113上方之ILD層115,形成溝槽201、203及205。之後,溝槽201、203及205係藉由CVD用例如Co、W或Ru之金屬來填充,厚度例如為50nm至200nm。然後,將該金屬向下平坦化至側壁間隔物107,形成TS結構301、303及305,如第3圖所示。接著,在第4圖中,藉由RIE或濕蝕刻使TS結構301、303與305、及相鄰側壁間隔物107凹陷,形成TS結構301'、303'與305'、側壁間隔物107'及溝槽401、403與405。
請參閱第5圖,金屬氧化物襯墊501係於ILD層115、側壁間隔物107、覆蓋層125及溝槽401、403與405上方藉由ALD採保形方式由Al2O3、TiO2、HfO2或類似材料所構成,厚度例如為2nm至10nm,從而形成溝槽503、505與507。接著,溝槽503、505與507係以包括SiN、SiCN、SiOCN、SiOC或類似材料之覆蓋層601來填充,如第6圖所示。之後,在金屬氧化物襯墊501及覆蓋層601上方形成ILD層701,如 第7圖所示。
隨後,在第8圖中,將ILD層701之第一部分蝕刻,形成ILD層701'。然後移除TS結構301'與305'上方之覆蓋層601。結果,金屬氧化物層501之第一部分被向下蝕刻至TS結構301'與305',形成金屬氧化物層501'及溝槽801。然後,在第10圖中,溝槽801係以例如Co、W或Ru之金屬層1001來填充,形成連至RSD 111及113之CA。金屬層1001之上表面與ILD層701'之上表面共面。
請參閱第9圖,將ILD層701'之第二部分蝕刻,形成ILD層701"。然後移除TS結構303'上方之覆蓋層601。應了解,可在形成CB期間移除TS結構301'與305'上方的覆蓋層601之部分,形成覆蓋層601'。接著,將金屬氧化物層501'之第二部分向下蝕刻至閘極結構121上方之覆蓋層125,形成金屬氧化物層501"。隨後,移除覆蓋層125,形成溝槽901。之後,在第11圖中,溝槽901係以例如Co、W或Ru之金屬層1101來填充,形成連至閘極結構121之CB。金屬層1101之上表面與ILD層701"之上表面共面。
第12至24圖根據一例示性具體實施例,示意性繪示用於形成CA及CB之程序流程的截面圖。請參閱第12圖,類似於上面對照第1圖所述之程序步驟,在基板1203之鰭片1201之一部分上方形成側向分開之第一虛設閘極(為便於說明而未展示),並且在鰭片1201之外部分、及相鄰於鰭片1201之STI層1205上方形成側向分開之第二虛設閘極(為便於說明而未展示)。在一項實例中,STI層1205包括SiO2或類似材料。之後,側壁間隔物107係藉由CVD在第一虛設閘極及第二虛設閘極之側壁上由例如SiOCN、SiO2、SiN、SiCN、SiOC或類似材料所構成,寬度例如為2nm至10nm。接著,在該等第一虛設閘極之間的鰭片1201之一部分中形 成RSD 1209,以及在該等第一虛設閘極及該等第二虛設閘極之間的鰭片1201之一部分中形成RSD 1211與1213。在一項實例中,RSD 1209、1211及1213包括EPI材料,其中用於NFET RSD之EPI材料為經過P型摻雜之SiP,而用於PFET RSD之EPI材料為經過B型摻雜之SiGe。隨後,ILD層1215係在基板1203上方由例如SiO2、SiOC、SiN或類似材料所構成,並且予以向下平坦化至側壁間隔物1207。然後,移除該等第一虛設閘極及該等第二虛設閘極。之後,在諸側壁間隔物1207之間及沿著其一部分形成厚度例如為2nm至10nm之HKMG層1217。據此,金屬層1219係在HKMG層1217上方、以及在諸側壁間隔物1207之間、及沿著側壁間隔物1207之剩餘部分由例如Co、W或Ru所構成,分別形成閘極結構1221與1223。
如第13圖所示,藉由RIE來移除諸側壁間隔物1207之間、及RSD 1209、1211及1213上方之ILD層1215,形成溝槽1301、1303及1305。之後,溝槽1301、1303及1305係藉由CVD用例如Co、W或Ru之金屬來填充,厚度例如為50nm至200nm。然後,將該金屬向下平坦化至側壁間隔物1207,形成TS結構1401、1403及1405,如第14圖所示。接著,在第15圖中,藉由RIE或濕蝕刻使TS結構1401、1403與1405凹陷,形成TS結構1401'、1403'與1405'、及溝槽1501、1503與1505。之後,在第16圖中,於TS結構1401'、1403'及1405'上方形成包括SiN、SiCN、SiOCN、SiOC或類似材料之覆蓋層,將溝槽1501、1503及1505填充。然後,將該覆蓋層平坦化至側壁間隔物1207,形成覆蓋層1601。
請參閱第17圖,使金屬層1219及相鄰側壁間隔物1207凹陷,形成金屬層1219'、側壁間隔物1207'、溝槽1701、1703、1705與1707以及閘極結構1221'與1223'。之後,在第18圖中,金屬氧化物襯墊1801 係藉由ALD在ILD層1215、溝槽1701、1703、1705與1707、以及覆蓋層1601上方採保形方式由例如Al2O3、TiO2或HfO2所構成,厚度例如為2nm至10nm,從而形成溝槽1803、1805、1807與1809。接著,溝槽1803、1805、1807與1809係以包括SiN、SiCN、SiOCN、SiOC或類似材料之覆蓋層1901來填充,如第19圖所示。之後,在金屬氧化物襯墊1801及覆蓋層1901上方形成ILD層2001,如第20圖所示。
隨後,在第21圖中,將ILD層2001之第一部分蝕刻,形成ILD層2001'。然後,將金屬氧化物層1801與覆蓋層1901之第一部分向下蝕刻至TS結構1401’與1405’上方之覆蓋層1601。接著,移除TS結構1401'與1405'上方之覆蓋層1601,形成溝槽2101。隨後,以例如Co、W或Ru之金屬層2301填充溝槽2101,形成連至RSD 1211及1213之CA,如第23圖所示。金屬層2301之上表面與ILD層2001'之上表面共面。
請參閱第22圖,將ILD層2001'之第二部分蝕刻,形成ILD層2001"。然後,移除閘極結構1221上方之覆蓋層1901。接著移除金屬氧化物層1801'之第二部分、及覆蓋層1601,形成金屬氧化物層1801"、覆蓋層1601'及溝槽2201。隨後,以例如Co、W或Ru之金屬層2401填充溝槽2201,形成連至閘極結構1221’之CB,如第24圖所示。金屬層2401之上表面與ILD層2001'之上表面共面。
本揭露之具體實施例可達成數種技術功效,例如用以在主動閘極上方施作接觸之穩健整合方案、密度改善、良率更高以及裝置效能改善。根據本揭露之具體實施例所形成的裝置符合各種產業應用的利用性要求,例如微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD錄影機與播放器、汽車導航、印表機與週邊裝置、網路連結與電信設備、遊戲系統及數位相機。本揭露在各種類型之高度整合型半導體裝置之任一 者中享有產業利用性,尤其是對於7nm及更先進的技術節點而言。
在前述說明中,本揭露係參照其具體例示性具體實施例作說明。然而,將會證實可對其進行各種修改及變更,但不會脫離本揭露的更廣泛精神與範疇,如申請專利範圍中所提。本說明書及圖式從而要視為說明性而非作為限制。據了解,本揭露能夠使用各種其它組合及具體實施例,並且如本文中所表達,能夠在本發明概念的範疇內作任何變更或修改。
Claims (20)
- 一種方法,包含:形成位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之淺溝槽隔離(STI)層上方;形成位在該等第一閘極結構之間的該鰭片之一部分中之第一隆起源極/汲極(RSD)、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;形成位在該第一RSD及各該第二RSD上方之溝槽矽化物(TS)結構;形成位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上方之第一覆蓋層;採保形方式形成位在該基板上方之金屬氧化物襯墊,複數個溝槽從而形成;用第二覆蓋層填充該複數個溝槽;形成位在該基板上方之層間介電(ILD)層;形成穿過該ILD層之第一部分、及該金屬氧化物層向下至該第二RSD上方的該等TS結構的源極/汲極接觸(CA);以及形成穿過該ILD層之第二部分、及該金屬氧化物層向下至該等第一閘極結構的閘極接觸(CB)。
- 如申請專利範圍第1項所述之方法,其中,該等第一閘極結構及該等第二閘極結構係藉由以下步驟所形成:形成在該基板之該鰭片上方側向分開之第一虛設閘極、及各在該鰭片之該外部分及相鄰於該鰭片之該STI層上方側向分開之第二虛設閘極; 形成位在該等第一虛設閘極及該等第二虛設閘極之各側壁上之側壁間隔物;繼該第一RSD及該第二RSD之該形成後,形成位在該基板上方之第二ILD層;將該第二ILD層向下平坦化至該等側壁間隔物;移除該等第一虛設閘極及該等第二虛設閘極;形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之一部分的高k/金屬閘極(HKMG)層;以及形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等側壁間隔物之剩餘部分的該HKMG層上方之金屬層。
- 如申請專利範圍第2項所述之方法,其中,該等TS結構係藉由以下步驟所形成:分別移除該第一RSD與該第二RSD上方介於該等側壁間隔物之間的該第二ILD層,第一溝槽與第二溝槽從而形成;用鈷(Co)、鎢(W)或釕(Ru)填充該第一溝槽與該第二溝槽;以及將該Co、W或Ru向下平坦化至該等側壁間隔物。
- 如申請專利範圍第2項所述之方法,其中,該金屬層係沿著該等側壁間隔物之該第二部分形成,該方法包含:形成位在該基板上方之該第一覆蓋層;以及將該第一覆蓋層向下平坦化至該等側壁間隔物。
- 如申請專利範圍第4項所述之方法,更包含在形成該金屬氧化物層前,先使該等TS結構及相鄰側壁間隔物凹陷。
- 如申請專利範圍第4項所述之方法,更包含:形成穿過該第二RSD上方的該第二覆蓋層之該CA;以及 形成穿過該等第一閘極結構上方的該第一覆蓋層、及該等第一閘極結構之間的該第二覆蓋層之該CB。
- 如申請專利範圍第2項所述之方法,其中,該金屬層係沿著該等側壁間隔物之剩餘部分形成,該方法包含:使該等TS結構凹陷;形成位在該基板上方之該第一覆蓋層;以及將該第一覆蓋層向下平坦化至該金屬層。
- 如申請專利範圍第4項所述之方法,更包含在形成該金屬氧化物層前,先使該金屬層及相鄰側壁間隔物凹陷。
- 如申請專利範圍第4項所述之方法,更包含:形成穿過該第二RSD上方的該第一覆蓋層之該CA;以及形成穿過該等第一閘極結構上方的該第二覆蓋層之該CB。
- 如申請專利範圍第1項所述之方法,其中,該金屬氧化物襯墊藉由原子層沉積(ALD)包含氧化鋁(Al 2O 3)、二氧化鈦(TiO 2)或氧化鉿(HfO 2)。
- 一種裝置,包含:位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之淺溝槽隔離(STI)層上方;位在該等第一閘極結構之間的該鰭片之一部分中之第一隆起源極/汲極(RSD)、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;位在該第一RSD及各該第二RSD上方之溝槽矽化物(TS)結構;位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上方之第一覆蓋層; 位在該基板上方之金屬氧化物襯墊,複數個溝槽從而形成;用第二覆蓋層填充之該複數個溝槽;位在該基板上方之層間介電(ILD)層;穿過該ILD層之第一部分、及該金屬氧化物層向下至該第二RSD上方的該等TS結構的源極/汲極接觸(CA);以及穿過該ILD層之第二部分、及該金屬氧化物層向下至該等第一閘極結構的閘極接觸(CB)。
- 如申請專利範圍第11項所述之裝置,其中,該等第一閘極結構及該等第二閘極結構包含:介於側壁間隔物之間、及沿著該等側壁間隔物之一部分的高k/金屬閘極(HKMG)層;以及介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等側壁間隔物之剩餘部分的該HKMG層上方之金屬層。
- 如申請專利範圍第11項所述之裝置,更包含:穿過該第二RSD上方的該第二覆蓋層之該CA;以及穿過該等第一閘極結構上方的該第一覆蓋層、及該等第一閘極結構之間的該第二覆蓋層之該CB。
- 如申請專利範圍第11項所述之裝置,更包含:穿過該第二RSD上方的該第一覆蓋層之該CA;以及穿過該等第一閘極結構上方的該第二覆蓋層之該CB。
- 如申請專利範圍第11項所述之裝置,其中,該等TS結構包含鈷(Co)、鎢(W)或釕(Ru)。
- 如申請專利範圍第11項所述之裝置,其中,該等TS結構形成有厚度50奈米(nm)至200nm。
- 如申請專利範圍第10項所述之裝置,其中,該金屬氧化物襯墊形成有厚度2nm至10nm。
- 一種方法,包含:形成位在基板之鰭片上方之第一閘極結構、及第二閘極結構,各者位在該鰭片之外部分、及相鄰於該鰭片之淺溝槽隔離(STI)層上方;形成位在該等第一閘極結構之間的該鰭片之一部分中之第一隆起源極/汲極(RSD)、及位在該等第一閘極結構與該等第二閘極結構之間的該鰭片之該部分中之第二RSD;形成位在該第一RSD及各該第二RSD上方之由鈷(Co)、鎢(W)或釕(Ru)構成之溝槽矽化物(TS)結構;形成位在該等第一閘極結構及該等第二閘極結構上方、或位在該等TS結構上方之由氮化矽(SiN)、碳氮化矽(SiCN)、矽氧碳氮化物(SiOCN)或SiOC構成之第一覆蓋層;在該基板上方藉由原子層沉積(ALD)採保形方式形成由氧化鋁(Al 2O 3)、二氧化鈦(TiO 2)或氧化鉿(HfO 2)構成之金屬氧化物襯墊,複數個溝槽從而形成;用包含SiO 2、SiOC或SiN之第二覆蓋層填充該複數個溝槽;形成位在該基板上方之由二氧化矽(SiO 2)、碳氧化矽(SiOC)或SiN構成之層間介電(ILD)層;形成穿過該ILD層之第一部分、及該金屬氧化物層向下至該第二RSD上方該等TS結構的源極/汲極接觸(CA);以及形成穿過該ILD層之第二部分、及該金屬氧化物層向下至該等第一閘極結構的閘極接觸(CB)。
- 如申請專利範圍第18項所述之方法,其中,該等第一閘極結構及該等第二閘極結構係藉由以下步驟所形成:形成在該基板之該鰭片上方側向分開之第一虛設閘極、及各在該鰭片之該外部分及相鄰於該鰭片之該STI層上方側向分開之第二虛設閘極;形成位在該等第一虛設閘極及該等第二虛設閘極之各側壁上之側壁間隔物;繼該第一RSD及該第二RSD之該形成後,形成位在該基板上方之第二ILD層;將該第二ILD層向下平坦化至該等側壁間隔物;移除該等第一虛設閘極及該等第二虛設閘極;形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之一部分的高k/金屬閘極(HKMG)層;以及形成介於該等側壁間隔物之間、及沿著該等側壁間隔物之第二部分、或沿著該等側壁間隔物之剩餘部分的該HKMG層上方之金屬層。
- 如申請專利範圍第18項所述之方法,其中,該等TS結構係藉由以下步驟所形成:分別移除該第一RSD與該第二RSD上方介於該等側壁間隔物之間的該第二ILD層,第一溝槽與第二溝槽從而形成;用鈷(Co)、鎢(W)或釕(Ru)填充該第一溝槽與該第二溝槽;以及將該Co、W或Ru向下平坦化至該等側壁間隔物。
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TW544787B (en) | 2002-09-18 | 2003-08-01 | Promos Technologies Inc | Method of forming self-aligned contact structure with locally etched gate conductive layer |
US6884715B1 (en) | 2004-06-04 | 2005-04-26 | International Business Machines Corporation | Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby |
WO2013101007A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process |
US9412840B1 (en) | 2015-05-06 | 2016-08-09 | International Business Machines Corporation | Sacrificial layer for replacement metal semiconductor alloy contact formation |
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2018
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- 2019-03-25 TW TW108110301A patent/TWI677911B/zh active
- 2019-04-24 DE DE102019205807.8A patent/DE102019205807B4/de active Active
Cited By (2)
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TWI798857B (zh) * | 2021-05-26 | 2023-04-11 | 南亞科技股份有限公司 | 具有錐形輪廓接觸點的半導體元件及其製備方法 |
US11688772B2 (en) | 2021-05-26 | 2023-06-27 | Nanya Technology Corporation | Semiconductor device with contact having tapered profile and method for fabricating the same |
Also Published As
Publication number | Publication date |
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DE102019205807B4 (de) | 2022-08-11 |
DE102019205807A1 (de) | 2019-10-31 |
TWI677911B (zh) | 2019-11-21 |
US10347541B1 (en) | 2019-07-09 |
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