TW201939704A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TW201939704A
TW201939704A TW107127794A TW107127794A TW201939704A TW 201939704 A TW201939704 A TW 201939704A TW 107127794 A TW107127794 A TW 107127794A TW 107127794 A TW107127794 A TW 107127794A TW 201939704 A TW201939704 A TW 201939704A
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insulating material
material layer
conductive
layer
semiconductor wafer
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TW107127794A
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黃崑永
陳彥儒
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力成科技股份有限公司
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Abstract

一種封裝結構的製造方法，本方法包括以下步驟。於載板上接合半導體晶片，其中半導體晶片包括多個導電接墊。於載板上形成絕緣材料層以密封半導體晶片，且絕緣材料層的厚度大於半導體晶片的厚度。對絕緣材料層的第一表面進行圖案化以形成第一開口以及第二開口，其中第一開口暴露出半導體晶片的導電接墊，第二開口穿透絕緣材料層。於第一開口中形成多個導電柱，其中多個導電柱與半導體晶片中的多個導電接墊電性連接。於第二開口中形成多個導通孔。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構，且特別是有關一種封裝結構及其製造方法。
為了使得電子設備能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。然而，隨著這些封裝件的尺寸減小，半導體封裝的製程的複雜性變得越來越具有挑戰性。因此，如何在半導體封裝微型化的同時還能夠維持製程的簡單性實為本領域的技術人員的一大挑戰。
本發明提供一種封裝結構及其製造方法，其可以簡化製程且減少了製造成本。
本發明提供了一種封裝結構的製造方法。製造方法包括以下步驟。提供載板。於載板上接合半導體晶片，其中半導體晶片包括多個導電接墊。於載板上形成絕緣材料層，絕緣材料層密封半導體晶片，其中絕緣材料層包括第一表面以及相對於第一表面的第二表面，且絕緣材料層的厚度大於半導體晶片的厚度。對絕緣材料層的第一表面進行圖案化以形成多個第一開口以及多個第二開口，其中多個第一開口暴露出半導體晶片的多個導電接墊，多個第二開口貫穿絕緣材料層。於多個第一開口中形成多個導電柱，其中多個導電柱與半導體晶片中的多個導電接墊電性連接。於多個第二開口中形成多個導通孔。於絕緣材料層的第一表面上形成重佈線路層，其中重佈線路層電性連接至多個導通孔以及多個導電柱。移除載板。於絕緣材料層的第二表面形成多個導電端子，其中多個導電端子藉由多個導通孔電性連接至重佈線路層。
在本發明的一實施例中，前述的晶種層包括鈦層或銅層。
在本發明的一實施例中，前述的絕緣材料層為光敏絕緣材料層。
在本發明的一實施例中，前述的絕緣材料層的厚度範圍為200微米至250微米。
在本發明的一實施例中，前述的方法更包括以下步驟。於前述的載板上接合前述的半導體晶片之前，於前述的載板上形成離型層，其中前述的離型層及前述的載板於剝離製程時自前述的絕緣材料層及前述的半導體晶片分離。
在本發明的一實施例中，前述的離型層及前述的載板在施加紫外光雷射後自前述的絕緣材料層及前述的半導體晶片分離。
在本發明的一實施例中，前述的多個導通孔的高度大於前述的絕緣材料層的厚度。
本發明提供了一種半導體封裝結構。半導體封裝結構包括半導體晶片、絕緣材料層、多個導通孔、多個導電柱、重佈線路層以及多個導電端子。半導體晶片包括多個導電接墊。絕緣材料層密封半導體晶片，其中絕緣材料層包括第一表面以及相對於前述的第一表面的第二表面，且絕緣材料層的厚度大於半導體晶片的厚度。多個導通孔位於絕緣材料層的第一表面上且貫穿絕緣材料層。多個導電柱位於絕緣材料層的第一表面上且電性連接至半導體晶片。重佈線路層位於絕緣材料層的第一表面且電性連接至多個導通孔及多個導電柱。多個導電端子位於絕緣材料層的第二表面上且電性連接至多個導通孔。
在本發明的一實施例中，前述的第一晶種層及前述的第二晶種層包括鈦層或銅層。
在本發明的一實施例中，前述的絕緣材料層為光敏絕緣材料層。
在本發明的一實施例中，前述的絕緣材料層的厚度範圍為200微米至250微米。
基於上述，本發明的封裝結構為先形成絕緣材料層，並圖案化絕緣材料層以形成第一開口以及第二開口，然後，於第一開口與第二開口中形成導電柱以及導通孔。因此，可以省略傳統製程中導通孔表面、半導體晶片以及絕緣密封體所需的薄化步驟。換句話說，封裝結構的製程被簡化了並減少了製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1至圖8是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。請參照圖1，提供載板101。載板101可以由矽、聚合物或其他適宜的材料所製成。在一些實施例中，載板101可以是玻璃基板或玻璃支撐板。其他合適的基板材料也可以作為載板101，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。如圖1所示，於載板101上形成緩衝層103。在一些實施例中，緩衝層103可以包括離型層103A以及介電層103B。介電層103B可以由介電材料所製成，介電材料包括苯並環丁烯（benzocyclobutene；BCB）、聚苯噁唑（polybenzoxazole；PBO）或其他適宜的聚合物介電材料。離型層103A例如是光熱轉換（light to heat conversion；LTHC）離型層，其可以在室溫下透過將雷射施加至離型層103A上，而使得離型層103A從載板101上剝離。然而，本發明不限於此。在一些替代的實施例中，離型層103A可以視需求而選擇其他適宜的材料。
請參照圖2，於載板101上接合半導體晶片104。在一些實施例中，半導體晶片104可以藉由晶粒黏著膜（die attach film；DAF）（未繪示）接合於載板101上。如圖2所示，半導體晶片104包括半導體基板104a以及配置於半導體基板104a上的多個導電接墊104b。半導體基板104a可以是塊狀矽（bulk silicon substrate）基板或絕緣層上覆矽（silicon-on-insulator；SOI）基板。此外，半導體基板104a中可以包括主動元件（例如電晶體或其類似者）以及可以選擇性地形成包括被動元件（例如電阻、電容、電感或其類似者）。導電接墊104b可以是鋁接墊、銅接墊或其它適宜的金屬接墊。在示例性的實施例中，半導體晶片104具有主動面AS以及相對於主動面AS的背面BS。多個導電接墊104b位於半導體晶片104的主動面AS上，而半導體晶片104的背面BS黏著至緩衝層103上。
請參照圖3，於載板101上形成絕緣材料層106，以密封半導體晶片104。舉例而言，絕緣材料層106可以是光敏絕緣材料層（photosensitive insulating material layer），光敏絕緣材料層包括光敏材料例如是苯並環丁烯（benzocyclobutene；BCB）、聚苯噁唑（polybenzoxazole；PBO）、環氧樹脂（epoxy）、聚醯亞胺（polyimide）或其他適宜的光敏絕緣材料。在一些實施例中，絕緣材料層106可以包括分佈在其中的填充物。然而，本發明不限於此。在一些實施例中，絕緣材料層106中沒有添加填充物。此外，如圖3所示，絕緣材料層106的厚度T1大於半導體晶片104的厚度T2。在一些實施例中，絕緣材料層106的厚度T1的範圍為200微米（micrometer；μm）至250微米。在示例性實施例中，藉由絕緣材料層106密封半導體晶片104中的多個導電接墊104b，以使多個導電接墊104b受到良好的保護。換句話說，在這個階段中，絕緣材料層106不會暴露出半導體晶片104。此外，絕緣材料層106具有第一表面106-1以及相對於第一表面106-1的第二表面106-2。絕緣材料層106的第一表面106-1遠離載板101，而絕緣材料層106的第二表面106-2與緩衝層103物理接觸。
請參照圖4，在形成絕緣材料層106之後，對絕緣材料層106的第一表面106-1上進行圖案化，以形成第一開口OP1以及第二開口OP2。在本實施例中，第一開口OP1暴露出半導體晶片104的多個導電接墊104b，而第二開口OP2貫穿絕緣材料層106。換句話說，第二開口OP2從絕緣材料層106的第一表面106-1貫穿到第二表面106-2，以暴露出位於下方的緩衝層103。在一些實施例中，絕緣材料層106可以藉由微影（lithography）製程進行圖案化。由於絕緣材料層106是由光敏絕緣材料所製成，因此，絕緣材料層106可以藉由微影製程有效地進行圖案化。然而，本發明不限於此。在一些實施例中，絕緣材料層106可以藉由其他製程來進行圖案化。
請參照圖5，在形成第一開口OP1以及第二開口OP2之後，形成晶種層107以覆蓋於絕緣材料層106上。舉例而言，晶種層107可以藉由物理氣相沉積法（physical vapor deposition；PVD）形成。在一些實施例中，晶種層107的材質可以包括鈦層、銅層或其類似者。如圖5所示，晶種層107可以覆蓋絕緣材料層106的第一表面106-1，並且填入第一開口OP1中，以覆蓋第一開口OP1的側壁SW1，以及填入第二開口OP2中，以覆蓋第二開口OP2的側壁SW2。
請參照圖6，在形成晶種層107之後，於晶種層107上覆蓋導電材料層（未繪示），以填入第一開口OP1以及第二開口OP2中。接著，可以圖案化導電材料層以及位於其下方的晶種層107以形成多個導電柱108A、多個導通孔108B、第一晶種層107A以及第二晶種層107B。在一些實施例中，導電材料層的材料可以包括銅或銅合金，但本發明不以此為限。在一些實施例中，導通孔108B為絕緣體貫孔（insulator vias）或扇出型貫孔（fan-out vias）。
如圖6所示，多個導電柱108A填充於第一開口OP1內並且延伸超過第一開口OP1的高度。換句話說，導電柱108A設置於絕緣材料層106的第一表面106-1上並延伸超過絕緣材料層106的第一表面106-1，且與半導體晶片104中的導電接墊104b電性連接。在一些實施例中，多個導通孔108B填充於第二開口OP2內，並且延伸超過第二開口OP2的高度。換句話說，導通孔108B設置於絕緣材料層106的第一表面106-1上並延伸超過絕緣材料層106的第一表面106-1，且穿透絕緣材料層106。如圖6所示，多個導通孔108B的上表面108BT基本上與多個導電柱108A的上表面108AT共面。導通孔108B的上表面108BT與導電柱108A的上表面108AT可以高於絕緣材料層106的第一表面106-1。此外，多個導通孔108B的高度T3大於絕緣材料層106的厚度T1。
在示例性的實施例中，在圖案化製程之後，晶種層107可以被分成第一晶種層107A以及第二晶種層107B。如圖6所示，第一晶種層107A可以夾在導電柱108A和絕緣材料層106之間，而第一晶種層107A覆蓋導電柱108A的側壁108AS。類似地，第二晶種層107B可以夾在導通孔108B和絕緣材料層106之間，而第二晶種層107B覆蓋導通孔108B的側壁108BS。
請參照圖7，在形成導電柱108A和導通孔108B之後，於絕緣材料層106的第一表面106-1、導電柱108A以及導通孔108B上形成重佈線路層110。重佈線路層110可以包括交替堆疊的多個介電層110A和多個導電元件110B。多個介電層110A可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯等的非有機或有機介電材料所製成。多個導電元件110B可以由銅、鋁、鎳或其他適宜的導電材料所製成。雖然圖7僅繪示了兩層的導電元件110B以及三層的介電層110A，但本發明不以此為限。在其他實施例中，導電元件110B以及介電層110A的層數可以視產品需求決定。在一些實施例中，重佈線路層110中的導電元件110B可以與多個導通孔108B以及多個導電柱108A電性連接。
在形成重佈線路層110之後，可以於重佈線路層110上設置多個導電球112。導電球112的材料例如是銅、錫、金、鎳或其他適宜的導電材料。在一些實施例中，重佈線路層110中最上面的介電層110A可以包括形成於其上的多個導電接墊110C。舉例而言，導電接墊110C可以是凸塊底金屬（Under bump metallurgy；UBM），以用於後續的置球製程（ball mount process）。在一些實施例中，導電球112可以經過植球製程（ball placement process）配置於導電接墊110C上。在一些實施例中，導電球112經由重佈線路層110中的導電元件110B與半導體晶片104以及多個導通孔108B電性連接。
請參照圖8，在形成導電球112之後，載板101被剝離。舉例而言，介電層103B可以從離型層103A上分離，使得離型層103A和載板101自絕緣材料層106和半導體晶片104分離。在一些實施例中，載板101可以藉由剝離離型層103A時而一併移除。剝離製程可以將紫外光雷射、可見光或熱等外部能量施加到至離型層103A。其他適宜的方法可以用於剝離製程。此外，如圖8所示，介電層103B被圖案化，而形成接觸窗開口以暴露出導通孔108B（貫孔）的底面。舉例而言，可以使用雷射鑽孔製程（laser drilling process）形成介電層103B上的接觸窗開口。在形成接觸窗開口後，多個導電端子114被配置於絕緣材料層106的第二表面106-2上以及被填入接觸窗開口中。導電端子114經由多個導通孔108B與重佈線路層110中的導電元件110B電性連接。在所繪示的實施例中，在形成導電球112和導電端子114後，便可以實現具有雙側導電端子的封裝結構。
綜上所述，本發明的封裝結構為先形成絕緣材料層，並圖案化絕緣材料層以形成第一開口以及第二開口，然後，於第一開口與第二開口中形成導電柱以及導通孔。由於本發明是將絕緣材料層圖案化所形成的開口來形成導電柱與導通孔，因此，導電柱和導通孔可以藉由簡化的製程容易地限定於開口內。此外，還可以省略傳統製程中導通孔表面、半導體晶片以及絕緣密封體所需的薄化步驟。換句話說，封裝結構的製程被簡化了並減少了製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
101‧‧‧載板
103‧‧‧緩衝層
103A‧‧‧離型層
103B、110A‧‧‧介電層
104‧‧‧半導體晶片
104a‧‧‧半導體基板
104b、110C‧‧‧導電接墊
106‧‧‧絕緣材料層
106-1‧‧‧第一表面
106-2‧‧‧第二表面
107‧‧‧晶種層
107A‧‧‧第一晶種層
107B‧‧‧第二晶種層
108A‧‧‧導電柱
108B‧‧‧導通孔
108BT‧‧‧導通孔的上表面
108AT‧‧‧導電柱的上表面
108AS‧‧‧導電柱的側壁
108BS‧‧‧導通孔的側壁
110‧‧‧重佈線路層
110B‧‧‧導電元件
112‧‧‧導電球
114‧‧‧導電端子
AS‧‧‧主動面
BS‧‧‧背面
T1‧‧‧絕緣材料層的厚度
T2‧‧‧半導體晶片的厚度
T3‧‧‧高度
OP1‧‧‧第一開口
OP2‧‧‧第二開口
SW1‧‧‧第一開口的側壁
SW2‧‧‧第二開口的側壁
圖1至圖8是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。

Claims (10)

  1. 一種封裝結構的製造方法，包括： 提供載板； 於所述載板上接合半導體晶片，其中所述半導體晶片包括多個導電接墊； 於所述載板上形成絕緣材料層，所述絕緣材料層密封所述半導體晶片，其中所述絕緣材料層包括第一表面以及相對於所述第一表面的第二表面，且所述絕緣材料層的厚度大於所述半導體晶片的厚度； 對所述絕緣材料層的所述第一表面進行圖案化以形成多個第一開口以及多個第二開口，其中所述多個第一開口暴露出所述半導體晶片的所述多個導電接墊，所述多個第二開口貫穿所述絕緣材料層； 於所述多個第一開口中形成多個導電柱，其中所述多個導電柱與所述半導體晶片中的所述多個導電接墊電性連接； 於所述多個第二開口中形成多個導通孔； 於所述絕緣材料層的所述第一表面上形成重佈線路層，其中所述重佈線路層電性連接至所述多個導通孔以及所述多個導電柱； 移除所述載板；以及 於所述絕緣材料層的所述第二表面形成多個導電端子，其中所述多個導電端子藉由所述多個導通孔電性連接至所述重佈線路層。
  2. 如申請專利範圍第1項所述的封裝結構的製造方法，更包括： 形成晶種層，以覆蓋於所述絕緣材料層、所述多個第一開口的側壁以及所述多個第二開口的側壁上，其中所述晶種層形成於所述多個導電柱以及所述多個導通孔之前。
  3. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述絕緣材料層藉由微影製程被圖案化。
  4. 如申請專利範圍第1項所述的封裝結構的製造方法，更包括： 於所述重佈線路層上形成多個導電球，其中所述多個導電球藉由所述重佈線路層電性連接至所述半導體晶片及所述多個導通孔。
  5. 一種封裝結構，包括： 半導體晶片，其中所述半導體晶片包括多個導電接墊； 絕緣材料層，密封所述半導體晶片，其中所述絕緣材料層具有第一表面以及相對於所述第一表面的第二表面，且所述絕緣材料層的厚度大於所述半導體晶片的厚度； 多個導通孔，位於所述絕緣材料層的所述第一表面上且貫穿所述絕緣材料層； 多個導電柱，位於所述絕緣材料層的所述第一表面上且電性連接至所述半導體晶片； 重佈線路層，位於所述絕緣材料層的所述第一表面且電性連接至所述多個導通孔及所述多個導電柱；以及 多個導電端子，位於所述絕緣材料層的所述第二表面上且電性連接至所述多個導通孔。
  6. 如申請專利範圍第5項所述的封裝結構，更包括： 第一晶種層，覆蓋所述多個導電柱的側壁；以及 第二晶種層，覆蓋所述多個導通孔的側壁，且所述第一晶種層與所述第二晶種層彼此分離。
  7. 如申請專利範圍第5項所述的封裝結構，更包括： 介電層，位於所述絕緣材料層的所述第二表面以及所述半導體晶片的背面上，其中所述介電層具有多個接觸窗開口以暴露出所述多個導通孔，且所述多個導電端子配置於所述接觸窗開口內以電性連接至所述多個導通孔。
  8. 如申請專利範圍第5項所述的封裝結構，其中所述多個導通孔的高度大於所述絕緣材料層的厚度。
  9. 如申請專利範圍第5項所述的封裝結構，更包括： 多個導電球，位於所述重佈線路層上，其中所述多個導電球藉由所述重佈線路層電性連接至所述半導體晶片及所述多個導通孔。
  10. 如申請專利範圍第5項所述的封裝結構，其中所述多個導通孔的上表面與所述多個導電柱的上表面基本上共面，以及所述多個導通孔的所述上表面與所述多個導電柱的所述上表面高於所述絕緣材料層的所述第一表面。
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