TW201925532A - 用鈷填充基板特徵的方法與設備 - Google Patents

用鈷填充基板特徵的方法與設備 Download PDF

Info

Publication number
TW201925532A
TW201925532A TW107133304A TW107133304A TW201925532A TW 201925532 A TW201925532 A TW 201925532A TW 107133304 A TW107133304 A TW 107133304A TW 107133304 A TW107133304 A TW 107133304A TW 201925532 A TW201925532 A TW 201925532A
Authority
TW
Taiwan
Prior art keywords
cobalt
feature
chamber
substrate
layer
Prior art date
Application number
TW107133304A
Other languages
English (en)
Other versions
TWI782094B (zh
Inventor
侯文婷
雷建新
李正周
龍 陶
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201925532A publication Critical patent/TW201925532A/zh
Application granted granted Critical
Publication of TWI782094B publication Critical patent/TWI782094B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04Coating on selected surface areas, e.g. using masks
    • C23C14/046Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24Vacuum evaporation
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • C23C14/5806Thermal treatment
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/045Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02697Forming conducting materials on a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67248Temperature monitoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882Reflowing or applying of pressure to better fill the contact hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883Post-treatment or after-treatment of the conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thermal Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)

Abstract

於此提供了用於用鈷填充特徵的方法和設備。在一些實施例中,一種用於處理基板的方法包括:經由化學氣相沉積(CVD)處理在基板的頂上和設置在基板中的特徵內沉積第一鈷層;及藉由在具有鈷靶材的物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中而至少部分地用鈷或含鈷材料填充特徵。PVD腔室可配置成從設置在PVD腔室中的鈷靶材同步地沉積鈷或含鈷材料在特徵內。

Description

用鈷填充基板特徵的方法與設備
本揭示內容的實施例一般關於半導體製造處理的領域,更具體地,關於用於在半導體基板的特徵中沉積含鈷層的方法。
鈷是用於在10/7 nm節點中的接點和BEOL(線路的後端)互連件填充應用的新材料解決方案的一個候選者。鎢(W)接點包括鈦(Ti)/氮化鈦(TiN)阻擋層,發明人已經觀察到此是有問題的,因為Ti/TiN阻擋層增加了界面電阻並限制了特徵(如,互連件)的向下縮放。另外,發明人已經觀察到當阻擋層/襯裡經由電阻縮放而增加界面電阻及負面影響時,銅(Cu)通孔是有問題的。
此外,發明人已經觀察到藉由化學氣相沉積(CVD)的共形鈷填充通常不期望地導致嵌入到特徵中的空隙,並形成微空隙。即使使用侵蝕性退火處理(如,更高的溫度和更長的退火時間),微孔隙也難以移除並且可能不期望地保留在特徵中。此外,BEOL處理包括有限的退火溫度以保護基板上的介電材料。
因此,發明人提供了一種用鈷填充基板特徵的改進方法。
於此提供了用於用鈷填充特徵的方法和設備。在一些實施例中,一種用於處理基板的方法包括:經由化學氣相沉積(CVD)處理在基板的頂上和設置在基板中的特徵內沉積第一鈷層;及藉由在具有鈷靶材的物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中而至少部分地用鈷填充特徵。在實施例中,在物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中包括從設置在PVD腔室中的鈷靶材同步地沉積鈷在特徵內。
任選地,實施例可包括在沉積第一鈷層之前在特徵內沉積底層;及將第一鈷層直接沉積在底層的頂上。
在一些實施例中,一種用於處理基板的方法包括:在設置在基板中的特徵內沉積底層;經由化學氣相沉積(CVD)處理在基板的頂上並直接在底層的頂上沉積第一鈷層;藉由在物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中而用鈷部分地填充特徵;及經由CVD處理沉積第二鈷層以完全填充特徵。在實施例中,在物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中包括從設置在PVD腔室中的鈷靶材同步地沉積鈷在特徵內。
在一些實施例中,一種用於在基板上膜沉積的設備包括:中央真空傳送腔室;化學氣相沉積(CVD)處理腔室,配置成沉積氮化鈦並耦接到中央真空傳送腔室;化學氣相沉積(CVD)處理腔室,配置成沉積鈷並耦接到中央真空傳送腔室;及物理氣相沉積(PVD)腔室,配置成沉積鈷並耦接到中央真空傳送腔室。在實施例中,PVD腔室配置成在物理氣相沉積(PVD)腔室中執行電漿處理,以將第一鈷層的一部分回流到特徵中,同時從設置在PVD腔室中的鈷靶材同步地沉積鈷在特徵內。
以下描述本揭示內容的其他和進一步的實施例。
本揭示內容的實施例提供了用於處理基板的方法,方法在當處理包括一個或多個金屬填充特徵的基板時提供改進的特徵填充。
發明人已經觀察到,經由根據本揭示內容的金屬填充處理,沉積在特徵內的鈷有利地顯示更大的晶粒、更低的電阻率和更好的粗糙度。此外,與用於接點應用的鎢相比,根據本揭示內容的鈷(Co)填充產生的金屬線電阻低約5至約8倍,並且與用於7nm節點處的互連件應用的銅填充相比,通孔電阻降低>45%。根據本揭示內容,CVD處理與PVD處理相結合,以產生高品質的金屬填充特徵。在實施例中,使用CVD處理將鈷沉積在基板上的至少一個特徵中,並接著移動到PVD腔室,在PVD腔室中執行處理以增加鈷的密度和純度,同時降低鈷的電阻率。在實施例中,PVD處理是在加熱環境中執行的PVD處理,如下面更詳細描述的。可在處理之間有或沒有真空中斷的情況下執行處理。
第1圖是根據本揭示內容的一些實施例的用於處理基板的方法100的流程圖。方法100關於如第2A圖至第2F圖所示的處理基板的階段而描述於下,並且可(例如)在合適的群集工具和處理腔室中執行,諸如關於第3圖而描述於下。可用以執行於此所揭露的方法的示例性處理系統可包括(但不限於)可從加州聖克拉拉市的應用材料公司商購獲得的ENDURA®、CENTURA®或PRODUCER®品牌處理系統的任一者。其他處理腔室(包括可從其他製造商獲得的處理腔室)也可適當地與於此提供的教示結合使用。
方法100通常在提供給處理腔室的處理空間的基板200上執行,例如,關於第3圖而描述於下的基板處理腔室314和基板處理腔室338。在一些實施例中,如第2A圖所示,基板200包括待填充的一個或多個特徵202(第2A圖至第2F圖中所示的一個),形成在基板200的層212中,並朝向基板200的基部204延伸。儘管以下描述是關於一個特徵202而作出,基板200可包括任何數量的特徵202(諸如通孔、溝槽或類似者)。
基板200可為具有在基板200或層212中形成的特徵202的任何合適的基板。例如,基板200可包括矽(Si)、氧化矽(SiO2 )或類似者的一者或多者。在實施例中,基板200可包括在介電層中形成的特徵202。例如,低k材料(如,具有介電常數小於氧化矽或小於約3.9的材料)或類似者。在一些實施例中,層212可設置在第二介電層(未圖示)的頂上,諸如氧化矽、氮化矽、碳化矽或類似者。
另外,基板200可包括額外的材料層,或可具有形成在基板200中或基板200上的一個或多個完成的或部分完成的結構或裝置。在一些實施例中,層216(諸如邏輯裝置或類似者),或需要電連接的裝置的一部分(諸如閘極、接觸墊、鈷墊、導電線或通孔或類似者)可設置在基板200的基部204中並與特徵202對準。例如,特徵202可用導電材料填充,以形成到層216的導電通路。如於此所使用的,層216不需要是在基板的整個表面上延伸的連續結構,但是可為較小的部件,諸如裝置、部分裝置、導電通路或類似者。
在實施例中,基板200可為(例如)摻雜或未摻雜的矽基板、III-V化合物基板、矽鍺(SiGe)基板、磊晶基板、絕緣體上矽(SOI)基板、顯示基板(諸如液晶顯示器(LCD)、電漿顯示器、電致發光(EL)燈顯示器、發光二極體(LED)基板、太陽能電池陣列、太陽能電池板或類似者)。在一些實施例中,基板200可為半導體晶圓。
基板200不限於任何特定尺寸或形狀。基板可為圓形晶圓,其具有200mm直徑、300mm直徑或其他直徑(諸如450mm等)。基板也可為任何多邊形、正方形、矩形、彎曲或其他非圓形工件(諸如在平板顯示器的製造中所使用的多邊形玻璃基板)。
可藉由使用任何合適的蝕刻處理來蝕刻基板200而形成特徵202。在一些實施例中,特徵202由一個或多個側壁214、底表面206和上角落220而界定。在一些實施例中,特徵202可為通孔、溝槽、雙鑲嵌或類似者。在一些實施例中,特徵202可具有高深寬比(如,在約5:1和約15:1之間的深寬比)。如於此所用的,深寬比是特徵的深度與特徵的寬度的比率。在實施例中,特徵202具有小於或等於15nm的寬度。
參考第1圖(以虛線圖示的106)和第2A圖至第2F圖,底層207(以虛線圖示)可任選地沉積在配置成沉積層的處理腔室(如,下面論述的基板處理腔室312、314)中的基板200上及特徵202內。底層207可為沿著特徵的側壁及/或下表面的至少一部分而共形地形成的層,使得在沉積層之前,特徵的實質部分在層沉積之後保持未填充。在一些實施例中,底層207可沿著特徵202的整個側壁214和底表面206形成。底層207可為潤濕層,其設置用以增強設置在底層207之上的金屬層的黏著性。
在一些實施例中,底層207具有約2埃至約100埃,或約2埃至約20埃的厚度。在一些實施例中,底層207是含金屬層。例如,在一些實施例中,底層207可含有或可主要含有鎢(W)、鋁(Al)、鈦(Ti)、鉭(Ta)、其氧化物或氮化物、其矽化物、其衍生物或其組合。在一些實施例中,底層207是金屬或金屬氮化物材料,諸如鈦(Ti)、氮化鈦(TiN)、其合金或其組合。在實施例中,底層207包含氮化鈦(TiN)或由氮化鈦(TiN)組成。在一些實施例中,底層207可藉由化學氣相沉積(CVD)腔室或原子層沉積(ALD)腔室(諸如下面關於第3圖而描述的任何基板處理腔室312、314)而沉積。例如。在一些實施例中,底層207具有約2埃至約100埃,或約2埃至約5埃的厚度,並藉由ALD或CVD沉積。在一些實施例中,底層207是藉由CVD或ALD沉積的具有約2埃至約100埃,或約2埃至約5埃的厚度的氮化鈦(TiN)。
接下來,在102處,將第一鈷層208沉積在第一處理腔室中的基板200上和特徵202中的底層207的頂上。替代地,在未沉積任選的底層207的實施例中,方法可在102處藉由將第一鈷層208沉積在第一處理腔室中的基板200上和特徵202中來開始。第一鈷層208可包含純鈷或由純鈷組成。在實施例中,第一鈷層208包括鈷或鈷合金。例如,有用的鈷合金包括鈷-鎢合金、鈷-磷合金、鈷-錫合金、鈷-硼合金和三元合金(諸如鈷-鎢-磷和鈷-鎢-硼)。然而,第一鈷層208亦可包括其他金屬、金屬合金和摻雜劑,諸如鎳、錫、鈦、鉭、鎢、鉬、鉑、鐵、鈮、鈀、鎳鈷合金、摻雜的鈷和其組合。在實施例中,第一鈷層208的鈷和含鈷材料是實質純鈷,或具有不超過5%雜質的鈷。在實施例中,第一鈷層是具有不超過5%的其他金屬於其中的鈷材料。
在一些實施例中,如第2B圖所示,第一鈷層208沉積在基板200的第一表面222的頂上及在第一表面222中形成的特徵202內。可使用任何合適的(多種)CVD沉積處理而沉積第一鈷層208。適用於沉積第一鈷層208的CVD處理的非限制性實例揭露於2012年2月7日公告的授予Ganguli等人的共同擁有的美國專利第8,110,489號中。在一些實施例中,第一鈷層208是用以填充特徵202的導電鈷材料,例如,以形成導電通路。在一些實施例中,使用合適的鈷前驅物經由CVD處理而沉積第一鈷層208,以形成含鈷材料,諸如在2012年2月7日公告的授予Ganguli等人的共同擁有的美國專利第8,110,489號、2015年6月19日公告的授予Lu等人的共同擁有的美國專利第9,051,641號及2017年6月20日公告的授予Zope等人的美國專利第9,685,371號中描述的彼等。
在一些實施例中,第一鈷層208的厚度是預定的,諸如約20埃至約150埃,或約50埃至約150埃。在實施例中,第一鈷層208的形狀是實質均勻且共形的,如第2A圖至第2E圖中大致所示,然而可發生變化且可在特徵202中形成非共形的間隙形狀。在一些實施例中,第一鈷層208可任選地直接形成在特徵202的整個側壁214和底表面206的頂上。在一些實施例中,第一鈷層208可直接形成在底層207的頂上,底層207設置在特徵202的側壁214和底表面206的頂上。
在104和第2C圖處,藉由在物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層208的一部分回流到特徵202中而至少部分地用鈷填充特徵202。例如,PVD處理回流內層210a和210b的一部分(第2B圖中所示),以在區域215中形成至少部分填充的特徵202。例如,特徵202可藉由在從特徵202的底表面206朝上角落220沉積的物理氣相沉積(PVD)中執行電漿處理而填充約20%至95%、填充約30%至約85%、填充約40-60%,或至少約25%、至少約50%或至少約75%。部分填充的特徵的非限制性實例包括使用根據本揭示內容的PVD處理而從底部到頂部填充至少50%、60%、70%、75%、80%、90%、95%、96%、97%、98%或99%,但不填充100%的一個或多個特徵。在一些實施例中,並且如第2D圖中所示,使用根據本揭示內容的PVD處理,特徵202可從特徵202的底表面206到上角落220及/或在上角落220上方完全的用鈷填充。
在一些實施例中,處理在第二處理腔室332或338(第3圖)中進行,第二處理腔室332或338可為配置成以於此揭露的方式沉積鈷和含鈷材料的任何PVD腔室。適合於根據於此的教示進行修改並適合於執行上述處理的一個示例性PVD處理系統是可從加州聖克拉拉市的應用材料公司商購獲得的ENDURA® CirrusTM HTX PVD系統。在實施例中,合適的PVD腔室包括2014年8月5日公告的授予Ritchie等人的美國專利第8,795,487號和2002年10月10日公告的Rong Tao等人的美國專利揭示案第2002/0144889號中描述的彼等。
為了執行沉積處理以回流第一鈷層208,將RF和DC功率提供給設置在PVD處理腔室內的鈷或含鈷靶材。可以從約13至約60MHz,或27至約40MHz,或約40MHz的頻率向靶材提供約0.25至約6千瓦的RF能量。在實施例中,向鈷或含鈷靶材提供約0.5至5.0千瓦的DC功率。
另外,PVD處理腔室保持在約4mTorr至約150mTorr,或約10mTorr至約150mTorr的壓力下。可以約5至約30MHz,或約10至約15MHz,或約13.56MHz的頻率向基板支撐件提供約0.1W至310W(例如至少約300W)的RF偏壓功率。
PVD處理包括合適的氣體,以促進回流處理。氣體源可提供合適的氣體物種,諸如惰性氣體(諸如氬氣、氪氣、氖氣或類似者)、氫氣(H2 )或其組合。在一些實施例中,電漿處理包括由氫氣或惰性氣體形成的電漿。在一些實施例中,僅提供H2 氣體。
仍然參考回流第一鈷層208的處理,電漿處理腔室可包括高溫加熱器,適於將基板加熱至約350℃至約500℃或約350℃至約450℃的溫度。
在一些實施例中,靶材原子撞擊基板。以0.1-10埃/秒的沉積速率適用於根據本揭示內容的用途。因此,物理氣相沉積腔室可配置為以0.1-10埃/秒應用鈷沉積速率。
在實施例中,高密度PVD鈷應用減少雜質,並促進鈷晶粒生長,同時能獲得從特徵202的底部向上的無空隙鈷間隙填充。如上面關於第2D圖所解釋的,可執行PVD處理,使得特徵從底部到頂部完全或基本上完全填充。替代地,參考108和第2E圖,可執行上面論述的PVD處理,以僅部分地填充特徵,且可在CVD處理腔室(諸如CVD處理腔室334或336(第3圖))中在基板200上和特徵202內沉積另外的鈷金屬材料209,以完全填充特徵。在一些實施例中,如第2E圖所示,鈷金屬材料209沉積在特徵202的頂上及/或特徵202內。鈷金屬材料209可使用任何合適的(多種)CVD沉積處理而沉積,諸如上面關於102而論述的彼等。合適的鈷材料包括上面關於第一鈷層208而描述的鈷材料。在一些實施例中,鈷金屬材料209是用以填充特徵202的導電鈷材料,例如,以形成導電通路。
在一些實施例中,108處的CVD應用從底部到頂部完全填充特徵。在實施例中,如第2E圖所示,108處的CVD應用過度填充一個或多個特徵。在一些實施例中,如第2E圖所示,由於在208處執行CVD沉積,可能在鈷金屬材料209內形成(多個)空隙211和微空隙213。因此,在110處,可退火基板和特徵以促進其中的均勻性,移除(多個)空隙211和微空隙213。任選的退火處理包括以在約50℃至約1400℃之間(如,在約50℃和500℃之間;在約100℃和約300℃之間;在約300℃和500℃之間)對特徵施加溫度。在熱退火處理期間,包括至少含氫氣體及/或惰性氣體(如,氬氣500℃)的氣體混合物被供應到腔室中。可使用在退火處理之前用氣體填充腔室的靜態處理或在退火處理期間將氣體混合物連續地流過腔室的連續流動處理任一者來將氣體混合物供應到退火腔室。
在實施例中,熱退火處理110可在與金屬沉積處理相同的處理腔室中原位執行。若CVD腔室(諸如腔室336(第3圖))具有將基板加熱到退火處理的溫度以及根據需要提供處理氣體的能力,則可在同一腔室中執行金屬層沉積和退火。替代地,熱退火處理可在單獨的處理腔室中執行。
參考第2F圖,圖示的特徵202填充有基本上沒有空隙和微空隙的鈷。在實施例中,特徵202沒有空隙和微空隙。例如,可使用本領域已知的化學機械平坦化(CMP)技術進一步處理基板200,以平坦化晶圓401的表面(如,以移除設置在基板的頂上和特徵之上方的過量鈷覆蓋層)。
在一些示例性實施例中,一種用於處理基板以用鈷填充特徵的方法包括經由化學氣相沉積(CVD)處理在基板的頂上和設置在基板中的特徵內將第一鈷層沉積到約20埃至約150埃的厚度。接著,藉由在物理氣相沉積(PVD)腔室中執行電漿處理以將第一鈷層的一部分回流到特徵中而用鈷至少部分地填充特徵。電漿處理可進一步為特徵增加約20埃至約150埃或約60埃的厚度。可經由第二化學氣相沉積(CVD)處理將額外的鈷沉積約20埃至約150埃的厚度到特徵中,其中第二CVD處理完全填充特徵。接著可對填充的特徵進行退火。
於此描述的方法可在單獨的處理腔室中執行,處理腔室可以獨立配置的方式而提供或作為一個或多個群集工具(例如,下面關於第3圖而描述的整合工具300(亦即,群集工具))的一部分而提供。在一些實施例中,上述處理基板的方法100可在作為獨立腔室或作為群集工具的一部分而提供的單獨處理腔室中執行。在實施例中,群集工具被配置用於執行如於此所述的用於處理基板的方法,包括:經由化學氣相沉積(CVD)處理沉積第一鈷層;藉由在物理氣相沉積(PVD)腔室中執行電漿處理而用鈷至少部分地填充特徵;任選地經由第二化學氣相沉積(CVD)處理沉積額外的鈷;及任選地對填充的特徵進行退火。在一些實施例中,群集工具可被配置為僅用於沉積,且退火可在單獨的腔室中執行。在一些實施例中,退火可在PVD或CVD處理腔室的任一個中進行。
整合工具300的實例包括可從加州聖克拉拉市的應用材料公司獲得的CENTURA®和ENDURA®整合工具。然而,於此描述的方法可使用具有與其耦合的合適處理腔室的其他群集工具來實施,或在其他合適的處理腔室中實施。例如,在一些實施例中,上面論述的本發明的方法可有利地在整合工具中執行,使得在處理時存在有限的真空中斷或沒有真空中斷。
整合工具300可包括兩個負載鎖定腔室306A、306B,用於將基板傳送到整合工具300中和從整合工具300中傳出。通常,由於整合工具300處於真空下,負載鎖定腔室306A、306B可對引入到整合工具300中的基板「抽真空(pump down)」。第一機器人310可在負載鎖定腔室306A、306B和耦接到第一中央傳送腔室350的第一組一個或多個基板處理腔室312、314、316、318(圖示為四個)之間傳送基板。每個基板處理腔室312、314、316、318可經配備以執行多個基板處理操作。在一些實施例中,第一組一個或多個基板處理腔室312、314、316、318可包括PVD、ALD、CVD、蝕刻或脫氣腔室的任何組合。例如,在一些實施例中,處理腔室312和314包括配置成沉積諸如底層207的氮化鈦的CVD及/或ALD處理腔室。
第一機器人310亦可將基板傳送到兩個中間傳送腔室322、324或自兩個中間傳送腔室322、324傳送。中間傳送腔室322、324可用以維持超高真空條件,同時允許基板在整合工具300內傳送。第二機器人330可在中間傳送腔室322、324和耦接到第二中央傳送腔室355的第二組一個或多個基板處理腔室332、334、335、336、338之間傳送基板。基板處理腔室332、334、335、336、338可經配備以執行各種基板處理操作,包括上述方法100以及物理氣相沉積處理(PVD)、化學氣相沉積(CVD)、蝕刻、定向和其他基板處理。在一些實施例中,第二組一個或多個基板處理腔室332、334、335、336、338可包括PVD、ALD、CVD、蝕刻或脫氣腔室的任何組合。例如,在一些實施例中,基板處理腔室332、334、335、336、338包括三個CVD腔室334、335和336,以及兩個PVD腔室332和338。,若對於由整合工具300執行的特定處理不是必需的,則基板處理腔室312、314、316、318、332、334、335、336、338的任一者可從整合工具300移除。
本揭示內容的實施例包括用於在基板上沉積膜的設備,包含:中央真空傳送腔室(諸如腔室350或355);化學氣相沉積(CVD)及/或原子層沉積(ALD)處理腔室(諸如腔室312及/或314),配置成沉積氮化鈦並耦接到中央真空傳送腔室;化學氣相沉積(CVD)處理腔室(諸如腔室334及/或335),配置成沉積如於此所述的鈷和含鈷材料,耦接到中央真空傳送腔室;物理氣相沉積(PVD)腔室(諸如腔室332和338),配置成回流及/或沉積如於此所述的鈷和含鈷材料並耦接到中央真空傳送腔室350及/或355。
可使用其他半導體基板處理系統來實施本揭示內容,其中在不背離本揭示內容的精神的情況下,藉由利用於此揭露的教示,熟悉本領域者可調整處理參數以實現可接受的特性。儘管前述內容涉及本揭示內容的實施例,但是可在不背離本揭示內容的基本範疇的情況下設計本揭示內容的其他和進一步的實施例。
100‧‧‧方法
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
110‧‧‧熱退火處理
200‧‧‧基板
202‧‧‧特徵
204‧‧‧基部
206‧‧‧底表面
207‧‧‧底層
208‧‧‧第一鈷層
209‧‧‧鈷金屬材料
210a‧‧‧內層
210b‧‧‧內層
211‧‧‧空隙
212‧‧‧層
213‧‧‧微空隙
214‧‧‧側壁
215‧‧‧區域
216‧‧‧層
220‧‧‧上角落
222‧‧‧第一表面
300‧‧‧整合工具
306A‧‧‧負載鎖定腔室
306B‧‧‧負載鎖定腔室
310‧‧‧第一機器人
312‧‧‧基板處理腔室
314‧‧‧基板處理腔室
316‧‧‧基板處理腔室
318‧‧‧基板處理腔室
322‧‧‧中間傳送腔室
324‧‧‧中間傳送腔室
330‧‧‧第二機器人
332‧‧‧基板處理腔室
334‧‧‧基板處理腔室
335‧‧‧基板處理腔室
336‧‧‧基板處理腔室
338‧‧‧基板處理腔室
350‧‧‧中央真空傳送室
355‧‧‧中央真空傳送室
401‧‧‧晶圓
藉由參考附隨的圖式中描繪的本揭示內容的說明性實施例,可理解以上簡要概述並在下面更詳細論述的本揭示內容的實施例。然而,附隨的圖式僅圖示了本揭示內容的典型實施例,且因此不應視為對範疇的限制,因為本揭示內容可允許其他同等有效的實施例。
第1圖描繪了根據本揭示內容的實施例的用於在半導體裝置的特徵中沉積鈷金屬的方法的流程圖。
第2A圖至第2F圖分別描繪了根據本揭示內容的第1圖的實施例的在半導體裝置的特徵中沉積金屬的製造階段。
第3圖描繪了根據本揭示內容的一些實施例的適合於執行用於處理基板的方法的群集工具。
為促進理解,在可能的情況下,使用相同的元件符號來表示圖式中共有的相同元件。圖式未按比例繪製,且為了清楚起見可簡化。一個實施例的元件和特徵可有利地併入其他實施例中而無需進一步敘述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無

Claims (20)

  1. 一種用於處理一基板的方法,包含以下步驟: 經由一化學氣相沉積(CVD)處理在一基板的頂上和設置在該基板中的一特徵內沉積一第一鈷層;及藉由在具有一鈷靶材的一物理氣相沉積(PVD)腔室中執行一電漿處理以將該第一鈷層的一部分回流到該特徵中而至少部分地用鈷填充該特徵。
  2. 如請求項1所述之方法,其中該電漿處理包括在該特徵內從設置在該PVD腔室中的一鈷靶材沉積鈷。
  3. 如請求項1或2所述之方法,進一步包含以下步驟: 在沉積該第一鈷層之前在該特徵內沉積一底層,並將該第一鈷層直接沉積在該底層的頂上。
  4. 如請求項3所述之方法,其中該底層包含氮化鈦。
  5. 如請求項4所述之方法,其中該氮化鈦具有約2埃至約20埃的一厚度。
  6. 如請求項1或2所述之方法,其中該電漿處理在約350℃至約500℃的一溫度下執行。
  7. 如請求項1或2所述之方法,其中該電漿處理包含由氫氣或一惰性氣體形成的一電漿。
  8. 如請求項1或2所述之方法,其中該電漿處理包含由氬、氪或氖中的一者或多者形成的一電漿。
  9. 如請求項1或2所述之方法,其中在該電漿處理期間完全填充該特徵。
  10. 如請求項9所述之方法,進一步包含以下步驟: 藉由對該特徵施加約50℃和約1400℃之間的一溫度進行退火。
  11. 如請求項1或2所述之方法,其中該特徵僅在該電漿處理期間被部分填充,且進一步包含以下步驟: 隨後經由一CVD處理沉積一第二鈷層以完全填充該特徵。
  12. 如請求項11所述之方法,進一步包含以下步驟: 藉由對該特徵施加約50℃和約1400℃之間的一溫度進行退火。
  13. 如請求項1或2所述之方法,其中該特徵具有小於或等於15nm的一寬度。
  14. 如請求項1或2所述之方法,其中該第一鈷層沉積至約20埃至約150埃的一厚度。
  15. 一種用於處理一基板的方法,包含以下步驟: 在設置在一基板中的一特徵內沉積一底層;經由一化學氣相沉積(CVD)處理在該基板的頂上並直接在該底層的頂上沉積一第一鈷層;藉由在一物理氣相沉積(PVD)腔室中執行一電漿處理以將該第一鈷層的一部分回流到該特徵中而用鈷部分地填充該特徵,同時從設置在該PVD腔室中的一鈷靶材同步地沉積鈷在該特徵內;及隨後經由一CVD處理沉積一第二鈷層以完全填充該特徵。
  16. 如請求項15所述之方法,進一步包含以下步驟: 藉由對該特徵施加約50℃和約1400℃之間的一溫度進行退火。
  17. 一種用於在一基板上膜沉積的設備,包含: 一中央真空傳送腔室;一化學氣相沉積(CVD)處理腔室及/或原子層沉積(ALD)處理腔室,配置成沉積氮化鈦並耦接到該中央真空傳送腔室;一化學氣相沉積(CVD)處理腔室,配置成沉積鈷並耦接到該中央真空傳送腔室;及一物理氣相沉積(PVD)腔室,配置成沉積鈷並耦接到該中央真空傳送腔室。
  18. 如請求項17所述之設備,其中該物理氣相沉積腔室配置為將鈷加熱至約350℃至約500℃的一溫度。
  19. 如請求項17或18所述之設備,其中該物理氣相沉積腔室被配置為以0.1-10埃/秒而施加鈷沉積速率。
  20. 如請求項17或18所述之設備,其中該物理氣相沉積腔室配置成以約20埃至約150埃的一厚度而沉積鈷。
TW107133304A 2017-09-21 2018-09-21 用鈷填充基板特徵的方法與設備 TWI782094B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/711,169 2017-09-21
US15/711,169 US10304732B2 (en) 2017-09-21 2017-09-21 Methods and apparatus for filling substrate features with cobalt

Publications (2)

Publication Number Publication Date
TW201925532A true TW201925532A (zh) 2019-07-01
TWI782094B TWI782094B (zh) 2022-11-01

Family

ID=65720533

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107133304A TWI782094B (zh) 2017-09-21 2018-09-21 用鈷填充基板特徵的方法與設備

Country Status (6)

Country Link
US (1) US10304732B2 (zh)
JP (1) JP7309697B2 (zh)
KR (1) KR102572732B1 (zh)
CN (1) CN111133558B (zh)
TW (1) TWI782094B (zh)
WO (1) WO2019060296A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410891B2 (en) 2019-08-26 2022-08-09 International Business Machines Corporation Anomaly detection and remedial recommendation
US11164815B2 (en) 2019-09-28 2021-11-02 International Business Machines Corporation Bottom barrier free interconnects without voids
US11776980B2 (en) * 2020-03-13 2023-10-03 Applied Materials, Inc. Methods for reflector film growth
US11527437B2 (en) 2020-09-15 2022-12-13 Applied Materials, Inc. Methods and apparatus for intermixing layer for enhanced metal reflow

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015719A (ko) * 1994-10-12 1996-05-22 이온 충돌을 이용하여 반도체 기판상에 평탄한 층을 형성하기 위한 방법 및 장치
US20030029715A1 (en) * 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US9051641B2 (en) * 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
WO2003030224A2 (en) * 2001-07-25 2003-04-10 Applied Materials, Inc. Barrier formation using novel sputter-deposition method
US20070184652A1 (en) 2006-02-07 2007-08-09 Texas Instruments, Incorporated Method for preparing a metal feature surface prior to electroless metal deposition
TW200746268A (en) * 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
JP2008141050A (ja) * 2006-12-04 2008-06-19 Ulvac Japan Ltd 半導体装置の製造方法及び半導体装置の製造装置
US20080132050A1 (en) * 2006-12-05 2008-06-05 Lavoie Adrien R Deposition process for graded cobalt barrier layers
KR20090103058A (ko) 2008-03-27 2009-10-01 주식회사 하이닉스반도체 반도체 소자 및 이의 제조 방법
US20090246952A1 (en) 2008-03-28 2009-10-01 Tokyo Electron Limited Method of forming a cobalt metal nitride barrier film
US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US8795487B2 (en) 2010-03-31 2014-08-05 Applied Materials, Inc. Physical vapor deposition chamber with rotating magnet assembly and centrally fed RF power
US8524600B2 (en) * 2011-03-31 2013-09-03 Applied Materials, Inc. Post deposition treatments for CVD cobalt films
US9499901B2 (en) 2012-01-27 2016-11-22 Applied Materials, Inc. High density TiN RF/DC PVD deposition with stress tuning
US9330939B2 (en) * 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US9218980B2 (en) * 2013-09-13 2015-12-22 Applied Materials, Inc. Surface treatment to improve CCTBA based CVD co nucleation on dielectric substrate
CN110066984B (zh) * 2013-09-27 2021-06-08 应用材料公司 实现无缝钴间隙填充的方法
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9741577B2 (en) * 2015-12-02 2017-08-22 International Business Machines Corporation Metal reflow for middle of line contacts
US10128151B2 (en) * 2016-12-16 2018-11-13 Globalfoundries Inc. Devices and methods of cobalt fill metallization
TWI809712B (zh) * 2017-01-24 2023-07-21 美商應用材料股份有限公司 用於在基板上形成鈷層的方法

Also Published As

Publication number Publication date
US10304732B2 (en) 2019-05-28
KR102572732B1 (ko) 2023-08-29
TWI782094B (zh) 2022-11-01
KR20200045563A (ko) 2020-05-04
JP2020534702A (ja) 2020-11-26
CN111133558A (zh) 2020-05-08
WO2019060296A1 (en) 2019-03-28
JP7309697B2 (ja) 2023-07-18
CN111133558B (zh) 2024-04-02
US20190088540A1 (en) 2019-03-21

Similar Documents

Publication Publication Date Title
US9947578B2 (en) Methods for forming low-resistance contacts through integrated process flow systems
TWI782094B (zh) 用鈷填充基板特徵的方法與設備
TWI621161B (zh) 用於內連線的釕金屬特徵部填補
US6554914B1 (en) Passivation of copper in dual damascene metalization
CN106887380B (zh) 实现无缝钴间隙填充的方法
US6566246B1 (en) Deposition of conformal copper seed layers by control of barrier layer morphology
KR102345466B1 (ko) Mol(middle of the line) 애플리케이션들을 위한 유기 금속 텅스텐을 형성하기 위한 방법들
US20150203961A1 (en) Methods for forming a cobalt-ruthenium liner layer for interconnect structures
US7704886B2 (en) Multi-step Cu seed layer formation for improving sidewall coverage
US9048296B2 (en) Method to fabricate copper wiring structures and structures formed thereby
US20190189508A1 (en) Metallic interconnect structures with wrap around capping layers
WO2011114989A1 (ja) 薄膜の形成方法
TW202141585A (zh) 用於在介電層頂上由下而上間隙填充的選擇性沉積鎢的方法
JP4169950B2 (ja) 半導体装置の製造方法
US20190385908A1 (en) Treatment And Doping Of Barrier Layers
TWI515854B (zh) 用以分離合金元素並減少銅合金層之殘留電阻率之方法
CN116153861B (zh) 一种半导体结构及制备方法
KR20180034265A (ko) 니켈 배선의 제조 방법
WO2016088440A1 (ja) Cu配線の形成方法および半導体装置の製造方法
US20150130064A1 (en) Methods of manufacturing semiconductor devices and a semiconductor structure
TW202341354A (zh) 使用雙官能自組裝單層的金屬表面的選擇性阻擋
US20130146468A1 (en) Chemical vapor deposition (cvd) of ruthenium films and applications for same
JP2024503626A (ja) 低温グラフェンの成長
TW452959B (en) A novel hole-filling technique using CVD aluminium and PVD aluminum integration
JP2001015517A (ja) 半導体装置及びその製造方法