TW201922677A - 具有與金屬或金屬混合箔連接之厚膜膠媒介基板的邏輯電源模組 - Google Patents

具有與金屬或金屬混合箔連接之厚膜膠媒介基板的邏輯電源模組 Download PDF

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TW201922677A
TW201922677A TW107121190A TW107121190A TW201922677A TW 201922677 A TW201922677 A TW 201922677A TW 107121190 A TW107121190 A TW 107121190A TW 107121190 A TW107121190 A TW 107121190A TW 201922677 A TW201922677 A TW 201922677A
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Taiwan
Prior art keywords
thick film
ceramic substrate
logic
power module
metal foil
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TW107121190A
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English (en)
Inventor
安東 米里奇
凱 郝詩特
米理安 諾爾
克里斯堤安 揚
彼得 戴崔奇
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德商賀利氏德國有限責任兩合公司
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Publication of TW201922677A publication Critical patent/TW201922677A/zh

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Abstract

本發明描述一種邏輯電源模組，其包含至少一個邏輯組件、至少一個電源組件及基板，其中邏輯元件及該電源組件設置在該基板上之各別區域中。該基板上之該邏輯組件係藉由厚印刷銅提供；且該電源組件係藉由含金屬厚膜層提供，且在該含金屬厚膜層上設置金屬箔。

Description

具有與金屬或金屬混合箔連接之厚膜膠媒介基板的邏輯電源模組
本發明係關於一種邏輯電源模組，其包含至少一個邏輯組件、至少一個電源組件及基板，其中邏輯組件及電源組件設置在基板上之各別區域中。
此外，本發明係關於一種製備該邏輯電源模組之方法及該邏輯電源模組之用途。
邏輯電源模組可以完全獨立的部件來建造，電源模組通常在DCB-Al2 O3 基板上(直接銅連接)、在DCB-AlN基板上、在DCB-Si3 N4 基板上或在IMS基板(絕緣金屬基板)上製得，且邏輯模組係在環氧PCB上或藉由使用厚膜技術製造。藉由使用此厚膜技術，可以製備諸多可能的不同厚度之邏輯模組。在一些情況下，可以在同一基板上製備厚度在約300 μm範圍內之厚邏輯模組及厚度在約10 μm範圍內之稍薄一些的邏輯模組。此外，厚膜技術允許印刷導電及不導電多層及彼此之頂部，其中導電層可以藉由所謂的通孔連接。
在替代方案中，已知組合的電子邏輯及電源模組，其中邏輯組件及電源組件各自在厚膜基板上建構。此等組合的電子及電源模組描述於例如EP 0 751 570A中。
此等邏輯及電源模組之電源組件通常藉由所謂的DCB技術製備。直接銅連接(Direct copper bonded，DCB)基板因為其極佳的熱導率而常用於電源模組中。其由瓷磚(通常為氧化鋁)構成，其中一片銅藉由高溫氧化製程連接至一側或兩側(將銅及基板在含有約30 ppm氧氣之氮氣氛圍中加熱至精心控制的溫度；在此等條件下，形成銅-氧共晶，其成功地連接至銅及氧化物，被用作基板)。頂部銅層可以在燒製之前預先形成或使用印刷電路板技術進行化學蝕刻以形成電路，而底部銅層通常保持平坦。藉由將底部銅層焊接至均熱片(heat spreader)而使基板附接至均熱片。
在DCB技術中，用共晶熔體將銅箔連接至陶瓷基板上。此製程技術存在一些缺點，諸如大量廢品，在陶瓷基板與銅箔之間產生空腔，且耐溫度變化性相對較低(這導致在一些熱循環之後分層)。例如在DE 10 2010 025 313 A中描述了相應的技術，其中將金屬與此金屬之氧化物的混合物施加在陶瓷基板上，隨後經由DCB製程對其進行連接。另一方面，亦已知基於厚印刷技術製備之基板。此等基板具有生產成本高及由燒結層之多孔性引起的低電子電導率及熱導率的缺點。作為此問題之解決方案，未公開的先前專利申請案PCT/EP2016/082161提出一種金屬陶瓷基板，其藉由以下製備：將厚膜膠施加至陶瓷基板上；將金屬箔施加至陶瓷基板之厚膜層上；及經由厚膜層連接金屬箔與陶瓷基板。此金屬陶瓷基板展現改進的穩定性(亦即，分層風險降低)、高傳導性及高耐久性，且生產成本下降。然而，未公開的先前專利申請案PCT/EP2016/082161未揭示基礎技術在邏輯電源模組領域中之使用。
本發明現在提供PCT/EP2016/082161之基礎技術的進一步應用，且提供在一個基板上包含邏輯組件及電源組件的邏輯電源模組，其中電源組件藉由經過修改的如在未公開的先前專利申請案PCT/EP2016/082161中所述之DCB技術製備。
因此，本發明係關於一種邏輯電源模組，其包含至少一個邏輯組件、至少一個電源組件及基板，其中邏輯組件及電源組件設置在基板上之各別區域中。
根據本發明之邏輯電源模組之特徵在於： (a) 基板上之邏輯組件藉由厚印刷金屬提供；且 (b) 電源組件藉由含金屬厚膜層提供，且在該含金屬厚膜層上設置金屬箔。
在本發明中，邏輯組件係指邏輯電源模組之部件，其尤其包含用於數位及類比信號之導體、晶粒黏著結構(上面例如設置晶片)及被動電子組件，諸如電阻器、電容器等。
在本發明中，厚印刷金屬尤其意謂厚印刷銅及厚印刷銀，其中厚印刷銅較佳。
相對於通常已知的邏輯電源模組，根據本發明之邏輯電源模組之當前佈置具有若干優點，如以下所概述：
與通常已知的邏輯電源模組相比，基於改進的DCB技術，可以較不費力地在同一基板上實現邏輯組件與電源組件之組合，在該改進的DCB技術中，電源組件由含金屬厚膜層提供且在該含金屬厚膜層上設置金屬箔。而且，與厚印刷銅技術相比，可能實現更厚的金屬化物，由此達成改進的散熱(散熱片)及較高的載流能力(載流量)。使用根據本發明之邏輯電源模組的多層構造，電源組件與邏輯組件一樣以最小電感值安裝部件變得可能。藉由使用低電感功率路徑，可能可以切換較高的電壓，且可以較高的總體效能使用整個系統。低電感邏輯路徑能夠改進開關頻率，邏輯元件能夠偵測故障且較早地對故障作出反應。在例如SiC及GaN之具有寬帶隙之半導體的情況下，這尤其較佳，因為此等半導體切換較快。多層構造由導電路徑及絕緣體組成且可設置於基板表面上，該基板表面設置有銅箔或無覆蓋。
此外，本發明允許在一個方法步驟中(亦即同時)印刷邏輯組件之厚金屬層及電源組件之含金屬厚膜層，這有利於根據本發明之邏輯電源模組之製造。
此外，與普通DCB基板相比，未公開的先前專利申請案PCT/EP2016/082161中所述之技術允許較低的偏轉，對應使用較薄的基板或使用較厚的銅層，這降低了熱阻且增加了熱容量。
根據本發明之邏輯電源模組如圖1所示。在此圖中，附圖標記1代表邏輯電源模組，附圖標記2代表邏輯組件，附圖標記3代表電源組件，附圖標記4代表基板，在該基板上，邏輯組件之區域由附圖標記4a表示，而電源組件之區域由附圖標記4b表示。
如上文已概述，根據本發明之邏輯電源模組1在同一陶瓷基板上包含一個邏輯組件2及至少一個電源組件3。下面將更詳細地描述兩個部件：邏輯組件2及電源組件3。
邏輯組件 根據本發明之邏輯電源模組之邏輯組件2可藉由導電膠，較佳藉由銅膠製備，使其沈積、乾燥及燒結，較佳藉由燒製。燒製製程可以在保護性氛圍中進行，諸如氮氣氛圍或氬氣氛圍。
藉由沈積製程形成邏輯組件。
在本發明之意義上，可以藉由單個印刷步驟或藉由若干個印刷步驟在陶瓷基板上提供厚印刷金屬膠，其中在若干個印刷步驟的情況下，可以使用相同的厚膜金屬膠或不同的厚印刷金屬膠。而且，可以在厚印刷金屬膠層之間佈置介電層。在導電及介電堆疊層之情況下，導電層可以藉由所謂的通孔彼此電連接。
在本發明之一個特定實施例中，在一個或若干個印刷步驟中使用單一厚膜金屬膠。
在另一實施例中，可以藉由不同的厚印刷金屬膠提供邏輯組件，不同的厚印刷金屬膠由單獨的印刷步驟提供。
在此情況下，可以區分基層組合物及頂層組合物中之導電金屬膠，較佳銅膠。基層組合物通常直接施加至基板上，且提供與陶瓷基板之最佳黏著。頂層組合物通常施加於燒製基層組合物層或另一燒製頂層組合物層上。為了在基板上之邏輯區域中建造金屬導體、較佳銅導體至所要厚度，可以施加多層頂層組合物。
因此，可以首先將基層導電金屬膠組合物、較佳銅膠組合物沈積在陶瓷基板上，乾燥並燒結，較佳燒製。頂層導電金屬膠組合物、較佳銅膠組合物之後續層可以沈積在燒製的基層或預先燒製的頂層上，以使金屬導體堆積至所要厚度。
亦有可能將基層導電金屬膠、較佳導電銅膠沈積在陶瓷基板上，乾燥，且在其上印刷金屬膠、較佳銅膠之後續層，而不預先燒結、較佳燒製底層膠層。在印刷後續層之前，可以乾燥每層。在最終步驟中，可以燒結、較佳燒製該等層，以形成呈所要厚度之金屬導體。
導電金屬膠組合物，較佳銅膠組合物，可以經由網版印刷、模板印刷、直接沈積或熟習此項技術者已知的任何其他方法施加至陶瓷基板上。較佳的施加方法為網版印刷。網版印刷製程通常採用包含預定電路之具有乳劑層的不鏽鋼網篩。
印刷導電金屬膠組合物，較佳銅膠組合物，通常在中等溫度下乾燥，以防止金屬粒子氧化。通常，乾燥溫度為約100℃至130℃，較佳125℃，且乾燥時間為約5至15分鐘。
導電金屬膠組合物、較佳銅膠組合物及陶瓷基板之燒製通常在爐子中在約850℃至1050℃、較佳925℃至950℃之峰值溫度下在低氧氣氛圍，諸如O2 含量通常低於10至20 ppm、較佳約1至3 ppm O2 之氮氣氛圍中進行。通常，在峰值燒製溫度下之停留時間為約5至10分鐘，較佳8至10分鐘。
在一個實施例中，可以使用導電金屬膠、較佳銅膠，藉由包含以下之方法在陶瓷基板上製備邏輯組件： (i) 在陶瓷基板上沈積第一層基層導電膠、較佳銅膠； (ii) 視情況在約100℃至約125℃之溫度下乾燥已沈積基層導電膠、較佳銅膠之陶瓷基板約5至約10分鐘； (iii) 視情況使所沈積之基層導電膠、較佳銅膠及陶瓷基板在包含約1至約20 ppm氧氣之氮氣氛圍中經受約900℃至約1000℃之溫度； (iv) 視情況在陶瓷基板上沈積第二層導電膠、較佳銅膠作為頂層； (v) 視情況在約100℃至約125℃之溫度下乾燥已沈積頂層導電膠、較佳銅膠之陶瓷基板約5至約10分鐘；及 (vi) 使沈積層及陶瓷基板在包含約1至約20 ppm氧氣之氮氣氛圍中經受約900℃至約1000℃之溫度。
如上文所定義之方法可以進一步包含一或多個沈積其他導電層、尤其是銅層及/或介電層的步驟。
藉由重複步驟(iv)至(vi)，邏輯組件中之金屬導體可以建造至所要厚度。對導電金屬膠之每層而言，金屬導體之燒製厚度為約10至75 µm，較佳15至50 µm。舉例而言，步驟(iv)至(vi)可以重複1至10次。邏輯組件中燒製厚度為約300 µm之金屬導體可以由一層基層膠及多達十層頂層膠達成。
用於邏輯組件之導電膠組合物可包含玻璃料，其中基層導電膠組合物可包含比頂層導電膠組合物更高的量的玻璃料。在一較佳實施例中，基層導電膠包含約1重量%至約5重量%之玻璃料。在另一較佳實施例中，頂層導電膠包含較佳0至20重量%、更佳0至5重量%之玻璃料。
用於邏輯組件之導電膠組合物亦可不包含玻璃料。
用於邏輯組件之導電膠組合物通常包含助黏劑，其中基層可包含比頂層導電膠組合物更高的量的助黏劑。在一較佳實施例中，基層導電膠包含約1重量%至約5重量%之助黏劑，較佳約2重量%至約4重量%、更佳約3重量%之助黏劑。在一較佳實施例中，頂層導電膠包含約0.25重量%至約1.25重量%之助黏劑，較佳約0.75重量%至約1.25重量%、更佳約1重量%之助黏劑。
用於邏輯組件之厚膜膠可包含銅作為金屬且視情況包含Bi2 O3 。
導電膠包含較佳40重量%至92重量%銅，更佳40重量%至小於92重量%銅，更佳70重量%至小於92重量%銅，最佳75重量%至90重量%銅，各自以導電膠之總重量計。
導電膠包含較佳0至50重量% Bi2 O3 ，更佳1重量%至20重量% Bi2 O3 ，最佳2重量%至15重量% Bi2 O3 ，各自以導電膠之總重量計。
導電膠中所用之銅粒子所具有的中值直徑(d50 )較佳在0.1至20 µm之間、更佳在1與10 µm之間、最佳在2與7 µm之間。
視情況用於導電膠中之Bi2 O3 粒子所具有的中值直徑(d50 )較佳小於100 µm、更佳小於20 µm、最佳小於10 µm。
在本發明之另一實施例中，導電膠可包含銅及如上文已提及之玻璃組分。
在同時使用玻璃組分之情況下，導電膠中之銅之量可以如上文所定義，亦即，銅量較佳為40重量%至92重量%、更佳為40重量%至小於92重量%，銅量更佳為70重量%至小於92重量%，銅量最佳為75重量%至90重量%，各自以導電膠之總重量計。
在導電膠中使用玻璃組分之情況下，導電膠包含較佳0至20重量%、更佳0至5重量%之玻璃組分，各自以厚膜膠之總重量計。
在厚膜膠中使用玻璃組分之情況下，銅粒子可以具有與上文所提及相同的中值直徑(d50 )，亦即較佳在0.1至20 µm之間，更佳在1與10 µm之間，最佳在2與7 µm之間。
在導電膠中使用玻璃組分之情況下，玻璃組分粒子可以具有的中值直徑(d50 )為小於100 µm，更佳小於20 µm，最佳小於10 µm。
導電膠，較佳在銅之基礎上，可包含除玻璃組分及Bi2 O3 以外的其他組分，該等其他組分選自由PbO、TeO2 、Bi2 O3 、ZnO、B2 O3 、Al2 O3 、TiO2 、CaO、K2 O、MgO、Na2 O、ZrO2 、Cu2 O、CuO及Li2 O組成之群。根據另一實施例，根據特定的輪廓在惰性(例如氮氣)氛圍中燒製總成。若在太富氧的環境中燒製金屬導電膠、較佳銅導電膠，則金屬組分可能開始氧化。然而，只需要最低含量之氧氣就能幫助燃盡膠中之有機黏合劑。因此，必須使氧氣含量最佳化。根據本發明之一個較佳實施例，在爐氛圍中存在約1至20 ppm之氧氣。更佳地，在爐氛圍中存在約1至10 ppm之氧氣，且最佳地，存在約1至3 ppm之氧氣。
較佳的導電膠組合物可購自Heraeus(厚膜導體系統，例如C7403及C7404系列)。
電源組件 藉由含金屬厚膜層在邏輯電源模組1之陶瓷基板上設置電源組件3，且在含金屬厚膜層上設置金屬箔。
在第一態樣中，此電源組件3可以藉由以下方法步驟製備： (1.1) 將厚膜膠施加至陶瓷基板上； (1.2) 將金屬箔施加至陶瓷基板之厚膜層上；及 (1.3) 經由厚膜層連接金屬箔與陶瓷基板。
因此，電源組件3之結構包含 (a) 陶瓷基板，且其上設置 (b) 含金屬厚膜層，且其上設置 (c) 金屬箔。
根據本發明，已經發現，基於厚膜技術，有可能提供用於電力電子學領域之基板，其中金屬箔經由金屬之厚膜膠連接至陶瓷基板(諸如Al2 O3 陶瓷、AlN陶瓷或Si3 N4 陶瓷)上。所得金屬-陶瓷基板具有高傳導性及高耐久性，且生產成本下降。
首先描述製備邏輯電源模組之電源組件3的方法。因此，製備電源組件3之方法可以在兩個實施例中進行：
第一實施例 - 在陶瓷基板 4 上在電源組件之區域 4b 中施加厚膜 ： 在第一方法步驟中，將厚膜膠施加至陶瓷基板上陶瓷基板4之區域4b中，其中所得邏輯電源模組1必須包含電源組件3。
在第一態樣 中，可將厚膜膠不連續地施加至陶瓷基板4上，使得厚膜膠僅施加在陶瓷基板4之對應於最終金屬-陶瓷基板之既定電子電路的彼等部分上。
之後，可以在陶瓷基板4之整個厚膜層上在電源組件之區域4b中連續地施加金屬箔。此後，使金屬箔與陶瓷基板連接，且隨後例如藉由蝕刻進行結構化。
在此第一態樣中，金屬箔亦可不連續地施加於僅在陶瓷基板之施加厚膜膠之彼等部分上的厚膜層上。
在第二態樣 中，將厚膜膠連續地施加至陶瓷基板4上之電源組件之區域4b中。
隨後，可以將金屬箔連續地施加在陶瓷基板4之整個厚膜層上之電源組件之區域4b中且金屬箔及厚膜層在連接後例如藉由蝕刻進行結構化。
金屬箔亦可不連續地僅施加在陶瓷基板4之電源組件之區域4b中對應於最終邏輯電源模組1之既定電子電路的彼等部分上。在此情況下，厚膜層在連接後例如藉由蝕刻進行結構化。
在將厚膜膠施加至陶瓷基板上之後，可以在將金屬箔施加至厚膜層上之前對厚膜膠進行空氣乾燥。
在將厚膜膠施加至陶瓷基板4上之電源組件之區域4b中之後，亦可在施加金屬箔之前對厚膜膠進行燒結。此類燒結製程可以藉由低於1025℃之溫度進行。燒結製程較佳藉由在300℃至1025℃範圍內、更佳在600℃至1025℃範圍內、更佳在900℃至1025℃範圍內、更佳在900℃至小於1025℃範圍內、更佳在900℃至1000℃範圍內之溫度進行。
燒結/燒製導電膠可從濕膜移除有機組分且確保厚膜銅良好連接至基板。相比於標準DCB製程，燒製導電膜之黏著在遠低於Cu-O共晶熔融溫度下形成。塊狀Cu箔與此燒製導電膜之連接隨後藉由純金屬對金屬燒結製程進行。因此，此製程不同於例如DE 10 2010 025 313 A中所述之製程。
在將厚膜膠施加至陶瓷基板上之後，亦可在將金屬箔施加至厚膜層上之前對厚膜膠進行空氣乾燥及燒結。燒結條件如上文所描述。
所施加厚膜膠之燒結製程通常在惰性氛圍下，諸如在氮氣氛圍下進行。
第二實施例 - 在金屬箔上施加厚膜 在製備邏輯電源模組1之電源組件3之進一步改良方法中，所主張之改良方法包含以下方法步驟： (2.1) 將厚膜膠施加至金屬箔上； (2.2) 將陶瓷基板4之電源組件3之區域4b施加至金屬箔之厚膜層上；及 (2.3) 經由厚膜層連接金屬箔與陶瓷基板4。
在此改良方法中，厚膜膠可以藉由網版印刷塗佈至金屬箔基板上。
在將厚膜膠施加至金屬箔上之後，可以首先對厚膜膠進行空氣乾燥，隨後將金屬箔施加至陶瓷上之電源組件3之區域4b中。
在將厚膜膠施加至金屬箔上之後，亦可在連接至陶瓷基板之前燒結厚膜膠。此類燒結製程可以藉由低於1025℃之溫度進行。燒結製程較佳藉由在300℃至1025℃範圍內、更佳在600℃至1025℃範圍內、更佳在900℃至1025℃範圍內、更佳在900℃至小於1025℃範圍內、更佳在900℃至1000℃範圍內之溫度進行。
在根據本發明之改良方法中，在經由厚膜層將金屬箔連接至陶瓷基板上之前或之後，藉由蝕刻對金屬箔及厚膜膠進行結構化。
針對上述兩個實施例給出以下解釋：
厚膜膠可以藉由多層印刷施加至陶瓷基板4上之電源組件3之區域4b中或金屬箔上。若施加多層塗層之方法步驟且將厚膜膠施加至陶瓷基板4上，則多層塗層之第一塗層可以設置有接觸線。
在製備邏輯電源模組1之電源組件3的兩種方法中，亦即第一及第二實施例，連接步驟(1.3)及/或(2.3)藉由燒製進行。燒製通常在750℃與1100℃之間、更佳在800℃與1085℃之間、甚至更佳在900℃與1085℃之間的溫度下進行。在此等連接步驟中，金屬箔經由厚膜膠連接至陶瓷基板上之電源組件之區域4b，基本上不施加DCB製程，因為金屬箔係與藉由厚膜膠提供之層而非陶瓷基板4接觸。
在上述兩個實施例中，金屬箔在經由厚膜層連接至陶瓷基板4上之電源組件之區域4b之前可以氧化。在另一實施例中，金屬箔在經由厚膜層連接至陶瓷基板4之前不氧化。
在兩個實施例之進一步改良中，厚膜層在金屬箔連接至陶瓷基板4上之前可以氧化。在另一實施例中，厚膜層在金屬箔連接至陶瓷基板4上之前不氧化。
將金屬箔連接至陶瓷基板4上之方法步驟(1.3)及/或(2.3)可以在壓力下進行。
在上述兩個實施例中，金屬箔較佳為銅箔。
下面更詳細地描述可以用於根據上述兩個實施例之方法中之厚膜膠：
根據本發明之方法中(普通方法中或改良方法中)所用的厚膜膠可包含銅作為金屬且視情況包含Bi2 O3 。
厚膜膠包含較佳40重量%至92重量%銅，更佳40重量%至小於92重量%銅，更佳70重量%至小於92重量%銅，最佳75重量%至90重量%銅，各自以厚膜膠之總重量計。
厚膜膠包含較佳0至50重量% Bi2 O3 ，更佳1重量%至20重量% Bi2 O3 ，最佳2重量%至15重量% Bi2 O3 ，各自以厚膜膠之總重量計。
厚膜膠中所用之銅粒子所具有的中值直徑(d50 )較佳在0.1至20 µm之間、更佳在1與10 µm之間、最佳在2與7 µm之間。
視情況用於厚膜膠中之Bi2 O3 粒子所具有之中值直徑(d50 )較佳小於100 µm、更佳小於20 µm、最佳小於10 µm。
在本發明之另一實施例中，含金屬厚膜膠可包含銅及玻璃組分。
在同時使用玻璃組分之情況下，厚膜膠中之銅之量可以如上文所定義，亦即，銅量較佳為40重量%至92重量%、更佳為40重量%至小於92重量%，銅量更佳為70重量%至小於92重量%，銅量最佳為75重量%至90重量%，各自以厚膜膠之總重量計。
在厚膜膠中使用玻璃組分之情況下，厚膜膠包含較佳0至50重量%、更佳1重量%至20重量%、最佳2重量%至15重量%之玻璃組分，各自以厚膜膠之總重量計。
在厚膜膠中使用玻璃組分之情況下，銅粒子可以具有與上文所提及相同的中值直徑(d50 )，亦即較佳在0.1至20 µm之間，更佳在1與10 µm之間，最佳在2與7 µm之間。
在厚膜膠中使用玻璃組分之情況下，玻璃組分粒子可以具有的中值直徑(d50 )為小於100 µm，更佳小於20 µm，最佳小於10 µm。
含金屬厚膜膠，較佳在銅之基礎上，可包含除玻璃組分及Bi2 O3 以外的其他組分，該等其他組分選自由PbO、TeO2 、Bi2 O3 、ZnO、B2 O3 、Al2 O3 、TiO2 、CaO、K2 O、MgO、Na2 O、ZrO2 、Cu2 O、CuO及Li2 O組成之群。
關於厚膜技術中之標準應用，較佳的導電膠組合物可購自Heraeus(厚膜導體系統，例如C7403及C7404系列)。在將厚膜膠施加至陶瓷基板4上或金屬箔上之後，層厚度較佳為5至150 µm、更佳為20至125 µm、最佳為30至100 µm。
在本發明之一較佳實施例中，厚膜膠中之氧化銅之量為小於2重量%、更佳小於1.9重量%、更佳小於1.8重量%、更佳小於1.5重量%。
下面更詳細地描述陶瓷基板4上之電源組件3。此電源組件3包含 (a) 陶瓷基板4，且其上設置 (b) 含金屬厚膜層，且其上設置 (c) 金屬箔。
金屬箔及/或含金屬厚膜層可以結構化。
設置於陶瓷基板上之厚膜層較佳包含銅作為金屬且視情況包含Bi2 O3 。
厚膜膠包含較佳40重量%至92重量%銅，更佳40重量%至小於92重量%銅，更佳70重量%至小於92重量%銅，最佳75重量%至90重量%銅，各自以厚膜膠之總重量計。
厚膜膠包含較佳0至50重量% Bi2 O3 ，更佳1重量%至20重量% Bi2 O3 ，最佳2重量%至15重量% Bi2 O3 ，各自以厚膜膠之總重量計。
厚膜膠中所用之銅粒子所具有的中值直徑(d50 )較佳在0.1至20 µm之間、更佳在1與10 µm之間、最佳在2與7 µm之間。
視情況用於厚膜膠中之Bi2 O3 粒子所具有之中值直徑(d50 )較佳小於100 µm、更佳小於20 µm、最佳小於10 µm。
在本發明之另一實施例中，含金屬厚膜膠可包含銅及玻璃組分。
在同時使用玻璃組分之情況下，厚膜膠中之銅之量可以如上文所定義，亦即，銅量較佳為40重量%至92重量%，銅量更佳為70重量%至92重量%，銅量最佳為75重量%至90重量%，各自以厚膜膠之總重量計。
在厚膜膠中使用玻璃組分之情況下，厚膜膠包含較佳0至50重量%、更佳1重量%至20重量%、最佳2重量%至15重量%之玻璃組分，各自以厚膜膠之總重量計。
在厚膜膠中使用玻璃組分之情況下，銅粒子可以具有與上文所提及相同的中值直徑(d50 )，亦即較佳在0.1至20 µm之間，更佳在1與10 µm之間，最佳在2與7 µm之間。
在厚膜膠中使用玻璃組分之情況下，玻璃組分粒子可以具有的中值直徑(d50)為小於100 µm，更佳小於20 µm，最佳小於10 µm。
含金屬厚膜膠可包含除玻璃組分及Bi2 O3 以外的其他組分，該等其他組分選自由PbO、TeO2 、Bi2 O3 、ZnO、B2 O3 、Al2 O3 、TiO2 、CaO、K2 O、MgO、Na2 O、ZrO2 、Cu2 O、CuO及Li2 O組成之群。
厚膜膠之層厚度較佳為10至150 µm、更佳20至125 µm、最佳30至100 µm。
金屬箔較佳為銅箔。
電源組件之厚膜膠及邏輯組件之導電金屬膠較佳在一個方法步驟中(亦即同時)設置於陶瓷基板上，這有利於根據本發明之邏輯電源模組之製造。在此情況下，同一組合物在陶瓷基板之整個表面上在電源組件之區域中印刷一次且在邏輯組件之區域中通常不連續地印刷，以便形成智慧型結構，尤其諸如導體、晶粒黏著結構(上面例如設置晶片)及被動電子組件，諸如電阻器、電容器。對邏輯組件及電源組件中之膠而言，乾燥及燒結、較佳燒製方法步驟亦可以在相同條件下同時進行。
實例部分 參照以下實例更詳細地描述本發明：
厚膜膠材料由以下玻璃組合物(以重量%計)開始製備： 媒劑調配物 膠調配物
由此等膠調配物開始，陶瓷金屬基板4上之電源組件3藉由將膠以40 µm之厚度印刷在Al2 O3 陶瓷基板上之電源組件3之區域4b中而製備。將膠在烘箱中在110℃下乾燥10分鐘且在950℃下燒結10分鐘，隨後將厚度300 µm之Cu箔施加至經乾燥之膠上且將複合物在烘箱中燒製150分鐘，其中在1040℃下之峰值溫度達5分鐘。
為了比較，由與膠之實例相同的陶瓷基板及相同的Cu箔開始，但是使用160分鐘連接時間及在1078℃範圍內之峰值溫度4分鐘的標準DCB製程製備陶瓷金屬基板。此陶瓷基板4包含藉由傳統DCB製程製備之用於電源組件4之區域4b。
使成品金屬陶瓷基板經歷熱循環(在-40℃下15分鐘，15秒轉移時間，在+150℃下15分鐘)。測試結果可見於下表中。
1‧‧‧邏輯電源模組
2‧‧‧邏輯組件
3‧‧‧電源組件
4‧‧‧基板
4a‧‧‧邏輯組件之區域
4b‧‧‧電源組件之區域
圖1顯示根據本發明之邏輯電源模組。

Claims (17)

  1. 一種邏輯電源模組(1)，其包含至少一個邏輯組件(2)、至少一個電源組件(3)及陶瓷基板(4)，其中該邏輯組件(2)及該電源組件(3)設置於該陶瓷基板(4)上之各別區域(4a，4b)中， 其特徵在於 該陶瓷基板(4)上之該邏輯組件(2)係藉由厚印刷導電金屬膠提供；且 該電源組件(3)係藉由含金屬厚膜層提供，且在該含金屬厚膜層上設置金屬箔。
  2. 如請求項1之邏輯電源模組(1)，其中該厚膜膠在該金屬箔與該陶瓷基板連接之前藉由低於1025℃之溫度燒結。
  3. 如請求項1之邏輯電源模組(1)，其中構成該電源組件(3)之該厚膜層係由厚膜膠製備。
  4. 如請求項1至3中任一項之邏輯電源模組(1)，其中該電源組件(3)係藉由將該厚膜膠連續施加於該陶瓷基板(4)上且將該金屬箔連續施加於該厚膜膠上而提供。
  5. 如請求項1至3中任一項之邏輯電源模組(1)，其中該電源組件(3)係藉由將該厚膜膠不連續施加於該陶瓷基板(4)上且將該金屬箔連續施加於該厚膜膠上而提供。
  6. 如請求項1至3中任一項之邏輯電源模組(1)，其中在該電源組件(3)中，該厚膜層係由厚膜膠形成，該厚膜膠係藉由網版印刷塗佈於該金屬箔或該基板上。
  7. 如請求項1至3中任一項之邏輯電源模組(1)，其中在該電源組件(3)中，該金屬箔及/或該厚膜層在連接至該基板之前經氧化。
  8. 如請求項1至3中任一項之邏輯電源模組(1)，其中在該電源組件(3)中，該厚膜膠係藉由多層印刷施加於該基板或金屬箔上。
  9. 如請求項1至3中任一項之邏輯電源模組(1)，其中該陶瓷基板(4)為氧化鋁陶瓷(Al2 O3 )、氮化鋁陶瓷(AlN)、氧化鋯增韌氧化鋁陶瓷(ZTA)、氧化鈹陶瓷(BeO)或Si3 N4 陶瓷。
  10. 如請求項1至3中任一項之邏輯電源模組(1)，其中該邏輯組件(2)之該厚印刷導電金屬膠與該電源組件(3)之該含金屬厚膜膠具有相同組成。
  11. 一種製備包含至少一個邏輯組件(2)、至少一個電源組件(3)及陶瓷基板(4)之邏輯電源模組(1)的方法，其中該邏輯組件(2)及該電源組件(3)設置於該陶瓷基板(4)上之各別區域(4a，4b)中， 其特徵在於 該陶瓷基板(4)上之該邏輯組件(2)係藉由網版印刷、模板印刷及/或直接沈積厚印刷銅而製備；且 該陶瓷基板(4)上之該電源組件(3)係藉由以下方法步驟製備： (1.1) 將厚膜膠施加至該陶瓷基板(4)上； (1.2) 將金屬箔施加至該陶瓷基板(4)之厚膜層上；及 (1.3) 經由該厚膜層連接該金屬箔與該陶瓷基板(4)； 或 (2.1) 將厚膜膠施加至金屬箔上； (2.2) 將該陶瓷基板(4)施加至該金屬箔之該厚膜層上；及 (2.3) 經由該厚膜層連接該金屬箔與該陶瓷基板。
  12. 如請求項11之方法，其中在該金屬箔與該陶瓷基板連接之前，藉由低於1025℃之溫度燒結該厚膜膠。
  13. 如請求項11或12之方法，其中藉由網版印刷將該電源組件(3)之該厚膜膠塗佈至該金屬箔或該陶瓷基板(4)上。
  14. 如請求項11或12之方法，其中該電源組件(3)之該金屬箔及/或該厚膜層在連接至該陶瓷基板(4)之前經氧化。
  15. 如請求項11或12之方法，其中藉由多層印刷將該電源組件(3)之該厚膜膠施加至該陶瓷基板(4)上或該金屬箔上。
  16. 一種根據請求項11至15中任一項之方法製備的邏輯電源模組(1)。
  17. 一種如請求項1至10或16中任一項之邏輯電源模組在電力電子電路中之用途。
TW107121190A 2017-06-21 2018-06-20 具有與金屬或金屬混合箔連接之厚膜膠媒介基板的邏輯電源模組 TW201922677A (zh)

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