TWI229351B - Multilayer ceramic composition - Google Patents

Multilayer ceramic composition Download PDF

Info

Publication number
TWI229351B
TWI229351B TW92109057A TW92109057A TWI229351B TW I229351 B TWI229351 B TW I229351B TW 92109057 A TW92109057 A TW 92109057A TW 92109057 A TW92109057 A TW 92109057A TW I229351 B TWI229351 B TW I229351B
Authority
TW
Taiwan
Prior art keywords
dielectric material
item
material layer
layer
composition according
Prior art date
Application number
TW92109057A
Other languages
Chinese (zh)
Other versions
TW200423155A (en
Inventor
Wen-Hsi Lee
Che-Yi Su
Yi-Jung Ling
Original Assignee
Yageo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yageo Corp filed Critical Yageo Corp
Priority to TW92109057A priority Critical patent/TWI229351B/en
Publication of TW200423155A publication Critical patent/TW200423155A/en
Application granted granted Critical
Publication of TWI229351B publication Critical patent/TWI229351B/en

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Compositions Of Oxide Ceramics (AREA)

Abstract

The present invention provides a multilayer ceramic composition comprising at least one layer of dielectric material M1 and at least one layer of dielectric material M2, wherein passive components are buried in both layers of dielectric material M1 and M2 that prevent each other from shrinkage in the X and Y dimensions during firing. Each layer of the multilayer ceramic composition according to the invention can be used as a substrate for burying the passive component and has the ability to prevent other layer with different dielectric constant from shrinkage. Hence, the multilayer ceramic composition has the advantages of smaller size and a better circuit precision.

Description

12293511229351

玖τ (發明說明雜明:發明所屬之技術領域、先前技術、内袁、實施方式及圖式簡單編) 【發明領域】 本發明係關於一種陶瓷組合物,特定言之,係關於一種 用於電子微波系統·之積層陶瓷組合物。 【先前技術】 為符合現爲電手產品對輕、薄、小之要求,互連電路板 成為必要.。該互連電路板為彼此以電性或機械上相互連結 之電子電路或次系統,該次系統如數個極小之被動元件及 組合排列之金屬化圖棄。此被動元件及金屬化圖案係為物 理性分離,且彼此相鄰地包埋在單一互連電路板上,而使 彼此%性連接及/或自互連電路板延伸。陶瓷組合物現已 廣泛應用於互連電路板上。 在陶瓷組合物中,複雜之電子電路一般需要數個絕緣_介 包層以分離導電層。為了符合不同介電常數以適於潔 造或包埋被動元件及金屬圖案之需求,開發一系列具有不 同介電常數之介電材料為必須。例如,陶资组合物之訊號 處理部份,以低介電常數材料較佳,其可增加其内訊號谓 達速度’以提/決_叾田. — 而在製造作為内埋式被動天 件如黾容器等,則以高介雷堂 %吊數材料較佳。過介電層孩 被動兀件及金屬化圖案互連之 · .^ s ^ 導兒路徑稱為通孔(vus)— 此夕層、、,口構可使電路更加緊密 據較少之空間。 ,、k積層陶瓷組合物之 万法逑於美國專利# 4,654,095,併於本文以供參考, 、 成積層陶堯組合物上已 1229351 ⑺ 印刷有被動元件及金屬化圖案如電阻、電容或導體,其以 延伸通過介電層之金屬化通孔使各種‘被動元件與金屬化 圖案相互連結,其中之陶瓷粉末可在適於使用高導電性金 屬如金、銀及銅之溫度下緻密化。特別地,緻密作用係在 於或低於 1 0 0 0 °C $成,以提供足以與金熔點(1 0 6 0 °c )區 別之誤差邊際。該等介電層係在適當溫度及壓力下對位堆 疊並壓合在一起"接著燒製以去除陶瓷生胚中之有機物如 黏合劑及可塑劑。所有陶瓷及異質材料因此而燒結緻密。 此方法之優點為僅進行一次燒製,可節省製造時間及勞 力,並限制了可移動金屬之擴散以避免導電層間短路。 然而,共燒具有高K介電及低K介電材料之單片結構 仍有問題;問題之一為電性質改變,另一為燒製時會發生 收縮導致錯位。 有關電性質改變部份,許多習知之組裝同時使用低介電 常數材料及高介電常數材料。其中該低介電常數材料含有 玻璃,導致介電常數增加及損失增加;該高介電常數材料 含鉛、鎂及鈮。然而,當低介電材料與高介電材料彼此接 觸,並於溫度高於8 0 0 °c共燒時,由於介面間擴散而發生 化學反應。基於此理由,低及高介電常數材料兩者之介電 常數均被改變,通常會發生高介電常數材料戲劇性地降 低。 於電子封裝之低及高介電常數材料間插入複數個緩衝 層係揭示於美國專利號5,7 5 7,6 1 1,其中由含2 5至1 0 0 % 鋇化合物之緩衝層產生更困難之化學擴散路徑,其可在緻玖 τ (miscellaneous description of the invention: the technical field to which the invention belongs, the prior art, the inner yuan, the embodiment, and the simplified drawings) [Field of the Invention] The present invention relates to a ceramic composition, specifically, a Electron microwave system · Laminated ceramic composition. [Previous technology] In order to meet the requirements for light, thin, and small electronic hand products, interconnecting circuit boards has become necessary. The interconnecting circuit board is an electronic circuit or a sub-system which is electrically or mechanically connected to each other. The sub-system is discarded as several extremely small passive components and a combination of metallization patterns. The passive component and the metallization pattern are physically separated, and are embedded next to each other on a single interconnect circuit board, so that they are connected to each other and / or extend from the interconnect circuit board. Ceramic compositions are now widely used in interconnect circuit boards. In ceramic compositions, complex electronic circuits typically require several insulation_cladding layers to separate the conductive layers. In order to meet the requirements of different dielectric constants for cleaning or embedding passive components and metal patterns, it is necessary to develop a series of dielectric materials with different dielectric constants. For example, the signal processing part of the ceramics composition is better with a low dielectric constant material, which can increase its internal signal speed to increase / decide _ Putian. — And is used as an embedded passive antenna in manufacturing Such as 黾 container, etc., it is better to use high-media Leitang% hanging number material. Passive dielectric elements and metallized patterns interconnect through the dielectric layer.. ^ S ^ The conductive path is called a through hole (vus)-this layer, the structure can make the circuit more compact and less space. The method of multilayer ceramic composition is described in U.S. Patent # 4,654,095, which is hereby incorporated by reference. The laminated Tao Yao composition has been 1229351. Passive components and metallized patterns such as resistors, capacitors or conductors are printed. It interconnects various passive components and metallized patterns with metalized through holes extending through the dielectric layer. The ceramic powder can be densified at a temperature suitable for the use of highly conductive metals such as gold, silver and copper. In particular, densification is at or below 100 ° C to provide a margin of error sufficient to distinguish it from the melting point of gold (106 ° C). The dielectric layers are stacked and pressed together at an appropriate temperature and pressure " and then fired to remove organic substances such as adhesives and plasticizers from the ceramic green body. All ceramics and heterogeneous materials are thus densely sintered. The advantage of this method is that the firing is performed only once, which can save manufacturing time and labor, and limit the diffusion of the movable metal to avoid short circuit between conductive layers. However, co-fired monolithic structures with high-K dielectrics and low-K dielectric materials still have problems; one of the problems is the change in electrical properties, and the other is that shrinkage occurs during firing and causes dislocation. Regarding the change of electrical properties, many conventional assemblies use both low dielectric constant materials and high dielectric constant materials. The low dielectric constant material contains glass, which results in an increase in dielectric constant and loss; the high dielectric constant material contains lead, magnesium, and niobium. However, when the low dielectric material and the high dielectric material are in contact with each other and co-fired at a temperature higher than 800 ° C, a chemical reaction occurs due to diffusion between the interfaces. For this reason, the dielectric constants of both low and high dielectric constant materials are changed, and a dramatic decrease in high dielectric constant materials usually occurs. The insertion of a plurality of buffer layers between low and high dielectric constant materials for electronic packaging is disclosed in US Patent No. 5,7 5 7,6 1 1, where a buffer layer containing 25 to 100% barium compound is used to generate more Difficult chemical diffusion path, which can cause

O:\82\82936.DOC 1229351 l_ (3) 密化之最初階段期間提供額外之物理障壁。通孔亦可形成 通過該緩衝層,以供被動元件部分與i號處理部分間導 電。利用玻璃形成添加劑及無機填充劑,可控制與被動元 件部分之高K介電層或與訊號處理部分之低K介電層接 觸之缓衝層收縮率a、熱膨脹及化學相容性。然而,該緩衝 層亦增大了電子封裝之厚度,因此亦無法作為包埋被動元 件之良好基材。- • - - 其他具有不同 K值之積層陶瓷生帶結構係示於美國專 利號6,0 5 5,1 5 1,其著眼於網印在低燒製溫度生帶上之油 墨,以形成内埋式元件如電容,以增加高精確放置之容忍 度。該電容層係夾在厚度足以避免生帶中低燒製溫度玻璃 擴散之兩個鈦酸鋇障壁層間。再者,該積層陶瓷生帶結構 藉由黏結玻璃黏合在金屬擔體結構上以避免收縮。然而, 低燒製溫度生帶與金屬擔體基材之收縮率並不相同,其在 燒製時需良好控制以免發生破裂。同樣地,積層陶瓷生帶 結構之厚度仍無法降低。 有關收縮部份,由於燒結時各元件之收縮並不相同,而 難以控制燒製條件。再者,在組裝大且複雜之電路時,因 X及Y方向之不確定性導致之錯位(misregistration)尤需 避免。一種於燒製陶瓷生胚時,可減少收縮之方法係揭示 於美國專利號5,0 8 5,720,其中陶瓷生胚之上部及底部各 施以一釋離層以形成「三明治」結構。於燒出及燒結期間, 在釋離層表面施加一單向壓力。釋離層之孔隙度並提供了 陶瓷生胚中揮發成分之逸出路徑。由於該釋離層在燒製期O: \ 82 \ 82936.DOC 1229351 l_ (3) Provide additional physical barriers during the initial stages of densification. Through-holes can also be formed through the buffer layer for conducting electricity between the passive element portion and the i-numbered processing portion. With glass-forming additives and inorganic fillers, the shrinkage a, thermal expansion, and chemical compatibility of the buffer layer in contact with the high-K dielectric layer of the passive element portion or the low-K dielectric layer of the signal processing portion can be controlled. However, the buffer layer also increases the thickness of the electronic package, so it cannot be used as a good substrate for embedding passive components. -•--Other laminated ceramic green belt structures with different K values are shown in US Patent No. 6,0 5 5, 1 51, which focuses on the inks printed on the green belt at low firing temperature to form the inner layer. Buried components such as capacitors to increase tolerance for highly accurate placement. The capacitor layer is sandwiched between two barium titanate barrier layers having a thickness sufficient to prevent low-fire temperature glass diffusion in the green belt. Furthermore, the laminated ceramic green tape structure is adhered to the metal support structure by the bonding glass to avoid shrinkage. However, the shrinkage rate of the low firing temperature green belt is not the same as that of the metal support substrate, and it needs to be well controlled during firing to avoid cracking. Similarly, the thickness of the laminated ceramic green belt structure cannot be reduced. Regarding the shrinkage part, since the shrinkage of each element is different during sintering, it is difficult to control the firing conditions. Furthermore, when assembling large and complex circuits, misregistration due to uncertainty in the X and Y directions needs to be avoided. A method for reducing shrinkage when firing ceramic green embryos is disclosed in U.S. Patent No. 5,0 8 5,720, in which a release layer is applied to the upper and bottom of the ceramic green embryos to form a "sandwich" structure. During firing and sintering, a unidirectional pressure is applied to the surface of the release layer. The porosity of the release layer provides a way for the volatile components in the ceramic embryo to escape. Since the release layer is in the firing period

O:\82\82936.DOC 1229351 (4) 間不收縮,因此可降低陶瓷生胚之X與Y方向收縮。另 一方面,覆蓋該陶瓷生胚上部及下部表面兩者之釋離層, 需在印刷及導體、電阻及電容燒結後移除,因此增加此方 法之成本。當製造多層陶變:層(如大於6層)時,陶资生胚 之中間層仍會因在^生胚上部及下部施加釋離層之力道不 均而產生收縮(亦即,施加在生胚上部及下部及中間層之 力道實質上並不相同)。 美國專利號5,0 8 5,720揭示了陶瓷生胚之些許改良,其 在陶瓷生胚層間設置避免可收縮之抑制層,並於最終產品 中保留該抑制層,以避免移除之缺點。然而,該抑制層無 法做為適當之介電材料,致使產品厚度增大。 為了解決上述問題,本發明發展出一種新穎之積層陶瓷 組合物,其優點為減小尺寸及當共燒具不同介電常數之兩 個介電材料及包埋於其内之被動元件時,減少X及Υ方 向之收縮,而提供較佳之電路精確度。 【發明内容】 本發明提供一種積層陶瓷;組合物,其包括至少一層介電 材料Μ!及至少一層介電材料Μ2,其中被動元件係包埋於 介電材料Μ1及Μ2兩層中,而於燒製時避免彼此在X及 Υ方向收縮。本發明之積層陶瓷組合物之各層皆可作為包 埋被動元件之基材,且可避免具不同介電常數之他層收 縮。因此,本積層陶變;組合物具有減小尺寸及較佳電路精 確度之優點。 本發明之一目的係提供一種積層陶瓷組合物,其包括:O: \ 82 \ 82936.DOC 1229351 (4) does not shrink between, so it can reduce the X and Y shrinkage of ceramic green embryos. On the other hand, the release layer covering both the upper and lower surfaces of the ceramic green body needs to be removed after printing and sintering of the conductor, resistor and capacitor, thus increasing the cost of this method. When manufacturing multi-layer ceramic deformation: layers (such as more than 6 layers), the middle layer of ceramic raw embryos will still shrink due to the uneven force applied to the upper and lower parts of the raw embryos (that is, the upper part of the raw embryos) And the strength of the lower and middle layers are substantially different). U.S. Patent No. 5,0 8 5,720 discloses a slight modification of ceramic green embryos, which includes a shrinkable inhibitor layer between the ceramic green embryo layers and retains the inhibitor layer in the final product to avoid the disadvantages of removal. However, the suppression layer cannot be used as a suitable dielectric material, resulting in increased product thickness. In order to solve the above problems, the present invention develops a novel multilayer ceramic composition, which has the advantages of reducing the size and reducing the temperature when two dielectric materials with different dielectric constants are co-fired and the passive components are embedded therein. X- and Y-direction shrinkage to provide better circuit accuracy. SUMMARY OF THE INVENTION The present invention provides a multilayer ceramic; a composition comprising at least one layer of a dielectric material M! And at least one layer of a dielectric material M2, wherein a passive element is embedded in two layers of the dielectric material M1 and M2, Avoid shrinking in the X and Υ directions when firing. Each layer of the multilayer ceramic composition of the present invention can be used as a substrate for embedding passive components, and can avoid shrinkage of other layers having different dielectric constants. Therefore, the laminated ceramics composition has the advantages of reduced size and better circuit accuracy. An object of the present invention is to provide a laminated ceramic composition, which includes:

O:\82\82936.DOC 1229351 (5) l^M] 至少一層具有介電常數Κι之介電材料層,且其内 具有至少一個内埋式被動元件;友 至少一層具有介電常數K2之介電材料層M2,且其内 具有至少一個内埋式被動元件,其係設置在該介電材 料層Μι之下有; 其中Κι與K2不同,且介電材料層Μι及介電材料層 M2可在燒結時避免彼此於X及Y方向之收縮。 【實施方式】 本發明提供一種積層陶瓷組合物,包括: 至少一層具有介電常數Κι之介電材料層Ml,且其内 具有至少一個内埋式被動元件;及 至少一層具有介電常數K2之介電材料層M2,且其内 具有至少一個内埋式被動元件,其係設置在該介電材 料層Μ 1之下方; 其中Κι與Κ2不同,且介電材料層Μι及介電材料層 M2可在燒結時避免彼此於X及Y方向之收縮。 本發明之積層陶瓷組合物1之一具體實施例示於圖1, 其包含複數層具有介電常數Κι之介電材料層Μι 11及複 數層具有介電常數K2之介電材料層M2 12,其中Κι不同 於Κ2。介電材料層Μι 11及介電材料層Μ2 12均可作為 内埋式被動元件1 5之基材。較佳地,金屬化圖案1 6係藉 由在介電材料層Μι 11及介電材料層Μ2 12上,依所選擇 之圖案施加所選擇量之導電金屬而產生。亦可衝打通過層 1 1、1 2而形成複數個通孔,其可為穿過層1 1、1 2之開孔, O:\82\82936.DOC -10- 1229351 ⑹ 通孔導體1 3可置入通孔内,以電性連結被動元件1 5與金 屬化圖案1 6。 ‘ 於本發明一較佳具體實施例中,該陶瓷組合物另包括其 内無被動元件或金屬化圖案之一覆蓋介電層。 本文所用之「内埋式被動元件」代表已裝配好之内埋式 被動元件,或是由介電層及金屬化圖案及/或通孔導體所 製得之電子元件6例如,已裝配好之被動元件包含電容、 電阻及電感;特別地,層1 1或12内之金屬化圖案16可 包含多層相反定向之電極14,其與層11或12 —起形成 電容。層1 1或1 2間之金屬化圖案1 6可形成訊號處理裝 置,如傳導/接收(T/R)模組及其類似物。 金屬化圖案1 6及通孔導體1 3較佳係包含高度導電之材 料如金、銀及銅及其合金,且其中更佳係包含銀,其熔點 為9 6 0 °C。因此,積層陶瓷:組合物1之緻密化需在低於用 以形成金屬化圖案 1 6之特定導電材料熔點之溫度下達 成。再者,對不同設計之電路而言,需要不同介電常數之 材料。 可用以製造本發明介電層之介電材料,皆適於作為 M i 及M2。依據本發明之一較佳具體實施例,Μι及M2中至 少一種材料包括提供適當電性質之陶f:固體粒及無機玻 璃。 本文所述之「陶瓷固體粒」代表一組合物,其本身並非 直接嚴格定義,只要該固體粒對系統中其他材料具化學惰 性,且相對介電材料系統之其他元件具有下列物理性質即 O:\82\82936.DOC -11 -O: \ 82 \ 82936.DOC 1229351 (5) l ^ M] at least one layer of a dielectric material having a dielectric constant K1 and at least one embedded passive component therein; and at least one layer having a dielectric constant K2 The dielectric material layer M2 has at least one embedded passive component therein, which is disposed below the dielectric material layer M1; where K1 is different from K2, and the dielectric material layer M1 and the dielectric material layer M2 It is possible to avoid shrinkage of each other in the X and Y directions during sintering. [Embodiment] The present invention provides a multilayer ceramic composition comprising: at least one dielectric material layer M1 having a dielectric constant K1, and having at least one embedded passive element therein; and at least one layer having a dielectric constant K2 The dielectric material layer M2 has at least one embedded passive component therein, which is disposed below the dielectric material layer M1; where Km is different from K2, and the dielectric material layer Mm and the dielectric material layer M2 It is possible to avoid shrinkage of each other in the X and Y directions during sintering. A specific embodiment of the multilayer ceramic composition 1 of the present invention is shown in FIG. 1 and includes a plurality of dielectric material layers M11 having a dielectric constant Km and a plurality of dielectric material layers M2 12 having a dielectric constant K2, wherein Kι is different from K2. Both the dielectric material layer Mm 11 and the dielectric material layer M2 12 can be used as the substrate of the embedded passive element 15. Preferably, the metallization pattern 16 is generated by applying a selected amount of conductive metal on the dielectric material layer M11 and the dielectric material layer M2 12 according to the selected pattern. It is also possible to punch through the layers 1 1 and 12 to form a plurality of through holes, which may be openings through the layers 1 1 and 12, O: \ 82 \ 82936.DOC -10- 1229351 ⑹ through hole conductor 1 3 can be placed in the through hole to electrically connect the passive element 15 and the metallized pattern 16. ‘In a preferred embodiment of the invention, the ceramic composition further includes a dielectric layer overlying one of the passive components or the metallization pattern. As used herein, "embedded passive component" refers to an assembled embedded passive component, or an electronic component made of a dielectric layer and a metallized pattern and / or a via conductor. 6 For example, an assembled passive component Passive components include capacitors, resistors, and inductors. In particular, the metallization pattern 16 in the layer 11 or 12 may include multiple layers of electrodes 14 oriented in opposite directions, which together with the layer 11 or 12 form a capacitor. The metallized patterns 16 between layers 1 1 or 12 may form signal processing devices such as a transmit / receive (T / R) module and the like. The metallization pattern 16 and the via-hole conductor 13 preferably include highly conductive materials such as gold, silver, copper, and alloys thereof, and more preferably includes silver with a melting point of 96 ° C. Therefore, the densification of the laminated ceramic: composition 1 needs to be achieved at a temperature lower than the melting point of the specific conductive material used to form the metallized pattern 16. Furthermore, for circuits of different designs, materials with different dielectric constants are required. The dielectric materials that can be used to make the dielectric layer of the present invention are suitable as M i and M 2. According to a preferred embodiment of the present invention, at least one of the materials M1 and M2 includes ceramic f that provides suitable electrical properties: solid particles and inorganic glass. The "ceramic solid particles" described in this article represent a group of compounds, which is not directly strictly defined, as long as the solid particles are chemically inert to other materials in the system, and have the following physical properties relative to other elements of the dielectric material system, namely O: \ 82 \ 82936.DOC -11-

1229351 ⑺ 可:(1)具有充分高於無機玻璃燒結溫度之燒結溫度,及 (2)在燒製時不經歷燒結者。陶瓷固體‘粒之實例包含無機 金屬、高熔點無機固體粒、及高軟化點玻璃。在一更佳具 體實施例中,該陶瓷包含鋇鈦氧化物、鋇釤鈮鈦氧化物、 矽氧化物、鋁氧化#物、鎂鋁矽氧化物及其混合物。再者, 該陶瓷固體粒可依據其介電及熱膨脹性質兩者加以選 擇。因此.,可選擇上述材料之混合物,以符合所應用任何 基材之熱膨脹特性。 本文所用之「無機玻璃」代表一無機材料,其對系統中 其他材料具化學惰性,且具有下列物理性質:(1)具有充 分低於陶瓷之燒結溫度,及(2)在燒製溫度下經歷黏度相 流動燒結者。適用於本發明之無機玻璃一般為玻璃,尤其 是燒製時結晶化或非結晶化玻璃。在一更佳具體實施例 中,該無機玻璃係選自由鉍氧化物、碲氧化物、硼氧化物、 其前驅物及其混合物所成之組群,其量在約0.5至約9 8 重量%之範圍内。 該陶瓷固體粒及無機玻璃係分散於一聚合黏合劑中。該 聚合黏合劑中視情況溶有其他材料,如可塑劑、釋離劑、 分散劑、脫模劑、消泡劑及濕潤劑。本技藝中已知適合製 造低溫共燒陶瓷之任何聚合黏合劑皆適用於本發明。 組合陶瓷固體粒及無機玻璃即可獲得具有不同介電常 數及燒結溫度之一系列材料。較佳地,本發明之介電材料 之介電常數在約4至約2000之範圍内。另一方面,本發 明介電材料之燒結溫度係自約4 5 0至約1 2 0 0 °C ,且其中 O:\82\82936.DOC 12 - 12293511229351 ⑺ Can: (1) have a sintering temperature sufficiently higher than the sintering temperature of inorganic glass, and (2) those who do not undergo sintering during firing. Examples of ceramic solid particles include inorganic metals, high-melting inorganic solid particles, and high softening point glass. In a more specific embodiment, the ceramic comprises barium titanium oxide, barium hafnium niobium titanium oxide, silicon oxide, aluminum oxide, magnesium aluminum silicon oxide, and mixtures thereof. Furthermore, the ceramic solid particles can be selected based on both their dielectric and thermal expansion properties. Therefore, a mixture of the above materials can be selected to meet the thermal expansion characteristics of any substrate used. "Inorganic glass" as used herein represents an inorganic material that is chemically inert to other materials in the system and has the following physical properties: (1) has a sintering temperature that is sufficiently lower than that of ceramics, and (2) experiences at the firing temperature Viscosity phase mobile sinterer. The inorganic glass suitable for use in the present invention is generally glass, especially crystallized or non-crystallized glass upon firing. In a more specific embodiment, the inorganic glass is selected from the group consisting of bismuth oxide, tellurium oxide, boron oxide, precursors and mixtures thereof, and the amount is about 0.5 to about 98% by weight. Within range. The ceramic solid particles and the inorganic glass are dispersed in a polymer binder. Other materials such as a plasticizer, a release agent, a dispersant, a release agent, a defoaming agent, and a wetting agent are dissolved in the polymerization adhesive as appropriate. Any polymeric binder known in the art to be suitable for making low temperature co-fired ceramics is suitable for use in the present invention. By combining ceramic solid particles and inorganic glass, a series of materials with different dielectric constants and sintering temperatures can be obtained. Preferably, the dielectric constant of the dielectric material of the present invention is in the range of about 4 to about 2000. On the other hand, the sintering temperature of the dielectric material of the present invention is from about 450 to about 12 0 ° C, and wherein O: \ 82 \ 82936.DOC 12-1229351

更佳地’该燒結溫度係低於約9 6 〇它,以供於陶瓷組合物 中與銀共同燒製。 - 依據本發明’介電材料層Μ1及m2彼此接觸放置可避 免 X 、 及Y方向之收縮,並使所有收縮發生在z方向。避 免收縮之機制視材,料Ml及M2之燒結溫度差異而定。例 如’介電材料Μ!之燒結溫度為Tl,介電材料m2之燒結 _度為丁2,其中T!大於τ2。當介電材料層M2在τ2開始 燒結時’其Χ及Υ方向之收縮受到在Τ2尚未收縮之介電 材料層M i所抑制而減低。此時,介電材料層Μ ι扮演抑 制層之角色以抑制介電材料層Μ 2收縮。當溫度升至Τ 1 時’介電材料層Μ2已完成且不再收縮,因而介電材料層 Μ1在X及Υ方向之收縮受到介電材料層Μ2之抑制而減 低。較佳地,Τ !大於τ 2 + 5 0 °C,以達到避免收縮之更佳效 果。 依據本發明,在介電材料層Μ1及介電材料層m2間可 加入黏結玻璃。無論燒結期間Z方向是否施加外力,均 可使用黏結玻璃。該力係足以使積層陶瓷組合物之各層彼 此接觸,且實質上使所有收縮發生在垂直陶瓷組合物之Z 方向上,亦即,陶瓷組合物之X及Y方向在燒製期間不 會收縮。當未施加壓力時需使用黏結破璃。該黏結玻璃可 直接加至Μι及/或m2材料中,或可在介電材料層Μ!及 介電材料層M2之間形成一黏結玻璃層。該黏結玻璃層之 製備係使玻璃顆粒溶於適當溶劑如油墨中,龙藉直接塗 佈、點狀沉積或蒸氣沉積而印刷在介電材料層M i及/或介More preferably, the sintering temperature is lower than about 960 ° C for co-firing with silver in the ceramic composition. -According to the present invention, the dielectric material layers M1 and m2 are placed in contact with each other to avoid shrinkage in the X, and Y directions, and cause all shrinkages to occur in the z direction. The mechanism to avoid shrinkage depends on the difference in sintering temperature of the materials, materials M1 and M2. For example, the sintering temperature of the dielectric material M! Is Tl, and the sintering degree of the dielectric material m2 is D2, where T! Is greater than τ2. When the dielectric material layer M2 starts to sinter at τ2, its shrinkage in the X and Y directions is suppressed and reduced by the dielectric material layer M i that has not contracted at T2. At this time, the dielectric material layer M1 functions as a suppressing layer to suppress the dielectric material layer M2 from shrinking. When the temperature rises to T1, the 'dielectric material layer M2 has completed and no longer shrinks, so the shrinkage of the dielectric material layer M1 in the X and Υ directions is suppressed by the dielectric material layer M2 and reduced. Preferably, T! Is greater than τ 2 + 50 ° C to achieve a better effect of avoiding shrinkage. According to the present invention, a bonding glass may be added between the dielectric material layer M1 and the dielectric material layer m2. Regardless of whether external force is applied in the Z direction during sintering, bonded glass can be used. This force is sufficient to bring the layers of the laminated ceramic composition into contact with each other and substantially cause all shrinkage to occur in the Z direction of the vertical ceramic composition, that is, the X and Y directions of the ceramic composition do not shrink during firing. Adhesive breaking glass is used when no pressure is applied. The bonding glass may be directly added to the Mm and / or m2 material, or a bonding glass layer may be formed between the dielectric material layer M! And the dielectric material layer M2. The bonding glass layer is prepared by dissolving glass particles in a suitable solvent such as ink, and printing on the dielectric material layer M i and / or the dielectric by direct coating, dot deposition or vapor deposition.

O:\82\82936.DOCO: \ 82 \ 82936.DOC

1229351 (9) 電材料層m2上。 本發明具有許多優點:(1)由於積層陶變;組合物每層皆 可作為包埋被動元件之基材,而不需要先前技藝之緩衝層 及/或障壁層,因此陶資組合物之總尺寸可相當地減小, 以符合現代電子產I品輕、薄及小之要求;(2)藉由兩個材 料層Μ 1及M2可避免彼此收縮之設計,本發明陶瓷組合 物之X及Y方向’並不發生收縮。因此,其上設計之電路 精確度可相當地改良,且良率因此提高;(3)由缺乏緩衝 層、障壁層及/或金屬擔體觀點觀之,可降低成本;(4)藉 由組合陶瓷固體粒及無機玻璃,可製得一系列具變化介電 常數及品質因子之材料,故可適用不同目的之電氣性質。 下列實例僅為說明目的而不用以限制本發明。 實例1至15 :介電材料層 混合表1所示之陶瓷固體粒無機玻璃之材料成分,接著 添加聚合黏合劑及可塑劑形成陶瓷條。該陶瓷條係使澆鑄 漿料通過厚度約 5 0微米之刮刀之下而成型。燒結溫度 (Ts)、介電常數(K)及品質因子(Q)亦說明於表1。 表1 : 實例 無機玻璃(B) 陶瓷固體粒(c) B/C Ts K Q 1 87% Bi203-3% B203-l〇%Te02 Ba(SmNd)2Ti5〇i4 30/70 745 55 450 2 87% Bi2〇3-3% B2O3-10%Te〇2 Ba(SmNd)2Ti5〇i4 50/50 632 40 320 3 87% Bi2〇3-3% B2O3-10%Te〇2 Ba(SmNd)2Ti5〇i4 70/30 545 38 ISO 4 65% Bi203-2.5% B2〇3-32.5%Te02 Ba(SmNd)2Ti5〇i4 65/35 635 37 250 5. 65% Bi203-2.5% B2〇3-32.5%Te02 Ba(SmNd)2Ti5014 50/50 666 46 340 6 16% Bi203-14% B2O3-70%TeO2 Ba(SmNd)2Ti5〇i4 20/80 680 65 421 O:\82\82936.DOC 14 1229351 (10) 7 16% Bi2〇3-14% B2〇3-70%TeO2 Ba(SmNd)2Ti5〇i4 30/701 577 I 60 1350 8 87% Bi203-3% B2〇3-l〇%Te02 BaTi03 65/35 677 850 150 9 87% Bi2〇3-3% B2O3-10%TeO2 BaTi03 50/50 760 1100 175 10 65% Bi203-2.5% B203-32.5%Te〇2 BaTi03 40/60 938 1500 230 11 65% Bi203-2.5% B203-32.5%Te02 BaTi03 65/35 834 700 145 12 65% Bi203-2.5% B2〇3-32.5%Te02 Si02 65/35 630 4 225 13 65% Bi203-2.5% B2〇3-32.5%Te02 AI2O3 65/35 710 5 350 14 65% Bi203-2.5°/〇 B2〇3-32.5%Te02 3Al203-2Si02 65/35 675 4 320 15 65% Bi2〇3-2.5% B203-32.5%Te02 Mg2Al4Sl5〇i8 65/35 665 3.5 250 實例1 6 :積層陶瓷組合物之收縮率 將實例1之介電層及Du Pont 95 1 PT®層經衝打通孔, 填充及網印電路。再將該等層堆疊及在4,0 0 0 p s i及6 0 °C 層壓1 0分鐘後燒製。測量具不同比例之實例1介電層及 Du Pont 951 PT⑧層之陶瓷組合物於X及Y方向之收縮 率’其結果示於圖2。 如圖2所示,本發明積層陶竞組合物X及γ方向之收 縮率相當低,顯示該兩層材料可有效避免彼此之收縮。 雖然已說明及描述本發明,但熟知本技藝者可作各種修 飾及改良。需了解本發明不限於所說明之特定形式,且不 達離本發明精神及範圍之所有修飾均在申請專利範圍所 界定之範圍内。 【圖式簡單說明】 圖1說明本發明積層陶瓷組合物之一具體實施例截面 示意圖。 圖2說明當共燒不同厚度比例之Μ1層及M2層時所測 O:\82\82936.DOC -15- 1229351 _ do 量之收縮率,其中Μ1代表實例1之介電材料,及M2代 表習知低溫共同燒結陶瓷(產品名稱為< Du Pont 95 1 PT⑧)。 【元件符號簡單說明】 I 積層陶竞組合物 II 介電材料層M i 12 介電材料層M2 13 導體 14 電極 1 5 被動元件 16 金屬化圖案 , O:\82\82936.DOC 16-1229351 (9) On the electric material layer m2. The invention has many advantages: (1) due to laminated ceramics; each layer of the composition can be used as a substrate for embedding passive components without the need for a buffer layer and / or a barrier layer of the prior art. The size can be considerably reduced to meet the requirements of light, thin and small products of modern electronic products; (2) the design of the two material layers M 1 and M 2 to avoid shrinking with each other, X and X of the ceramic composition of the present invention The 'direction Y' does not shrink. Therefore, the accuracy of the circuit designed on it can be improved considerably, and the yield is improved; (3) From the viewpoint of the lack of a buffer layer, a barrier layer and / or a metal support, the cost can be reduced; (4) by combining Ceramic solid particles and inorganic glass can be made into a series of materials with varying dielectric constants and quality factors, so they can be used for electrical properties of different purposes. The following examples are for illustrative purposes only and are not intended to limit the invention. Examples 1 to 15: Dielectric material layer The material components of the ceramic solid particulate inorganic glass shown in Table 1 were mixed, and then a polymer binder and a plasticizer were added to form a ceramic bar. The ceramic strip is formed by casting the casting slurry under a blade having a thickness of about 50 microns. The sintering temperature (Ts), dielectric constant (K) and quality factor (Q) are also described in Table 1. Table 1: Examples of inorganic glass (B) ceramic solid particles (c) B / C Ts KQ 1 87% Bi203-3% B203-10% Te02 Ba (SmNd) 2Ti5〇i4 30/70 745 55 450 2 87% Bi2 〇3-3% B2O3-10% Te〇2 Ba (SmNd) 2Ti5〇i4 50/50 632 40 320 3 87% Bi2〇3-3% B2O3-10% Te〇2 Ba (SmNd) 2Ti5〇i4 70 / 30 545 38 ISO 4 65% Bi203-2.5% B2 03-32.5% Te02 Ba (SmNd) 2Ti5〇i4 65/35 635 37 250 5. 65% Bi203-2.5% B2 03-32.5% Te02 Ba (SmNd) 2Ti5014 50/50 666 46 340 6 16% Bi203-14% B2O3-70% TeO2 Ba (SmNd) 2Ti5〇i4 20/80 680 65 421 O: \ 82 \ 82936.DOC 14 1229351 (10) 7 16% Bi2〇 3-14% B2〇3-70% TeO2 Ba (SmNd) 2Ti5〇i4 30/701 577 I 60 1350 8 87% Bi203-3% B2〇3-l0% Te02 BaTi03 65/35 677 850 150 9 87% Bi2〇3-3% B2O3-10% TeO2 BaTi03 50/50 760 1100 175 10 65% Bi203-2.5% B203-32.5% Te〇2 BaTi03 40/60 938 1500 230 11 65% Bi203-2.5% B203-32.5% Te02 BaTi03 65/35 834 700 145 12 65% Bi203-2.5% B2〇3-32.5% Te02 Si02 65/35 630 4 225 13 65% Bi203-2.5% B2 03-32.5% Te02 AI2O3 65/35 710 5 350 14 65% Bi203-2.5 ° / 〇B2〇3-32.5% Te02 3Al203-2Si02 65/35 675 4 320 15 65% B i203-2.5% B203-32.5% Te02 Mg2Al4Sl50i8 65/35 665 3.5 250 Example 16: Shrinkage of laminated ceramic composition The dielectric layer and Du Pont 95 1 PT® layer of Example 1 were punched through holes , Filling and screen printing circuits. The layers were stacked and laminated at 4,000 p s i and 60 ° C for 10 minutes and fired. The shrinkage ratios in the X and Y directions of the ceramic composition of Example 1 dielectric layer and Du Pont 951 PT⑧ layer with different ratios were measured. The results are shown in FIG. 2. As shown in FIG. 2, the shrinkage ratios of the laminated ceramic composition of the present invention in the X and γ directions are relatively low, indicating that the two layers of materials can effectively avoid shrinking with each other. Although the present invention has been illustrated and described, those skilled in the art can make various modifications and improvements. It should be understood that the present invention is not limited to the specific forms described, and all modifications that do not depart from the spirit and scope of the invention are within the scope defined by the scope of the patent application. [Brief description of the drawings] FIG. 1 illustrates a schematic cross-sectional view of a specific embodiment of a laminated ceramic composition of the present invention. Figure 2 illustrates the measured shrinkage of O: \ 82 \ 82936.DOC -15-1229351 _ do when co-firing different thickness ratios of M1 and M2 layers, where M1 represents the dielectric material of Example 1, and M2 represents Common low temperature co-sintered ceramics (product name < Du Pont 95 1 PT⑧). [Simple description of element symbols] I Multilayer ceramic composition II Dielectric material layer M i 12 Dielectric material layer M2 13 Conductor 14 Electrode 1 5 Passive element 16 Metallized pattern, O: \ 82 \ 82936.DOC 16-

Claims (1)

1229351 拾、申請專利範圍 1. 一種積層陶瓷:組合物,包括: 至少一層具有介電常數Κι之介電材料層Μι,且其 内具有至少一個内埋式被動元件;及 至少一層具^介電常數κ2之介電材料層M2,且其 内具有至少一·個内埋式被動元件,其係設置在該介電 材料層Ml之下方; 其中Κι與K2不同,且介電材料層Μι及介電材料 層M2可在燒製時避免彼此於X及Y方向之收縮。 2 ·如申請專利範圍第1項之組合物,其中K1及K2介於4 至2000之間。 3 ·如申請專利範圍第1項之組合物,其中Μ1及Μ2中至 少一層包括陶瓷固體粒及無機玻璃。 4.如申請專利範圍第3項之組合物,其中該陶資固體粒 係選自由無機金屬、而溶點無機固體粒及南軟化點玻 璃所成之組群。 5 ·如申請專利範圍第4項之組合物,其中該陶瓷固體粒 係選自由鋇鈦氧化物、鋇釤鈮鈦氧化物、矽氧化物、 鋁氧化物、鎂鋁矽氧化物及其混合物所成之組群。 6 ·.如申請專利範圍第3項之組合物,其中該無機玻璃係 選自由鉍氧化物、碲氧化物、硼氧化物、其前驅物及 1229351 其混合物所成之組群。 7 .如申請專利範圍第3項之組合物/其中該無機玻璃之 量為介於0.5至98重量%之間。 8 .如申請專利範圍第1項之組合物,其中該介電材料Μ! 之燒結溫度為ir!及該介電材料M2之燒結溫度為T2, 且Ti大於Τ2 0 . * 9·如申讀專利範圍第8項之組合物,其中+ 。 10. 申請專利範圍第8項之組合物,其中當介電材料層M2 在T2燒結時,其X及Y方向之收縮受到在T2尚未收 縮之介電材料層Μι所抑制,且當介電材料Μι在至h 燒結時,其X及Y方向之收縮受到已完成收縮之介電 材料層M2所抑制。 11. 如申請專利範圍第8項之組合物,其中Τι及T2介於 45 0°C 至 1 200°C 之間。 12·如申請專利範圍第1 1項之組合物,其中Τι及T2係低 於 9 60°C。 13. 如申請專利範圍第1項之組合物,其中内埋式被動元 間包含印刷在至少一層介電材料層Μ 1及至少一層介 電材料層Μ2上之金屬化圖案。 14. 如申請專利範圍第1 3項之組合物,其中該金屬化圖案 包含在該介電材料層内之複數個相對電極。 O:\82\82936.DOC 12293511229351 Patent application scope 1. A laminated ceramic: a composition comprising: at least one layer of a dielectric material layer having a dielectric constant Km, and having at least one embedded passive element therein; and at least one layer having a dielectric The dielectric material layer M2 with a constant κ2, and has at least one embedded passive element therein, which is disposed below the dielectric material layer M1; where Km is different from K2, and the dielectric material layer Mm and the dielectric The electrical material layer M2 can avoid shrinking with each other in the X and Y directions during firing. 2. The composition according to item 1 of the patent application range, wherein K1 and K2 are between 4 and 2000. 3. The composition according to item 1 of the patent application scope, wherein at least one of M1 and M2 includes ceramic solid particles and inorganic glass. 4. The composition according to item 3 of the patent application range, wherein the ceramic solid particles are selected from the group consisting of inorganic metals, melting solid inorganic particles and southern softening point glass. 5. The composition according to item 4 of the application, wherein the ceramic solid particles are selected from the group consisting of barium titanium oxide, barium hafnium niobium titanium oxide, silicon oxide, aluminum oxide, magnesium aluminum silicon oxide, and mixtures thereof. Into groups. 6. The composition according to item 3 of the scope of patent application, wherein the inorganic glass is selected from the group consisting of bismuth oxide, tellurium oxide, boron oxide, its precursor, and a mixture of 1229351. 7. The composition according to item 3 of the patent application / wherein the amount of the inorganic glass is between 0.5 and 98% by weight. 8. The composition according to item 1 of the scope of patent application, wherein the sintering temperature of the dielectric material M! Is ir! And the sintering temperature of the dielectric material M2 is T2, and Ti is greater than T2 0. * 9 · As stated in the application The composition of item 8 of the patent, wherein +. 10. The composition of the scope of patent application item 8, wherein when the dielectric material layer M2 is sintered at T2, the shrinkage in the X and Y directions is suppressed by the dielectric material layer M1 that has not contracted at T2, and when the dielectric material When Mm sinters to h, its shrinkage in the X and Y directions is suppressed by the dielectric material layer M2 that has completed shrinkage. 11. If the composition of the scope of application for item 8 of the patent, wherein Ti and T2 are between 45 ° C and 1200 ° C. 12. The composition according to item 11 of the patent application scope, in which Ti and T2 are lower than 9 60 ° C. 13. The composition as claimed in claim 1, wherein the embedded passive cell includes a metallized pattern printed on at least one dielectric material layer M1 and at least one dielectric material layer M2. 14. The composition according to item 13 of the patent application scope, wherein the metallization pattern comprises a plurality of opposing electrodes in the dielectric material layer. O: \ 82 \ 82936.DOC 1229351 15. 如申請專利範圍第1 3項之組合物,進一步包括通過該 介電材料層之通孔導體,而電性連結該内埋式被動元 件及金屬化圖案。 16. 如申請專利範圍第1項之組合物,其中該内埋式被動 元件包括已裝配完成之被動元件。 17. 如申請專利範·圍第1項之組合物,其中該内埋式被動 元件係選自由電容、電阻及電感所成之組群。 18. 如申請專利範圍第1項之組合物,進一步包括一覆蓋 介電層。 O:\82\82936.DOC15. The composition according to item 13 of the scope of patent application, further comprising electrically connecting the embedded passive element and the metallized pattern through the through-hole conductor of the dielectric material layer. 16. The composition of claim 1 in which the embedded passive component includes a passive component that has been assembled. 17. The composition according to claim 1 in which the embedded passive component is selected from the group consisting of a capacitor, a resistor and an inductor. 18. The composition according to item 1 of the patent application scope, further comprising a covering dielectric layer. O: \ 82 \ 82936.DOC
TW92109057A 2003-04-18 2003-04-18 Multilayer ceramic composition TWI229351B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92109057A TWI229351B (en) 2003-04-18 2003-04-18 Multilayer ceramic composition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92109057A TWI229351B (en) 2003-04-18 2003-04-18 Multilayer ceramic composition

Publications (2)

Publication Number Publication Date
TW200423155A TW200423155A (en) 2004-11-01
TWI229351B true TWI229351B (en) 2005-03-11

Family

ID=36071054

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92109057A TWI229351B (en) 2003-04-18 2003-04-18 Multilayer ceramic composition

Country Status (1)

Country Link
TW (1) TWI229351B (en)

Also Published As

Publication number Publication date
TW200423155A (en) 2004-11-01

Similar Documents

Publication Publication Date Title
US5757611A (en) Electronic package having buried passive components
EP0806056B1 (en) Glass bonding layer for a ceramic circuit board support substrate
US6337123B1 (en) Multilayered ceramic substrate and method of producing the same
US6588097B2 (en) Method of manufacturing multilayered ceramic substrate and green ceramic laminate
US7722732B2 (en) Thick film paste via fill composition for use in LTCC applications
JP2001060767A (en) Method for manufacturing ceramic board and unfired ceramic board
US5953203A (en) Multilayer ceramic circuit boards including embedded capacitors
JP5032772B2 (en) Low temperature co-fired ceramic structure and manufacturing method thereof
JP2002520878A (en) Method for producing a ceramic body with integrated passive electronic components, a body of this kind and the use of the body
US6893710B2 (en) Multilayer ceramic composition
US6776862B2 (en) Multilayered ceramic board, method for fabricating the same, and electronic device using multilayered ceramic board
KR20060050106A (en) High thermal cycle conductor system
TWI229351B (en) Multilayer ceramic composition
JP4578134B2 (en) Glass ceramic multilayer wiring board with built-in capacitor
KR100289959B1 (en) Manufacturing method of embedded capacitor of low temperature simultaneous firing ceramic
JP4688460B2 (en) Glass ceramic multilayer wiring board with built-in capacitor
KR100607119B1 (en) Multilayer ceramic composition
JP4077625B2 (en) Low temperature fired porcelain composition and method for producing low temperature fired porcelain
EP1471041A1 (en) Multilayer ceramic composition
JP2004200679A (en) Manufacturing method for multilayer circuit substrate
JP4658465B2 (en) Glass ceramic multilayer wiring board with built-in capacitor
JP2004119547A (en) Ceramic wiring board and its manufacturing method
JP2004319919A (en) Multilayer ceramic component
JP4623851B2 (en) Multilayer wiring board
JP2002368421A (en) Multilayer ceramic board and method for manufacturing the same