JP2004319919A - Multilayer ceramic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic component for preventing electric characteristics from being changed and/or a dielectric material layer from shrinking during baking. <P>SOLUTION: The multilayer ceramic component includes a dielectric material M<SB>1</SB>that is at least a layer of dielectric material M<SB>1</SB>having permittivity K<SB>1</SB>and has at least one passive element buried into the dielectric material M<SB>1</SB>; and a dielectric material M<SB>2</SB>that is at least a layer of dielectric material M<SB>2</SB>having permittivity K<SB>2</SB>, has at least one passive element buried into the dielectric material M<SB>2</SB>and is arranged under the layer of the dielectric material M<SB>1</SB>. In this case, K<SB>1</SB>differs from K<SB>2</SB>, and the layer of the dielectric material M<SB>1</SB>and that of the dielectric material M<SB>2</SB>prevent X and Y dimensions from shrinking during baking. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

（実施例１６：多層セラミック構成物の収縮率）
実施例１に従う誘電層およびＤｕ Ｐｏｎｔ ９５１ ＰＴ（登録商標）の層を、バイアパンチし、バイア充填し、そして回路にスクリーンプリントした。これらの層を積み重ね、そして４，０００ｐｓｉおよび６０℃で１０分間かけて積層し、そして焼付けした。実施例１に従う誘電層およびＤｕ Ｐｏｎｔ ９５１ＰＴ（登録商標）層の異なる比率を有するセラミック構成物のＸ寸法およびＹ寸法における収縮比を、測定し、そして図２に例示する。
【００５４】
図２に示されるように、本発明に従う多層セラミック構成物のＸ寸法およびＹ寸法における収縮比はかなり低く、２種の材料の層が互いの収縮を有効に防止し得ることを示した。
【００５５】
本発明の実施形態を例示し、そして記載してきたが、種々の改変および改良が、当業者によってなされ得る。本発明が、例示されるような特定の形態に限定されないこと、およびこれらの改良の全てが、本発明の精神および範囲から逸脱することなく、添付の特許請求の範囲に規定される範囲内にあることが、意図される。
【００５６】
本発明は、少なくとも１層の誘電材料Ｍ_１および少なくとも１層の誘電材料Ｍ_２を含む、多層セラミック構成物を提供し、ここで、受動素子が、誘電材料Ｍ_１およびＭ_２の両方の層に埋め込まれ、焼付けの間に、Ｘ寸法およびＹ寸法が互いに収縮するのを防止する。本発明に従って、多層セラミック構成物の各層は、受動素子を埋め込むための基板として使用され得、そして異なる誘電率を有する他の層が収縮するのを防止する能力を有する。従って、多層セラミック構成物が、小さな大きさの利点および回路の良好な精度を有する。
【００５７】
【発明の効果】
本発明により、焼付けの間に、電気的特性の変化および／または誘電材料層の収縮が生じない多層セラミック構成物が得られる。
【図面の簡単な説明】
【図１】図１は、本発明に従う多層セラミック構成物の１実施形態の概略断面図を示す。
【図２】図２は、異なる厚さ比のＭ_１層およびＭ_２層が同時焼付けされる場合に測定された収縮率を示す。ここで、Ｍ_１は、実施例１に従う誘電材料を指し、そしてＭ_２は、従来の低温で同時焼付けされたセラミック（Ｄｕ Ｐｏｎｔ ９５１ ＰＴ（登録商標）との名前の製品）を指す。
【符号の説明】
１ 多層セラミック構成物
１１ 誘電材料Ｍ_１の層
１２ 誘電材料Ｍ_２の層
１３ バイア導体
１５ 受動素子
１６ 金属化パターン[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to ceramic components, and more particularly to multilayer ceramic components for the performance of electronic microwave systems.
[0002]
[Prior art]
Interconnect circuit boards are necessary for modern electronic products to meet the requirements of being lightweight, thin and small. An interconnect circuit board is an electronic circuit that is electrically or mechanically interconnected with each other or with subsystems such as a large number of extremely small passive elements and metallization patterns integrated into an arrangement. is there. Such passive components and metallization patterns can be physically isolated and embedded adjacent to one another in a single interconnect circuit board, electrically connected to each other, and / or thereby interconnected Extends from the circuit board. These days, ceramic components are commonly applied to interconnect circuit boards.
[0003]
In ceramic constructions, complex electronic circuits generally require several insulating dielectric layers to separate the layers of the conductor. To meet the requirements of different dielectric constants (K), suitable for the fabrication or embedding of passive elements and metallization patterns, a series of dielectric materials with different dielectric constants are required. For example, in the signal processing portion of the ceramic structure, low dielectric constant materials are preferred to improve the speed of signal propagation and provide faster processing; and when making capacitors as embedded passives. Is preferably a material having a high dielectric constant. The conductive path that interconnects the passive element and the metallization pattern through the dielectric layer is called a via. Such a multilayer structure allows the circuit to be smaller and take up less space.
[0004]
A multilayer ceramic in which passive components and metallization patterns (eg, resistors, capacitors, or wires) are printed with metallized vias extending through the dielectric layer to interconnect the various passive components and metallization patterns. A method for co-firing a composition is described, which is incorporated herein by reference (see, for example, US Pat. Ceramic powders can be densified at temperatures compatible with the use of high conductivity metallizations such as gold, silver, and copper. In particular, densification is achieved below 1000 ° C. to provide a distribution of errors well away from the melting point of gold (1060 ° C.). The dielectric layers are layered in register and pressed together at the appropriate temperature and pressure and then baked to drive out organics such as binders and plasticizers in the green ceramic body. All of the ceramic and dissimilar materials are sintered and thereby densified. This method has the advantages of performing only one bake, saving fabrication time and effort, and limiting the diffusion of movable metal so as to prevent shorts between conductive layers.
[0005]
However, simultaneous firing of monolithic structures having high and low K dielectric constant materials is problematic. One of these problems is the change in electrical properties, and the other is the shrinkage mismatch that occurs during baking.
[0006]
With respect to changes in electrical properties, many conventional assemblies utilize low and high dielectric constant materials, which include glass, resulting in increased dielectric constant and loss. And this high dielectric constant material includes lead, magnesium and niobium. However, when low and high dielectric constant materials come in contact at temperatures higher than 800 ° C. during the co-firing process, a chemical reaction occurs due to interfacial diffusion. For this reason, the dielectric constants of both low and high dielectric constant materials change. Usually, a dramatic drop in high dielectric constant materials occurs.
[0007]
Several buffer layers intervening between the low and high dielectric constant materials of an electronic package have been disclosed (see US Pat. No. 6,037,045). Buffer layers containing 25-100% barium compounds provide an additional physical barrier during the initial stages of densification by creating a more difficult path for chemical diffusion. Vias may also be formed through the buffer layer for electrical conduction of the passive component portion and the signal processing portion. The glass forming additives and the inorganic filler control the shrinkage, thermal expansion and chemical compatibility of the buffer layer in contact with either the high K dielectric layer of the passive component part or the low K dielectric layer of the signal processing part. On the other hand, the buffer layer increases the thickness of the electronic package and therefore cannot serve as a good substrate at all for embedding passive components.
[0008]
Other multi-layer ceramic green tape structures having different K are also shown (see, for example, US Pat. No. 6,037,045), which is screen printed on low sintering temperature green tape. And inks that form embedded components (eg, capacitors) with tight tolerances and high precision placement. The capacitor layer is sandwiched between two barium titanate barrier layers, the barrier layer having a sufficient thickness to prevent diffusion of the low sintering temperature glass of the green tape. Further, the multilayer ceramic green tape structure is bonded to the metal support substrate by bonding glass to prevent shrinkage. However, the shrinkage ratio of the low sintering temperature green tape and the metal support substrate is different and should be well controlled during sintering to avoid breakage. Moreover, the thickness of the multilayer ceramic green tape structure cannot be reduced yet.
[0009]
With respect to shrinkage, sintering conditions are difficult to control due to shrinkage of the element when the shrinkage is not the same. Furthermore, this uncertainty in the X and Y dimensions, which results in misalignment during assembly of large and complex circuits, is particularly undesirable. A method is disclosed for reducing shrinkage during firing of a green ceramic body (see, for example, US Pat. A release layer is applied to each of the top and bottom of the green ceramic body to form a "sandwich" structure. During the complete burning out and sintering, non-directional pressure is applied to the surface of the release layer. The porosity of the release layer provides an escape passage for volatile components of the green ceramic body. Since the release layer does not shrink during baking, shrinkage in the X and Y dimensions of the green ceramic body is reduced. On the other hand, the release layer covers both the top and bottom surfaces of the green ceramic layer, and the removal of these release layers is necessary to print and sinter the conductors, resistors, and capacitors. Should be done after the conclusion. Thus, the costs for the method increase. When making multiple ceramic layers (e.g., more than 6 layers), the layers of the central green ceramic body are evenly distributed by applying a release layer to the top and bottom of the green ceramic body. As a result of the forces that do not (i.e., the forces on the top and bottom of the green body and the central layer are quite different), they still contract.
[0010]
Some modifications of the green ceramic body have been disclosed in which a constraining layer to prevent shrinkage is secured between the layers of the green ceramic body (see, for example, US Pat. Has been done. The constraining layer remains in the final product and prevents the disadvantage of removal. However, the limiting layer is not a suitable dielectric material; therefore, the thickness of the product increases.
[0011]
[Patent Document 1]
U.S. Pat. No. 4,654,095
[Patent Document 2]
US Pat. No. 5,757,611
[Patent Document 3]
US Patent No. 6,055,151
[Patent Document 4]
US Pat. No. 5,085,720
[Problems to be solved by the invention]
Conventional ceramic components have the problem that during baking, changes in electrical properties and / or shrinkage of the dielectric material layer occur.
[0016]
[Means for Solving the Problems]
In one aspect, the invention is a multilayer ceramic composition, comprising:
Having a dielectric constant K _1, having a dielectric material M ₁ at least one layer, at least one of the embedded passive components in the dielectric material M _1, a dielectric material M _1;
Having a dielectric constant K _2, a dielectric material M ₂ at least one layer has at least one of the embedded passive components in the dielectric material M _2, it is arranged below the layer of the dielectric material M ₁ The dielectric material M ₂ ,
Including
Here, K ₁ is different from K ₂ and the layer of dielectric material M _{1 and} the layer of dielectric material M ₂ prevent the X and Y dimensions from shrinking during baking,
A multilayer ceramic composition is provided.
[0017]
In a preferred embodiment, _{K 1} and _{K 2,} can be from about 4 to about 2000 range.
[0018]
In a preferred embodiment, at least one of M ₁ and M ₂ may include a ceramic solid and an inorganic glass.
[0019]
In a preferred embodiment, the ceramic solid may be selected from the group consisting of an inorganic metal, a high melting inorganic solid, and a high softening point glass.
[0020]
In a preferred embodiment, the ceramic solid may be selected from the group consisting of barium titanium oxide, barium samarium neodymium titanium oxide, silicon oxide, aluminum oxide, magnesium aluminum silicon oxide, and mixtures thereof.
[0021]
In a preferred embodiment, the inorganic glass may be selected from the group consisting of bismuth oxide, tellurium oxide, boron oxide, precursors thereof, and mixtures thereof.
[0022]
In a preferred embodiment, the amount of inorganic glass can range from about 0.5 to about 98% by weight.
[0023]
In a preferred embodiment, the sintering temperature of the dielectric material M ₁ is a T _1, and the sintering temperature of the dielectric material M ₂ is a T ₂ and T _1, is may be higher than T ₂ .
[0024]
In a preferred embodiment, T ₁ > T ₂ + 50 ° C.
[0025]
In a preferred embodiment, the layer of dielectric material M ₂ is, when sintered at T _2, contraction of the X and Y dimensions are prevented by said layer of dielectric material M ₁ which does not sintered at T ₂ and the dielectric material, a layer of M ₁ is, when sintered at T _1, contraction of the X and Y dimensions, may be prevented by a layer of the dielectric material M ₂ which shrinkage is complete.
[0026]
In a preferred embodiment, _{T 1} and _{T 2,} can range from about 450 ° C. ~ about 1200 ° C..
[0027]
In a preferred embodiment, T ₁ and T ₂ can be less than about 960 ° C.
[0028]
In a preferred embodiment, the embedded passive device may comprise a dielectric material M ₁ and at least one layer of dielectric material M ₂ printed metallization pattern on the at least one layer.
[0029]
In a preferred embodiment, the metallization pattern may include a plurality of inverted electrodes in the dielectric material layer.
[0030]
In a preferred embodiment, the composition may further comprise a conductor passing through the layer of dielectric material to electrically connect the embedded passive element and the metallization pattern.
[0031]
In a preferred embodiment, the embedded passive elements may include constructed passive elements.
[0032]
In a preferred embodiment, the embedded passive device may be selected from the group consisting of a capacitor, a resistor, and an inductor.
[0033]
In a preferred embodiment, the composition may further include an overlying dielectric layer.
[0034]
In order to solve the above-mentioned problems, the present invention reduces shrinkage in the X and Y dimensions when co-firing two dielectric materials having different dielectric constants and a passive element embedded therebetween. This develops novel multilayer ceramic constructions that have the advantages of reduced size and better circuit accuracy.
[0035]
The present invention provides a multi-layer ceramic construction comprising at least one layer of dielectric material M ₁ and at least one layer of dielectric material M ₂ , wherein the passive element comprises both layers of dielectric material M ₁ and M ₂ , Which prevent each other from shrinking in the X and Y dimensions during baking. Each layer of the multilayer ceramic construction according to the present invention can be used as a substrate for embedding passive elements and has the ability to prevent other layers with different dielectric constants from shrinking. Thus, this multilayer ceramic construction has the advantages of reduced size and better circuit accuracy.
[0036]
One object of the present invention is as follows:
Has a dielectric constant of K _1, at least one passive element is embedded therein, the dielectric material M ₁ at least one _layer; has a dielectric constant of, and K _2, and at least one passive element is embedded therein the, a dielectric material M ₂ at least one layer, is fixed to the lower layers of dielectric material M _1, a dielectric material M _2;
Wherein K ₁ is different from K ₂ and the layers of dielectric material M ₁ and M ₂ exhibit shrinkage in the X and Y dimensions during baking. To provide a multilayer ceramic composition, which prevents each other.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention provides a multilayer ceramic composition, comprising:
Having at least one embedded passive devices therein, at least one layer of dielectric material M ₁ having a dielectric constant K _1; set under and dielectric material M ₁ layer, at least one therein with embedded passive elements, at least one layer of dielectric material M ₂ having a dielectric constant K _2;
Including
Here, K _1, unlike K _2, and the layer and the layer of dielectric material M ₂ of dielectric material M ₁ prevents shrinkage in the X and Y dimensions between baking each other.
[0038]
The embodiment of the multilayer ceramic composition 1 according to the invention shown in FIG. 1 comprises a plurality of layers 11 of a dielectric material M ₁ having a dielectric constant K ₁ and a plurality of layers 12 of a dielectric material M ₂ having a dielectric constant K _2. And K ₁ is different from K ₂ . Both dielectric material M ₁ layer 11 and the dielectric material M ₂ of layer 12 can be used as a substrate for embedding the passive element 15. Preferably, the metallization pattern 16, on the layer 12 of dielectric material M ₁ layer 11 and the dielectric material M _2, is produced by applying a conductive metal in an amount selected in the selected pattern. Many vias can also be drilled through layers 11,12, these can be openings through layers 11,12, and via conductors 13 can be placed in these vias and passivated with passive elements 15 and metallization. The pattern 16 can be electrically connected.
[0039]
In a preferred embodiment of the present invention, the ceramic construction further comprises an overlying dielectric layer, which has no passive elements or printed metallization patterns thereon.
[0040]
As used herein, the term "embedded passive device" refers to an embedded, manufactured passive device, and an electrical device made from dielectric layers and metallized patterns and / or via conductors. Say. For example, manufactured passive elements include capacitors, resistors, and inductors. In particular, a metallization pattern 16 in layer 11 or 12 may comprise a plurality of opposing electrodes 14 together with layer 11 or 12 to form a capacitor. The metallization pattern 16 between the layers 11 or 12 forms various signal processing devices (eg, transmit / receive (T / R) modules, etc.).
[0041]
The metallization pattern 16 and via conductor 13 preferably comprise a highly conductive material (such as, for example, gold, silver, copper and their alloys), and more preferably silver (which has a melting point of 960 ° C.). Having). Therefore, the densification of the multilayer ceramic structure 1 must be performed at a temperature lower than the melting point of the specific conductive material forming the metallization pattern 16. In addition, different circuit designs require materials with different dielectric constants.
[0042]
Dielectric materials that may be used to produce the dielectric layer according to the present invention are suitable for use as M ₁ and M _2. According to a preferred embodiment of the present invention, at least one of the materials M ₁ and M ₂ comprises a ceramic solid and an inorganic glass providing suitable electrical properties.
[0043]
As used herein, the term "ceramic solids" refers to those solids that are chemically inert with respect to other materials in the system and that are incompatible with other components of the dielectric material system. Refers to components that are not directly important, as long as they have the following physical properties in comparison: (1) they have a sintering temperature well above the sintering temperature of the inorganic glass, and (2) they Does not undergo sintering during the baking step of the present invention. Examples of ceramic solids include inorganic metals, high melting inorganic solids, and high softening point glasses. In a more preferred embodiment, the ceramic includes barium titanium oxide, barium samarium neodymium titanium oxide, silicon oxide, aluminum oxide, magnesium aluminum silicon oxide, and mixtures thereof. Further, a ceramic solid can be selected based on both its dielectric and thermal expansion properties. Accordingly, mixtures of such materials can be selected to match the thermal expansion characteristics of any substrate to which they are applied.
[0044]
As used herein, the term "inorganic glass" refers to an inorganic material that is chemically inert to other materials in the system and has the appropriate physical properties as follows: : (1) it has a sintering temperature well below the sintering temperature of the ceramic; and (2) it undergoes viscous flow sintering at the baking temperature used. Inorganic glasses suitable for the present invention are usually glasses, in particular glasses that crystallize or do not crystallize on baking. In a more preferred embodiment, the inorganic glass is selected from the group consisting of bismuth oxide, tellurium oxide, boron oxide, or precursors thereof, and mixtures thereof, in an amount ranging from about 0.5 to about 98% by weight. You.
[0045]
Ceramic solids and inorganic glass are dispersed in a polymer binder. The polymer binder optionally has other materials dissolved therein, such as plasticizers, release agents, dispersants, stripping agents, defoamers and wetting agents. Any polymer binder known in the art useful for producing low temperature co-fired ceramics is suitable for use in the present invention.
[0046]
The combination of ceramic solids and inorganic glass results in a series of materials with different dielectric constants and sintering temperatures. Preferably, the dielectric constant of the dielectric material according to the present invention ranges from about 4 to about 2000. In another aspect, the sintering temperature of the dielectric material according to the present invention is in the range of about 450 ° C. to about 1200 ° C., more preferably, the sintering temperature is such that the co-bake with silver in the ceramic component. Below about 960 ° C.
[0047]
In accordance with the present invention, a layer of dielectric material M ₁ and M ₂ are disposed in contact with each other, to prevent shrinkage in the X and Y dimensions. Thus, all shrinkage occurs in the Z dimension. Mechanism for preventing shrinkage depends on the difference in the sintering temperature of the material M ₁ and M _2. For example, the sintering temperature of the dielectric material _{M 1} is _{T 1,} and the sintering temperature of the dielectric material _{M 2} is _{T 2, T 1} is greater than _{T 2.} A layer of dielectric material M ₂ is, when initiating a sintered at T _2, shrinkage in the X and Y dimensions is prevented and reduced by a layer of dielectric material M ₁ which does not still shrink at T _2. At this point, the layers of dielectric material M _1, play the role of the constraining layer to prevent the shrinkage of the layer of dielectric material M _2. If the temperature is raised to T _1, the layer of dielectric material M _2, to complete the sintering and without further shrinkage, therefore, shrinkage in the X and Y dimensions of the layer of dielectric material M _1, the dielectric material It is prevented and reduced by a layer of M _2. Preferably, T ₁ is higher than T ₂ + 50 ° C. to achieve a better effect of preventing shrinkage.
[0048]
In accordance with the present invention, coupling the glass, between the layers of dielectric material M ₂ of dielectric material M _1, it is added as required. Bonding glass can be used regardless of whether a Z-direction force is applied during baking. This force is sufficient for the layers of the multilayer ceramic component to come into contact with each other and, as a result, substantially causes all shrinkage in the Z direction perpendicular to the ceramic component. That is, the X and Y dimensions of the ceramic component do not shrink during baking. Binder glass should be used when no pressure is applied. Binding glass may be in the form of M ₁ material and / or M ₂ or materials may be added directly to, or bound glass layer between the dielectric material M ₁ layer and the layer of dielectric material M _2. The binding glass layer is prepared by dissolving the ink glass particles in a suitable solvent, and either directly coated by spotter deposition or vapor deposition, layers and / or layers of dielectric material M ₂ of dielectric material M ₁ Printed on
[0049]
The present invention has many advantages. (1) Since all layers of the multilayer ceramic construction can act as a substrate for embedding passive components without the need for buffer and / or barrier layers in the prior art, the overall size of this ceramic construction is greatly increased It has been reduced to meet the lightness, thinness and small size requirements for modern electronic products. (2) to prevent the mutual contraction, the design of the two materials M ₁ and M ₂ layers, shrinkage in the X and Y dimensions of the ceramic composition according to the present invention does not occur. Therefore, the accuracy of the circuit designed thereon is greatly improved, and thereby the production volume is increased. (3) costs are reduced in the absence of buffer layers, barrier layers and / or metal supports; (4) By combining ceramic solids and inorganic glasses, a range of materials with different dielectric constants and quality factors are made, which can be applied for different intended electronic properties.
[0050]
【Example】
The following examples are given for illustrative purposes only and are not intended to limit the scope of the invention.
[0051]
(Examples 1 to 15: Layer of dielectric material)
As shown in Table 1, the ceramic solid and inorganic glass material components were mixed, and then a polymer binder and a plasticizer were added to form a ceramic slip. The ceramic slip was formed by passing the cast slurry under a blade having a thickness of about 50 μm. Table 1 also shows the sintering point (Ts), the dielectric constant (K), and the quality factor (Q).
[0052]
(Table 1 :)
[0053]
[Table 1]

(Example 16: Shrinkage rate of multilayer ceramic component)
The dielectric layer according to Example 1 and a layer of Du Pont 951 PT® were via punched, via filled, and screen printed on the circuit. The layers were stacked and laminated at 4,000 psi and 60 ° C. for 10 minutes and baked. The shrinkage ratio in the X and Y dimensions of a ceramic composition having different ratios of the dielectric layer and the DuPont 951PT® layer according to Example 1 was measured and is illustrated in FIG.
[0054]
As shown in FIG. 2, the shrinkage ratio in the X and Y dimensions of the multilayer ceramic construction according to the present invention is quite low, indicating that the two material layers can effectively prevent each other from shrinking.
[0055]
While embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. It is intended that the invention not be limited to the specific forms as illustrated, and that all such modifications come within the scope defined by the appended claims without departing from the spirit and scope of the invention. It is intended.
[0056]
The present invention provides a multi-layer ceramic construction comprising at least one layer of dielectric material M ₁ and at least one layer of dielectric material M ₂ , wherein the passive element comprises both layers of dielectric material M ₁ and M ₂ To prevent the X and Y dimensions from shrinking together during baking. In accordance with the present invention, each layer of the multilayer ceramic construction can be used as a substrate for embedding passive components and has the ability to prevent other layers having different dielectric constants from shrinking. Thus, the multilayer ceramic structure has the advantage of small size and good accuracy of the circuit.
[0057]
【The invention's effect】
The present invention provides a multilayer ceramic composition that does not undergo changes in electrical properties and / or shrinkage of the dielectric material layer during baking.
[Brief description of the drawings]
FIG. 1 shows a schematic cross-sectional view of one embodiment of a multilayer ceramic construction according to the present invention.
Figure 2 shows the measured shrinkage when M ₁ layer and M ₂ layers of different thickness ratio are simultaneously baked. Here, M ₁ refers to the dielectric material according to Example 1 and M ₂ refers to a conventional low-temperature co-fired ceramic (product named Du Pont 951 PT®).
[Explanation of symbols]
1 multilayer ceramic composition 11 dielectric material _{M 1} in the layer 12 of dielectric material _{M 2} layer 13 via conductor 15 the passive device 16 metallization pattern

Claims (18)

A multilayer ceramic composition, comprising:
Having a dielectric constant K _1, having at least one embedded passive elements a dielectric material M ₁ at least one layer, in the dielectric material M _1, a dielectric material M _1;
Having a dielectric constant K _2, a dielectric material M ₂ at least one layer has at least one of the embedded passive components in the dielectric material M _2, it is disposed below the dielectric material M ₁ layer The dielectric material M ₂ ,
Including
Here, K ₁ is different from K ₂ and the layer of dielectric material M _{1 and} the layer of dielectric material M ₂ prevent the X and Y dimensions from shrinking together during baking,
Multilayer ceramic composition. K ₁ and _{K 2} is in the range of from about 4 to about 2000, construction of claim 1. The composition of claim 1, wherein at least one of M ₁ and M ₂ comprises a ceramic solid and an inorganic glass. The composition of claim 3, wherein the ceramic solid is selected from the group consisting of an inorganic metal, a high melting inorganic solid, and a high softening point glass. The composition of claim 4, wherein the ceramic solid is selected from the group consisting of barium titanium oxide, barium samarium neodymium titanium oxide, silicon oxide, aluminum oxide, magnesium aluminum silicon oxide, and mixtures thereof. Composition. The composition of claim 3, wherein the inorganic glass is selected from the group consisting of bismuth oxide, tellurium oxide, boron oxide, precursors thereof, and mixtures thereof. 4. The composition of claim 3, wherein the amount of inorganic glass ranges from about 0.5 to about 98% by weight. A composition according to claim 1, wherein the sintering temperature of the dielectric material M ₁ is a T _1, and the sintering temperature of the dielectric material M ₂ is a T _2, and T ₁ is higher than T _2, construct. 9. The composition according to claim 8, wherein T ₁ > T ₂ + 50 ° C. A composition according to claim 8, wherein the dielectric material M ₂ layers, when sintered at T _2, contraction of the X and Y dimensions are by a layer of said dielectric material M ₁ which does not sintered at T ₂ It is prevented, and a layer of dielectric material M ₁ is, when sintered at T _1, contraction of the X and Y dimensions is prevented by a layer of dielectric material M ₂ which shrinkage is completed, the configuration thereof. T ₁ and _{T 2} ranges from about 450 ° C. ~ about 1200 ° C., construction of claim 8. The composition of claim 11, wherein T ₁ and T ₂ are less than about 960 ° C. A composition according to claim 1, wherein the embedded passive device comprises a printed metal pattern on the dielectric material M ₂ of dielectric material M ₁ and at least one layer of at least one layer arrangement . 14. The composition of claim 13, wherein the metallization pattern includes a plurality of inverted electrodes in the dielectric material layer. 14. The composition of claim 13, further comprising a conductor passing through the layer of dielectric material to electrically connect the embedded passive device and the metallization pattern. The composition of claim 1, wherein the embedded passive element comprises a constructed passive element. The composition of claim 1, wherein the embedded passive element is selected from the group consisting of a capacitor, a resistor, and an inductor. The composition of claim 1, further comprising an overlying dielectric layer.

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