TW201916260A - 半導體結構的形成方法 - Google Patents

半導體結構的形成方法 Download PDF

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TW201916260A
TW201916260A TW106139478A TW106139478A TW201916260A TW 201916260 A TW201916260 A TW 201916260A TW 106139478 A TW106139478 A TW 106139478A TW 106139478 A TW106139478 A TW 106139478A TW 201916260 A TW201916260 A TW 201916260A
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Taiwan
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layer
silicon
epitaxial layer
forming
recess
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TW106139478A
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English (en)
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沙哈吉Ｂ 摩爾
李承翰
潘正揚
王俊傑
張世杰
楊懷德
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台灣積體電路製造股份有限公司
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Publication of TW201916260A publication Critical patent/TW201916260A/zh

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Abstract

本發明實施例描述形成p型完全應變通道或n型完全應變通道的例示性方法，其可減少因製程造成通道區中的磊晶成長缺陷或結構變形。例示性方法可包含(i)搭配三氟化氮與氨的電漿之兩個或多個表面預清潔處理循環，之後進行熱處理；(ii)預烘烤；以及(iii)搭配矽晶種層、矽鍺晶種層、或上述之組合磊晶成長矽鍺。

Description

半導體結構的形成方法
本發明實施例關於半導體裝置，更特別關於完全應變通道與其形成方法。
互補金氧半裝置中的完全應變通道，可改善載子移動率並降低裝置的通道電阻。此外，具有縮小通道長度的互補金氧半裝置，可因載子移動率改善而保留應變誘發的增大驅動電流。
本發明一實施例提供之半導體結構的形成方法，包括：提供摻雜區於基板的頂部上；成長第一磊晶層於摻雜區上；形成凹陷於第一磊晶層中，且凹陷對準摻雜區，其中形成凹陷的步驟包括部份蝕刻第一磊晶層；進行一或多道的表面預清潔處理循環，其中每一表面預清潔處理循環包括：暴露凹陷至電漿；以及進行回火；以及形成第二磊晶層於凹陷中，其中形成第二磊晶層的步驟包括：在第一溫度下進行預烘烤；在第二溫度下形成晶種層於凹陷中；以及在第三溫度下形成第二磊晶層於晶種層上，以填滿凹陷。
H、530‧‧‧高度
W、520‧‧‧寬度
100‧‧‧方法
110、120、130、140、150、160‧‧‧步驟
200‧‧‧基板
210、820‧‧‧氧化物層
300‧‧‧光阻層
310‧‧‧開口
320‧‧‧n型區
400‧‧‧p型區
410、510‧‧‧矽磊晶層
420‧‧‧蓋層
500‧‧‧凹陷
540‧‧‧區域
700‧‧‧矽鍺磊晶層
800‧‧‧堆疊
810‧‧‧矽層
830‧‧‧氮化物層
900、910‧‧‧鰭狀物
920‧‧‧氮化物襯墊
1000‧‧‧介電層
第1圖係一些實施例中，在鰭狀物上形成完全應變通道區 的例示性方法其流程圖。
第2圖係一些實施例中，具有氧化物層成長其上的基板剖視圖。
第3圖係一些實施例中，光阻層中的開口對準n型區的剖視圖。
第4圖係一些實施例中，矽磊晶層形成於基板的p型區與n型區上的剖視圖。
第5圖係一些實施例中，在蝕刻製程後形成凹陷於矽磊晶層中的剖視圖。
第6圖係一些實施例中，在表面預清潔處理步驟之後，矽磊晶層中的凹陷其剖視圖。
第7圖係一些實施例中，成長於矽磊晶層中的凹陷中的矽鍺磊晶層其剖視圖。
第8圖係一些實施例中，在化學機械平坦化步驟以及沉積矽層、氧化物層、與氮化物層之後，成長於矽磊晶層中的凹陷中的矽鍺磊晶層其剖視圖。
第9圖係一些實施例中，具有矽鍺磊晶層與矽磊晶層形成其上的鰭狀物其剖視圖。
第10圖係一些實施例中，在沉積介電層於鰭狀物之間後，具有矽鍺磊晶層與矽磊晶層的鰭狀物其剖視圖。
第11圖係一些實施例中，在使鰭狀物之間的介電層凹陷後，具有矽鍺磊晶層與矽磊晶層的鰭狀物其剖視圖。
下述內容提供的不同實施例或實例可實施本發明 的不同結構。特定構件與排列的例子係用以簡化本發明而非侷限本發明。舉例來說，形成第一結構於第二結構上的敘述包含兩者直接接觸，或兩者之間隔有其他額外結構而非直接接觸。此外，本發明之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
場效電晶體指的是金氧半場效電晶體。金氧半場效電晶體可為建立在基板如半導體晶圓之平坦表面之中或之上的平面結構。金氧半場效電晶體亦可為三維垂直取向結構，其可具有稱作鰭狀物的半導體材料。用語「鰭狀場效電晶體」指的是形成於半導體如矽的鰭狀物上的場效電晶體，且鰭狀物相對於晶圓的平面表面為垂直取向。
用語「磊晶層」指的是結晶材料的層狀物或結構。同樣地，用語「磊晶成長」指的是成長結晶材料之層狀物或結構的製程。磊晶成長的材料可摻雜或未摻雜。
此處所述的用語「名義上的」，指的是在產品或製程的設計階段時，用於構件或製程之特性或參數的期望值或目標值，以及高於及/或低於期望值的範圍。數值範圍通常來 自於製程中的微小變數或容忍度。除非特別定義，此處所述的技術或科學用語將與本技術領域中具有通常知識者通常理解的意義相同。
互補式金氧半裝置中的完全應變通道，可改善載子移動率並降低裝置的通道電阻。此外，改善載子移動率可增加應變誘導的驅動電流，仍可維持於通道長度縮小的互補式金氧半裝置中。用於p型場效電晶體與n型場效電晶體中的應變通道材料可不同。舉例來說(但不限於下述例子)，完全應變的矽/摻雜碳的矽通道可增加n型場效電晶體中的電子移動率，而完全應變的矽鍺通道可增加p型場效電晶體中的電洞移動率。
完全應變磊晶通道，可由矽鰭狀物的頂部上之磊晶層形成。完全應變通道的形成製程需要多道光微影、蝕刻、預處理、回火、及成長步驟。一些步驟可能具有挑戰性並導致不想要的效應，比如因磊晶成長層中存在的應力而產生的通道區變形(如非垂直的側壁)與磊晶成長缺陷(如堆疊錯誤)。這些不想要的效應會抵消全應變通道的改良移對率。與n型全應變通道(可採用矽、摻雜碳的矽、或上述之組合)相較，p型全應變通道之矽對矽鍺的晶格不匹配較大而更易產生缺陷。
此處所述的實施例關於p型全應變通道的例示性製作方法，其可緩解因製程造成的通道區結構變形或磊晶成長缺陷。在一些實施例中，例示性製程可包含(i)兩次或多次搭配三氟化氮與氨電漿的表面預清潔處理循環，接著進行熱處理；(ii)預烘烤(回火)；以及(iii)搭配矽晶種層、矽鍺晶種層、摻雜碳的矽晶種層、或上述的組合磊晶成長矽鍺。上述例示性方法 亦可用以形成n型全應變通道，其中步驟(iii)可置換為搭配矽晶種層磊晶成長摻雜碳的矽。
第1圖係例示性方法100的流程圖。方法100可形成p型的完全應變之矽鍺通道區於鰭狀物的頂部上，且一電晶體可具有此通道區。在一些實施例中，例示性的方法100可提供矽鍺通道區，其實質上不具有結構變形與磊晶成長缺陷如堆疊錯誤。在例示性方法100的多種步驟之間可進行其他步驟，但為簡化而省略其他步驟的說明。例示性方法100不限於下述步驟，而可包含額外步驟。
舉例來說，例示性方法100描述為形成p型全應變通道於矽鰭狀物的頂部中。依據下述說明，p型全應變通道亦可形成於平面電晶體中。平面電晶體亦屬本發明精神與範疇。此外如上所述，例示性方法100可用以形成n型全應變通道。
例示性方法100之步驟110形成n型區於基板的頂部中。舉例來說(但不限於下述例子)，n型區的形成方法如下述。如第2圖所示，沉積氧化物層210於基板200上。在一些實施例中，基板200可為基體半導體晶圓或絕緣層上半導體晶圓。此外，基板200之組成可為矽或另一半導體元素如鍺；半導體化合物如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；半導體合金如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦；或上述之組合。舉例來說，例示性方法100中的基板200可為矽(比如單晶)。依據上述內容，基板200亦可採用其他材料。這些材料屬於本發明精神與範疇。
在一些實施例中，氧化物層210的厚度可介於約30Å至約150Å之間(比如30Å至90Å)。在一些實施例中，氧化物層210為氧化矽層。在一些實施例中，氧化物層210可保護基板200的上表面免於污染，避免離子佈植對基板200的多餘損傷，以及控制離子佈植步驟時的摻質深度。
接著可沉積光阻層300於氧化物層210上，如第3圖所示。在一些實施例中，可圖案化光阻層300以形成開口310於部份的氧化物層210上，如第3圖所示。在一些實施例中，可採用離子佈植以形成n型區320於基板200中。在一些實施例中，n型區320實質上對準開口310，因此光阻層300可作為佈植遮罩。在一些實施例中，n型摻質可包含砷、銻、或磷。在一些實施例中，n型區320中的n型摻質濃度可介於約5×1016原子/cm3至約1×1019原子/cm3之間。舉例來說(但不限於下述例子)，n型區320的深度(沿著z方向)可介於約100nm至約500nm之間。然而n型區320其寬度(比如沿著x方向)與長度(比如沿著y方向)的變化可視裝置種類而定。舉例來說，裝置可為邏輯裝置、靜態隨機存取記憶體、或類似裝置。在形成n型區320後，可移除光阻層300。
在一些實施例中，與圖案化光阻層相關的類似製程可用以形成p型區400於基板200中。p型區400與n型區320相鄰，如第4圖所示。在一些實施例中，可採用p型摻質如硼的離子佈植製程，形成p型區400。舉例來說(但不限於下述例子)，p型區400的摻質濃度可介於約5×1016原子/cm3至約1×1019原子/cm3之間。
在形成n型區320與p型區400之後，可採用濕式清潔製程移除任何殘留的光阻層。在一些實施例中，可進行回火步驟以電性活化摻質(比如使摻質自間隙位置移動至矽晶格位置)，並修復在離子佈植步驟中發生的任何矽晶格損傷。舉例來說(但不限於下述例子)，晶體損傷修復可發生在約500℃，而摻質活化可發生在約950℃。舉例來說(但不限於下述例子)，回火步驟可在回火爐或快速熱回火腔室中進行。在一些實施例中，在摻質活化回火後可移除氧化物層210。
在第1圖所示的步驟120中，可直接磊晶成長矽磊晶層410於基板200上，如第4圖所示。在一些實施例中，矽磊晶層410的厚度可介於約300Å至約1000Å之間。舉例來說(但不限於下述例子)，矽磊晶層410的沉積方法可為化學氣相沉積製程。用於矽磊晶層的源氣體可包含矽烷、四氯化矽、三氯矽烷、或二氯矽烷。氫氣可作為反應物氣體，其可減少前述的源氣體。磊晶層的沉積溫度可介於約700℃至約1250℃之間，端視採用的氣體而定。舉例來說，氯原子越少的源氣體(如二氯矽烷)所需的磊晶成長溫度，低於氯原子越多的源氣體(如四氯矽烷)所需的磊晶成長溫度。上述氣體種類與參數範圍僅用以舉例說明而非侷限本發明。
在一些實施例中，蓋層420可成長於矽磊晶層410的頂部上。蓋層420的厚度可大於或等於約150Å(比如介於150Å至約300Å之間)。在一些實施例中，蓋層420可為氧化物層如氧化矽。在其他實施例中，蓋層420可為氮化物如氮化矽。
如第5圖與步驟130所示，可採用乾蝕刻製程形成 凹陷500於矽磊晶層410中。在一些實施例中，凹陷500可對準n型區320。在一些實施例中，凹陷500的至少一尺寸名義上等於n型區320的尺寸。舉例來說，凹陷500與n型區320沿著x方向的寬度可相同，但沿著y方向的長度不同。舉例來說，可藉由光微影使凹陷500對準n型區320。舉例來說(但不限於下述例子)，可施加光阻層於矽磊晶層410上。可依據所需圖案曝光並顯影光阻。舉例來說，所需圖案可為開口，其對準n型區320並露出部份的蓋層420。光阻未曝光的區域可由濕式清潔步驟移除，以保留顯影光阻之所需圖案於蓋層420上(比如p型區400上的矽磊晶層410與蓋層420上)。乾蝕刻製程可移除蓋層420的露出區域，並部份地蝕刻矽磊晶層410。顯影光阻(比如位於p型區400之頂部上)可覆蓋部份的蓋層420，保護其免於乾蝕刻製程的蝕刻化學品造成的蝕刻。一旦蝕刻蓋層420的露出區域與部份蝕刻矽磊晶層410，可採用濕式清潔步驟移除殘留的顯影光阻。此製程的結果為蝕刻部份的矽磊晶層410，以形成第5圖所示的凹陷500。形成凹陷500於矽磊晶層410中的乾蝕刻製程，可調整為不移除n型區320其頂部上的薄矽磊晶層如上述。在一些實施例中，保留於n型區320其頂部上的矽層510之厚度，可介於約50Å至約100Å之間。在一些實施例中，矽層510原本沉積為矽磊晶層410的一部份。在一些實施例中，乾蝕刻製程可採用不同的氣體化學品，以分別用於蓋層420與矽磊晶層410。
在一些實施例中，矽磊晶層410中的凹陷500可具有寬度520與高度530。寬度520可介於約1000Å至約5000Å之間，且名義上可等於n型區320的寬度。矽磊晶層410的厚度與 凹陷500其底部處的矽層510的厚度之間的差距，可等於凹陷500的高度530。
在一些實施例中，在形成凹陷500於矽磊晶層410中之後，凹陷500之頂角處的蓋層420其邊緣將圓潤化。上述圓潤化可能來自於蝕刻製程。此外，蝕刻製程中可能蝕刻部份蓋層420，因此蝕刻製程後可能薄化蓋層420。
如第1圖所示，步驟140可進行一或多個表面預清潔處理循環，使凹陷500的表面準備形成後續的磊晶層。在一些實施例中，表面預清潔處理循環可包含兩步製程：電漿蝕刻步驟與回火步驟。在一些實施例中，可重複表面預清潔處理循環，比如進行兩次或更多次的表面預清潔處理循環。在一些實施例中，表面預清潔處理係設計為處理矽磊晶層410中的凹陷500其露出的表面。蓋層420覆蓋的矽磊晶層410的表面(比如p型區400上的矽磊晶層410其上表面)，將不會暴露至表面預清潔處理，因此不會被處理。
在一些實施例中，電漿蝕刻步驟可包含三氟化氮與氨的氣體混合物。電漿亦可包含鈍氣如氬氣、氦氣、氫氣、氮氣、或上述之組合。在一些實施例中，提供至電漿的電源可為射頻或直流電。舉例來說(但不限於下述例子)，電漿蝕刻的溫度可介於室溫至約150℃之間，壓力可介於約0.5Torr至約10Torr之間(比如2Torr至5Torr之間)。然而製程參數不限於上述範圍，因為這些參數範圍取決於設備。在一些實施例中，電漿蝕刻可自凹陷500的表面移除原生氧化矽及/或污染如碳、氟、氯、或磷。在一些實施例中，電漿蝕刻可包含鹽酸蒸氣。
第6圖係第5圖之區域540的放大圖，其顯示暴露至三氟化氮與氨電漿後的凹陷500。由於三氟化氮與氨電漿的目標為氧化矽，電漿蝕刻製程會蝕刻部份的蓋層420。如此一來，可減少矽磊晶層410其頂部的蓋層厚度(或高度H)。此外，具有寬度W的凹陷可形成於凹陷500的頂角。如前所述，在形成凹陷時會使蓋層420圓潤化。在一些實施例中，高度H可大於或等於凹陷的寬度W，即HW。舉例來說，凹陷的蓋層420其高度H與寬度W的比例(H/W)可介於約1至1.5之間。在一些實施例中，依據電漿蝕刻條件，表面預清潔處理的循環次數、或每一表面預清潔處理循環的時間，蓋層420的高度H可縮小約50Å至200Å。在一些實施例中，可調整蓋層420的厚度以減緩蝕刻製程中的負載效應，因此可一致地蝕刻具有不同裝置密度的晶片。舉例來說，晶片的邏輯區、靜態隨機存取記憶體區、或輸入/輸出裝置所在的區域，可具有不同的裝置密度。在一些實施例中，可在後續的化學機械平坦化製程之前，先以稀氫氟酸進一步控制蓋層420的厚度。一些實施例中蓋層420的厚度，以及晶片中具有不同密度的區域(如邏輯區與靜態隨機存取記憶體)之間的化學機械平坦化負載之間具有相關性。如此一來，蓋層420的厚度可用以減緩晶片其高密度區(如靜態隨機存取記憶體)與低密度區(如邏輯區)之間的研磨速率差異(負載)。
可持續表面預清潔處理循環與回火步驟。回火步驟的溫度可介於約30℃至約200℃之間(比如60℃至200℃)。在一些實施例中，回火步驟的壓力小於電漿蝕刻步驟的壓力，比如低於1Torr(如0.6Torr)。在一些實施例中，回火步驟的氛 圍可為鈍氣如氬氣、氦氣、氮氣、或上述之組合。在一些實施例中，回火步驟可自凹陷500的表面誘發污染與水氣的脫氣。在一些實施例中，回火步驟可持續約30秒(如約25秒)。如前所述，可依需求重複表面預清潔處理(電漿蝕刻與回火)，使凹陷500的露出表面預備進行後續製程。
在一些實施例中，表面清潔處理的每一循環可包括下述步驟之一：(i)回火、蝕刻、與回火的組合；(ii)蝕刻與回火的組合；以及(iii)蝕刻而不回火。在一些實施例中，每一上述程序可具有不同的原生氧化物移除速率。如此一來，不同的上述程序可採用不同的循環次數。舉例來說，程序(i)與(ii)的循環次數可為兩次，而程序(iii)的循環次數可為一次。在一些實施例中，省略回火可改善晶圓中的蝕刻一致性(或晶圓對晶圓的蝕刻一致性)。在一些實施例中，原生氧化物的移除量可介於約30Å至約120Å之間。
方法100接著進行步驟150，以形成磊晶層於凹陷中。在一些實施例中，步驟150包含三個子步驟：(i)預烘烤、(ii)形成晶種層、以及(iii)形成磊晶層於晶種層上。
在一些實施例中，第一子步驟為加熱處理或預烘烤，其溫度T1可高於後續形成晶種與磊晶層的溫度T2與T3。換言之，溫度T1>溫度T2或溫度T3。舉例來說，預烘烤的溫度T1可比晶種層與磊晶層的形成溫度T2與T3高約20%至約30%之間。在一些實施例中，預烘烤溫度可介於約650℃至約1500℃之間，比如650℃至900℃之間或1000℃至1500℃之間。在一些實施例中，預烘烤氛圍可為鈍氣如氬氣、氮氣、氦氣、或上述 之組合。此外，預烘烤壓力可介於約1Torr至約500Torr之間(比如10Torr至50Torr之間或200Torr至300Torr之間)。舉例來說(但不限於下述例子)，若預烘烤溫度高則預烘烤壓力低，反之亦然。舉例來說，若預烘烤溫度介於約1000℃至約1500℃之間，則預烘烤壓力可介於約10Torr至約50Torr之間。相反地，若預烘烤溫度介於約650℃至約900℃之間，則預烘烤壓力可介於約200Torr至約300Torr之間。在一些實施例中，預烘烤時間可介於約50秒至約200秒之間(比如約100秒)。在一些實施例中，預烘烤製程可減少凹陷的表面粗糙度，並減緩寬度改變或側壁漸縮。在一些實施例中，在預烘烤步驟後，凹陷500的側壁與下表面之間的角度可大於或等於90°。
在步驟150的第二子步驟中，形成晶種層於蓋層420未覆蓋的矽磊晶層410其露出的表面上，比如凹陷500。在一些實施例中，晶種層可成長於蓋層420上。舉例來說，晶種層可成長於氧化矽或氮化矽上。在一些實施例中，晶種層可為矽層、摻雜碳的矽層、矽鍺層、或上述之組合，且其厚度介於約30Å至約100Å之間。舉例來說，晶種層可為矽/摻雜碳的矽/矽鍺、矽/矽鍺、或摻雜碳的矽/矽鍺。在一些實施例中，摻雜碳的矽中的碳摻質其原子%可介於約0.01原子%至約2原子%之間。在一些實施例中，晶種層的厚度不足以填滿凹陷。如此一來，晶種層覆蓋凹陷500其露出的表面，而不會填滿凹陷500。舉例來說(但不限於下述例子)，晶種層的沉積方法可為化學氣相沉積。舉例來說(但不限於下述例子)，在氫氣或氮氣的存在下可採用矽烷及/或二氯矽烷形成矽晶種 層。(i)矽烷、矽乙烷、鍺烷、或鹽酸與(ii)氫氣、氮氣、氦氣、或氬氣的組合，可用以形成矽鍺晶種層。前述的氣體種類僅用以舉例而非侷限本發明。
在一些實施例中，沉積晶種層的溫度T2可大於成長磊晶層的溫度T3。晶種層的沉積溫度T2可介於約600℃至約750℃之間(比如700℃至750℃之間)。在一些實施例中，在溫度T2的範圍上限(比如約750℃)可達較高品質的晶種層(具有較少缺陷)。在一些實施例中，晶種層的形成製程壓力可介於約5Torr至約30Torr之間(比如15Torr)。在一些實施例中，晶種層的沉積製程時間可介於約5秒至約15秒之間，端視晶種層的成長速率與所需的晶種層厚度而定。上述參數範圍僅用以舉例而非侷限本發明。一些實施例中，在之前製程擴大凹陷500的寬度520的情況下，可調整晶種層厚度以復原凹陷500的預定寬度522。厚度調整亦可減緩凹陷500中頂角與底角的圓潤化現象。
在步驟150的第三子步驟中，形成磊晶層於晶種層上，以填入凹陷500。在一些實施例中，磊晶層為矽鍺，且其成長的溫度T3可介於約550℃至約700℃之間。如前所述，溫度T3低於溫度T2與T1。舉例來說(但不限於下述例子)，用於成長矽鍺磊晶層的前驅物氣體可包含下述物質(i)與(ii)的組合：(i)矽烷、矽乙烷、二氯矽烷、鍺烷、或鹽酸；以及(ii)氫氣、氮氣、或氬氣。
在一些實施例中，矽鍺磊晶層沿著厚度方向的鍺濃度(原子%)可為定值，其介於約20原子%至約40原子%之間。在一些實施例中，矽鍺磊晶層可包含第一子層與第二子層，第 一子層的鍺濃度為約5原子%，而第二子層沿著矽鍺磊晶層的厚度方向之鍺濃度介於約20原子%至約40原子%之間。第一子層的厚度可介於約20Å至約100Å之間。
如第7圖所示，矽鍺磊晶層700成長於第6圖中的凹陷500中。矽鍺磊晶層700成長於晶種層上。此外，矽鍺磊晶層700不會形成於蓋層420上。舉例來說，矽鍺磊晶層700不會成長於氧化矽或氮化矽上。在一些實施例中，在成長矽鍺磊晶層700後的凹陷500其側壁，可實質上垂直於凹陷500的下表面。舉例來說，凹陷500的下表面與側壁之間的角度，可介於約90°至100°之間。舉例來說(但不限於下述例子)，摻雜碳的矽磊晶可成長於p型區上的矽晶種層上，以用於形成n型全應變通道。在一些實施例中，後續的化學機械平坦化製程可平坦化矽鍺磊晶層700與矽磊晶層410。在化學機械平坦化製程中，可移除蓋層420、部份的矽鍺磊晶層700、與部份的矽磊晶層410，如第8圖所示。
在一些實施例中，上述步驟150的子步驟可成功地進行，而不需破真空。舉例來說，可在單一大型主機的不同製程腔室中進行每一子步驟。換言之，例示性方法100的步驟150為臨場製程。
如第1圖所示的一些實施例中，例示性方法100的步驟160可蝕刻第8圖中的部份堆疊800以形成鰭狀物，其可包含n型區320組成的底部、矽磊晶層510組成的中間部、與晶種層及矽鍺磊晶層700組成的頂部。在一些實施例中，鰭狀物亦可包含p型區400組成的底部，與矽磊晶層410組成的頂部。
舉例來說(但不限於下述例子)，鰭狀物的形成製程可先沉積矽層810於矽鍺磊晶層700與矽磊晶層410的平坦化表面上。在一些實施例中，矽層810的厚度可介於約10Å至約100Å之間(如30Å)，且其成長方法可與用以成長矽磊晶層410的方法類似。接著可沉積氧化物層820與氮化物層830於矽層810上。矽層810、氮化物層820、與氮化物層830在後續的蝕刻製程中，可保護矽鍺磊晶層700與矽磊晶層410。光微影可定義鰭狀的尺寸與鰭狀物之間的空間(間距)。舉例來說，可塗佈光阻層於氮化物層上。接著可依據所需圖案曝光及顯影光阻。可進行濕式清潔以移除光阻的未曝光區，並保留顯影光阻的所需圖案於氮化物層830上。舉例來說，所需圖案可為決定所需鰭狀物間距(鰭狀物之間的所需距離)及鰭狀物長度的開口。光阻可作為蝕刻遮罩，因此可移除光阻未遮罩的堆疊材料。
舉例來說，乾蝕刻製程可自堆疊800移除圖案化光阻未覆蓋的材料。舉例來說(但不限於下述例子)，乾蝕刻製程可包含多個步驟，且每一步驟具有不同的蝕刻化學品，端視欲蝕刻的材料而定。在蝕刻製程後，可採用濕式清潔製程移除顯影的光阻。在一些實施例中，形成的鰭狀物900與910如第9圖所示。第9圖中所示的鰭狀物數目僅用以舉例而非侷限本發明。如此一來，鰭狀物的數目可更少或更多，端視鰭狀物間距與每一鰭狀物所需的寬度而定。在一些實施例中，鰭狀物900可包含n型區320的底部、矽磊晶層510的中間部、以及晶種層與矽鍺磊晶層700的頂部。鰭狀物910可包含p型區400的底部與矽磊晶層410的頂部。
在一些實施例中，可沉積氮化物襯墊920於鰭狀物900與910上，以覆蓋鰭狀物900與910的側壁及p型區320與n型區400的水平表面。舉例來說，氮化物襯墊920可為氮化矽。在一些實施例中，氮化物襯墊920可在後續製程中，提供結構支撐至鰭狀物900與910。在一些實施例中，介電層1000可沉積於鰭狀物900與910上，以填入鰭狀物之間的空間，如第10圖所示。舉例來說，介電層1000可為淺溝槽隔離如氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數介電材料、或具有適當填充性質的的其他合適絕緣材料。此外，介電層可包含多層結構，比如具有一或多層的介電層。在一些實施例中，介電層的沉積方法可為化學氣相沉積、電漿增強化學氣相沉積、或可流動的化學氣相沉積。
在一些實施例中，化學機械平坦化製程可移除鰭狀物900與910上的部份介電層1000。在一些實施例中，化學機械平坦化製程可停止於氮化物襯墊920上。後續的回蝕刻製程可使介電層1000凹陷至n型區320與p型區400的高度，如第11圖所示。在前述的回蝕刻步驟中，可移除氮化物層830、氧化物層820、與矽層810。此外，亦可使氮化物襯墊920凹陷至介電層1000的高度。
如上所述，例示性的方法100可用以形成n型的完全應變通道。舉例來說，在步驟110中形成p型的摻雜區，以及在步驟150中成長摻雜碳的矽於矽晶種層上以作為磊晶層，即可形成n型的完全應變通道。
本發明關於p型或n型完全應變通道的例示性製作 方法，其可減少通道區中的磊晶成長缺陷如堆疊錯誤。此外，例示性的製作方法可減少通道區中的結構變形，比如因製程產生的側壁漸縮。在一些實施例中，例示性的製程包括(i)兩次或多次搭配三氟化氮與氨電漿的表面預清潔處理循環，接著進行熱處理；(ii)預烘烤(回火)；以及(iii)搭配矽晶種層、矽鍺晶種層、或上述的組合磊晶成長矽鍺，或搭配矽晶種層之磊晶成長摻雜碳的矽。在一些實施例中，形成的鰭狀物可包含具有摻雜區的底部、具有矽磊晶層的中間部、以及具有晶種及磊晶層的頂部。
在一些實施例中，半導體結構的形成方法包括：提供摻雜區於基板的頂部上，以及成長第一磊晶層於摻雜區上。接著形成凹陷於第一磊晶層中，且凹陷對準摻雜區。形成凹陷的步驟包括部份蝕刻第一磊晶層。進行一或多道的表面預清潔處理循環。每一表面預清潔處理循環包括：暴露凹陷至電漿；以及進行回火。形成第二磊晶層於凹陷中，包括：在第一溫度下進行預烘烤；在第二溫度下形成晶種層於凹陷中；以及在第三溫度下形成第二磊晶層於晶種層上，以填滿凹陷。
在一些實施例中，上述方法更包括：將光阻置於第二磊晶層上；形成至少兩個開口於光阻中，以露出第二磊晶層的至少兩個個別部份；以及形成鰭狀物，其中形成鰭狀物的步驟包括：蝕刻穿過光阻層中的至少兩個開口、晶種層、第一磊晶層、與部份的摻雜區；以及形成介電層於鰭狀物之間。
在一些實施例中，上述方法的鰭狀物包括具有摻雜區的底部、具有第一磊晶層的中間部、以及具有晶種層與第 二磊晶層的頂部。
在一些實施例中，上述方法在形成第二磊晶層之後，凹陷的側壁角度介於90°至100°之間。
在一些實施例中，上述方法之摻雜區包含n型材料。
在一些實施例中，上述方法之電漿包含三氟化氮、氨、與鈍氣。
在一些實施例中，上述方法之晶種層包含矽、摻雜碳的矽、矽鍺、或上述之組合，且晶種層的厚度介於10Å至100Å之間。
在一些實施例中，上述方法之第一溫度介於650℃至1500℃之間，且第一溫度高於第二溫度與第三溫度。
在一些實施例中，第二溫度介於600℃至750℃之間，且第三溫度介於500℃至700℃之間。
在一些實施例中，上述方法之第一磊晶層包含矽，且第二磊晶層包含矽鍺。
在一些實施例中，半導體結構的形成方法包括：形成n型區於基板的頂部上，以及成長矽磊晶層於n型區上。形成介電層於矽磊晶層上。形成開口於介電層中，其對準n型區以露出矽磊晶層。此外，經由開口，部份地蝕刻矽磊晶層以形成凹陷。進行預清潔處理循環，以及形成磊晶堆疊於凹陷中，其中形成磊晶堆疊的步驟包括：進行預烘烤，形成晶種層於凹陷中，以及形成磊晶層於晶種層上，以填滿凹陷。
在一些實施例中，上述方法之預清潔處理循環包 括：將凹陷暴露至電漿；以及進行回火。
在一些實施例中，上述方法更包括：形成鰭狀物，其中形成鰭狀物的步驟包括：沉積光阻於矽磊晶層上；形成至少兩個開口於光阻中，以露出磊晶層的至少兩個個別部份；蝕刻穿過光阻層中的至少兩個開口，以移除磊晶層、晶種層、矽磊晶層、與部份的n型區；以及形成介電層於鰭狀物之間。
在一些實施例中，上述方法的磊晶層為矽鍺。
在一些實施例中，上述方法的晶種層包括矽、矽鍺、摻雜碳的矽、或上述之組合。
在一些實施例中，上述方法之電漿包括三氟化氮、氨、與鈍氣。
在一些實施例中，上述方法之回火的溫度介於60℃至200℃之間，且壓力介於0.2Torr至1Torr之間。
在一些實施例中，半導體結構包括：鰭狀物位於基板上，且鰭狀物包括：n型摻雜區位於基板上；矽磊晶層位於n型摻雜區上；以及磊晶堆疊位於矽磊晶層上。此外，襯墊物圍繞鰭狀物的n型摻雜區，而介電物圍繞襯墊物。
在一些實施例中，上述半導體結構的磊晶堆疊包含第一子層與第二子層，第一子層的鍺濃度為約5原子%，而第二子層的鍺濃度介於20原子%至40原子%之間。
在一些實施例中，上述半導體結構的矽磊晶層厚度介於50Å至100Å之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理 解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。

Claims (1)

  1. 一種半導體結構的形成方法，包括：提供一摻雜區於一基板的頂部上；成長一第一磊晶層於該摻雜區上；形成一凹陷於該第一磊晶層中，且該凹陷對準該摻雜區，其中形成該凹陷的步驟包括部份蝕刻該第一磊晶層；以及進行一或多道的表面預清潔處理循環，其中每一表面預清潔處理循環包括：暴露該凹陷至一電漿；進行一回火；以及形成一第二磊晶層於該凹陷中，其中形成該第二磊晶層的步驟包括：在一第一溫度下進行預烘烤；在一第二溫度下形成一晶種層於該凹陷中；以及在一第三溫度下形成該第二磊晶層於該晶種層上，以填滿該凹陷。
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