JP6432305B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6432305B2 JP6432305B2 JP2014236883A JP2014236883A JP6432305B2 JP 6432305 B2 JP6432305 B2 JP 6432305B2 JP 2014236883 A JP2014236883 A JP 2014236883A JP 2014236883 A JP2014236883 A JP 2014236883A JP 6432305 B2 JP6432305 B2 JP 6432305B2
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Description
半導体装置の一態様には、半導体基板の第1の領域に形成された絶縁膜と、前記半導体基板の前記第1の領域に、前記絶縁膜より深く位置する部分を有し、平面視で前記絶縁膜を間に挟んで位置する第1導電型の第1の不純物領域及び前記第1導電型の第2の不純物領域と、前記第1の不純物領域上に形成され、前記第1の不純物領域とショットキー接合した金属シリサイド膜と、が含まれる。前記第1の不純物領域は、前記第1導電型の第1の不純物をその濃度プロファイルのピークが前記絶縁膜の底より深く位置し、前記絶縁膜の底より深い位置で一のピークとなるように含有し、前記第2の不純物領域は、前記第1導電型の第2の不純物を前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有し、前記第1の不純物領域と前記第2の不純物領域とは前記絶縁膜の底よりも深い位置で互いに接している。
半導体装置の製造方法の一態様では、半導体基板の第1の領域に第1導電型の第1の不純物領域を形成し、前記半導体基板の第1の領域に前記第1の不純物領域と接する前記第1導電型の第2の不純物領域を形成し、前記半導体基板の第1の領域に、前記第1の不純物領域の表面と前記第2の不純物領域の表面とを分離する絶縁膜を、前記第1の不純物領域及び前記第2の不純物領域より浅く、かつ前記絶縁膜の底よりも深い位置で前記第1の不純物領域と前記第2の不純物領域とが互いに接するように形成し、前記第1の不純物領域上に、前記第1の不純物領域とショットキー接合する金属シリサイド膜を形成する。前記第1の不純物領域を形成する際には、前記第1導電型の第1の不純物を、その濃度プロファイルのピークが前記絶縁膜の底より深く位置し、前記絶縁膜の底より深い位置で一のピークとなるように導入し、前記第2の不純物領域を形成する際には、前記第1導電型の第2の不純物を、前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有するように導入する。
先ず、ショットキーバリアダイオードの参考例について説明する。図1は参考例の構成を示す図であり、図1(a)は平面図、図1(b)は図1(a)中のI−I線に沿った断面図である。
次に、第1の実施形態について説明する。第1の実施形態は、ショットキーバリアダイオードを備えた半導体装置に関する。図2は第1の実施形態に係る半導体装置の構成を示す図であり、図2(a)は平面図、図2(b)は図2(a)中のI−I線に沿った断面図である。
次に、第2の実施形態について説明する。第2の実施形態は、ショットキーバリアダイオードを備えた半導体装置に関する。図5は第2の実施形態に係る半導体装置の構成を示す図であり、図5(a)は平面図、図5(b)は図5(a)中のI−I線に沿った断面図である。
次に、第3の実施形態について説明する。第3の実施形態は、DDCトランジスタ、高電圧トランジスタ、低抵抗ダイオード(LRD:low resistance diode)及びショットキーバリアダイオード(SBD:Schottky barrier diode)を含む半導体装置に関する。図7は、第3の実施形態に係る半導体装置の構成を示す断面図である。DDCトランジスタは、不純物の統計的揺らぎによる閾値電圧のばらつきを抑制する効果が大きく、ロジック回路等に用いられる低電圧(例えば0.9V)動作の高速トランジスタ等に有用である。高電圧NMOSトランジスタは、DDCトランジスタの駆動電圧よりも高電圧(例えば3.3V)が印加されるトランジスタであり、例えば3.3V I/Oに使用される。LRDは、例えばPN接合ダイオードであり、例えばサージ保護のために含まれる。SBDは、例えばDDCトランジスタのラッチアップの防止のために含まれる。
次に、第4の実施形態について説明する。第4の実施形態は、DDCトランジスタ、高電圧トランジスタ、LRD及びSBDを含む半導体装置に関する。図36は、第4の実施形態に係る半導体装置の構成を示す断面図である。
半導体基板の第1の領域に形成された絶縁膜と、
前記半導体基板の前記第1の領域に、前記絶縁膜より深く位置する部分を有し、平面視で前記絶縁膜を間に挟んで位置する第1導電型の第1の不純物領域及び前記第1導電型の第2の不純物領域と、
前記第1の不純物領域上に形成され、前記第1の不純物領域とショットキー接合した金属シリサイド膜と、
を有し、
前記第1の不純物領域は、前記第1導電型の第1の不純物をその濃度プロファイルのピークが前記絶縁膜の底より深く位置するように含有し、
前記第2の不純物領域は、前記第1導電型の第2の不純物を前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有し、
前記第1の不純物領域と前記第2の不純物領域とは前記絶縁膜の底よりも深い位置で互いに接していることを特徴とする半導体装置。
前記第1の不純物領域の前記絶縁膜の底より深い部分における前記第1の不純物の濃度は、前記第2の不純物領域における前記第2の不純物の濃度より高いことを特徴とする付記1に記載の半導体装置。
前記第1の不純物領域と前記金属シリサイド膜との間に局所的に形成された前記第1導電型とは異なる第2導電型の第3の不純物領域を有することを特徴とする付記1又は2に記載の半導体装置。
前記第3の不純物領域は、前記絶縁膜に接することを特徴とする付記3に記載の半導体装置。
前記半導体基板の第2の領域に形成されたゲート電極と、
前記ゲート電極の下方に形成された第1導電型の第4の不純物領域と、
を有し、
前記第4の不純物領域における前記第1導電型の第3の不純物の濃度プロファイルは、前記第1の不純物領域における前記第1の不純物の濃度プロファイルの一部と実質的に同一であることを特徴とする付記1乃至4のいずれか1項に記載の半導体装置。
前記半導体基板の第2の領域に形成された前記第1導電型の第4の不純物領域と、
前記第4の不純物領域上に形成された半導体層と、
前記第2の領域の前記半導体層上に形成されたゲート電極と、
を有することを特徴とする付記1乃至4のいずれか1項に記載の半導体装置。
半導体基板の第1の領域に第1導電型の第1の不純物領域を形成する工程と、
前記半導体基板の第1の領域に前記第1の不純物領域と接する前記第1導電型の第2の不純物領域を形成する工程と、
前記半導体基板の第1の領域に、前記第1の不純物領域の表面と前記第2の不純物領域の表面とを分離する絶縁膜を、前記第1の不純物領域及び前記第2の不純物領域より浅く、かつ前記絶縁膜の底よりも深い位置で前記第1の不純物領域と前記第2の不純物領域とが互いに接するように形成する工程と、
前記第1の不純物領域上に、前記第1の不純物領域とショットキー接合する金属シリサイド膜を形成する工程と、
を有し、
前記第1の不純物領域を形成する工程では、前記第1導電型の第1の不純物を、その濃度プロファイルのピークが前記絶縁膜の底より深く位置するように導入し、
前記第2の不純物領域を形成する工程では、前記第1導電型の第2の不純物を、前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有するように導入することを特徴とする半導体装置の製造方法。
前記第1の不純物領域の前記絶縁膜の底より深い部分における前記第1の不純物の濃度は、前記第2の不純物領域における前記第2の不純物の濃度より高いことを特徴とする付記7に記載の半導体装置の製造方法。
前記第1の不純物領域と前記金属シリサイド膜との間に前記第1導電型とは異なる第2導電型の第3の不純物領域を局所的に形成する工程を有することを特徴とする付記7又は8に記載の半導体装置の製造方法。
前記第3の不純物領域は、前記絶縁膜に接することを特徴とする付記9に記載の半導体装置の製造方法。
前記半導体基板の第2の領域に、前記第1導電型の第4の不純物領域を前記第1の不純物領域と並行して形成する工程と、
前記半導体基板で前記第4の不純物領域の上方にゲート電極を形成する工程と、
を有し、
前記第4の不純物領域における前記第1導電型の第3の不純物の濃度プロファイルは、前記第1の不純物領域における前記第1の不純物の濃度プロファイルと実質的に同一であることを特徴とする付記7乃至10のいずれか1項に記載の半導体装置の製造方法。
前記半導体基板の第2の領域に、前記第1導電型の第4の不純物領域を前記第1の不純物領域と並行して形成する工程と、
前記第4の不純物領域の形成跡であって前記絶縁膜を形成する工程の前に、前記半導体基板上に半導体層を形成する工程と、
前記半導体基板の第2の領域の前記半導体層上にゲート電極を形成する工程と、
を有することを特徴とする付記7乃至10のいずれか1項に記載の半導体装置の製造方法。
11、411:Nウェル
12、412:深部
13、413:浅部
16、416:Nウェル
32、432:絶縁膜
83a、483a:金属シリサイド膜
114:ショットキーバリアダイオード
Claims (15)
- 半導体基板の第1の領域に形成された絶縁膜と、
前記半導体基板の前記第1の領域に、前記絶縁膜より深く位置する部分を有し、平面視で前記絶縁膜を間に挟んで位置する第1導電型の第1の不純物領域及び前記第1導電型の第2の不純物領域と、
前記第1の不純物領域上に形成され、前記第1の不純物領域とショットキー接合した金属シリサイド膜と、
を有し、
前記第1の不純物領域は、前記第1導電型の第1の不純物をその濃度プロファイルのピークが前記絶縁膜の底より深く位置するように含有し、
前記第2の不純物領域は、前記第1導電型の第2の不純物を前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有し、
前記第1の不純物領域と前記第2の不純物領域とは前記絶縁膜の底よりも深く、前記絶縁膜の下方の位置で互いに接していることを特徴とする半導体装置。 - 前記第1の不純物領域の垂直な面の少なくとも一部と前記第2の不純物領域とが互いに接していることを特徴とする請求項1に記載の半導体装置。
- 前記第1の不純物領域と前記第2の不純物領域とが互いに接している面が前記半導体基板に対して垂直であることを特徴とする請求項1に記載の半導体装置。
- 前記第1の不純物領域と前記第2の不純物領域とが互いに接している面が前記絶縁膜の底に接していることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 半導体基板の第1の領域に形成された絶縁膜と、
前記半導体基板の前記第1の領域に、前記絶縁膜より深く位置する部分を有し、平面視で前記絶縁膜を間に挟んで位置する第1導電型の第1の不純物領域及び前記第1導電型の第2の不純物領域と、
前記第1の不純物領域上に形成され、前記第1の不純物領域とショットキー接合した金属シリサイド膜と、
を有し、
前記第1の不純物領域は、前記第1導電型の第1の不純物をその濃度プロファイルのピークが前記絶縁膜の底より深く位置し、前記絶縁膜の底より深い位置で一のピークとなるように含有し、
前記第2の不純物領域は、前記第1導電型の第2の不純物を前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有し、
前記第1の不純物領域と前記第2の不純物領域とは前記絶縁膜の底よりも深い位置で互いに接していることを特徴とする半導体装置。 - 前記第1の不純物領域の前記絶縁膜の底より深い部分における前記第1の不純物の濃度は、前記第2の不純物領域における前記第2の不純物の濃度より高いことを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
- 前記第1の不純物領域と前記金属シリサイド膜との間に局所的に形成された前記第1導電型とは異なる第2導電型の第3の不純物領域を有することを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。
- 前記第3の不純物領域は、前記絶縁膜に接することを特徴とする請求項7に記載の半導体装置。
- 前記半導体基板の第2の領域に形成されたゲート電極と、
前記ゲート電極の下方に形成された第1導電型の第4の不純物領域と、
を有し、
前記第4の不純物領域における前記第1導電型の第3の不純物の濃度プロファイルは、前記第1の不純物領域における前記第1の不純物の濃度プロファイルの一部と実質的に同一であることを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置。 - 半導体基板の第1の領域に第1導電型の第1の不純物領域を形成する工程と、
前記半導体基板の第1の領域に前記第1の不純物領域と接する前記第1導電型の第2の不純物領域を形成する工程と、
前記半導体基板の第1の領域に、前記第1の不純物領域の表面と前記第2の不純物領域の表面とを分離する絶縁膜を、前記第1の不純物領域及び前記第2の不純物領域より浅く、かつ前記絶縁膜の底よりも深く、前記絶縁膜の下方の位置で前記第1の不純物領域と前記第2の不純物領域とが互いに接するように形成する工程と、
前記第1の不純物領域上に、前記第1の不純物領域とショットキー接合する金属シリサイド膜を形成する工程と、
を有し、
前記第1の不純物領域を形成する工程では、前記第1導電型の第1の不純物を、その濃度プロファイルのピークが前記絶縁膜の底より深く位置するように導入し、
前記第2の不純物領域を形成する工程では、前記第1導電型の第2の不純物を、前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有するように導入することを特徴とする半導体装置の製造方法。 - 半導体基板の第1の領域に第1導電型の第1の不純物領域を形成する工程と、
前記半導体基板の第1の領域に前記第1の不純物領域と接する前記第1導電型の第2の不純物領域を形成する工程と、
前記半導体基板の第1の領域に、前記第1の不純物領域の表面と前記第2の不純物領域の表面とを分離する絶縁膜を、前記第1の不純物領域及び前記第2の不純物領域より浅く、かつ前記絶縁膜の底よりも深い位置で前記第1の不純物領域と前記第2の不純物領域とが互いに接するように形成する工程と、
前記第1の不純物領域上に、前記第1の不純物領域とショットキー接合する金属シリサイド膜を形成する工程と、
を有し、
前記第1の不純物領域を形成する工程では、前記第1導電型の第1の不純物を、その濃度プロファイルのピークが前記絶縁膜の底より深く位置し、前記絶縁膜の底より深い位置で一のピークとなるように導入し、
前記第2の不純物領域を形成する工程では、前記第1導電型の第2の不純物を、前記第1の不純物領域の前記絶縁膜の底より浅い部分よりも高い濃度で含有するように導入することを特徴とする半導体装置の製造方法。 - 前記第1の不純物領域の前記絶縁膜の底より深い部分における前記第1の不純物の濃度は、前記第2の不純物領域における前記第2の不純物の濃度より高いことを特徴とする請求項10又は11に記載の半導体装置の製造方法。
- 前記第1の不純物領域と前記金属シリサイド膜との間に前記第1導電型とは異なる第2導電型の第3の不純物領域を局所的に形成する工程を有することを特徴とする請求項10乃至12のいずれか1項に記載の半導体装置の製造方法。
- 前記第3の不純物領域は、前記絶縁膜に接することを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記半導体基板の第2の領域に、前記第1導電型の第4の不純物領域を前記第1の不純物領域と並行して形成する工程と、
前記半導体基板で前記第4の不純物領域の上方にゲート電極を形成する工程と、
を有し、
前記第4の不純物領域における前記第1導電型の第3の不純物の濃度プロファイルは、前記第1の不純物領域における前記第1の不純物の濃度プロファイルの一部と実質的に同一であることを特徴とする請求項10乃至14のいずれか1項に記載の半導体装置の製造方法。
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US10535736B2 (en) * | 2017-09-28 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fully strained channel |
US10879124B2 (en) * | 2017-11-21 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to form a fully strained channel region |
US10608122B2 (en) * | 2018-03-13 | 2020-03-31 | Semicondutor Components Industries, Llc | Schottky device and method of manufacture |
US11495463B2 (en) | 2020-10-27 | 2022-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US11920254B2 (en) | 2021-08-30 | 2024-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Detection of contact formation between a substrate and contact pins in an electroplating system |
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JPS62179142A (ja) | 1986-01-31 | 1987-08-06 | Sanyo Electric Co Ltd | 半導体装置 |
US5614755A (en) * | 1993-04-30 | 1997-03-25 | Texas Instruments Incorporated | High voltage Shottky diode |
JP3287269B2 (ja) | 1997-06-02 | 2002-06-04 | 富士電機株式会社 | ダイオードとその製造方法 |
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JP5085241B2 (ja) | 2007-09-06 | 2012-11-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5255305B2 (ja) | 2008-03-27 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2012174878A (ja) | 2011-02-22 | 2012-09-10 | Hitachi Ltd | 半導体装置、及びそれを用いた装置 |
JP6213006B2 (ja) | 2013-07-19 | 2017-10-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
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