TW201913766A - 製造半導體裝置的方法及半導體裝置 - Google Patents

製造半導體裝置的方法及半導體裝置 Download PDF

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TW201913766A
TW201913766A TW107130389A TW107130389A TW201913766A TW 201913766 A TW201913766 A TW 201913766A TW 107130389 A TW107130389 A TW 107130389A TW 107130389 A TW107130389 A TW 107130389A TW 201913766 A TW201913766 A TW 201913766A
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layer
fin structure
source
etching process
drain region
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TWI685025B (zh
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陳彥廷
李威養
楊豐誠
陳燕銘
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台灣積體電路製造股份有限公司
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Abstract

FinFET裝置的鰭結構在基板上方形成。第一層在鰭結構上方形成。閘極層在鰭結構上方並在第一層上方形成。閘極層經圖案化為纏繞在鰭結構周圍的閘極堆疊。第二層在第一層上方並在閘極堆疊上方形成。進行第一蝕刻製程以移除在鰭結構上方形成的第二層的部分,第一層在第一蝕刻製程期間作為蝕刻停止層。進行第二蝕刻製程以移除第一層的部分來暴露出鰭結構的一部分。移除第一層的部分不實質上影響第二層。源極/汲極區域在鰭結構的暴露部分上磊晶生長。

Description

使用含金屬的層作為蝕刻停止層並對鰭 狀場效電晶體的汲極/源極區域進行圖案化
為了追求較高裝置密度、較高效能及較低成本,半導體工業已經進展到奈米技術製程節點。隨著此進展發生,來自製造及設計問題二者的挑戰已經導致三維設計的發展,諸如鰭狀場效電晶體(FinFET)裝置。典型的FinFET裝置利用從基板延伸的薄「鰭」(或鰭狀結構)來製造。鰭通常包含矽並形成電晶體裝置的主體。電晶體的通道在此豎直的鰭中形成。閘極在鰭上方提供(例如,纏繞在鰭周圍)。此類型的閘極允許對通道的更好控制。FinFET裝置的其他優點包括減少的短通道效應及更高的電流。
然而,習知FinFET裝置仍可具有某些缺點。一個缺點係界定習知FinFET製造的源極/汲極區域的方式尚未經優化。例如,在形成源極/汲極區域時FinFET裝置可能遭受磊晶選擇性損失。
因此,儘管現有的FinFET裝置及其製造已經通常適用於其意欲目的,但其等的每個態樣尚未完全令人滿意。
50‧‧‧FinFET裝置
60‧‧‧閘極
60A‧‧‧閘電極部件
60B‧‧‧閘極介電部件
70‧‧‧源極
80‧‧‧汲極
100‧‧‧FinFET裝置
110‧‧‧半導體層
120A‧‧‧N阱
120B‧‧‧P阱
150A‧‧‧鰭結構
150B‧‧‧鰭結構
160‧‧‧隔離結構
170‧‧‧凹陷
180‧‧‧未摻雜之半導體層
200‧‧‧層
205‧‧‧厚度
220‧‧‧閘電極層
230‧‧‧介電層
250‧‧‧硬遮罩層
300‧‧‧蝕刻製程
310‧‧‧SiGe通道
330‧‧‧光阻層
350‧‧‧蝕刻製程
370‧‧‧磊晶生長製程
380‧‧‧源極/汲極區域
390‧‧‧蝕刻製程
400‧‧‧層
450‧‧‧凹陷蝕刻製程
460‧‧‧凹陷
470‧‧‧磊晶生長製程
480‧‧‧源極/汲極區域
600‧‧‧閘極堆疊
610‧‧‧ILD
800‧‧‧方法
810‧‧‧步驟
820‧‧‧步驟
830‧‧‧步驟
840‧‧‧步驟
850‧‧‧步驟
860‧‧‧步驟
870‧‧‧步驟
880‧‧‧步驟
當結合隨附圖式閱讀時,自以下詳細描述將很好地理解本揭示。應注意,根據工業中的標準實務,各特徵並非按比例繪製,並且僅出於說明目的而使用。事實上,出於論述清晰之目的,可任意增加或減小各特徵之尺寸。
第1圖係示例FinFET裝置的透視圖。
第2A圖至第12A圖係根據本揭示的實施例的FinFET裝置在製造的各個階段處的Y切線橫截面側視圖。
第5B圖至第8B圖以及第10B圖至第12B圖係根據本揭示的實施例的FinFET裝置在製造的各個階段處的X切線橫截面側視圖。
第4B圖係根據本揭示的實施例的FinFET裝置在製造的某一階段處的俯視圖。
第5C圖、第7C圖、第8C圖、第11C圖及第12C圖係根據本揭示的實施例的FinFET裝置在製造的不同階段處的三維透視圖。
第7D圖、第8D圖及第11D圖至第12D圖係根據本揭示的實施例的FinFET裝置的一部分在製造的不同階段處的放大之Y切線橫截面側視圖。
第13圖係根據本揭示的實施例的FinFET裝置在製造的某一階段處的三維透視圖。
第14圖係圖示根據本揭示的實施例的製造FinFET裝置的方法的流程圖。
應當理解,以下揭示內容提供了眾多不同的實施例或實例,以用於實施本揭示的不同特徵。下文描述部件及佈置之特定實例以簡化本揭示。當然,此等僅為實例且並不意欲為限制性。例如,以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例,且亦可包括在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外,本揭示可在各實例中重複元件符號及/或字母。此重複係出於簡便性及清晰的緣故且本身並不指示所論述之各實施例及/或配置之間的關係。此外,各種特徵可出於簡便性及清晰的緣故而以不同比例任意繪製。
另外,為了便於描述,本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外,空間相對性術語意欲包含使用或操作中裝置之不同定向。例如,若圖中的裝置翻轉,則描述為在其他元件或特徵的「下方」或「之下」的元件應在其他元件或特徵「上方」定向。因此,示例性術語「下方」可以包含上方及下方的定向兩者。設備可經其他方式定向(旋轉90度或處於其他定向)且由此可類似解讀本文所使用之空間相對性描述詞。
本揭示係關於但不以其他方式限於鰭狀場效電晶體(FinFET)裝置。例如,FinFET裝置可係互補金屬氧化 物半導體(CMOS)裝置,其包括P型金屬氧化物半導體(PMOS)FinFET裝置及N型金屬氧化物半導體(NMOS)FinFET裝置。以下揭示將利用一或多個FinFET實例繼續以說明本揭示的各個實施例。然而,應當理解,本申請案不應限於特定類型的裝置,除非特別地主張。
FinFET裝置的使用已經在半導體工業中得到普及。參看第1圖,圖示了示例FinFET裝置50的透視圖。FinFET裝置50係在基板(諸如整體基板)上方構建的非平面多閘極電晶體。含薄矽的「鰭狀」結構(後文稱為「鰭」)形成FinFET裝置50的主體。鰭沿著第1圖所示的X方向延伸。鰭具有沿著與X方向正交的Y方向量測的鰭寬度W。FinFET裝置50的閘極60纏繞在此鰭周圍,例如,纏繞在鰭的頂表面及相對的側壁表面周圍。因此,閘極60的一部分在與X方向及Y方向二者正交的Z方向中位於鰭上方。
LG指示在X方向中量測的閘極60的長度(或寬度,取決於透視)。閘極60可包括閘電極部件60A及閘極介電部件60B。閘極介電質60B具有在Y方向中量測的厚度tox。閘極60的一部分位於諸如淺溝槽隔離(STI)的介電隔離結構上方。FinFET裝置50的源極70及汲極80在閘極60的相對側面上的鰭的延伸部中形成。由閘極60纏繞在周圍的鰭的一部分作為FinFET裝置50的通道。FinFET裝置50的有效通道長度由鰭的尺寸確定。
FinFET裝置提供優於傳統金屬氧化物半導體場效電晶體(MOSFET)裝置(亦稱為平面電晶體裝置)的 若干優點。此些優點可包括較佳的晶片面積效率、改良的載流子遷移率、及與平面裝置的製造處理相容的製造處理。FinFET裝置亦與高介電常數金屬閘極(HKMG)製程流相容。因此,FinFET裝置可以作為HKMG裝置實施,其中閘極各自具有高介電常數閘極介電質及金屬閘電極。針對上文論述的此等益處,可期望使用FinFET裝置來設計積體電路(IC)晶片以用於IC晶片的一部分或整個IC晶片。
然而,傳統FinFET製造方法仍可具有缺點。一個缺點係尚未優化界定習知FinFET製造的源極/汲極區域的方式。因此,在形成源極/汲極區域時FinFET裝置可遭受磊晶選擇性損失。如下文更詳細論述,為了改良與習知FinFET裝置相關的問題,本揭示在圖案化製程中採用含金屬層以幫助界定FinFET裝置的源極/汲極區域。更詳細而言,第2A圖至第12A圖係FinFET裝置100在製造的各個階段處的Y切線橫截面側視圖,第5B圖至第8B圖以及第10B圖至第12B圖係FinFET裝置100在製造的各個階段處的X切線橫截面側視圖,第4B圖係FinFET裝置100在製造的階段處的俯視圖,第5C圖、第7C圖、第8C圖、第11C圖、第12C圖及第13圖係FinFET裝置100在製造的不同階段處的三維透視圖,且第7D圖、第8D圖及第11D圖至第12D圖係FinFET裝置的一部分在製造的不同階段處的放大之Y切線橫截面側視圖。
現參看第2A圖,FinFET裝置100包括在基板上方形成的半導體層110。在一個實施例中,半導體層110 包括晶體矽材料,諸如矽或鍺矽。可進行佈植製程以將複數個摻雜劑離子佈植到半導體層110。取決於需要n型FET(NFET或NMOS)還是p型FET(PFET或PMOS),摻雜劑離子在一些實施例中可包括n型材料,例如砷(As)或磷(P),或摻雜劑離子在一些其他實施例中可包括p型材料,例如硼(B)。例如,N阱120A可針對PFET形成,且P阱120B可針對NFET形成。
複數個鰭結構藉由經由一或多個微影製程圖案化半導體層110來形成。例如,鰭結構150A針對PFET形成,且鰭結構150B針對NFET形成。用於形成鰭結構150A/150B的微影製程可包括:形成圖案化之光阻劑,使用圖案化之光阻劑來圖案化其下方的硬遮罩層,以及使用圖案化之硬遮罩層來界定鰭結構150A/150B。應當理解,鰭結構150A/150B的部分可作為FinFET裝置100的源極、汲極或通道區域。通道區域可包含矽或鍺矽。
形成隔離結構160以電氣隔離鰭結構150A/150B。隔離結構160亦可被稱為淺溝槽隔離(STI)結構。在一些實施例中,隔離結構160含有介電材料,諸如氧化矽或氮化矽。隔離結構160可藉由以下操作形成:沉積介電材料以填充由鰭結構150A/150B界定的開口,以及隨後進行拋光製程(諸如化學機械拋光)以平坦化所沉積的介電材料的表面。一或多個蝕刻製程可隨後對介電材料進行以藉由從隔離結構160移除材料的部分(但並非全部)來形成凹 陷170。蝕刻製程界定鰭結構150A/150B的「高度」(在第1圖的Z方向中)。
如第2A圖所示,鰭結構150A/150B向上突出(例如,沿著第1圖的Z軸向上)並突出到隔離結構160外。換言之,每個鰭結構150A/150B的至少一部分暴露出並且不由隔離結構160覆蓋。亦應當理解,可選的未摻雜之半導體層(例如,未摻雜之矽)180在一些實施例中可設置在鰭結構150A與N阱之間。在其他實施例中,可省略層180。
現參看第3A圖,層200在鰭結構150A/150B的側表面及頂表面上方形成以用於PFET及NFET二者。層200亦在隔離結構160的上表面上方形成並部分填充凹陷170。層200在稍後的蝕刻製程中作為蝕刻停止層,此將在後文更詳細論述。習知FinFET製造製程不形成此層200。
在一些實施例中,層200包括介電層,例如,含金屬介電層。在層200中存在金屬幫助促進在稍後進行的濕式蝕刻製程中移除層200,其中SCI溶液(H2O:H2O2:NH4OH)及/或SC2溶液(HCl:H2O2:H2O)可作為蝕刻劑。在一些實施例中,磷酸(H3PO4)亦可在濕式蝕刻製程中作為蝕刻劑。在隨後的蝕刻製程中輕易移除層200使層200成為用於圖案化層的良好候選。在一些實施例中,層200包括氧化鋁(Al2O3)。可使用任何適宜沉積技術(例如,CVD、HDP-CVD、ALD等等)將層200形成為任何適宜厚度。在圖示的實施例中,層200使用保形CVD及/或ALD沉積製程來形成,並且形成具有厚度205的層200。 在一些實施例中,厚度205係在約2奈米(nm)至約20nm之範圍中。應當理解,層200的材料組成及厚度範圍經特定配置為使得層200可以適當地作為蝕刻停止層並且亦促進在下文的濕式蝕刻製程中輕易移除。
現參看第4A圖,閘電極層220在鰭結構150A/150B上方並在層200上方形成。在一些實施例中,閘電極層220係將在稍後的製程中移除的虛擬閘電極層。例如,閘電極層220可包括多晶矽,其在稍後的製造步驟中的閘極替代製程中移除並利用金屬閘電極替代。閘電極層220可由一或多個沉積製程形成,諸如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其組合。
在沉積閘電極層220之後,一或多個蝕刻製程可對閘電極層220進行以界定閘極長度Lg(如第1圖所示在X方向中量測的)。換言之,閘電極層220藉由一或多個蝕刻製程圖案化為分離的閘電極堆疊220。此在第4B圖中更詳細地圖示,第4B圖係FinFET裝置100的俯視圖。如第4B圖的俯視圖中所示,複數個鰭結構(例如,鰭結構150A/150B)在X方向(如第1圖所示的相同X方向)中延伸,且複數個圖案化之閘電極堆疊220在Y方向(如第1圖所示的相同Y方向)中延伸。在俯視圖中的FinFET裝置100的Y切線(在Y方向中)產生第4A圖所示的橫截面圖。在俯視圖中的FinFET裝置100的X切線(在X方向中)將產生不同的橫截面圖,此將在下文參考第5B圖至第8B圖以及第10B圖至第12B圖更詳細地論述。
現參看第5A圖、第5B圖及第5C圖,介電層230在層200上方形成並且亦在圖案化之閘電極堆疊220上方形成。第5A圖係使用Y切線獲得的橫截面圖,且第5B圖係使用X切線獲得的橫截面圖。X切線及Y切線亦在第5C圖中圖示,第5C圖係FinFET裝置100的三維透視圖。
如在第5C圖中(並且亦在根據Y切線獲得的第5A圖中)所示,層200在鰭結構150A及150B的每一者的側表面及頂表面上形成。介電層230隨後在層200的側表面及頂表面上形成。注意到,在第5A圖中,由於Y切線在閘電極堆疊220外部截取,閘電極堆疊220不應在第5A圖的橫截面中直接可見。然而,為了促進對本揭示的理解,閘電極堆疊220之一者仍利用第5A圖中的虛線圖示,以圖示閘電極堆疊220位於鰭結構150A/150B以及層200及230的「後方」。
如在第5C圖中(並且亦在根據X切線獲得的第5B圖中)所示,由於在沉積層200之後形成並界定閘電極堆疊220,在閘電極堆疊220的側壁上不形成層200的部分。但在形成閘電極堆疊220之後形成介電層230,且因此在閘電極堆疊220的側壁上形成介電層230。注意到,如第5A圖及第5C圖所示,在每個閘電極堆疊220上方可設置的一或多個硬遮罩層250。一或多個硬遮罩層250用於圖案化閘電極堆疊220並界定閘電極堆疊220的尺寸。在一些實施例中,一或多個硬遮罩層250包括氧化物材料,例如,氧化矽。如第5B圖及第5C圖所示,介電層230在硬遮罩層250的側表面及頂表面上方形成。
應當理解,介電層230及層200的材料組成經配置為使得在隨後的蝕刻製程中在介電層230與層200之間存在蝕刻選擇性。換言之,介電層230及層200在隨後的蝕刻製程中具有實質上不同的蝕刻速率(例如,10倍或更多倍)。在一些實施例中,介電層230包括氮化物材料,例如氮化矽,而層200包括含金屬的氧化物材料,諸如氧化鋁(Al2O3)。介電層230用於界定FinFET裝置100的有源區域及源極/汲極區域。介電層230亦作為虛擬間隔件。
亦注意到,截取以獲得第5B圖的X切線在鰭結構150A/150B外部截取,且因此鰭結構150A/150B在第5B圖的橫截面圖中不可見,而是替代地將隔離結構160圖示為位於閘電極堆疊220下方。應當理解,若將X切線移動至一點,此處X切線與鰭結構150A或150B之一者交叉(如同下文論述的圖中的一些圖的情形),則鰭結構150A或150B應圖示為位於閘電極堆疊220下方,由於每個閘電極堆疊220纏繞在鰭結構150A及150B的頂表面及側表面周圍。
現參看第6A圖及第6B圖,對FinFET裝置100進行蝕刻製程300以移除在鰭結構150A及150B上方形成的介電層230的部分,而不移除在閘電極堆疊220的側壁上形成的介電層230的部分。注意到,如第6B圖所示,蝕刻製程300亦移除在硬遮罩250上方的介電層230的部分。在一些實施例中,蝕刻製程300包括乾式蝕刻製程,其促進介電層230的選擇性移除(亦即,對於鰭結構150A/150B而言移除介電層230,而對於閘電極堆疊220而言保持介電層 230)。再者,由於對應於第6B圖的X切線在鰭結構150A/150B外部截取,在鰭結構150A及150B上方的介電層230的移除可能不在第6B圖中直接呈現。
如上文論述,介電層230及層200的材料組成經配置為使得在蝕刻製程300中在介電層230與層200之間存在蝕刻選擇性。因此,層200在蝕刻製程300期間作為蝕刻停止層。亦即,蝕刻製程300移除位於鰭結構150A/150B的頂表面及側表面上方的介電層230的部分,但層200防止蝕刻製程300蝕刻鰭結構150A/150B本身。
現參看第7A圖、第7B圖及第7C圖,針對PFET界定源極/汲極區域。類似於上文論述的第5C圖,第7C圖係FinFET裝置100的三維透視圖,第7A圖係使用Y切線獲得的橫截面圖,且第7B圖係使用X切線獲得的橫截面圖。如同針對第5A圖的情形,對應於第7A圖的Y切線在鰭結構處截取。然而,現移動對應於第7B圖的X切線(相較於第5B圖),使得X切線現與PFET的鰭結構150A交叉。因此,由第7C圖中的X切線產生的第7B圖現圖示了鍺矽(SiGe)通道310的一部分,其係鰭結構150A的一部分。亦如第7B圖所示,N阱120A位於SiGe通道310下方。
為了針對PFET界定源極/汲極區域,FinFET裝置100的NFET部分由圖案化之光阻層330覆蓋。露出FinFET裝置100的PFET部分。隨後對FinFET裝置100的PFET部分進行蝕刻製程350。在一些實施例中,蝕刻製程350包括濕式蝕刻製程。歸因於在層200與介電層230之間 的蝕刻選擇性,蝕刻製程350移除層200,但使介電層230保持完整。注意到,如第7C圖所示,先前的蝕刻製程300已經移除在鰭結構150A/150B上方形成的介電層230的部分,但介電層230的部分仍餘留在閘電極堆疊220的側壁上。由此,蝕刻製程350使設置在閘電極堆疊220的側壁上的介電層230的部分保持完整,而移除層200。
在一些實施例中,蝕刻製程350使用SC1溶液(H2O:H2O2:NH4OH)及/或SC2溶液(HCl:H2O2:H2O)作為蝕刻劑。在一些其他實施例中,磷酸(H3PO4)亦可在蝕刻製程350中作為蝕刻劑。用於層200的材料組成經配置為使得層可由蝕刻製程350輕易地移除。例如,在層200含有氧化鋁的實施例中,氧化鋁可由SC1溶液及/或SC2溶液或藉由磷酸輕易地移除。層200的輕易可移除性使得其成為用於進行圖案化製程的適宜層。
如第7A圖所示,針對PFET的層200的移除暴露出鰭結構150A的頂表面及側表面。應當理解,在實際製造中,層200的移除可以不係100%。換言之,甚至在進行蝕刻製程350之後可仍餘留層200的剩餘部分。例如,儘管在進行蝕刻製程350以移除層200之後可暴露出鰭結構150A的頂表面及側壁的上部,鰭結構150A的下部仍可具有設置在其上的層200的殘留物,例如,如第7D圖所示,第7D圖係第7A圖的PFET的更加放大的橫截面圖。如第7D圖所示,儘管暴露出鰭結構150A的上部,甚至在進行蝕刻製程 350之後,層200的殘留物仍可設置在鰭結構150A的下部的側壁上。
類似地,在先前的蝕刻製程300中移除介電層230亦可能不完全移除介電層230。例如,如第7D圖所示,在進行蝕刻製程350之後,介電層230的剩餘部分亦可保持設置在層200的殘留物上。在任何情形下,鰭結構150A的暴露部分(亦即,上部)能夠磊晶生長PFET的源極/汲極區域,此將在下文論述。
同時,由於層200(歸因於由圖案化之光阻層330保護而未移除層200)仍設置在鰭結構150B上,未暴露針對NFET的鰭結構150B。以此方式,針對PFET(但不針對NFET)移除介電層200暴露出針對PFET的鰭結構,由此允許界定PFET的S/D區域。
現參看第8A圖、第8B圖、第8C圖及第8D圖,移除圖案化之光阻層330,且進行磊晶生長製程370以磊晶生長PFET的源極/汲極區域380。類似於第7A圖至第7D圖,第8C圖係FinFET裝置100的三維透視圖,第8A圖係使用Y切線獲得的橫截面圖,且第8B圖係使用X切線獲得的橫截面圖,且第8D圖係第8A圖的PFET的更加放大的橫截面圖。
如第8A圖至第8D圖所示,在製程370期間源極/汲極區域380在鰭結構150A的暴露部分(例如,上部)上生長。源極/汲極區域380在Z方向中向上突出並在Y方向中橫向突出。在鰭結構150A包含SiGe的實施例中,針對PFET 的源極/汲極區域380亦包含SiGe。如第8D圖所示,層200及230的殘留物仍可保持在鰭結構150A的下部的側壁上形成,且源極/汲極區域380的部分在層200及230的殘留物上方形成。
由於FinFET裝置100的NFET部分仍由層200覆蓋,針對NFET尚未形成源極/汲極區域。換言之,由於鰭結構150B仍由層200及230覆蓋,磊晶生長製程370不針對NFET在鰭結構150B上生長任何事物。在某些習知方案中,針對PFET及NFET的源極/汲極區域同時生長,並且因此含SiGe的源極/汲極可針對NFET而生長,及/或含Si的源極/汲極可針對PFET而生長。此係不期望的且可被稱為磊晶選擇性損失。相比之下,本文的層200允許針對PFET的源極/汲極區域獨立於針對NFET的源極/汲極區域而形成。因此,針對PFET形成的源極/汲極區域380包含SiGe,但將實質上不具有Si,且針對NFET形成的源極/汲極區域(在下文論述的隨後製程中)將包含Si,但將實質上不具有SiGe。因此,本揭示的製程提供了磊晶選擇性損失抗擾性。
現參看第9A圖,針對NFET移除層200。在一些實施例中,層200的移除可使用與蝕刻製程350類似的蝕刻製程390來進行。如上文論述,由於在層200與介電層230之間存在蝕刻選擇性,藉由蝕刻移除層200不實質上移除介電層230。在移除層200之後,暴露出鰭結構150B。本文移除層200的一個原因是為了製程控制穩定性。其幫助穩定製 程控制以移除層200,並且隨後再沉積層(如將參考後文論述的第10A圖至第10B圖完成),以用於下一輪圖案化。
現參看第10A圖及第10B圖,層400針對NFET在鰭結構150B的側表面及頂表面上方形成,並針對PFET在源極/汲極區域380的側表面及頂表面上方形成。層400亦在隔離結構160的上表面上方形成。在一些實施例中,層400的形成涉及保形沉積製程。在一些實施例中,層400及層200具有相同的材料組成。例如,層400亦可包括介電層,例如含金屬的介電層。在一些實施例中,層400包括氧化鋁(Al2O3)。應當理解,層400將實質上提供與上文論述的層200相同的功能。換言之,據說層400的形成等同於再沉積層200。
注意到,第10B圖藉由在FinFET裝置100的兩個不同部分處截取X切線來獲得。第10B圖所示的PFET藉由跨鰭結構150A之一者截取X切線來獲得,且第10B圖所示的NFET藉由跨鰭結構150B之一者截取X切線來獲得。第10B圖所示的NFET圖示針對NFET的矽通道410,其中矽通道係針對NFET的鰭結構150B的一部分。P阱120B位於矽通道410下方。
現參看第11A圖、第11B圖、第11C圖及第11D圖,針對NFET界定源極/汲極區域。第11C圖係FinFET裝置100的三維透視圖,第11A圖係使用Y切線獲得的橫截面圖,第11B圖係在FinFET裝置的兩個不同部分處使用X切線(PFET處的一個X切線及NFET處的另一個X切線)獲得 的橫截面圖。第11D圖係第11A圖的NFET的更加放大的橫截面圖。
針對NFET的源極/汲極的界定與上文參考第7A圖至第7D圖所論述的針對PFET的源極/汲極的界定類似(除了切換NFET及PFET之外)。例如,作為NFET源極/汲極界定的一部分,FinFET裝置100的PFET部分可由圖案化之光阻層覆蓋(出於簡便性原因,在本文中未具體地圖示)。隨後暴露出FinFET裝置100的NFET部分。對FinFET裝置100的NFET部分進行與上文論述的蝕刻製程300類似的蝕刻製程,以移除在鰭結構150B上方形成的介電層230的部分。層400在此蝕刻製程期間作為蝕刻停止層。其後,歸因於在層400與介電層230之間的蝕刻選擇性,進行與上文論述的蝕刻製程350類似的蝕刻製程以移除針對NFET的層400的部分,但使介電層230保持完整。層400的移除暴露出針對NFET的鰭結構150B的部分。同時,由於層400(歸因於由圖案化之光阻層保護而未移除層400)仍設置在針對PFET的源極/汲極區域380上,未暴露出針對PFET的源極/汲極區域380。
凹陷蝕刻製程450隨後對FinFET裝置100進行,以蝕刻NFET中的凹陷460。如第11B圖至第11C圖所示,凹陷460在鰭結構150B中形成,例如藉由蝕刻掉鰭結構150B的部分。因此,鄰近NFET的矽通道410形成凹陷460。第11C圖及第11D圖亦圖示了在蝕刻層400之後仍餘 留的層400的部分。層400的此些剩餘部分在Z方向中有效地進一步向上延伸凹陷460。
由於凹陷460對應於鰭結構150B的缺失,歸因於在凹陷460處截取的Y切線,凹陷460在第11A圖中不立即或明顯地可見。然而,為了促進對本揭示的理解,在第11A圖中圖示在鰭結構150B的剩餘部分上方的虛線以表示凹陷460(亦即,已經針對NFET移除的鰭結構150B的部分)。
現參看第12A圖、第12B圖、第12C圖、及第12D圖,進行磊晶生長製程470以磊晶生長NFET的源極/汲極區域480。其後移除層400。特定而言,第12C圖係FinFET裝置100的三維透視圖,第12A圖係使用Y切線獲得的橫截面圖,且第12B圖係使用針對PFET的一個X切線及針對NFET的另一個X切線獲得的橫截面圖,且第12D圖係第12A圖的NFET的更加放大的橫截面圖。
如第12A圖、第12C圖及第12D圖所示,在磊晶生長製程470期間針對NFET的源極/汲極區域480在鰭結構150B的暴露部分上生長。源極/汲極區域480填充凹陷460並在Z方向中向上突出到凹陷460外且在Y方向中橫向突出。在鰭結構150B包含Si的實施例中,源極/汲極區域480亦包含Si。如上文所論述,PFET源極/汲極區域380已經在形成NFET源極/汲極區域480之前形成。PFET及NFET源極/汲極區域的分離形成(其可能由本揭示之獨特製程流進行)允許FinFET裝置100的源極/汲極區域的較高品質磊晶生長。亦如第12D圖所示,由於層400及230的移 除可能不係100%,層400及230之殘留物可以保持在源極/汲極區域480下方形成。層400及230亦可設置在源極/汲極區域480的下部的側壁上。
注意到,在第12C圖所示的製造的階段中,介電層230(但不係層400)仍設置在閘電極堆疊220的側壁上。此等介電層230將在隨後製程中移除,且低介電常數介電材料將沉積為用於閘電極堆疊220的側壁間隔件。此外,由於層200、400、230的移除可能不係100%,在磊晶生長的源極/汲極區域380及480下面可存在層200、400及/或介電層230的剩餘部分,例如,如第12C圖所示。注意到,在一些實施例中(諸如在第12A圖至第12D圖所示的實施例中),NFET及PFET之一者(例如,NFET)包含凹陷之鰭,而NFET及PFET之另一者(例如,PFET)包含未凹陷之鰭,其上方可形成源極/汲極。
進行複數個其他製程以完成FinFET裝置100的製造。例如,可進行閘極替代製程以利用金屬閘電極堆疊替代閘電極堆疊220,其係虛擬閘電極堆疊。例如,作為閘極替代製程的一部分,層間介電(ILD)在隔離結構160上方形成。ILD可含有氧化矽。進行諸如化學機械拋光(CMP)的拋光製程以平坦化ILD的上表面。隨後移除虛擬閘電極堆疊220,且可在每個移除之虛擬閘電極堆疊的位置處形成金屬閘電極堆疊。在一些實施例中,金屬閘電極堆疊可包括工作函數金屬部件及填充金屬部件。工作函數金屬部件經配置為調諧其對應的FinFET的工作函數以達到期望的閾值電壓 Vt。在各個實施例中,工作函數金屬部件可含有:TiAl、TiAlN、TaCN、TiN、WN或W、或其組合。填充金屬部件經配置為作為閘電極的主導電部分。在各個實施例中,填充金屬部件可含有鋁(Al)、鎢(W)、銅(Cu)、或其組合。亦應當理解,高介電常數閘極介電質可在每個金屬閘電極堆疊下面形成。高介電常數介電材料係具有大於SiO2之介電常數的介電常數(其近似為4)的材料。在實施例中,高介電常數閘極介電質包括氧化鉿(HfO2),其具有在從近似18至近似40的範圍中的介電常數。在替代實施例中,高介電常數閘極介電質可包括ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO或SrTiO。
現參看第13圖,FinFET裝置100的三維圖解在已經進行上文論述的閘極替代製程之後圖示。如第13圖所示,形成閘極堆疊600以替代虛擬閘電極堆疊220。閘極堆疊600可包括如上文論述的高介電常數閘極介電質及金屬閘電極。ILD 610在閘極堆疊600的側壁上形成。閘極堆疊600及ILD在隔離結構160上方形成。第13圖所示的FinFET裝置100的部分係NFET,且因此形成鰭結構150B及磊晶生長的源極/汲極區域480。
如上文論述,歸因於製程窗限制,層400及230的一些剩餘部分仍可保持在源極/汲極區域480的下部的側壁上(且在源極/汲極區域480的上部下方)形成。類似地,層200及230的一些剩餘部分可保持在針對PFET的鰭結構 150A的下部的側壁上形成(諸如第8D圖及第12D圖中圖示),但出於簡便性原因,PFET未在第13圖中圖示。
應當理解,由於此等層的剩餘部分大部分歸因於製程瑕疵,在製造的此階段處(亦即,在閘極替代之後)層230及200/400的存在並非是有意的,此等層亦不在此點處提供重要功能。儘管如此,在製造的此階段處存在此等層230及200/400係已經進行上文論述的獨特製造流程的證據。換言之,若發現來自給定製造商的最終的FinFET裝置在上文參考第8D圖、第12C圖至第12D圖及第13圖所論述的位置中含有層230及200/400的殘留物,可能使用本揭示的獨特製造流程製造最終的FinFET裝置。
第14圖係根據本揭示的各個態樣的用於製造FinFET裝置的方法800的流程圖。方法800包括在基板上方形成FinFET裝置之鰭結構的步驟810。
方法800包括在鰭結構上方形成第一層的步驟820。在一些實施例中,形成第一層包含形成含金屬層作為第一層。在一些實施例中,形成含金屬層包含形成具有在約1nm與約10nm之間的厚度的氧化鋁(Al2O3)層,並藉由保形CVD及/或ALD製程沉積為第一層。
方法800包括在鰭結構上方並在第一層上方形成閘極層的步驟830。
方法800包括將閘極層圖案化為纏繞在鰭結構周圍的閘極堆疊的步驟840。
方法800包括在第一層上方並在閘極堆疊上方形成第二層的步驟850。在一些實施例中,形成第二層包含形成含有氮化矽的層作為第二層。
方法800包括進行第一蝕刻製程以移除在鰭結構上方形成的第二層的部分的步驟860。在第一蝕刻製程中,在第一層與第二層之間存在第一蝕刻選擇性,使得第一層在第一蝕刻製程期間作為蝕刻停止層。在一些實施例中,第一蝕刻製程包含乾式蝕刻製程。
方法800包括進行第二蝕刻製程以移除第一層的部分來暴露出鰭結構的一部分的步驟870。在第二蝕刻製程中,在第一層與第二層之間存在第二蝕刻選擇性,使得移除第一層的部分不實質上影響第二層。在一些實施例中,第二蝕刻製程包含濕式蝕刻製程。
方法800包括在鰭結構之暴露部分上磊晶生長源極/汲極區域的步驟880。
在一些實施例中,第二蝕刻製程不完全移除第一層,但仍將第一層的殘留物餘留在鰭結構的側壁上。在一些實施例中,第一蝕刻製程不完全移除第二層,但仍將第二層的殘留物餘留在第一層的側壁上。
應當理解,在上文論述的步驟810至880之前、期間或之後可進行額外製程步驟,以完成半導體裝置的製造。例如,閘極堆疊可包含虛擬閘電極,且方法800可進一步包括以下步驟:利用金屬閘電極替代虛擬閘電極。此外,在一些實施例中針對FinFET裝置的PFET進行步驟860至 880,在此情形下方法800可進一步針對FinFET裝置的NFET重複步驟860至880。作為另一實例,方法800可包括以下步驟:在NFET的源極/汲極區域已經磊晶生長之後但在重複之前移除第一層並再沉積第一層。出於簡便性原因,本文並未論述其他製程步驟。
基於以上論述,可以看到本揭示提供優於習知FinFET及其製造的優點。然而,應當理解,其他實施例可提供額外優點,且本文不必揭示所有優點,且所有實施例並不需要特定優點。一個優點係含金屬層(例如,氧化鋁層)的形成允許其作為蝕刻停止層以用於其上方形成的介電層(例如,氮化矽層),此係歸因於在此等兩層之間的良好蝕刻選擇性。另一優點係含金屬層可在濕式蝕刻製程中輕易地移除,此使得金屬層適用於圖案化。又一優點係所論述的獨特製造流程可以在形成PFET及NFET的源極/汲極區域期間減少磊晶選擇性損失。本揭示的又一優點係本文論述的獨特製造步驟容易實施並與現有製造製程流程相容。由此,實施本揭示不導致成本增加。
本揭示的一個態樣涉及一種製造半導體裝置的方法。FinFET裝置的鰭結構在基板上方形成。第一層在鰭結構上方形成。閘極層在鰭結構上方並在第一層上方形成。閘極層經圖案化為纏繞在鰭結構周圍的閘極堆疊。第二層在第一層上方並在閘極堆疊上方形成。進行第一蝕刻製程以移除在鰭結構上方形成的第二層的部分。在第一蝕刻製程中,在第一層與第二層之間存在第一蝕刻選擇性,使得第一層在 第一蝕刻製程期間作為蝕刻停止層。進行第二蝕刻製程以移除第一層的部分來暴露出鰭結構的一部分。在第二蝕刻製程中,在第一層與第二層之間存在第二蝕刻選擇性,使得移除第一層的部分不實質上影響第二層。源極/汲極區域在鰭結構的暴露部分上磊晶生長。
本揭示的另一態樣涉及一種半導體裝置。半導體裝置包括突出到基板外的鰭結構。源極/汲極區域設置在鰭結構的上部的側壁上。含金屬材料設置在鰭結構的下部的側壁上。
本揭示的又一態樣涉及一種半導體裝置。半導體裝置包括突出到基板外的鰭結構。鰭結構的上部包括凹陷。源極/汲極區域設置在鰭結構上方。源極/汲極區域填充凹陷。含金屬材料設置在源極/汲極區域的下部的側壁上。含金屬材料設置在源極/汲極區域的下部下方。
上文概述了若干實施例之特徵,使得熟習此項技術者可更好地理解本揭示之態樣。熟習此項技術者應瞭解,可輕易使用本揭示作為設計或修改其他製程及結構的基礎,以便實施本文所介紹之實施例的相同目的及/或實現相同優點。熟習此項技術者亦應認識到,此類等效結構並未脫離本揭示之精神及範疇,且可在不脫離本揭示之精神及範疇的情況下產生本文的各種變化、替代及更改。

Claims (20)

  1. 一種方法,包含:在一基板上方形成一FinFET裝置的一鰭結構;在該鰭結構上方形成一第一層;在該鰭結構上方並在該第一層上方形成一閘極層;將該閘極層圖案化為纏繞在該鰭結構周圍的一閘極堆疊;在該第一層上方並在該閘極堆疊上方形成一第二層;進行一第一蝕刻製程以移除在該鰭結構上方形成的該第二層的部分,其中在該第一蝕刻製程中,在該第一層與該第二層之間存在一第一蝕刻選擇性,使得該第一層在該第一蝕刻製程期間作為一蝕刻停止層;進行一第二蝕刻製程以移除該第一層的部分來暴露該鰭結構的一部分,其中在該第二蝕刻製程中,在該第一層與該第二層之間存在一第二蝕刻選擇性,使得該第一層的該等部分的一移除不實質上影響該第二層;以及在該鰭結構的該暴露部分上磊晶生長一源極/汲極區域。
  2. 如請求項1所述之方法,其中該進行該第一蝕刻製程、該進行該第二蝕刻製程、及該磊晶生長該源極/汲極區域針對該FinFET裝置的一PFET進行,並且其中該方法更包含:針對該FinFET裝置的一NFET重複該進行該第一蝕刻製程、該進行該第二蝕刻製程、及該磊晶生長該源極/汲極區域。
  3. 如請求項2所述之方法,更包含:在該NFET的該源極/汲極區域已經磊晶生長之後但在該重複之前移除該第一層並再沉積該第一層。
  4. 如請求項1所述之方法,其中該形成該第一層包含形成一含金屬層作為該第一層。
  5. 如請求項4所述之方法,其中該形成該含金屬層包含形成一氧化鋁(Al 2O 3)層作為該第一層。
  6. 如請求項1所述之方法,其中該形成該第二層包含形成一含有氮化矽的層作為該第二層。
  7. 如請求項1所述之方法,其中該第一蝕刻製程包含一乾式蝕刻製程。
  8. 如請求項1所述之方法,其中該第二蝕刻製程包含一濕式蝕刻製程。
  9. 如請求項1所述之方法,其中:該第二蝕刻製程不完全移除該第一層,但仍將該第一層的殘留物餘留在該鰭結構的側壁上;以及該第一蝕刻製程不完全移除該第二層,但仍將該第二層的殘留物餘留在該第一層的側壁上。
  10. 如請求項1所述之方法,其中該閘極堆疊包含一虛擬閘電極,且其中該方法更包含:利用一金屬閘電極替代該虛擬閘電極。
  11. 一種半導體裝置,包含:一鰭結構,突出到一基板外;一源極/汲極區域,設置在該鰭結構的一上部的一側壁上;以及 一含金屬材料,設置在該鰭結構的一下部的一側壁上。
  12. 如請求項11所述之半導體裝置,其中該含金屬材料包含氧化鋁。
  13. 如請求項11所述之半導體裝置,更包含:設置在該含金屬材料上的一氮化物材料。
  14. 如請求項11所述之半導體裝置,其中該源極/汲極區域係一P型FinFET的一源極/汲極區域。
  15. 如請求項14所述之半導體裝置,其中該鰭結構及該源極/汲極區域的每一者包括鍺矽。
  16. 一種半導體裝置,包含:一鰭結構,突出到一基板外,其中該鰭結構的一上部包括一凹陷;一源極/汲極區域,設置在該鰭結構上方,其中該源極/汲極區域填充該凹陷;以及一含金屬材料,設置在該源極/汲極區域的一下部的一側壁上,且其中該含金屬材料設置在該源極/汲極區域的一上部下方。
  17. 如請求項16所述之半導體裝置,其中該含金屬材料包含氧化鋁。
  18. 如請求項16所述之半導體裝置,更包含:設置在該含金屬材料上的一氮化物材料。
  19. 如請求項16所述之半導體裝置,其中該源極/汲極區域係一N型FinFET的一源極/汲極區域。
  20. 如請求項19所述之半導體裝置,其中該鰭結構及該源極/汲極區域的每一者包含矽。
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TWI685025B (zh) 2020-02-11
US20200043804A1 (en) 2020-02-06
CN109427872B (zh) 2022-08-12

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